From 6910c59944ac90431e821ec9ffbea97dfd1226a0 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Tue, 11 Aug 2020 15:31:23 +1000 Subject: [PATCH] Remove trailing carriage-return characters Signed-off-by: Paul Mackerras --- rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl | 23176 ++++++++-------- .../vhdl/ibm/std_ulogic_function_support.vhdl | 10306 +++---- rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl | 3034 +- rel/src/vhdl/ibm/std_ulogic_support.vhdl | 5356 ++-- rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl | 692 +- rel/src/vhdl/work/acq_soft.vhdl | 9032 +++--- rel/src/vhdl/work/pcq_psro_soft.vhdl | 50 +- rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl | 2068 +- 8 files changed, 26857 insertions(+), 26857 deletions(-) diff --git a/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl index f0aa046..aba65a7 100644 --- a/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl @@ -1,11588 +1,11588 @@ ---*************************************************************************** --- Copyright 2020 International Business Machines --- --- Licensed under the Apache License, Version 2.0 (the “License”); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- http://www.apache.org/licenses/LICENSE-2.0 --- --- The patent license granted to you in Section 3 of the License, as applied --- to the “Work,” hereby includes implementations of the Work in physical form. --- --- Unless required by applicable law or agreed to in writing, the reference design --- distributed under the License is distributed on an “AS IS” BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ---*************************************************************************** -library ibm,ieee ; -use ieee.std_logic_1164.all ; -use ibm.std_ulogic_support.all; - -package std_ulogic_ao_support is - -- ============================================================= - -- 2 input Port AO/OA Gates - -- ============================================================= - -- Single bit case - -- Multiple vectors logically ed bitwise - function gate_ao_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1 : function is 1; - attribute pin_bit_information of gate_ao_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1 : function is 1; - attribute pin_bit_information of ao_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1 : function is 1; - attribute pin_bit_information of aoi_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1 : function is 1; - attribute pin_bit_information of gate_oa_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1 : function is 1; - attribute pin_bit_information of oa_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1 : function is 1; - attribute pin_bit_information of gate_oai_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1 : function is 1; - attribute pin_bit_information of oai_2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2 : function is 1; - attribute pin_bit_information of gate_ao_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2 : function is 1; - attribute pin_bit_information of ao_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2 : function is 1; - attribute pin_bit_information of gate_aoi_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2 : function is 1; - attribute pin_bit_information of aoi_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2 : function is 1; - attribute pin_bit_information of gate_oa_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2 : function is 1; - attribute pin_bit_information of oa_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2 : function is 1; - attribute pin_bit_information of gate_oai_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2 : function is 1; - attribute pin_bit_information of oai_2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - -- ============================================================= - -- 2x3 input Port AO/OA Gates - -- ============================================================= - -- Vectored primitive input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function gate_ao_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1x1 : function is 1; - attribute pin_bit_information of gate_ao_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1x1 : function is 1; - attribute pin_bit_information of ao_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1x1 : function is 1; - attribute pin_bit_information of aoi_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1x1 : function is 1; - attribute pin_bit_information of gate_oa_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1x1 : function is 1; - attribute pin_bit_information of oa_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1x1 : function is 1; - attribute pin_bit_information of gate_oai_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1x1 : function is 1; - attribute pin_bit_information of oai_2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x1 : function is 1; - attribute pin_bit_information of gate_ao_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x1 : function is 1; - attribute pin_bit_information of ao_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x1 : function is 1; - attribute pin_bit_information of aoi_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x1 : function is 1; - attribute pin_bit_information of gate_oa_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x1 : function is 1; - attribute pin_bit_information of oa_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x1 : function is 1; - attribute pin_bit_information of gate_oai_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x1 : function is 1; - attribute pin_bit_information of oai_2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2 : function is 1; - attribute pin_bit_information of gate_ao_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2 : function is 1; - attribute pin_bit_information of ao_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2 : function is 1; - attribute pin_bit_information of gate_aoi_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2 : function is 1; - attribute pin_bit_information of aoi_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2 : function is 1; - attribute pin_bit_information of gate_oa_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2 : function is 1; - attribute pin_bit_information of oa_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2 : function is 1; - attribute pin_bit_information of gate_oai_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2 : function is 1; - attribute pin_bit_information of oai_2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - -- ============================================================= - -- 2x4 input Port AO/OA Gates - -- ============================================================= - -- Vectored primitive input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function gate_ao_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x1x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1x1x1 : function is 1; - attribute pin_bit_information of gate_ao_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x1x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1x1x1 : function is 1; - attribute pin_bit_information of ao_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x1x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x1x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1x1x1 : function is 1; - attribute pin_bit_information of aoi_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x1x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1x1x1 : function is 1; - attribute pin_bit_information of gate_oa_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x1x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1x1x1 : function is 1; - attribute pin_bit_information of oa_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x1x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1x1x1 : function is 1; - attribute pin_bit_information of gate_oai_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x1x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1x1x1 : function is 1; - attribute pin_bit_information of oai_2x1x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x1x1 : function is 1; - attribute pin_bit_information of gate_ao_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x1x1 : function is 1; - attribute pin_bit_information of ao_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x1x1 : function is 1; - attribute pin_bit_information of aoi_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x1x1 : function is 1; - attribute pin_bit_information of gate_oa_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x1x1 : function is 1; - attribute pin_bit_information of oa_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x1x1 : function is 1; - attribute pin_bit_information of gate_oai_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x1x1 : function is 1; - attribute pin_bit_information of oai_2x2x1x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2x1 : function is 1; - attribute pin_bit_information of gate_ao_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2x1 : function is 1; - attribute pin_bit_information of ao_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is 1; - attribute pin_bit_information of gate_aoi_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2x1 : function is 1; - attribute pin_bit_information of aoi_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2x1 : function is 1; - attribute pin_bit_information of gate_oa_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2x1 : function is 1; - attribute pin_bit_information of oa_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2x1 : function is 1; - attribute pin_bit_information of gate_oai_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2x1 : function is 1; - attribute pin_bit_information of oai_2x2x2x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_2x2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2x2 : function is 1; - attribute pin_bit_information of gate_ao_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_2x2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2x2 : function is 1; - attribute pin_bit_information of ao_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_2x2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is 1; - attribute pin_bit_information of gate_aoi_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_2x2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2x2 : function is 1; - attribute pin_bit_information of aoi_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_2x2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2x2 : function is 1; - attribute pin_bit_information of gate_oa_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_2x2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2x2 : function is 1; - attribute pin_bit_information of oa_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_2x2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2x2 : function is 1; - attribute pin_bit_information of gate_oai_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_2x2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2x2 : function is 1; - attribute pin_bit_information of oai_2x2x2x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - -- ============================================================= - -- 3 input Port AO/OA Gates - -- ============================================================= - -- Vectored primitive input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function gate_ao_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_3x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x1 : function is 1; - attribute pin_bit_information of gate_ao_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_3x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x1 : function is 1; - attribute pin_bit_information of ao_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_3x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x1 : function is 1; - attribute pin_bit_information of gate_aoi_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_3x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x1 : function is 1; - attribute pin_bit_information of aoi_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_3x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x1 : function is 1; - attribute pin_bit_information of gate_oa_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_3x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x1 : function is 1; - attribute pin_bit_information of oa_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_3x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x1 : function is 1; - attribute pin_bit_information of gate_oai_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_3x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x1 : function is 1; - attribute pin_bit_information of oai_3x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_3x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x2 : function is 1; - attribute pin_bit_information of gate_ao_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_3x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x2 : function is 1; - attribute pin_bit_information of ao_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_3x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x2 : function is 1; - attribute pin_bit_information of gate_aoi_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_3x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x2 : function is 1; - attribute pin_bit_information of aoi_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_3x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x2 : function is 1; - attribute pin_bit_information of gate_oa_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_3x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x2 : function is 1; - attribute pin_bit_information of oa_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_3x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x2 : function is 1; - attribute pin_bit_information of gate_oai_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_3x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x2 : function is 1; - attribute pin_bit_information of oai_3x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_3x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x3 : function is 1; - attribute pin_bit_information of gate_ao_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_3x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x3 : function is 1; - attribute pin_bit_information of ao_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_3x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x3 : function is 1; - attribute pin_bit_information of gate_aoi_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_3x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x3 : function is 1; - attribute pin_bit_information of aoi_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_3x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x3 : function is 1; - attribute pin_bit_information of gate_oa_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_3x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x3 : function is 1; - attribute pin_bit_information of oa_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_3x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x3 : function is 1; - attribute pin_bit_information of gate_oai_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_3x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x3 : function is 1; - attribute pin_bit_information of oai_3x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - -- ============================================================= - -- 4 input Port AO/OA Gates - -- ============================================================= - -- Vectored primitive input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function gate_ao_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_4x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x1 : function is 1; - attribute pin_bit_information of gate_ao_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_4x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x1 : function is 1; - attribute pin_bit_information of ao_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_4x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x1 : function is 1; - attribute pin_bit_information of gate_aoi_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_4x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x1 : function is 1; - attribute pin_bit_information of aoi_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_4x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x1 : function is 1; - attribute pin_bit_information of gate_oa_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_4x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x1 : function is 1; - attribute pin_bit_information of oa_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_4x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x1 : function is 1; - attribute pin_bit_information of gate_oai_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_4x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x1 : function is 1; - attribute pin_bit_information of oai_4x1 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_4x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x2 : function is 1; - attribute pin_bit_information of gate_ao_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_4x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x2 : function is 1; - attribute pin_bit_information of ao_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_4x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x2 : function is 1; - attribute pin_bit_information of gate_aoi_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_4x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x2 : function is 1; - attribute pin_bit_information of aoi_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_4x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x2 : function is 1; - attribute pin_bit_information of gate_oa_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_4x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x2 : function is 1; - attribute pin_bit_information of oa_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_4x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x2 : function is 1; - attribute pin_bit_information of gate_oai_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_4x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x2 : function is 1; - attribute pin_bit_information of oai_4x2 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_4x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x3 : function is 1; - attribute pin_bit_information of gate_ao_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_4x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x3 : function is 1; - attribute pin_bit_information of ao_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_4x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x3 : function is 1; - attribute pin_bit_information of gate_aoi_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_4x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x3 : function is 1; - attribute pin_bit_information of aoi_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_4x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x3 : function is 1; - attribute pin_bit_information of gate_oa_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_4x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x3 : function is 1; - attribute pin_bit_information of oa_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_4x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x3 : function is 1; - attribute pin_bit_information of gate_oai_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_4x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x3 : function is 1; - attribute pin_bit_information of oai_4x3 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_ao_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_ao_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_ao_4x4 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x4 : function is 1; - attribute pin_bit_information of gate_ao_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function ao_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function ao_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of ao_4x4 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x4 : function is 1; - attribute pin_bit_information of ao_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_aoi_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_aoi_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_aoi_4x4 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x4 : function is 1; - attribute pin_bit_information of gate_aoi_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function aoi_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function aoi_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of aoi_4x4 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x4 : function is 1; - attribute pin_bit_information of aoi_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oa_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oa_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oa_4x4 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x4 : function is 1; - attribute pin_bit_information of gate_oa_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oa_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oa_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oa_4x4 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x4 : function is 1; - attribute pin_bit_information of oa_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function gate_oai_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function gate_oai_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_oai_4x4 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x4 : function is 1; - attribute pin_bit_information of gate_oai_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function oai_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - function oai_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of oai_4x4 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x4 : function is 1; - attribute pin_bit_information of oai_4x4 : function is - (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - -end std_ulogic_ao_support; - -package body std_ulogic_ao_support is - -- ============================================================= - -- 2 input port ao/oa gates - -- ============================================================= - function gate_ao_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or gate1 ; - return result ; - end gate_ao_2x1 ; - - function gate_ao_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) ; - return result ; - end gate_ao_2x1 ; - - function ao_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or in1a; - return result ; - end ao_2x1 ; - - function ao_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or in1a; - return result ; - end ao_2x1 ; - - function gate_aoi_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ( ( gate0 and in0 ) or gate1 ); - return result ; - end gate_aoi_2x1 ; - - function gate_aoi_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) ); - return result ; - end gate_aoi_2x1 ; - - function aoi_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or in1a ) ; - return result ; - end aoi_2x1 ; - - function aoi_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or in1a ) ; - return result ; - end aoi_2x1 ; - - function gate_oa_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and gate1 ; - return result ; - end gate_oa_2x1 ; - - function gate_oa_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) ; - return result ; - end gate_oa_2x1 ; - - function oa_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and in1a ; - return result ; - end oa_2x1 ; - - function oa_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and in1a ; - return result ; - end oa_2x1 ; - - function gate_oai_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and gate1 ) ; - return result ; - end gate_oai_2x1 ; - - function gate_oai_2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) ) ; - return result ; - end gate_oai_2x1 ; - - function oai_2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and in1a ) ; - return result ; - end oai_2x1 ; - - function oai_2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and in1a ) ; - return result ; - end oai_2x1 ; - - function gate_ao_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( ( gate0 and in0 ) or ( gate1 and in1 ) ) ; - return result ; - end gate_ao_2x2 ; - - function gate_ao_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) ; - return result ; - end gate_ao_2x2 ; - - function ao_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ((in0a and in0b) or (in1a and in1b)); - return result ; - end ao_2x2 ; - - function ao_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ((in0a and in0b) or (in1a and in1b)); - return result ; - end ao_2x2 ; - - function gate_aoi_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((gate0 and in0) or (gate1 and in1)); - return result ; - end gate_aoi_2x2 ; - - function gate_aoi_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in0'length-1 => gate1 ) and in1 ) ); - return result ; - end gate_aoi_2x2 ; - - function aoi_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((in0a and in0b) or (in1a and in1b)); - return result ; - end aoi_2x2 ; - - function aoi_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not ( ( in0a and in0b ) or ( in1a and in1b ) ); - return result ; - end aoi_2x2 ; - - function gate_oa_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ((gate0 or in0) and (gate1 or in1)); - return result ; - end gate_oa_2x2 ; - - function gate_oa_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ); - return result ; - end gate_oa_2x2 ; - - function oa_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ((in0a or in0b) and (in1a or in1b)); - return result ; - end oa_2x2 ; - - function oa_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( in0a or in0b ) and ( in1a or in1b ) ); - return result ; - end oa_2x2 ; - - function gate_oai_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((gate0 or in0) and (gate1 or in1)); - return result ; - end gate_oai_2x2 ; - - function gate_oai_2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) ); - return result ; - end gate_oai_2x2 ; - - function oai_2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((in0a or in0b) and (in1a or in1b)); - return result ; - end oai_2x2 ; - - function oai_2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not ( ( in0a or in0b ) and ( in1a or in1b ) ); - return result ; - end oai_2x2 ; - - -- ============================================================= - -- 3x2 input Port AO/OA Gates - -- ============================================================= - - function gate_ao_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 ) or - ( gate2 ); - return result ; - end gate_ao_2x1x1 ; - - function gate_ao_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) or - ( 0 to in0'length-1 => gate2 ) ; - return result ; - end gate_ao_2x1x1 ; - - function ao_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or ( in1a ) or ( in2a ) ; - return result ; - end ao_2x1x1 ; - - function ao_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a ) or - ( in2a ) ; - return result ; - end ao_2x1x1 ; - - function gate_aoi_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ( ( gate0 and in0 ) or - ( gate1 ) or - ( gate2 ) ); - return result ; - end gate_aoi_2x1x1 ; - - function gate_aoi_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) or - ( 0 to in0'length-1 => gate2 ) ); - return result ; - end gate_aoi_2x1x1 ; - - function aoi_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((in0a and in0b) or (in1a) or (in2a)); - return result ; - end aoi_2x1x1 ; - - function aoi_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not ( ( in0a and in0b ) or - ( in1a ) or - ( in2a ) ); - return result ; - end aoi_2x1x1 ; - - function gate_oa_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 ) and - ( gate2 ); - return result ; - end gate_oa_2x1x1 ; - - function gate_oa_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) and - ( 0 to in0'length-1 => gate2 ) ; - return result ; - end gate_oa_2x1x1 ; - - function oa_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( ( in0a or in0b ) and ( in1a ) and ( in2a ) ); - return result ; - end oa_2x1x1 ; - - function oa_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0a'length-1); - begin - result := ( ( in0a or in0b ) and - ( in1a ) and - ( in2a ) ); - return result ; - end oa_2x1x1 ; - - function gate_oai_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ( ( gate0 or in0 ) and - ( gate1 ) and - ( gate2 ) ) ; - return result ; - end gate_oai_2x1x1 ; - - function gate_oai_2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) and - ( 0 to in0'length-1 => gate2 ) ) ; - return result ; - end gate_oai_2x1x1 ; - - function oai_2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not ((in0a or in0b) and (in1a) and (in2a)); - return result ; - end oai_2x1x1 ; - - function oai_2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not ((in0a or in0b) and - (in1a) and - (in2a)); - return result ; - end oai_2x1x1 ; - - function gate_ao_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 ) ; - return result ; - end gate_ao_2x2x1 ; - - function gate_ao_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( 0 to in0'length-1 => gate2 ) ; - return result ; - end gate_ao_2x2x1 ; - - function ao_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) ; - return result ; - end ao_2x2x1 ; - - function ao_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ((in0a and in0b) or - (in1a and in1b) or - (in2a)); - return result ; - end ao_2x2x1 ; - - function gate_aoi_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 ) ) ; - return result ; - end gate_aoi_2x2x1 ; - - function gate_aoi_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( 0 to in0'length-1 => gate2 ) ) ; - return result ; - end gate_aoi_2x2x1 ; - - function aoi_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) ) ; - return result ; - end aoi_2x2x1 ; - - function aoi_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) ) ; - return result ; - end aoi_2x2x1 ; - - function gate_oa_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 ) ; - return result ; - end gate_oa_2x2x1 ; - - function gate_oa_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( 0 to in0'length-1 => gate2 ) ; - return result ; - end gate_oa_2x2x1 ; - - function oa_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) ; - return result ; - end oa_2x2x1 ; - - function oa_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) ; - return result ; - end oa_2x2x1 ; - - function gate_oai_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 ) ); - return result ; - end gate_oai_2x2x1 ; - - function gate_oai_2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( 0 to in0'length-1 => gate2 ) ) ; - return result ; - end gate_oai_2x2x1 ; - - function oai_2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) ); - return result ; - end oai_2x2x1 ; - - function oai_2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) ); - return result ; - end oai_2x2x1 ; - - function gate_ao_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) ; - return result ; - end gate_ao_2x2x2 ; - - function gate_ao_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) ; - return result ; - end gate_ao_2x2x2 ; - - function ao_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) ; - return result ; - end ao_2x2x2 ; - - function ao_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) ; - return result ; - end ao_2x2x2 ; - - function gate_aoi_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) ); - return result ; - end gate_aoi_2x2x2 ; - - function gate_aoi_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) ) ; - return result ; - end gate_aoi_2x2x2 ; - - function aoi_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) ); - return result ; - end aoi_2x2x2 ; - - function aoi_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) ); - return result ; - end aoi_2x2x2 ; - - function gate_oa_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) ; - return result ; - end gate_oa_2x2x2 ; - - function gate_oa_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) ; - return result ; - end gate_oa_2x2x2 ; - - function oa_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) ; - return result ; - end oa_2x2x2 ; - - function oa_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) ; - return result ; - end oa_2x2x2 ; - - function gate_oai_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) ) ; - return result ; - end gate_oai_2x2x2 ; - - function gate_oai_2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) ) ; - return result ; - end gate_oai_2x2x2 ; - - function oai_2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) ) ; - return result ; - end oai_2x2x2 ; - - function oai_2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) ) ; - return result ; - end oai_2x2x2 ; - - -- ============================================================= - -- 4x2 input Port AO/OA Gates - -- ============================================================= - - function gate_ao_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 ) or - ( gate2 ) or - ( gate3 ) ; - return result ; - end gate_ao_2x1x1x1 ; - - function gate_ao_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) or - ( 0 to in0'length-1 => gate2 ) or - ( 0 to in0'length-1 => gate3 ) ; - return result ; - end gate_ao_2x1x1x1 ; - - function ao_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a ) or - ( in2a ) or - ( in3a ) ; - return result ; - end ao_2x1x1x1 ; - - function ao_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a ) or - ( in2a ) or - ( in3a ) ; - return result ; - end ao_2x1x1x1 ; - - function gate_aoi_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 ) or - ( gate2 ) or - ( gate3 ) ) ; - return result ; - end gate_aoi_2x1x1x1 ; - - function gate_aoi_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( 0 to in0'length-1 => gate1 ) or - ( 0 to in0'length-1 => gate2 ) or - ( 0 to in0'length-1 => gate3 ) ) ; - return result ; - end gate_aoi_2x1x1x1 ; - - function aoi_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a ) or - ( in2a ) or - ( in3a ) ) ; - return result ; - end aoi_2x1x1x1 ; - - function aoi_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a ) or - ( in2a ) or - ( in3a ) ) ; - return result ; - end aoi_2x1x1x1 ; - - function gate_oa_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 ) and - ( gate2 ) and - ( gate3 ); - return result ; - end gate_oa_2x1x1x1 ; - - function gate_oa_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) and - ( 0 to in0'length-1 => gate2 ) and - ( 0 to in0'length-1 => gate3 ); - return result ; - end gate_oa_2x1x1x1 ; - - function oa_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a ) and - ( in2a ) and - ( in3a ) ; - return result ; - end oa_2x1x1x1 ; - - function oa_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a ) and - ( in2a ) and - ( in3a ) ; - return result ; - end oa_2x1x1x1 ; - - function gate_oai_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 ) and - ( gate2 ) and - ( gate3 ) ) ; - return result ; - end gate_oai_2x1x1x1 ; - - function gate_oai_2x1x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( 0 to in0'length-1 => gate1 ) and - ( 0 to in0'length-1 => gate2 ) and - ( 0 to in0'length-1 => gate3 ) ) ; - return result ; - end gate_oai_2x1x1x1 ; - - function oai_2x1x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a ) and - ( in2a ) and - ( in3a ) ) ; - return result ; - end oai_2x1x1x1 ; - - function oai_2x1x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a ) and - ( in2a ) and - ( in3a ) ) ; - return result ; - end oai_2x1x1x1 ; - - function gate_ao_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 ) or - ( gate3 ) ; - return result ; - end gate_ao_2x2x1x1 ; - - function gate_ao_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( 0 to in0'length-1 => gate2 ) or - ( 0 to in0'length-1 => gate3 ) ; - return result ; - end gate_ao_2x2x1x1 ; - - function ao_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) or - ( in3a ) ; - return result ; - end ao_2x2x1x1 ; - - function ao_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) or - ( in3a ) ; - return result ; - end ao_2x2x1x1 ; - - function gate_aoi_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 ) or - ( gate3 ) ) ; - return result ; - end gate_aoi_2x2x1x1 ; - - function gate_aoi_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( 0 to in0'length-1 => gate2 ) or - ( 0 to in0'length-1 => gate3 ) ) ; - return result ; - end gate_aoi_2x2x1x1 ; - - function aoi_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) or - ( in3a ) ) ; - return result ; - end aoi_2x2x1x1 ; - - function aoi_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a ) or - ( in3a ) ) ; - return result ; - end aoi_2x2x1x1 ; - - function gate_oa_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 ) and - ( gate3 ) ; - return result ; - end gate_oa_2x2x1x1 ; - - function gate_oa_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( 0 to in0'length-1 => gate2 ) and - ( 0 to in0'length-1 => gate3 ) ; - return result ; - end gate_oa_2x2x1x1 ; - - function oa_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) and - ( in3a ) ; - return result ; - end oa_2x2x1x1 ; - - function oa_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) and - ( in3a ) ; - return result ; - end oa_2x2x1x1 ; - - function gate_oai_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 ) and - ( gate3 ) ) ; - return result ; - end gate_oai_2x2x1x1 ; - - function gate_oai_2x2x1x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( 0 to in0'length-1 => gate2 ) and - ( 0 to in0'length-1 => gate3 ) ) ; - return result ; - end gate_oai_2x2x1x1 ; - - function oai_2x2x1x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) and - ( in3a ) ) ; - return result ; - end oai_2x2x1x1 ; - - function oai_2x2x1x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a ) and - ( in3a ) ) ; - return result ; - end oai_2x2x1x1 ; - - function gate_ao_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 ) ; - return result ; - end gate_ao_2x2x2x1 ; - - function gate_ao_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( 0 to in0'length-1 => gate3 ) ; - return result ; - end gate_ao_2x2x2x1 ; - - function ao_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a ) ; - return result ; - end ao_2x2x2x1 ; - - function ao_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a ) ; - return result ; - end ao_2x2x2x1 ; - - function gate_aoi_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 ) ); - return result ; - end gate_aoi_2x2x2x1 ; - - function gate_aoi_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( 0 to in0'length-1 => gate3 ) ); - return result ; - end gate_aoi_2x2x2x1 ; - - function aoi_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a ) ) ; - return result ; - end aoi_2x2x2x1 ; - - function aoi_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a ) ) ; - return result ; - end aoi_2x2x2x1 ; - - function gate_oa_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) and - ( gate3 ) ; - return result ; - end gate_oa_2x2x2x1 ; - - function gate_oa_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) and - ( 0 to in0'length-1 => gate3 ) ; - return result ; - end gate_oa_2x2x2x1 ; - - function oa_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a ) ; - return result ; - end oa_2x2x2x1 ; - - function oa_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a ) ; - return result ; - end oa_2x2x2x1 ; - - function gate_oai_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) and - ( gate3 ) ) ; - return result ; - end gate_oai_2x2x2x1 ; - - function gate_oai_2x2x2x1 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) and - ( 0 to in0'length-1 => gate3 ) ) ; - return result ; - end gate_oai_2x2x2x1 ; - - function oai_2x2x2x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a ) ) ; - return result ; - end oai_2x2x2x1 ; - - function oai_2x2x2x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a ) ) ; - return result ; - end oai_2x2x2x1 ; - - function gate_ao_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ) ; - return result ; - end gate_ao_2x2x2x2 ; - - function gate_ao_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; - return result ; - end gate_ao_2x2x2x2 ; - - function ao_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a and in3b ) ; - return result ; - end ao_2x2x2x2 ; - - function ao_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a and in3b ) ; - return result ; - end ao_2x2x2x2 ; - - function gate_aoi_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ) ) ; - return result ; - end gate_aoi_2x2x2x2 ; - - function gate_aoi_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of BLOCK_DATA : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; - return result ; - end gate_aoi_2x2x2x2 ; - - function aoi_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a and in3b ) ) ; - return result ; - end aoi_2x2x2x2 ; - - function aoi_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b ) or - ( in1a and in1b ) or - ( in2a and in2b ) or - ( in3a and in3b ) ) ; - return result ; - end aoi_2x2x2x2 ; - - function gate_oa_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) and - ( gate3 or in3 ) ; - return result ; - end gate_oa_2x2x2x2 ; - - function gate_oa_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) and - ( ( 0 to in3'length-1 => gate3 ) or in3 ) ; - return result ; - end gate_oa_2x2x2x2 ; - - function oa_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a or in3b ) ; - return result ; - end oa_2x2x2x2 ; - - function oa_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a or in3b ) ; - return result ; - end oa_2x2x2x2 ; - - function gate_oai_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0 ) and - ( gate1 or in1 ) and - ( gate2 or in2 ) and - ( gate3 or in3 ) ) ; - return result ; - end gate_oai_2x2x2x2 ; - - function gate_oai_2x2x2x2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and - ( ( 0 to in1'length-1 => gate1 ) or in1 ) and - ( ( 0 to in2'length-1 => gate2 ) or in2 ) and - ( ( 0 to in3'length-1 => gate3 ) or in3 ) ) ; - return result ; - end gate_oai_2x2x2x2 ; - - function oai_2x2x2x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in2a : std_ulogic ; - in2b : std_ulogic ; - in3a : std_ulogic ; - in3b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a or in3b ) ) ; - return result ; - end oai_2x2x2x2 ; - - function oai_2x2x2x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in2a : std_ulogic_vector ; - in2b : std_ulogic_vector ; - in3a : std_ulogic_vector ; - in3b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b ) and - ( in1a or in1b ) and - ( in2a or in2b ) and - ( in3a or in3b ) ) ; - return result ; - end oai_2x2x2x2 ; - - -- ============================================================= - -- 3 input Port AO/OA Gates - -- ============================================================= - - function gate_ao_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b) or - ( gate1 ) ; - return result ; - end gate_ao_3x1 ; - - function gate_ao_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or - ( 0 to in0a'length-1 => gate1 ) ; - return result ; - end gate_ao_3x1 ; - - function ao_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c ) or - ( in1a ) ; - return result ; - end ao_3x1 ; - - function ao_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector( 0 to in0a'length-1 ) ; - begin - result := ( in0a and in0b and in0c ) or - ( in1a ) ; - return result ; - end ao_3x1 ; - - function gate_aoi_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b) or - ( gate1 ) ) ; - return result ; - end gate_aoi_3x1 ; - - function gate_aoi_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or - ( 0 to in0a'length-1 => gate1 ) ) ; - return result ; - end gate_aoi_3x1 ; - - function aoi_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a ) ); - return result ; - end aoi_3x1 ; - - function aoi_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a ) ); - return result ; - end aoi_3x1 ; - - function gate_oa_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b ) and - ( gate1 ) ; - return result ; - end gate_oa_3x1 ; - - function gate_oa_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( 0 to in0a'length-1 => gate1 ) ; - return result ; - end gate_oa_3x1 ; - - function oa_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c ) and - ( in1a ) ; - return result ; - end oa_3x1 ; - - function oa_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c ) and - ( in1a ) ; - return result ; - end oa_3x1 ; - - function gate_oai_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b ) and - ( gate1 ) ) ; - return result ; - end gate_oai_3x1 ; - - function gate_oai_3x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( 0 to in0a'length-1 => gate1 ) ) ; - return result ; - end gate_oai_3x1 ; - - function oai_3x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a ) ); - return result ; - end oai_3x1 ; - - function oai_3x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a ) ); - return result ; - end oai_3x1 ; - - function gate_ao_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b ) or - ( gate1 and in1a ) ; - return result ; - end gate_ao_3x2 ; - - function gate_ao_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; - return result ; - end gate_ao_3x2 ; - - function ao_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c ) or - ( in1a and in1b ) ; - return result ; - end ao_3x2 ; - - function ao_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c ) or - ( in1a and in1b ) ; - return result ; - end ao_3x2 ; - - function gate_aoi_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b ) or - ( gate1 and in1a ) ) ; - return result ; - end gate_aoi_3x2 ; - - function gate_aoi_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; - return result ; - end gate_aoi_3x2 ; - - function aoi_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a and in1b ) ) ; - return result ; - end aoi_3x2 ; - - function aoi_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a and in1b ) ) ; - return result ; - end aoi_3x2 ; - - function gate_oa_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b ) and - ( gate1 or in1a ) ; - return result ; - end gate_oa_3x2 ; - - function gate_oa_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; - return result ; - end gate_oa_3x2 ; - - function oa_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c ) and - ( in1a or in1b ) ; - return result ; - end oa_3x2 ; - - function oa_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c ) and - ( in1a or in1b ) ; - return result ; - end oa_3x2 ; - - function gate_oai_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b ) and - ( gate1 or in1a ) ); - return result ; - end gate_oai_3x2 ; - - function gate_oai_3x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); - return result ; - end gate_oai_3x2 ; - - function oai_3x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a or in1b ) ); - return result ; - end oai_3x2 ; - - function oai_3x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a or in1b ) ); - return result ; - end oai_3x2 ; - - function gate_ao_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b ) or - ( gate1 and in1a and in1b ) ; - return result ; - end gate_ao_3x3 ; - - function gate_ao_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; - return result ; - end gate_ao_3x3 ; - - function ao_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c ) or - ( in1a and in1b and in1c ) ; - return result ; - end ao_3x3 ; - - function ao_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c ) or - ( in1a and in1b and in1c ) ; - return result ; - end ao_3x3 ; - - function gate_aoi_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b ) or - ( gate1 and in1a and in1b ) ) ; - return result ; - end gate_aoi_3x3 ; - - function gate_aoi_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length => gate0 ) and in0a and in0b ) or - ( ( 0 to in1a'length => gate1 ) and in1a and in1b ) ) ; - return result ; - end gate_aoi_3x3 ; - - function aoi_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a and in1b and in1c ) ); - return result ; - end aoi_3x3 ; - - function aoi_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c ) or - ( in1a and in1b and in1c ) ); - return result ; - end aoi_3x3 ; - - function gate_oa_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b ) and - ( gate1 or in1a or in1b ) ; - return result ; - end gate_oa_3x3 ; - - function gate_oa_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; - return result ; - end gate_oa_3x3 ; - - function oa_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c ) and - ( in1a or in1b or in1c ) ; - return result ; - end oa_3x3 ; - - function oa_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c ) and - ( in1a or in1b or in1c ) ; - return result ; - end oa_3x3 ; - - function gate_oai_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b ) and - ( gate1 or in1a or in1b ) ) ; - return result ; - end gate_oai_3x3 ; - - function gate_oai_3x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; - return result ; - end gate_oai_3x3 ; - - function oai_3x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a or in1b or in1c ) ) ; - return result ; - end oai_3x3 ; - - function oai_3x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c ) and - ( in1a or in1b or in1c ) ) ; - return result ; - end oai_3x3 ; - - -- ============================================================= - -- 4 input Port AO/OA Gates - -- ============================================================= - - function gate_ao_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b and in0c ) or - ( gate1 ) ; - return result ; - end gate_ao_4x1 ; - - function gate_ao_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( 0 to in0a'length-1 => gate1 ) ; - return result ; - end gate_ao_4x1 ; - - function ao_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a ) ; - return result ; - end ao_4x1 ; - - function ao_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a ) ; - return result ; - end ao_4x1 ; - - function gate_aoi_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b and in0c ) or - ( gate1 ) ); - return result ; - end gate_aoi_4x1 ; - - function gate_aoi_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( 0 to in0a'length-1 => gate1 ) ) ; - return result ; - end gate_aoi_4x1 ; - - function aoi_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a ) ) ; - return result ; - end aoi_4x1 ; - - function aoi_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a ) ) ; - return result ; - end aoi_4x1 ; - - function gate_oa_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b or in0c ) and - ( gate1 ) ; - return result ; - end gate_oa_4x1 ; - - function gate_oa_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( 0 to in0a'length-1 => gate1 ) ; - return result ; - end gate_oa_4x1 ; - - function oa_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a ) ; - return result ; - end oa_4x1 ; - - function oa_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a ) ; - return result ; - end oa_4x1 ; - - function gate_oai_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b or in0c ) and - ( gate1 ) ) ; - return result ; - end gate_oai_4x1 ; - - function gate_oai_4x1 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( 0 to in0a'length-1 => gate1 ) ) ; - return result ; - end gate_oai_4x1 ; - - function oai_4x1 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a ) ) ; - return result ; - end oai_4x1 ; - - function oai_4x1 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a ) ) ; - return result ; - end oai_4x1 ; - - function gate_ao_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a ) ; - return result ; - end gate_ao_4x2 ; - - function gate_ao_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; - return result ; - end gate_ao_4x2 ; - - function ao_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b ) ; - return result ; - end ao_4x2 ; - - function ao_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b ) ; - return result ; - end ao_4x2 ; - - function gate_aoi_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a ) ) ; - return result ; - end gate_aoi_4x2 ; - - function gate_aoi_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; - return result ; - end gate_aoi_4x2 ; - - function aoi_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b ) ) ; - return result ; - end aoi_4x2 ; - - function aoi_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b ) ) ; - return result ; - end aoi_4x2 ; - - function gate_oa_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a ) ; - return result ; - end gate_oa_4x2 ; - - function gate_oa_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; - return result ; - end gate_oa_4x2 ; - - function oa_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b ) ; - return result ; - end oa_4x2 ; - - function oa_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b ) ; - return result ; - end oa_4x2 ; - - function gate_oai_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a ) ); - return result ; - end gate_oai_4x2 ; - - function gate_oai_4x2 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); - return result ; - end gate_oai_4x2 ; - - function oai_4x2 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b ) ) ; - return result ; - end oai_4x2 ; - - function oai_4x2 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b ) ) ; - return result ; - end oai_4x2 ; - - function gate_ao_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a and in1b ) ; - return result ; - end gate_ao_4x3 ; - - function gate_ao_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; - return result ; - end gate_ao_4x3 ; - - function ao_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c ) ; - return result ; - end ao_4x3 ; - - function ao_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c ) ; - return result ; - end ao_4x3 ; - - function gate_aoi_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a and in1b ) ) ; - return result ; - end gate_aoi_4x3 ; - - function gate_aoi_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ) ; - return result ; - end gate_aoi_4x3 ; - - function aoi_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c ) ) ; - return result ; - end aoi_4x3 ; - - function aoi_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c ) ) ; - return result ; - end aoi_4x3 ; - - function gate_oa_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a or in1b ) ; - return result ; - end gate_oa_4x3 ; - - function gate_oa_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; - return result ; - end gate_oa_4x3 ; - - function oa_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c ) ; - return result ; - end oa_4x3 ; - - function oa_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c ) ; - return result ; - end oa_4x3 ; - - function gate_oai_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a or in1b ) ) ; - return result ; - end gate_oai_4x3 ; - - function gate_oai_4x3 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; - return result ; - end gate_oai_4x3 ; - - function oai_4x3 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c ) ) ; - return result ; - end oai_4x3 ; - - function oai_4x3 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c ) ) ; - return result ; - end oai_4x3 ; - - function gate_ao_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a and in1b and in1c ) ; - return result ; - end gate_ao_4x4 ; - - function gate_ao_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ; - return result ; - end gate_ao_4x4 ; - - function ao_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c and in1d ) ; - return result ; - end ao_4x4 ; - - function ao_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c and in1d ) ; - return result ; - end ao_4x4 ; - - function gate_aoi_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0a and in0b and in0c ) or - ( gate1 and in1a and in1b and in1c ) ) ; - return result ; - end gate_aoi_4x4 ; - - function gate_aoi_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or - ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ) ; - return result ; - end gate_aoi_4x4 ; - - function aoi_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c and in1d ) ) ; - return result ; - end aoi_4x4 ; - - function aoi_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a and in0b and in0c and in0d ) or - ( in1a and in1b and in1c and in1d ) ) ; - return result ; - end aoi_4x4 ; - - function gate_oa_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a or in1b or in1c ) ; - return result ; - end gate_oa_4x4 ; - - function gate_oa_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ; - return result ; - end gate_oa_4x4 ; - - function oa_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c or in1d ) ; - return result ; - end oa_4x4 ; - - function oa_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c or in1d ) ; - return result ; - end oa_4x4 ; - - function gate_oai_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - gate1 : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 or in0a or in0b or in0c ) and - ( gate1 or in1a or in1b or in1c ) ) ; - return result ; - end gate_oai_4x4 ; - - function gate_oai_4x4 - (gate0 : std_ulogic ; - in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - gate1 : std_ulogic ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and - ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ) ; - return result ; - end gate_oai_4x4 ; - - function oai_4x4 - (in0a : std_ulogic ; - in0b : std_ulogic ; - in0c : std_ulogic ; - in0d : std_ulogic ; - in1a : std_ulogic ; - in1b : std_ulogic ; - in1c : std_ulogic ; - in1d : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c or in1d ) ) ; - return result ; - end oai_4x4 ; - - function oai_4x4 - (in0a : std_ulogic_vector ; - in0b : std_ulogic_vector ; - in0c : std_ulogic_vector ; - in0d : std_ulogic_vector ; - in1a : std_ulogic_vector ; - in1b : std_ulogic_vector ; - in1c : std_ulogic_vector ; - in1d : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0a'length-1); - begin - result := not( ( in0a or in0b or in0c or in0d ) and - ( in1a or in1b or in1c or in1d ) ) ; - return result ; - end oai_4x4 ; - -end std_ulogic_ao_support; - +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_ao_support is + -- ============================================================= + -- 2 input Port AO/OA Gates + -- ============================================================= + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1 : function is 1; + attribute pin_bit_information of ao_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1 : function is 1; + attribute pin_bit_information of aoi_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1 : function is 1; + attribute pin_bit_information of oa_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1 : function is 1; + attribute pin_bit_information of oai_2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2 : function is 1; + attribute pin_bit_information of ao_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2 : function is 1; + attribute pin_bit_information of aoi_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2 : function is 1; + attribute pin_bit_information of oa_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2 : function is 1; + attribute pin_bit_information of oai_2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1 : function is 1; + attribute pin_bit_information of ao_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1 : function is 1; + attribute pin_bit_information of aoi_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1 : function is 1; + attribute pin_bit_information of oa_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1 : function is 1; + attribute pin_bit_information of oai_2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1 : function is 1; + attribute pin_bit_information of ao_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1 : function is 1; + attribute pin_bit_information of aoi_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1 : function is 1; + attribute pin_bit_information of oa_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1 : function is 1; + attribute pin_bit_information of oai_2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2 : function is 1; + attribute pin_bit_information of ao_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2 : function is 1; + attribute pin_bit_information of aoi_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2 : function is 1; + attribute pin_bit_information of oa_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2 : function is 1; + attribute pin_bit_information of oai_2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 2x4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x1x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x1x1x1 : function is 1; + attribute pin_bit_information of ao_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x1x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x1x1x1 : function is 1; + attribute pin_bit_information of aoi_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x1x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x1x1x1 : function is 1; + attribute pin_bit_information of oa_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x1x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x1x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x1x1x1 : function is 1; + attribute pin_bit_information of oai_2x1x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x1x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x1x1 : function is 1; + attribute pin_bit_information of ao_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x1x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x1x1 : function is 1; + attribute pin_bit_information of aoi_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x1x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x1x1 : function is 1; + attribute pin_bit_information of oa_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x1x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x1x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x1x1 : function is 1; + attribute pin_bit_information of oai_2x2x1x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x1 : function is 1; + attribute pin_bit_information of ao_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x1 : function is 1; + attribute pin_bit_information of aoi_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x1 : function is 1; + attribute pin_bit_information of oa_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x1 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x1 : function is 1; + attribute pin_bit_information of oai_2x2x2x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_2x2x2x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_2x2x2x2 : function is 1; + attribute pin_bit_information of ao_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_2x2x2x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_2x2x2x2 : function is 1; + attribute pin_bit_information of aoi_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_2x2x2x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_2x2x2x2 : function is 1; + attribute pin_bit_information of oa_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_2x2x2x2 : function is 1; + attribute pin_bit_information of gate_oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_2x2x2x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_2x2x2x2 : function is 1; + attribute pin_bit_information of oai_2x2x2x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","C ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x1 : function is 1; + attribute pin_bit_information of gate_ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x1 : function is 1; + attribute pin_bit_information of ao_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x1 : function is 1; + attribute pin_bit_information of gate_aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x1 : function is 1; + attribute pin_bit_information of aoi_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x1 : function is 1; + attribute pin_bit_information of gate_oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x1 : function is 1; + attribute pin_bit_information of oa_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x1 : function is 1; + attribute pin_bit_information of gate_oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x1 : function is 1; + attribute pin_bit_information of oai_3x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x2 : function is 1; + attribute pin_bit_information of gate_ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x2 : function is 1; + attribute pin_bit_information of ao_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x2 : function is 1; + attribute pin_bit_information of gate_aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x2 : function is 1; + attribute pin_bit_information of aoi_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x2 : function is 1; + attribute pin_bit_information of gate_oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x2 : function is 1; + attribute pin_bit_information of oa_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x2 : function is 1; + attribute pin_bit_information of gate_oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x2 : function is 1; + attribute pin_bit_information of oai_3x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_3x3 : function is 1; + attribute pin_bit_information of gate_ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_3x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_3x3 : function is 1; + attribute pin_bit_information of ao_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_3x3 : function is 1; + attribute pin_bit_information of gate_aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_3x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_3x3 : function is 1; + attribute pin_bit_information of aoi_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_3x3 : function is 1; + attribute pin_bit_information of gate_oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_3x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_3x3 : function is 1; + attribute pin_bit_information of oa_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_3x3 : function is 1; + attribute pin_bit_information of gate_oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_3x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_3x3 : function is 1; + attribute pin_bit_information of oai_3x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + -- Vectored primitive input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x1 : function is 1; + attribute pin_bit_information of gate_ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x1 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x1 : function is 1; + attribute pin_bit_information of ao_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x1 : function is 1; + attribute pin_bit_information of gate_aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x1 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x1 : function is 1; + attribute pin_bit_information of aoi_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x1 : function is 1; + attribute pin_bit_information of gate_oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x1 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x1 : function is 1; + attribute pin_bit_information of oa_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x1 : function is 1; + attribute pin_bit_information of gate_oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x1 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x1 : function is 1; + attribute pin_bit_information of oai_4x1 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x2 : function is 1; + attribute pin_bit_information of gate_ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x2 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x2 : function is 1; + attribute pin_bit_information of ao_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x2 : function is 1; + attribute pin_bit_information of gate_aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x2 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x2 : function is 1; + attribute pin_bit_information of aoi_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x2 : function is 1; + attribute pin_bit_information of gate_oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x2 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x2 : function is 1; + attribute pin_bit_information of oa_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x2 : function is 1; + attribute pin_bit_information of gate_oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x2 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x2 : function is 1; + attribute pin_bit_information of oai_4x2 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x3 : function is 1; + attribute pin_bit_information of gate_ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x3 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x3 : function is 1; + attribute pin_bit_information of ao_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x3 : function is 1; + attribute pin_bit_information of gate_aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x3 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x3 : function is 1; + attribute pin_bit_information of aoi_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x3 : function is 1; + attribute pin_bit_information of gate_oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x3 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x3 : function is 1; + attribute pin_bit_information of oa_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x3 : function is 1; + attribute pin_bit_information of gate_oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x3 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x3 : function is 1; + attribute pin_bit_information of oai_4x3 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of gate_ao_4x4 : function is 1; + attribute pin_bit_information of gate_ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of ao_4x4 : function is "VHDL-AO" ; + attribute recursive_synthesis of ao_4x4 : function is 1; + attribute pin_bit_information of ao_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of gate_aoi_4x4 : function is 1; + attribute pin_bit_information of gate_aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of aoi_4x4 : function is "VHDL-AOI" ; + attribute recursive_synthesis of aoi_4x4 : function is 1; + attribute pin_bit_information of aoi_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of gate_oa_4x4 : function is 1; + attribute pin_bit_information of gate_oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oa_4x4 : function is "VHDL-OA" ; + attribute recursive_synthesis of oa_4x4 : function is 1; + attribute pin_bit_information of oa_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of gate_oai_4x4 : function is 1; + attribute pin_bit_information of gate_oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of oai_4x4 : function is "VHDL-OAI" ; + attribute recursive_synthesis of oai_4x4 : function is 1; + attribute pin_bit_information of oai_4x4 : function is + (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","A ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","B ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","B ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_ao_support; + +package body std_ulogic_ao_support is + -- ============================================================= + -- 2 input port ao/oa gates + -- ============================================================= + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or gate1 ; + return result ; + end gate_ao_2x1 ; + + function gate_ao_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function ao_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or in1a; + return result ; + end ao_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or gate1 ); + return result ; + end gate_aoi_2x1 ; + + function gate_aoi_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) ); + return result ; + end gate_aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function aoi_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or in1a ) ; + return result ; + end aoi_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and gate1 ; + return result ; + end gate_oa_2x1 ; + + function gate_oa_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ; + return result ; + end gate_oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function oa_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and in1a ; + return result ; + end oa_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and gate1 ) ; + return result ; + end gate_oai_2x1 ; + + function gate_oai_2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) ) ; + return result ; + end gate_oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function oai_2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and in1a ) ; + return result ; + end oai_2x1 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( gate0 and in0 ) or ( gate1 and in1 ) ) ; + return result ; + end gate_ao_2x2 ; + + function gate_ao_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ; + return result ; + end gate_ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function ao_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or (in1a and in1b)); + return result ; + end ao_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 and in0) or (gate1 and in1)); + return result ; + end gate_aoi_2x2 ; + + function gate_aoi_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in0'length-1 => gate1 ) and in1 ) ); + return result ; + end gate_aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a and in1b)); + return result ; + end aoi_2x2 ; + + function aoi_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or ( in1a and in1b ) ); + return result ; + end aoi_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oa_2x2 ; + + function gate_oa_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ); + return result ; + end gate_oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ((in0a or in0b) and (in1a or in1b)); + return result ; + end oa_2x2 ; + + function oa_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oa_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((gate0 or in0) and (gate1 or in1)); + return result ; + end gate_oai_2x2 ; + + function gate_oai_2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) ); + return result ; + end gate_oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a or in1b)); + return result ; + end oai_2x2 ; + + function oai_2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a or in0b ) and ( in1a or in1b ) ); + return result ; + end oai_2x2 ; + + -- ============================================================= + -- 3x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ); + return result ; + end gate_ao_2x1x1 ; + + function gate_ao_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or ( in1a ) or ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function ao_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ; + return result ; + end ao_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function gate_aoi_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) ); + return result ; + end gate_aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a and in0b) or (in1a) or (in2a)); + return result ; + end aoi_2x1x1 ; + + function aoi_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) ); + return result ; + end aoi_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ); + return result ; + end gate_oa_2x1x1 ; + + function gate_oa_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( ( in0a or in0b ) and ( in1a ) and ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function oa_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0a'length-1); + begin + result := ( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) ); + return result ; + end oa_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function gate_oai_2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not ( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not ((in0a or in0b) and (in1a) and (in2a)); + return result ; + end oai_2x1x1 ; + + function oai_2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not ((in0a or in0b) and + (in1a) and + (in2a)); + return result ; + end oai_2x1x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function gate_ao_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ; + return result ; + end ao_2x2x1 ; + + function ao_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ((in0a and in0b) or + (in1a and in1b) or + (in2a)); + return result ; + end ao_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function gate_aoi_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function aoi_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) ) ; + return result ; + end aoi_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function gate_oa_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ; + return result ; + end gate_oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function oa_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ; + return result ; + end oa_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) ); + return result ; + end gate_oai_2x2x1 ; + + function gate_oai_2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) ) ; + return result ; + end gate_oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function oai_2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) ); + return result ; + end oai_2x2x1 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function gate_ao_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ; + return result ; + end gate_ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function ao_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ; + return result ; + end ao_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ); + return result ; + end gate_aoi_2x2x2 ; + + function gate_aoi_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) ) ; + return result ; + end gate_aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function aoi_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) ); + return result ; + end aoi_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function gate_oa_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ; + return result ; + end gate_oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function oa_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ; + return result ; + end oa_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function gate_oai_2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) ) ; + return result ; + end gate_oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + function oai_2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) ) ; + return result ; + end oai_2x2x2 ; + + -- ============================================================= + -- 4x2 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function gate_ao_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function ao_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function gate_aoi_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( 0 to in0'length-1 => gate1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function aoi_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function gate_oa_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ); + return result ; + end gate_oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function oa_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function gate_oai_2x1x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( 0 to in0'length-1 => gate1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function oai_2x1x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x1x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function gate_ao_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function ao_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ; + return result ; + end ao_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 ) or + ( gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function gate_aoi_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( 0 to in0'length-1 => gate2 ) or + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function aoi_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function gate_oa_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function oa_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ; + return result ; + end oa_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function gate_oai_2x2x1x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( 0 to in0'length-1 => gate2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function oai_2x2x1x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a ) and + ( in3a ) ) ; + return result ; + end oai_2x2x1x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function gate_ao_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function ao_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ; + return result ; + end ao_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function gate_aoi_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( 0 to in0'length-1 => gate3 ) ); + return result ; + end gate_aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function aoi_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a ) ) ; + return result ; + end aoi_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function gate_oa_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ; + return result ; + end gate_oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function oa_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ; + return result ; + end oa_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function gate_oai_2x2x2x1 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( 0 to in0'length-1 => gate3 ) ) ; + return result ; + end gate_oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function oai_2x2x2x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a ) ) ; + return result ; + end oai_2x2x2x1 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function gate_ao_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end gate_ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function ao_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ; + return result ; + end ao_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function gate_aoi_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of BLOCK_DATA : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end gate_aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function aoi_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b ) or + ( in1a and in1b ) or + ( in2a and in2b ) or + ( in3a and in3b ) ) ; + return result ; + end aoi_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function gate_oa_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ; + return result ; + end gate_oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function oa_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ; + return result ; + end oa_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0 ) and + ( gate1 or in1 ) and + ( gate2 or in2 ) and + ( gate3 or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function gate_oai_2x2x2x2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) or in0 ) and + ( ( 0 to in1'length-1 => gate1 ) or in1 ) and + ( ( 0 to in2'length-1 => gate2 ) or in2 ) and + ( ( 0 to in3'length-1 => gate3 ) or in3 ) ) ; + return result ; + end gate_oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in2a : std_ulogic ; + in2b : std_ulogic ; + in3a : std_ulogic ; + in3b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + function oai_2x2x2x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in2a : std_ulogic_vector ; + in2b : std_ulogic_vector ; + in3a : std_ulogic_vector ; + in3b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b ) and + ( in1a or in1b ) and + ( in2a or in2b ) and + ( in3a or in3b ) ) ; + return result ; + end oai_2x2x2x2 ; + + -- ============================================================= + -- 3 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b) or + ( gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function gate_ao_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function ao_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector( 0 to in0a'length-1 ) ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a ) ; + return result ; + end ao_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b) or + ( gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function gate_aoi_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function aoi_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a ) ); + return result ; + end aoi_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function gate_oa_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function oa_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a ) ; + return result ; + end oa_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function gate_oai_3x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function oai_3x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a ) ); + return result ; + end oai_3x1 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function gate_ao_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function ao_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b ) ; + return result ; + end ao_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function gate_aoi_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function aoi_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function gate_oa_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function oa_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b ) ; + return result ; + end oa_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function gate_oai_3x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function oai_3x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b ) ); + return result ; + end oai_3x2 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function gate_ao_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function ao_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function gate_aoi_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length => gate0 ) and in0a and in0b ) or + ( ( 0 to in1a'length => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function aoi_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c ) or + ( in1a and in1b and in1c ) ); + return result ; + end aoi_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function gate_oa_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function oa_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function gate_oai_3x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + function oai_3x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_3x3 ; + + -- ============================================================= + -- 4 input Port AO/OA Gates + -- ============================================================= + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function gate_ao_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function ao_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a ) ; + return result ; + end ao_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 ) ); + return result ; + end gate_aoi_4x1 ; + + function gate_aoi_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function aoi_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a ) ) ; + return result ; + end aoi_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function gate_oa_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ; + return result ; + end gate_oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function oa_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a ) ; + return result ; + end oa_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function gate_oai_4x1 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( 0 to in0a'length-1 => gate1 ) ) ; + return result ; + end gate_oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function oai_4x1 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a ) ) ; + return result ; + end oai_4x1 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function gate_ao_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ; + return result ; + end gate_ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function ao_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ; + return result ; + end ao_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function gate_aoi_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a ) ) ; + return result ; + end gate_aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function aoi_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b ) ) ; + return result ; + end aoi_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function gate_oa_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ; + return result ; + end gate_oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function oa_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ; + return result ; + end oa_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function gate_oai_4x2 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a ) ); + return result ; + end gate_oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function oai_4x2 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b ) ) ; + return result ; + end oai_4x2 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function gate_ao_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ; + return result ; + end gate_ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function ao_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ; + return result ; + end ao_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function gate_aoi_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b ) ) ; + return result ; + end gate_aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function aoi_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c ) ) ; + return result ; + end aoi_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function gate_oa_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ; + return result ; + end gate_oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function oa_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ; + return result ; + end oa_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function gate_oai_4x3 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b ) ) ; + return result ; + end gate_oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function oai_4x3 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c ) ) ; + return result ; + end oai_4x3 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function gate_ao_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ; + return result ; + end gate_ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function ao_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ; + return result ; + end ao_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0a and in0b and in0c ) or + ( gate1 and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function gate_aoi_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) and in0a and in0b and in0c ) or + ( ( 0 to in1a'length-1 => gate1 ) and in1a and in1b and in1c ) ) ; + return result ; + end gate_aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function aoi_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a and in0b and in0c and in0d ) or + ( in1a and in1b and in1c and in1d ) ) ; + return result ; + end aoi_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function gate_oa_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ; + return result ; + end gate_oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function oa_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ; + return result ; + end oa_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + gate1 : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 or in0a or in0b or in0c ) and + ( gate1 or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function gate_oai_4x4 + (gate0 : std_ulogic ; + in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + gate1 : std_ulogic ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( ( 0 to in0a'length-1 => gate0 ) or in0a or in0b or in0c ) and + ( ( 0 to in1a'length-1 => gate1 ) or in1a or in1b or in1c ) ) ; + return result ; + end gate_oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic ; + in0b : std_ulogic ; + in0c : std_ulogic ; + in0d : std_ulogic ; + in1a : std_ulogic ; + in1b : std_ulogic ; + in1c : std_ulogic ; + in1d : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + + function oai_4x4 + (in0a : std_ulogic_vector ; + in0b : std_ulogic_vector ; + in0c : std_ulogic_vector ; + in0d : std_ulogic_vector ; + in1a : std_ulogic_vector ; + in1b : std_ulogic_vector ; + in1c : std_ulogic_vector ; + in1d : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0a'length-1); + begin + result := not( ( in0a or in0b or in0c or in0d ) and + ( in1a or in1b or in1c or in1d ) ) ; + return result ; + end oai_4x4 ; + +end std_ulogic_ao_support; + diff --git a/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl index c61991c..b002e1f 100644 --- a/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl @@ -1,5153 +1,5153 @@ ---*************************************************************************** --- Copyright 2020 International Business Machines --- --- Licensed under the Apache License, Version 2.0 (the “License”); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- http://www.apache.org/licenses/LICENSE-2.0 --- --- The patent license granted to you in Section 3 of the License, as applied --- to the “Work,” hereby includes implementations of the Work in physical form. --- --- Unless required by applicable law or agreed to in writing, the reference design --- distributed under the License is distributed on an “AS IS” BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ---*************************************************************************** -library ibm,ieee ; -use ieee.std_logic_1164.all ; -use ibm.std_ulogic_support.all; - -package std_ulogic_function_support is - -- Subtypes used for constraining return values in package - subtype std_return_2 is std_ulogic_vector(0 to 1); - subtype std_return_4 is std_ulogic_vector(0 to 3); - subtype std_return_8 is std_ulogic_vector(0 to 7); - subtype std_return_16 is std_ulogic_vector(0 to 15); - subtype std_return_32 is std_ulogic_vector(0 to 31); - subtype std_return_64 is std_ulogic_vector(0 to 63); - -- Test Case Evaluation Attributes - -- These attributes are used to control the generation of TCE tests - -- within the VHDL code. - -- Valid on PORT, SIGNAL and LABEL . - - -- Used to turn task model generation on or off. The attribute is applied - -- to a label. If on a block it turns off generation for the whole block. - -- If on a statement it is for that statement alone. - -- The string specifies which task statement alone. - -- attribute TCE_ON of : label is "T,LTP,STP,DLTP,LST,STC,ASSRT,CMBN | ALL" ; - attribute tce_on : string; - attribute tce_off : string; - attribute tce_last : string; - attribute tce_reset : string; - attribute tce_all_off : string; - attribute tce_ignore : string; - -- The string specifies which task statement alone. - attribute tce_assertion : string; - attribute tce_combination : string; - attribute tce_seqcond : string; - - -- Global Signals - -- Synopsys translate_off - signal audit_bit_dump : std_ulogic ; - signal assertion_summary : boolean ; - signal assertion_clock : std_ulogic ; - -- Synopsys translate_on - - -- Synopsys translate_off - component assertion - generic( counted : boolean := false; - Delay : natural := 0; - Duration : natural := 0); - port( - assert_in : in std_ulogic ; - sample : in std_ulogic ; - assert_out : out std_ulogic - ); - end component; - -- Synopsys translate_on - - -- Function Declarations and Attributes - -- Gate Function - function gate - (in0 : std_ulogic_vector; - cond : std_ulogic ) - return std_ulogic_vector ; - -- Synopsys translate_off - attribute btr_name of gate : function is "AND" ; - attribute recursive_synthesis of gate : function is 1 ; - attribute pin_bit_information of gate : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 3 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Dot Functions - function dot_and - (in0 : std_ulogic_vector ) - return std_ulogic ; - -- Synopsys translate_off - attribute btr_name of dot_and : function is "VHDL-DOTA" ; - attribute recursive_synthesis of dot_and : function is 1 ; - attribute pin_bit_information of dot_and : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function dot_or - (in0 : std_ulogic_vector ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of dot_or : function is "VHDL-DOTO" ; - attribute recursive_synthesis of dot_or : function is 1 ; - attribute pin_bit_information of dot_or : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function clock_tree_dot - (in0 : std_ulogic_vector ) - return std_ulogic ; - - function clock_tree_dot - (in0 : bit_vector ) - return bit ; - -- Synopsys translate_off - attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ; - attribute recursive_synthesis of clock_tree_dot : function is 1 ; - attribute pin_bit_information of clock_tree_dot : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - -- Generic Terminator - procedure terminator - (in0 : in std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ); - - procedure terminator - (in0 : in std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ); - -- synopsys translate_off - attribute btr_name of terminator : procedure is "TERMINATOR"; - attribute recursive_synthesis of terminator : procedure is 1 ; - attribute pin_bit_information of terminator : procedure is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," ")); - -- Synopsys translate_on - - -- Generic Delay - function delay - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - - function delay - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of delay : function is "IDENT" ; - attribute recursive_synthesis of delay : function is 1 ; - attribute block_data of delay : function is - "SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of delay : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Generic Buffer - function buff - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - - function buff - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of buff : function is "IDENT" ; - attribute recursive_synthesis of buff : function is 1 ; - attribute block_data of buff : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of buff : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Invert single bit - function invert - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- inverter vectored - function invert - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of invert : function is "NOT" ; - attribute recursive_synthesis of invert : function is 1 ; - attribute pin_bit_information of invert : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Compare single bit - function compare - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- compare multi-bit - function compare - (in0 : std_ulogic_vector; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of compare : function is "VHDL-COMPARE" ; - attribute recursive_synthesis of compare : function is 1 ; - attribute pin_bit_information of compare : function is - (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), - 2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","EQ ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - -- Parity Functions - -- General XOR_Tree Building Parity Function - function parity - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of parity : function is "XOR" ; - attribute recursive_synthesis of parity : function is 1 ; - attribute pin_bit_information of parity : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - function parity_map - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - - -- synopsys translate_off - attribute btr_name of parity_map : function is "XOR" ; - attribute recursive_synthesis of parity_map : function is 1 ; - attribute block_data of parity_map : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of parity_map : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - -- Parity gneration/checking functions - function parity_gen_odd - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - - -- synopsys translate_off - attribute btr_name of parity_gen_odd : function is "XNOR" ; - attribute recursive_synthesis of parity_gen_odd : function is 1; - attribute pin_bit_information of parity_gen_odd : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function parity_gen_even - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic ; - -- Synopsys translate_off - attribute btr_name of parity_gen_even : function is "XOR" ; - attribute recursive_synthesis of parity_gen_even : function is 1; - attribute pin_bit_information of parity_gen_even : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function is_parity_odd - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic ; - -- Synopsys translate_off - attribute btr_name of is_parity_odd : function is "XOR" ; - attribute recursive_synthesis of is_parity_odd : function is 1; - attribute pin_bit_information of is_parity_odd : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function is_parity_even - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic ; - -- Synopsys translate_off - attribute btr_name of is_parity_even : function is "XNOR" ; - attribute recursive_synthesis of is_parity_even : function is 1; - attribute pin_bit_information of is_parity_even : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - -- Full Adder - procedure full_add - (add_1 : in std_ulogic ; - add_2 : in std_ulogic ; - cryin : in std_ulogic ; - signal sum : out std_ulogic ; - signal carry : out std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ); - procedure full_add - (add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - cryin : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ; - signal carry : out std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ); - -- synopsys translate_off - attribute btr_name of full_add : procedure is "VHDL-FA"; - attribute recursive_synthesis of full_add : procedure is 1 ; - attribute pin_bit_information of full_add : procedure is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","CIN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","SUM ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","COUT ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," ")); - -- Synopsys translate_on - - -- Ripple Adder function - procedure ripple_adder - (add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ; - signal carry : out std_ulogic ) ; - - procedure ripple_adder - (add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ); - - -- Generic Tie Blocks - function tie_0 - -- synopsys translate_off - (btr : in string :="" - ;blkdata : in string :="" - ) - -- synopsys translate_on - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of tie_0 : function is "VHDL-TIDN" ; - attribute recursive_synthesis of tie_0 : function is 1 ; - attribute block_data of tie_0 : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of tie_0 : function is - (1 => (" ","PASS "," "," "), - 2 => (" ","PASS "," "," "), - 3 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function vector_tie_0 - (width : integer := 1 - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ; - attribute recursive_synthesis of vector_tie_0 : function is 1 ; - attribute block_data of vector_tie_0 : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of vector_tie_0 : function is - (1 => (" ","IGNR "," "," "), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function tie_1 - -- synopsys translate_off - (btr : in string :="" - ;blkdata : in string :="" - ) - -- synopsys translate_on - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of tie_1 : function is "VHDL-TIUP" ; - attribute recursive_synthesis of tie_1 : function is 1 ; - attribute block_data of tie_1 : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of tie_1 : function is - (1 => (" ","PASS "," "," "), - 2 => (" ","PASS "," "," "), - 3 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function vector_tie_1 - (width : integer := 1 - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ; - attribute recursive_synthesis of vector_tie_1 : function is 1 ; - attribute block_data of vector_tie_1 : function is - "LOGIC_STYLE=/DIRECT/" ; - attribute pin_bit_information of vector_tie_1 : function is - (1 => (" ","IGNR "," "," "), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function reverse - (arg: std_ulogic_vector) - return std_ulogic_vector ; - - function and_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of and_reduce : function is "AND" ; - attribute recursive_synthesis of and_reduce : function is 1 ; - attribute pin_bit_information of and_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function or_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of or_reduce : function is "OR" ; - attribute recursive_synthesis of or_reduce : function is 1 ; - attribute pin_bit_information of or_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function nand_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of nand_reduce : function is "NAND" ; - attribute recursive_synthesis of nand_reduce : function is 1 ; - attribute pin_bit_information of nand_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function nor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of nor_reduce : function is "NOR" ; - attribute recursive_synthesis of nor_reduce : function is 1 ; - attribute pin_bit_information of nor_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function xor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of xor_reduce : function is "XOR" ; - attribute recursive_synthesis of xor_reduce : function is 1 ; - attribute pin_bit_information of xor_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function xnor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- synopsys translate_off - attribute btr_name of xnor_reduce : function is "XNOR" ; - attribute recursive_synthesis of xnor_reduce : function is 1 ; - attribute pin_bit_information of xnor_reduce : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - -- Vector of gating bits gating a single vector of data bits - function gate_and - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - function gate_and - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_and - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_and : function is "AND" ; - attribute recursive_synthesis of gate_and : function is 1 ; - attribute pin_bit_information of gate_and : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function gate_or - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - function gate_or - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_or - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_or : function is "OR" ; - attribute recursive_synthesis of gate_or : function is 1 ; - attribute pin_bit_information of gate_or : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function gate_nand - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - function gate_nand - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_nand - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_nand : function is "NAND" ; - attribute recursive_synthesis of gate_nand : function is 1 ; - attribute pin_bit_information of gate_nand : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function gate_nor - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - function gate_nor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_nor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_nor : function is "NOR" ; - attribute recursive_synthesis of gate_nor : function is 1 ; - attribute pin_bit_information of gate_nor : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function gate_xor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_xor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_xor : function is "XOR" ; - attribute recursive_synthesis of gate_xor : function is 1 ; - attribute pin_bit_information of gate_xor : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function gate_xnor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic ; - function gate_xnor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of gate_xnor : function is "XNOR" ; - attribute recursive_synthesis of gate_xnor : function is 1 ; - attribute pin_bit_information of gate_xnor : function is - (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 2 input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function and_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_2 : function is "AND" ; - attribute recursive_synthesis of and_2 : function is 1 ; - attribute pin_bit_information of and_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_2 : function is "OR" ; - attribute recursive_synthesis of or_2 : function is 1 ; - attribute pin_bit_information of or_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_2 : function is "NAND" ; - attribute recursive_synthesis of nand_2 : function is 1 ; - attribute pin_bit_information of nand_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_2 : function is "NOR" ; - attribute recursive_synthesis of nor_2 : function is 1 ; - attribute pin_bit_information of nor_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function xor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function xor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of xor_2 : function is "XOR" ; - attribute recursive_synthesis of xor_2 : function is 1 ; - attribute pin_bit_information of xor_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function xnor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function xnor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of xnor_2 : function is "XNOR" ; - attribute recursive_synthesis of xnor_2 : function is 1 ; - attribute pin_bit_information of xnor_2 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","PASS "," "," "), - 4 => (" ","PASS "," "," "), - 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 3 input functions - -- Single bit case - function and_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - -- multiple vectors logically ed bitwise - function and_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_3 : function is "AND" ; - attribute recursive_synthesis of and_3 : function is 1 ; - attribute pin_bit_information of and_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_3 : function is "OR" ; - attribute recursive_synthesis of or_3 : function is 1 ; - attribute pin_bit_information of or_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_3 : function is "NAND" ; - attribute recursive_synthesis of nand_3 : function is 1 ; - attribute pin_bit_information of nand_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_3 : function is "NOR" ; - attribute recursive_synthesis of nor_3 : function is 1 ; - attribute pin_bit_information of nor_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function xor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function xor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of xor_3 : function is "XOR" ; - attribute recursive_synthesis of xor_3 : function is 1 ; - attribute pin_bit_information of xor_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function xnor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function xnor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of xnor_3 : function is "XNOR" ; - attribute recursive_synthesis of xnor_3 : function is 1 ; - attribute pin_bit_information of xnor_3 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 4 input functions - -- Single bit case - function and_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_4 : function is "AND" ; - attribute recursive_synthesis of and_4 : function is 1 ; - attribute pin_bit_information of and_4 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_4 : function is "OR" ; - attribute recursive_synthesis of or_4 : function is 1 ; - attribute pin_bit_information of or_4 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_4 : function is "NAND" ; - attribute recursive_synthesis of nand_4 : function is 1 ; - attribute pin_bit_information of nand_4 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_4 : function is "NOR" ; - attribute recursive_synthesis of nor_4 : function is 1 ; - attribute pin_bit_information of nor_4 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 5 input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function and_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_5 : function is "AND" ; - attribute recursive_synthesis of and_5 : function is 1 ; - attribute pin_bit_information of and_5 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_5 : function is "OR" ; - attribute recursive_synthesis of or_5 : function is 1 ; - attribute pin_bit_information of or_5 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_5 : function is "NAND" ; - attribute recursive_synthesis of nand_5 : function is 1 ; - attribute pin_bit_information of nand_5 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_5 : function is "NOR" ; - attribute recursive_synthesis of nor_5 : function is 1 ; - attribute pin_bit_information of nor_5 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 6 input functions - -- Single bit case - function and_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_6 : function is "AND" ; - attribute recursive_synthesis of and_6 : function is 1 ; - attribute pin_bit_information of and_6 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_6 : function is "OR" ; - attribute recursive_synthesis of or_6 : function is 1 ; - attribute pin_bit_information of or_6 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_6 : function is "NAND" ; - attribute recursive_synthesis of nand_6 : function is 1 ; - attribute pin_bit_information of nand_6 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_6 : function is "NOR" ; - attribute recursive_synthesis of nor_6 : function is 1 ; - attribute pin_bit_information of nor_6 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 7 input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function and_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_7 : function is "AND" ; - attribute recursive_synthesis of and_7 : function is 1 ; - attribute pin_bit_information of and_7 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_7 : function is "OR" ; - attribute recursive_synthesis of or_7 : function is 1 ; - attribute pin_bit_information of or_7 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_7 : function is "NAND" ; - attribute recursive_synthesis of nand_7 : function is 1 ; - attribute pin_bit_information of nand_7 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_7 : function is "NOR" ; - attribute recursive_synthesis of nor_7 : function is 1 ; - attribute pin_bit_information of nor_7 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","PASS "," "," "), - 9 => (" ","PASS "," "," "), - 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - -- Vectored primitive 8 input functions - -- Single bit case - -- Multiple vectors logically ed bitwise - function and_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function and_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of and_8 : function is "AND" ; - attribute recursive_synthesis of and_8 : function is 1 ; - attribute pin_bit_information of and_8 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function or_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function or_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of or_8 : function is "OR" ; - attribute recursive_synthesis of or_8 : function is 1 ; - attribute pin_bit_information of or_8 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nand_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nand_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nand_8 : function is "NAND" ; - attribute recursive_synthesis of nand_8 : function is 1 ; - attribute pin_bit_information of nand_8 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function nor_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic ; - function nor_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of nor_8 : function is "NOR" ; - attribute recursive_synthesis of nor_8 : function is 1 ; - attribute pin_bit_information of nor_8 : function is - (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- Synopsys translate_on - - function decode( code : std_ulogic_vector ) return std_ulogic_vector; - -- Synopsys translate_off - attribute functionality of decode: function is "DECODER"; - -- Synopsys translate_on - - function decode_2to4 - (code : std_ulogic_vector(0 to 1) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_4 ; - -- synopsys translate_off - attribute btr_name of decode_2to4 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_2to4 : function is 1 ; - attribute pin_bit_information of decode_2to4 : function is - (1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function decode_3to8 - (code : std_ulogic_vector(0 to 2) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_8 ; - -- synopsys translate_off - attribute btr_name of decode_3to8 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_3to8 : function is 1 ; - attribute pin_bit_information of decode_3to8 : function is - (1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function decode_4to16 - (code : std_ulogic_vector(0 to 3) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_16 ; - -- synopsys translate_off - attribute btr_name of decode_4to16 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_4to16 : function is 1 ; - attribute pin_bit_information of decode_4to16 : function is - (1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function decode_5to32 - (code : std_ulogic_vector(0 to 4) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_32 ; - -- synopsys translate_off - attribute btr_name of decode_5to32 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_5to32 : function is 1 ; - attribute pin_bit_information of decode_5to32 : function is - (1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); - -- Synopsys translate_on - - function decode_6to64 - (code : std_ulogic_vector(0 to 5) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_64 ; - -- synopsys translate_off - attribute btr_name of decode_6to64 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_6to64 : function is 1 ; - attribute pin_bit_information of decode_6to64 : function is - (1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","PASS "," "," "), - 3 => (" ","PASS "," "," "), - 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); - -- Synopsys translate_on - -end std_ulogic_function_support; - -package body std_ulogic_function_support is - -- Function Declarations and Attributes - -- Gate Function - function gate - (in0 : std_ulogic_vector; - cond : std_ulogic ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 and vec_length'(0 to in0'length-1 => cond) ; - return result; - end gate; - - -- This function everses the range direction. - function reverse (arg: std_ulogic_vector) - return std_ulogic_vector - is - variable d, result : std_ulogic_vector(0 to arg'length-1); - begin - d := arg; - for i in 0 to d'length-1 loop - result(result'right - i) := d(i); - end loop; - return result; - end reverse; - - -- Generic Terminator - procedure terminator - (in0 : in std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - begin - result := in0 ; - end terminator ; - - procedure terminator - (in0 : in std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1); - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 ; - end terminator ; - - -- Generic Delay - function delay - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - -- initialize variable attribute values - result := in0; - return result; - end delay ; - - function delay - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0; - return result; - end delay ; - - function buff - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0; - return result; - end buff ; - - function buff - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0; - return result; - end buff ; - --- inverter single bit - function invert - (in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not in0; - return result; - end invert ; - - -- inverter vectored - function invert - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not in0; - return result; - end invert ; - - -- Comparator - function compare - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 = in1 ; - return result; - end compare ; - --- comparator mult-bit - function compare - (in0 : std_ulogic_vector; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 = in1 ; - return result; - end compare ; - - -- General XOR_Tree Building Parity Function - function parity - (In0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return Std_uLogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return result; - end parity ; - - -- Specific Size Parity Block Map Function - function parity_map - (In0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return result; - end parity_map ; - --- Parity gneration/checking functions - function parity_gen_odd - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return not result; - end parity_gen_odd ; - - function parity_gen_even - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return result; - end parity_gen_even ; - - function is_parity_odd - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return result; - end is_parity_odd ; - - function is_parity_even - (in0 : std_ulogic_vector - -- Synopsys translate_off - ;btr : in String :="" - ;blkdata : in String :="" - -- Synopsys translate_on - ) - return std_ulogic - is - -- Synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- Synopsys translate_on - variable result : std_ulogic; - begin - result := in0(in0'low); - for i in in0'low+1 to in0'high loop - result := in0(i) xor result ; - end loop; - return not result; - end is_parity_even ; - - function and_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0(in0'left) ; - for i in in0'range loop - result := result and in0(i); - end loop; - result := result ; - return result; - end and_reduce ; - - function or_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0(in0'left) ; - for i in in0'range loop - result := result or in0(i); - end loop; - result := result ; - return result; - end or_reduce ; - - function nand_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0(in0'left) ; - for i in in0'range loop - result := result and in0(i); - end loop; - result := not result ; - return result; - end nand_reduce ; - - function nor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0(in0'left) ; - for i in in0'range loop - result := result or in0(i); - end loop; - result := not result ; - return result; - end nor_reduce ; - - function xor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := '0' ; - for i in in0'range loop - result := result xor in0(i); - end loop; - result := result ; - return result ; - end xor_reduce ; - - function xnor_reduce - (in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := '0' ; - for i in in0'range loop - result := result xor in0(i); - end loop; - result := not result ; - return result ; - end xnor_reduce ; - - function gate_and - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate and in0 ; - return result; - end gate_and; - - function gate_and - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 and vec_length'(0 to in0'length-1 => gate) ; - return result; - end gate_and; - - function gate_or - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate or in0 ; - return result; - end gate_or; - - function gate_or - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 or vec_length'(0 to in0'length-1 => gate) ; - return result; - end gate_or; - - function gate_nand - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate nand in0 ; - return result; - end gate_nand; - - function gate_nand - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 nand vec_length'( 0 to in0'length-1 => gate ); - return result; - end gate_nand; - - function gate_nor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate nor in0 ; - return result; - end gate_nor; - - function gate_nor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 nor vec_length'(0 to in0'length-1 => gate) ; - return result; - end gate_nor; - - function gate_xor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate xor in0 ; - return result; - end gate_xor; - - function gate_xor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := in0 xor vec_length'(0 to in0'length-1 => gate) ; - return result; - end gate_xor; - - function gate_xnor - (gate : std_ulogic ; - in0 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := gate = in0 ; - return result; - end gate_xnor; - - function gate_xnor - (gate : std_ulogic ; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - result := not( in0 xor vec_length'(0 to in0'length-1 => gate) ) ; - return result; - end gate_xnor; - - function gate_and - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - variable gate_int : std_ulogic ; - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - gate_int := gate(gate'low) ; - for i in gate'low+1 to gate'high loop - gate_int := gate_int and gate(i); - end loop; - result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; - return result ; - end gate_and; - - function gate_or - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - variable gate_int : std_ulogic ; - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - gate_int := gate(gate'low) ; - for i in gate'low+1 to gate'high loop - gate_int := gate_int or gate(i); - end loop; - result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; - return result ; - end gate_or; - - function gate_nand - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - variable gate_int : std_ulogic ; - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - gate_int := gate(gate'low) ; - for i in gate'low+1 to gate'high loop - gate_int := gate_int and gate(i); - end loop; - result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; - result := not result ; - return result; - end gate_nand; - - function gate_nor - (gate : std_ulogic_vector; - in0 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - variable gate_int : std_ulogic ; - subtype vec_length is std_ulogic_vector(0 to in0'length-1); - begin - gate_int := gate(gate'low) ; - for i in gate'low+1 to gate'high loop - gate_int := gate_int or gate(i); - end loop; - result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; - result := not result ; - return result ; - end gate_nor; - - function xor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 xor in1 ; - return result ; - end xor_2 ; - - function xor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 xor in1; - return result ; - end xor_2 ; - - function xor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := (in0 xor in1 xor in2) ; - return result ; - end xor_3 ; - - function xor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 xor in1 xor in2 ; - return result ; - end xor_3 ; - - function xnor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 xor in1 ) ; - return result ; - end xnor_2 ; - - function xnor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 xor in1 ) ; - return result ; - end xnor_2 ; - - function xnor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 xor in1 xor in2 ) ; - return result ; - end xnor_3 ; - - function xnor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 xor in1 xor in2 ) ; - return result ; - end xnor_3 ; - - function and_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 ; - return result ; - end and_2 ; - - function and_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 ; - return result ; - end and_2 ; - - function and_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 ; - return result ; - end and_3 ; - - function and_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 ; - return result ; - end and_3 ; - - function and_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 ; - return result ; - end and_4 ; - - function and_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 ; - return result ; - end and_4 ; - - function and_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 ; - return result ; - end and_5 ; - - function and_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4; - return result ; - end and_5 ; - - function and_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 ; - return result ; - end and_6 ; - - function and_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 ; - return result ; - end and_6 ; - - function and_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; - return result ; - end and_7 ; - - function and_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; - return result ; - end and_7 ; - - function and_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; - return result ; - end and_8 ; - - function and_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; - return result ; - end and_8 ; - - function or_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 ; - return result ; - end or_2 ; - - function or_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 ; - return result ; - end or_2 ; - - function or_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 ; - return result ; - end or_3 ; - - function or_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 ; - return result ; - end or_3 ; - - function or_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 ; - return result ; - end or_4 ; - - function or_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 ; - return result ; - end or_4 ; - - function or_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 ; - return result ; - end or_5 ; - - function or_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 ; - return result ; - end or_5 ; - - function or_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 ; - return result ; - end or_6 ; - - function or_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 ; - return result ; - end or_6 ; - - function or_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; - return result ; - end or_7 ; - - function or_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; - return result ; - end or_7 ; - - function or_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; - return result ; - end or_8 ; - - function or_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; - return result ; - end or_8 ; - - function nand_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 ) ; - return result ; - end nand_2 ; - - function nand_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 ) ; - return result ; - end nand_2 ; - - function nand_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 ) ; - return result ; - end nand_3 ; - - function nand_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 ) ; - return result ; - end nand_3 ; - - function nand_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 ) ; - return result ; - end nand_4 ; - - function nand_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 ) ; - return result ; - end nand_4 ; - - function nand_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 ) ; - return result ; - end nand_5 ; - - function nand_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 ) ; - return result ; - end nand_5 ; - - function nand_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; - return result ; - end nand_6 ; - - function nand_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; - return result ; - end nand_6 ; - - function nand_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; - return result ; - end nand_7 ; - - function nand_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; - return result ; - end nand_7 ; - - function nand_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; - return result ; - end nand_8 ; - - function nand_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; - return result ; - end nand_8 ; - - function nor_2 - (in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 ) ; - return result ; - end nor_2 ; - - function nor_2 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 ) ; - return result ; - end nor_2 ; - - function nor_3 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 ) ; - return result ; - end nor_3 ; - - function nor_3 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 ) ; - return result ; - end nor_3 ; - - function nor_4 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 ) ; - return result ; - end nor_4 ; - - function nor_4 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 ) ; - return result ; - end nor_4 ; - - function nor_5 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 ) ; - return result ; - end nor_5 ; - - function nor_5 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 ) ; - return result ; - end nor_5 ; - - function nor_6 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; - return result ; - end nor_6 ; - - function nor_6 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; - return result ; - end nor_6 ; - - function nor_7 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; - return result ; - end nor_7 ; - - function nor_7 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; - return result ; - end nor_7 ; - - function nor_8 - (in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; - return result ; - end nor_8 ; - - function nor_8 - (in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector (0 to in0'length-1); - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; - return result ; - end nor_8 ; - - function tie_0 - -- synopsys translate_off - (btr : in string :=""; - blkdata : in string :="" - ) - -- synopsys translate_on - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := '0'; - return result; - end tie_0; - - function vector_tie_0 - (width : integer := 1 - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector(0 to width-1) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - for i in 0 to width-1 loop - result(i) := '0'; - end loop; - return result; - end vector_tie_0; - - function tie_1 - -- synopsys translate_off - (btr : in string :="" - ;blkdata : in string :="" - ) - -- synopsys translate_on - return std_ulogic - is - variable result : std_ulogic ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - result := '1'; - return result; - end tie_1; - - function vector_tie_1 - (width : integer := 1 - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_ulogic_vector - is - variable result : std_ulogic_vector(0 to width-1) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - for i in 0 to width-1 loop - result(i) := '1'; - end loop; - return result; - end vector_tie_1; - - function decode( code : std_ulogic_vector ) return std_ulogic_vector is - variable result : std_ulogic_vector(0 to (2**(code'length)-1)) := (others => '0'); - begin - result := (others => '0'); - result( tconv( code ) ) := '1'; - for i in code'low to code'high loop - if code(i) = 'U' then - result := (others => 'U'); - end if; - end loop; - for i in code'low to code'high loop - if code(i) = 'X' then - result := (others => 'X'); - end if; - end loop; - return result; - end decode; - - function decode_2to4 - (code : std_ulogic_vector(0 to 1) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_4 - is - variable result : std_ulogic_vector(0 to 3) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - case code is - when "00" => result := "1000"; - when "01" => result := "0100"; - when "10" => result := "0010"; - when "11" => result := "0001"; - when others => result := "XXXX"; - end case; - return result; - end decode_2to4; - - function decode_3to8 - (code : std_ulogic_vector(0 to 2) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_8 - is - variable result : std_ulogic_vector(0 to 7) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - case code is - when "000" => result := "10000000"; - when "001" => result := "01000000"; - when "010" => result := "00100000"; - when "011" => result := "00010000"; - when "100" => result := "00001000"; - when "101" => result := "00000100"; - when "110" => result := "00000010"; - when "111" => result := "00000001"; - when others => result := "XXXXXXXX"; - end case; - return result; - end decode_3to8; - - function decode_4to16 - (code : std_ulogic_vector(0 to 3) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_16 - is - variable result : std_ulogic_vector(0 to 15) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - case code is - when "0000" => result := "1000000000000000"; - when "0001" => result := "0100000000000000"; - when "0010" => result := "0010000000000000"; - when "0011" => result := "0001000000000000"; - when "0100" => result := "0000100000000000"; - when "0101" => result := "0000010000000000"; - when "0110" => result := "0000001000000000"; - when "0111" => result := "0000000100000000"; - when "1000" => result := "0000000010000000"; - when "1001" => result := "0000000001000000"; - when "1010" => result := "0000000000100000"; - when "1011" => result := "0000000000010000"; - when "1100" => result := "0000000000001000"; - when "1101" => result := "0000000000000100"; - when "1110" => result := "0000000000000010"; - when "1111" => result := "0000000000000001"; - when others => result := "XXXXXXXXXXXXXXXX"; - end case; - return result; - end decode_4to16; - - function decode_5to32 - (code : std_ulogic_vector(0 to 4) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_32 - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to 31) ; - begin - case code is - when "00000" => result := "10000000000000000000000000000000"; - when "00001" => result := "01000000000000000000000000000000"; - when "00010" => result := "00100000000000000000000000000000"; - when "00011" => result := "00010000000000000000000000000000"; - when "00100" => result := "00001000000000000000000000000000"; - when "00101" => result := "00000100000000000000000000000000"; - when "00110" => result := "00000010000000000000000000000000"; - when "00111" => result := "00000001000000000000000000000000"; - when "01000" => result := "00000000100000000000000000000000"; - when "01001" => result := "00000000010000000000000000000000"; - when "01010" => result := "00000000001000000000000000000000"; - when "01011" => result := "00000000000100000000000000000000"; - when "01100" => result := "00000000000010000000000000000000"; - when "01101" => result := "00000000000001000000000000000000"; - when "01110" => result := "00000000000000100000000000000000"; - when "01111" => result := "00000000000000010000000000000000"; - when "10000" => result := "00000000000000001000000000000000"; - when "10001" => result := "00000000000000000100000000000000"; - when "10010" => result := "00000000000000000010000000000000"; - when "10011" => result := "00000000000000000001000000000000"; - when "10100" => result := "00000000000000000000100000000000"; - when "10101" => result := "00000000000000000000010000000000"; - when "10110" => result := "00000000000000000000001000000000"; - when "10111" => result := "00000000000000000000000100000000"; - when "11000" => result := "00000000000000000000000010000000"; - when "11001" => result := "00000000000000000000000001000000"; - when "11010" => result := "00000000000000000000000000100000"; - when "11011" => result := "00000000000000000000000000010000"; - when "11100" => result := "00000000000000000000000000001000"; - when "11101" => result := "00000000000000000000000000000100"; - when "11110" => result := "00000000000000000000000000000010"; - when "11111" => result := "00000000000000000000000000000001"; - when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; - end case; - return result; - end decode_5to32; - - function decode_6to64 - (code : std_ulogic_vector(0 to 5) - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - return std_return_64 - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to 63) ; - begin - case code is - when "000000" => result := "1000000000000000000000000000000000000000000000000000000000000000"; - when "000001" => result := "0100000000000000000000000000000000000000000000000000000000000000"; - when "000010" => result := "0010000000000000000000000000000000000000000000000000000000000000"; - when "000011" => result := "0001000000000000000000000000000000000000000000000000000000000000"; - when "000100" => result := "0000100000000000000000000000000000000000000000000000000000000000"; - when "000101" => result := "0000010000000000000000000000000000000000000000000000000000000000"; - when "000110" => result := "0000001000000000000000000000000000000000000000000000000000000000"; - when "000111" => result := "0000000100000000000000000000000000000000000000000000000000000000"; - when "001000" => result := "0000000010000000000000000000000000000000000000000000000000000000"; - when "001001" => result := "0000000001000000000000000000000000000000000000000000000000000000"; - when "001010" => result := "0000000000100000000000000000000000000000000000000000000000000000"; - when "001011" => result := "0000000000010000000000000000000000000000000000000000000000000000"; - when "001100" => result := "0000000000001000000000000000000000000000000000000000000000000000"; - when "001101" => result := "0000000000000100000000000000000000000000000000000000000000000000"; - when "001110" => result := "0000000000000010000000000000000000000000000000000000000000000000"; - when "001111" => result := "0000000000000001000000000000000000000000000000000000000000000000"; - when "010000" => result := "0000000000000000100000000000000000000000000000000000000000000000"; - when "010001" => result := "0000000000000000010000000000000000000000000000000000000000000000"; - when "010010" => result := "0000000000000000001000000000000000000000000000000000000000000000"; - when "010011" => result := "0000000000000000000100000000000000000000000000000000000000000000"; - when "010100" => result := "0000000000000000000010000000000000000000000000000000000000000000"; - when "010101" => result := "0000000000000000000001000000000000000000000000000000000000000000"; - when "010110" => result := "0000000000000000000000100000000000000000000000000000000000000000"; - when "010111" => result := "0000000000000000000000010000000000000000000000000000000000000000"; - when "011000" => result := "0000000000000000000000001000000000000000000000000000000000000000"; - when "011001" => result := "0000000000000000000000000100000000000000000000000000000000000000"; - when "011010" => result := "0000000000000000000000000010000000000000000000000000000000000000"; - when "011011" => result := "0000000000000000000000000001000000000000000000000000000000000000"; - when "011100" => result := "0000000000000000000000000000100000000000000000000000000000000000"; - when "011101" => result := "0000000000000000000000000000010000000000000000000000000000000000"; - when "011110" => result := "0000000000000000000000000000001000000000000000000000000000000000"; - when "011111" => result := "0000000000000000000000000000000100000000000000000000000000000000"; - when "100000" => result := "0000000000000000000000000000000010000000000000000000000000000000"; - when "100001" => result := "0000000000000000000000000000000001000000000000000000000000000000"; - when "100010" => result := "0000000000000000000000000000000000100000000000000000000000000000"; - when "100011" => result := "0000000000000000000000000000000000010000000000000000000000000000"; - when "100100" => result := "0000000000000000000000000000000000001000000000000000000000000000"; - when "100101" => result := "0000000000000000000000000000000000000100000000000000000000000000"; - when "100110" => result := "0000000000000000000000000000000000000010000000000000000000000000"; - when "100111" => result := "0000000000000000000000000000000000000001000000000000000000000000"; - when "101000" => result := "0000000000000000000000000000000000000000100000000000000000000000"; - when "101001" => result := "0000000000000000000000000000000000000000010000000000000000000000"; - when "101010" => result := "0000000000000000000000000000000000000000001000000000000000000000"; - when "101011" => result := "0000000000000000000000000000000000000000000100000000000000000000"; - when "101100" => result := "0000000000000000000000000000000000000000000010000000000000000000"; - when "101101" => result := "0000000000000000000000000000000000000000000001000000000000000000"; - when "101110" => result := "0000000000000000000000000000000000000000000000100000000000000000"; - when "101111" => result := "0000000000000000000000000000000000000000000000010000000000000000"; - when "110000" => result := "0000000000000000000000000000000000000000000000001000000000000000"; - when "110001" => result := "0000000000000000000000000000000000000000000000000100000000000000"; - when "110010" => result := "0000000000000000000000000000000000000000000000000010000000000000"; - when "110011" => result := "0000000000000000000000000000000000000000000000000001000000000000"; - when "110100" => result := "0000000000000000000000000000000000000000000000000000100000000000"; - when "110101" => result := "0000000000000000000000000000000000000000000000000000010000000000"; - when "110110" => result := "0000000000000000000000000000000000000000000000000000001000000000"; - when "110111" => result := "0000000000000000000000000000000000000000000000000000000100000000"; - when "111000" => result := "0000000000000000000000000000000000000000000000000000000010000000"; - when "111001" => result := "0000000000000000000000000000000000000000000000000000000001000000"; - when "111010" => result := "0000000000000000000000000000000000000000000000000000000000100000"; - when "111011" => result := "0000000000000000000000000000000000000000000000000000000000010000"; - when "111100" => result := "0000000000000000000000000000000000000000000000000000000000001000"; - when "111101" => result := "0000000000000000000000000000000000000000000000000000000000000100"; - when "111110" => result := "0000000000000000000000000000000000000000000000000000000000000010"; - when "111111" => result := "0000000000000000000000000000000000000000000000000000000000000001"; - when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; - end case; - return result; - end decode_6to64; - --- full adder function - procedure full_add - (add_1 : in std_ulogic ; - add_2 : in std_ulogic ; - cryin : in std_ulogic ; - signal sum : out std_ulogic ; - signal carry : out std_ulogic - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - is - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - sum <= add_1 xor add_2 xor cryin; - carry <= (add_1 and add_2) or - (add_1 and cryin) or - (add_2 and cryin); - end full_add; - - procedure full_add - (add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - cryin : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ; - signal carry : out std_ulogic_vector - -- synopsys translate_off - ;btr : in string :="" - ;blkdata : in string :="" - -- synopsys translate_on - ) - is - variable sum_result : std_ulogic_vector(sum'range) ; - variable carry_result : std_ulogic_vector(carry'range) ; - -- synopsys translate_off - variable block_data : string(1 to 1) ; - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & btr & "/" & - blkdata ; - -- synopsys translate_on - begin - -- synopsys translate_off - assert (add_1'length = add_2'length) - report "Addends of Full_Add are not the same length." - severity error; - assert (add_1'length = cryin'length) and (add_2'length = cryin'length) - report "Addends of Full_Add are not the same length as the CryIn." - severity error; - -- synopsys translate_on - sum_result := add_1 xor add_2 xor cryin; - carry_result := (add_1 and add_2) or - (add_1 and cryin) or - (add_2 and cryin); - sum <= sum_result ; - carry <= carry_result ; - end full_add; - - -- Ripple adder function - procedure ripple_adder - ( add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ; - signal carry : out std_ulogic ) - is - -- Synopsys translate_off - attribute unroll_loop : boolean; - attribute unroll_loop of ripple : label is true; - -- Synopsys translate_on - variable a : std_ulogic_vector(1 to add_1'length) ; - variable b : std_ulogic_vector(1 to add_2'length) ; - variable c : std_ulogic_vector(0 to add_1'length) ; - variable result : std_ulogic_vector(1 to add_1'length) ; - begin - a := add_1; - b := add_2; - c(c'right) := '0' ; - ripple:for i in result'right downto 1 loop - c(i-1) := ( c(i) and a(i) ) or - ( c(i) and b(i) ) or - ( a(i) and b(i) ) ; - result(i) := a(i) xor b(i) xor c(i) ; - end loop ; - sum <= result ; - carry <= c(c'left) ; - end ripple_adder ; - - procedure ripple_adder - ( add_1 : in std_ulogic_vector ; - add_2 : in std_ulogic_vector ; - signal sum : out std_ulogic_vector ) - is - -- Synopsys translate_off - attribute unroll_loop : boolean; - attribute unroll_loop of ripple : label is true; - -- Synopsys translate_on - variable a : std_ulogic_vector(1 to add_1'length) ; - variable b : std_ulogic_vector(1 to add_2'length) ; - variable c : std_ulogic_vector(1 to add_1'length) ; - variable result : std_ulogic_vector(1 to add_1'length) ; - begin - a := add_1; - b := add_2; - c(c'right) := '0' ; - ripple:for i in result'right downto 2 loop - c(i-1) := ( c(i) and a(i) ) or - ( c(i) and b(i) ) or - ( a(i) and b(i) ) ; - result(i) := a(i) xor b(i) xor c(i) ; - end loop ; - result(1) := a(1) xor b(1) xor c(1) ; - sum <= result ; - end ripple_adder ; - - -- Dot Functions - function dot_and - (in0 : std_ulogic_vector ) - return std_ulogic - is - variable result : std_ulogic ; - begin - result := '1'; - for i in in0'range loop - result := in0(i) and result ; - end loop ; - return result; - end dot_and ; - - function dot_or - (in0 : std_ulogic_vector ) - return std_ulogic - is - variable result : std_ulogic ; - begin - result := '0'; - for i in in0'range loop - result := in0(i) or result ; - end loop ; - return result; - end dot_or ; - - function clock_tree_dot - (in0 : std_ulogic_vector ) - return std_ulogic - is - variable result : std_ulogic ; - begin - result := '1'; - for i in in0'range loop - result := in0(i) and result ; - end loop ; - return result; - end clock_tree_dot ; - - function clock_tree_dot - (in0 : bit_vector ) - return bit - is - variable result : bit ; - begin - result := '1'; - for i in in0'range loop - result := in0(i) and result ; - end loop ; - return result; - end clock_tree_dot ; - -end std_ulogic_function_support; - +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_function_support is + -- Subtypes used for constraining return values in package + subtype std_return_2 is std_ulogic_vector(0 to 1); + subtype std_return_4 is std_ulogic_vector(0 to 3); + subtype std_return_8 is std_ulogic_vector(0 to 7); + subtype std_return_16 is std_ulogic_vector(0 to 15); + subtype std_return_32 is std_ulogic_vector(0 to 31); + subtype std_return_64 is std_ulogic_vector(0 to 63); + -- Test Case Evaluation Attributes + -- These attributes are used to control the generation of TCE tests + -- within the VHDL code. + -- Valid on PORT, SIGNAL and LABEL . + + -- Used to turn task model generation on or off. The attribute is applied + -- to a label. If on a block it turns off generation for the whole block. + -- If on a statement it is for that statement alone. + -- The string specifies which task statement alone. + -- attribute TCE_ON of : label is "T,LTP,STP,DLTP,LST,STC,ASSRT,CMBN | ALL" ; + attribute tce_on : string; + attribute tce_off : string; + attribute tce_last : string; + attribute tce_reset : string; + attribute tce_all_off : string; + attribute tce_ignore : string; + -- The string specifies which task statement alone. + attribute tce_assertion : string; + attribute tce_combination : string; + attribute tce_seqcond : string; + + -- Global Signals + -- Synopsys translate_off + signal audit_bit_dump : std_ulogic ; + signal assertion_summary : boolean ; + signal assertion_clock : std_ulogic ; + -- Synopsys translate_on + + -- Synopsys translate_off + component assertion + generic( counted : boolean := false; + Delay : natural := 0; + Duration : natural := 0); + port( + assert_in : in std_ulogic ; + sample : in std_ulogic ; + assert_out : out std_ulogic + ); + end component; + -- Synopsys translate_on + + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector ; + -- Synopsys translate_off + attribute btr_name of gate : function is "AND" ; + attribute recursive_synthesis of gate : function is 1 ; + attribute pin_bit_information of gate : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 3 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of dot_and : function is "VHDL-DOTA" ; + attribute recursive_synthesis of dot_and : function is 1 ; + attribute pin_bit_information of dot_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of dot_or : function is "VHDL-DOTO" ; + attribute recursive_synthesis of dot_or : function is 1 ; + attribute pin_bit_information of dot_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit ; + -- Synopsys translate_off + attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ; + attribute recursive_synthesis of clock_tree_dot : function is 1 ; + attribute pin_bit_information of clock_tree_dot : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of terminator : procedure is "TERMINATOR"; + attribute recursive_synthesis of terminator : procedure is 1 ; + attribute pin_bit_information of terminator : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of delay : function is "IDENT" ; + attribute recursive_synthesis of delay : function is 1 ; + attribute block_data of delay : function is + "SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of delay : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Generic Buffer + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of buff : function is "IDENT" ; + attribute recursive_synthesis of buff : function is 1 ; + attribute block_data of buff : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of buff : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Invert single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of invert : function is "NOT" ; + attribute recursive_synthesis of invert : function is 1 ; + attribute pin_bit_information of invert : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Compare single bit + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- compare multi-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of compare : function is "VHDL-COMPARE" ; + attribute recursive_synthesis of compare : function is 1 ; + attribute pin_bit_information of compare : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","EQ ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity Functions + -- General XOR_Tree Building Parity Function + function parity + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of parity : function is "XOR" ; + attribute recursive_synthesis of parity : function is 1 ; + attribute pin_bit_information of parity : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + function parity_map + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_map : function is "XOR" ; + attribute recursive_synthesis of parity_map : function is 1 ; + attribute block_data of parity_map : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of parity_map : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + + -- synopsys translate_off + attribute btr_name of parity_gen_odd : function is "XNOR" ; + attribute recursive_synthesis of parity_gen_odd : function is 1; + attribute pin_bit_information of parity_gen_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of parity_gen_even : function is "XOR" ; + attribute recursive_synthesis of parity_gen_even : function is 1; + attribute pin_bit_information of parity_gen_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_odd : function is "XOR" ; + attribute recursive_synthesis of is_parity_odd : function is 1; + attribute pin_bit_information of is_parity_odd : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic ; + -- Synopsys translate_off + attribute btr_name of is_parity_even : function is "XNOR" ; + attribute recursive_synthesis of is_parity_even : function is 1; + attribute pin_bit_information of is_parity_even : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Full Adder + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ); + -- synopsys translate_off + attribute btr_name of full_add : procedure is "VHDL-FA"; + attribute recursive_synthesis of full_add : procedure is 1 ; + attribute pin_bit_information of full_add : procedure is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","CIN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","SUM ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","COUT ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," ")); + -- Synopsys translate_on + + -- Ripple Adder function + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) ; + + procedure ripple_adder + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ); + + -- Generic Tie Blocks + function tie_0 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of tie_0 : function is 1 ; + attribute block_data of tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_0 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ; + attribute recursive_synthesis of vector_tie_0 : function is 1 ; + attribute block_data of vector_tie_0 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_0 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ZERO ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of tie_1 : function is 1 ; + attribute block_data of tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of tie_1 : function is + (1 => (" ","PASS "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ; + attribute recursive_synthesis of vector_tie_1 : function is 1 ; + attribute block_data of vector_tie_1 : function is + "LOGIC_STYLE=/DIRECT/" ; + attribute pin_bit_information of vector_tie_1 : function is + (1 => (" ","IGNR "," "," "), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","ONE ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function reverse + (arg: std_ulogic_vector) + return std_ulogic_vector ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of and_reduce : function is "AND" ; + attribute recursive_synthesis of and_reduce : function is 1 ; + attribute pin_bit_information of and_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of or_reduce : function is "OR" ; + attribute recursive_synthesis of or_reduce : function is 1 ; + attribute pin_bit_information of or_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nand_reduce : function is "NAND" ; + attribute recursive_synthesis of nand_reduce : function is 1 ; + attribute pin_bit_information of nand_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of nor_reduce : function is "NOR" ; + attribute recursive_synthesis of nor_reduce : function is 1 ; + attribute pin_bit_information of nor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xor_reduce : function is "XOR" ; + attribute recursive_synthesis of xor_reduce : function is 1 ; + attribute pin_bit_information of xor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- synopsys translate_off + attribute btr_name of xnor_reduce : function is "XNOR" ; + attribute recursive_synthesis of xnor_reduce : function is 1 ; + attribute pin_bit_information of xnor_reduce : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + -- Vector of gating bits gating a single vector of data bits + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_and : function is "AND" ; + attribute recursive_synthesis of gate_and : function is 1 ; + attribute pin_bit_information of gate_and : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_or : function is "OR" ; + attribute recursive_synthesis of gate_or : function is 1 ; + attribute pin_bit_information of gate_or : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nand : function is "NAND" ; + attribute recursive_synthesis of gate_nand : function is 1 ; + attribute pin_bit_information of gate_nand : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_nor : function is "NOR" ; + attribute recursive_synthesis of gate_nor : function is 1 ; + attribute pin_bit_information of gate_nor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xor : function is "XOR" ; + attribute recursive_synthesis of gate_xor : function is 1 ; + attribute pin_bit_information of gate_xor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic ; + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of gate_xnor : function is "XNOR" ; + attribute recursive_synthesis of gate_xnor : function is 1 ; + attribute pin_bit_information of gate_xnor : function is + (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 2 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_2 : function is "AND" ; + attribute recursive_synthesis of and_2 : function is 1 ; + attribute pin_bit_information of and_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_2 : function is "OR" ; + attribute recursive_synthesis of or_2 : function is 1 ; + attribute pin_bit_information of or_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_2 : function is "NAND" ; + attribute recursive_synthesis of nand_2 : function is 1 ; + attribute pin_bit_information of nand_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_2 : function is "NOR" ; + attribute recursive_synthesis of nor_2 : function is 1 ; + attribute pin_bit_information of nor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_2 : function is "XOR" ; + attribute recursive_synthesis of xor_2 : function is 1 ; + attribute pin_bit_information of xor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_2 : function is "XNOR" ; + attribute recursive_synthesis of xnor_2 : function is 1 ; + attribute pin_bit_information of xnor_2 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","PASS "," "," "), + 4 => (" ","PASS "," "," "), + 5 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 3 input functions + -- Single bit case + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + -- multiple vectors logically ed bitwise + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_3 : function is "AND" ; + attribute recursive_synthesis of and_3 : function is 1 ; + attribute pin_bit_information of and_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_3 : function is "OR" ; + attribute recursive_synthesis of or_3 : function is 1 ; + attribute pin_bit_information of or_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_3 : function is "NAND" ; + attribute recursive_synthesis of nand_3 : function is 1 ; + attribute pin_bit_information of nand_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_3 : function is "NOR" ; + attribute recursive_synthesis of nor_3 : function is 1 ; + attribute pin_bit_information of nor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xor_3 : function is "XOR" ; + attribute recursive_synthesis of xor_3 : function is 1 ; + attribute pin_bit_information of xor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of xnor_3 : function is "XNOR" ; + attribute recursive_synthesis of xnor_3 : function is 1 ; + attribute pin_bit_information of xnor_3 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 4 input functions + -- Single bit case + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_4 : function is "AND" ; + attribute recursive_synthesis of and_4 : function is 1 ; + attribute pin_bit_information of and_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_4 : function is "OR" ; + attribute recursive_synthesis of or_4 : function is 1 ; + attribute pin_bit_information of or_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_4 : function is "NAND" ; + attribute recursive_synthesis of nand_4 : function is 1 ; + attribute pin_bit_information of nand_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_4 : function is "NOR" ; + attribute recursive_synthesis of nor_4 : function is 1 ; + attribute pin_bit_information of nor_4 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 5 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_5 : function is "AND" ; + attribute recursive_synthesis of and_5 : function is 1 ; + attribute pin_bit_information of and_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_5 : function is "OR" ; + attribute recursive_synthesis of or_5 : function is 1 ; + attribute pin_bit_information of or_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_5 : function is "NAND" ; + attribute recursive_synthesis of nand_5 : function is 1 ; + attribute pin_bit_information of nand_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_5 : function is "NOR" ; + attribute recursive_synthesis of nor_5 : function is 1 ; + attribute pin_bit_information of nor_5 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 6 input functions + -- Single bit case + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_6 : function is "AND" ; + attribute recursive_synthesis of and_6 : function is 1 ; + attribute pin_bit_information of and_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_6 : function is "OR" ; + attribute recursive_synthesis of or_6 : function is 1 ; + attribute pin_bit_information of or_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_6 : function is "NAND" ; + attribute recursive_synthesis of nand_6 : function is 1 ; + attribute pin_bit_information of nand_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_6 : function is "NOR" ; + attribute recursive_synthesis of nor_6 : function is 1 ; + attribute pin_bit_information of nor_6 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 7 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_7 : function is "AND" ; + attribute recursive_synthesis of and_7 : function is 1 ; + attribute pin_bit_information of and_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_7 : function is "OR" ; + attribute recursive_synthesis of or_7 : function is 1 ; + attribute pin_bit_information of or_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_7 : function is "NAND" ; + attribute recursive_synthesis of nand_7 : function is 1 ; + attribute pin_bit_information of nand_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_7 : function is "NOR" ; + attribute recursive_synthesis of nor_7 : function is 1 ; + attribute pin_bit_information of nor_7 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","PASS "," "," "), + 9 => (" ","PASS "," "," "), + 10 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + -- Vectored primitive 8 input functions + -- Single bit case + -- Multiple vectors logically ed bitwise + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of and_8 : function is "AND" ; + attribute recursive_synthesis of and_8 : function is 1 ; + attribute pin_bit_information of and_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of or_8 : function is "OR" ; + attribute recursive_synthesis of or_8 : function is 1 ; + attribute pin_bit_information of or_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nand_8 : function is "NAND" ; + attribute recursive_synthesis of nand_8 : function is 1 ; + attribute pin_bit_information of nand_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic ; + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of nor_8 : function is "NOR" ; + attribute recursive_synthesis of nor_8 : function is 1 ; + attribute pin_bit_information of nor_8 : function is + (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","IN ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- Synopsys translate_on + + function decode( code : std_ulogic_vector ) return std_ulogic_vector; + -- Synopsys translate_off + attribute functionality of decode: function is "DECODER"; + -- Synopsys translate_on + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 ; + -- synopsys translate_off + attribute btr_name of decode_2to4 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_2to4 : function is 1 ; + attribute pin_bit_information of decode_2to4 : function is + (1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 ; + -- synopsys translate_off + attribute btr_name of decode_3to8 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_3to8 : function is 1 ; + attribute pin_bit_information of decode_3to8 : function is + (1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 ; + -- synopsys translate_off + attribute btr_name of decode_4to16 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_4to16 : function is 1 ; + attribute pin_bit_information of decode_4to16 : function is + (1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 ; + -- synopsys translate_off + attribute btr_name of decode_5to32 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_5to32 : function is 1 ; + attribute pin_bit_information of decode_5to32 : function is + (1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 ; + -- synopsys translate_off + attribute btr_name of decode_6to64 : function is "VHDL-DECODE"; + attribute recursive_synthesis of decode_6to64 : function is 1 ; + attribute pin_bit_information of decode_6to64 : function is + (1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","PASS "," "," "), + 3 => (" ","PASS "," "," "), + 4 => (" ","F0 ","INCR","PIN_BIT_SCALAR")); + -- Synopsys translate_on + +end std_ulogic_function_support; + +package body std_ulogic_function_support is + -- Function Declarations and Attributes + -- Gate Function + function gate + (in0 : std_ulogic_vector; + cond : std_ulogic ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => cond) ; + return result; + end gate; + + -- This function everses the range direction. + function reverse (arg: std_ulogic_vector) + return std_ulogic_vector + is + variable d, result : std_ulogic_vector(0 to arg'length-1); + begin + d := arg; + for i in 0 to d'length-1 loop + result(result'right - i) := d(i); + end loop; + return result; + end reverse; + + -- Generic Terminator + procedure terminator + (in0 : in std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + begin + result := in0 ; + end terminator ; + + procedure terminator + (in0 : in std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1); + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 ; + end terminator ; + + -- Generic Delay + function delay + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- initialize variable attribute values + result := in0; + return result; + end delay ; + + function delay + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end delay ; + + function buff + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + + function buff + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0; + return result; + end buff ; + +-- inverter single bit + function invert + (in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- inverter vectored + function invert + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not in0; + return result; + end invert ; + + -- Comparator + function compare + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + +-- comparator mult-bit + function compare + (in0 : std_ulogic_vector; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 = in1 ; + return result; + end compare ; + + -- General XOR_Tree Building Parity Function + function parity + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return Std_uLogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity ; + + -- Specific Size Parity Block Map Function + function parity_map + (In0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_map ; + +-- Parity gneration/checking functions + function parity_gen_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end parity_gen_odd ; + + function parity_gen_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end parity_gen_even ; + + function is_parity_odd + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return result; + end is_parity_odd ; + + function is_parity_even + (in0 : std_ulogic_vector + -- Synopsys translate_off + ;btr : in String :="" + ;blkdata : in String :="" + -- Synopsys translate_on + ) + return std_ulogic + is + -- Synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- Synopsys translate_on + variable result : std_ulogic; + begin + result := in0(in0'low); + for i in in0'low+1 to in0'high loop + result := in0(i) xor result ; + end loop; + return not result; + end is_parity_even ; + + function and_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := result ; + return result; + end and_reduce ; + + function or_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := result ; + return result; + end or_reduce ; + + function nand_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result and in0(i); + end loop; + result := not result ; + return result; + end nand_reduce ; + + function nor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0(in0'left) ; + for i in in0'range loop + result := result or in0(i); + end loop; + result := not result ; + return result; + end nor_reduce ; + + function xor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := result ; + return result ; + end xor_reduce ; + + function xnor_reduce + (in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0' ; + for i in in0'range loop + result := result xor in0(i); + end loop; + result := not result ; + return result ; + end xnor_reduce ; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate and in0 ; + return result; + end gate_and; + + function gate_and + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 and vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_and; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate or in0 ; + return result; + end gate_or; + + function gate_or + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 or vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_or; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nand in0 ; + return result; + end gate_nand; + + function gate_nand + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nand vec_length'( 0 to in0'length-1 => gate ); + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate nor in0 ; + return result; + end gate_nor; + + function gate_nor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 nor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_nor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate xor in0 ; + return result; + end gate_xor; + + function gate_xor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := in0 xor vec_length'(0 to in0'length-1 => gate) ; + return result; + end gate_xor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := gate = in0 ; + return result; + end gate_xnor; + + function gate_xnor + (gate : std_ulogic ; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + result := not( in0 xor vec_length'(0 to in0'length-1 => gate) ) ; + return result; + end gate_xnor; + + function gate_and + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_and; + + function gate_or + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + return result ; + end gate_or; + + function gate_nand + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int and gate(i); + end loop; + result := in0 and vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result; + end gate_nand; + + function gate_nor + (gate : std_ulogic_vector; + in0 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + variable gate_int : std_ulogic ; + subtype vec_length is std_ulogic_vector(0 to in0'length-1); + begin + gate_int := gate(gate'low) ; + for i in gate'low+1 to gate'high loop + gate_int := gate_int or gate(i); + end loop; + result := in0 or vec_length'(0 to in0'length-1 => gate_int) ; + result := not result ; + return result ; + end gate_nor; + + function xor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 ; + return result ; + end xor_2 ; + + function xor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1; + return result ; + end xor_2 ; + + function xor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := (in0 xor in1 xor in2) ; + return result ; + end xor_3 ; + + function xor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 xor in1 xor in2 ; + return result ; + end xor_3 ; + + function xnor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 ) ; + return result ; + end xnor_2 ; + + function xnor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function xnor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 xor in1 xor in2 ) ; + return result ; + end xnor_3 ; + + function and_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 ; + return result ; + end and_2 ; + + function and_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 ; + return result ; + end and_3 ; + + function and_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 ; + return result ; + end and_4 ; + + function and_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 ; + return result ; + end and_5 ; + + function and_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4; + return result ; + end and_5 ; + + function and_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 ; + return result ; + end and_6 ; + + function and_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 ; + return result ; + end and_7 ; + + function and_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function and_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ; + return result ; + end and_8 ; + + function or_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 ; + return result ; + end or_2 ; + + function or_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 ; + return result ; + end or_3 ; + + function or_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 ; + return result ; + end or_4 ; + + function or_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 ; + return result ; + end or_5 ; + + function or_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 ; + return result ; + end or_6 ; + + function or_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 ; + return result ; + end or_7 ; + + function or_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function or_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ; + return result ; + end or_8 ; + + function nand_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 ) ; + return result ; + end nand_2 ; + + function nand_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 ) ; + return result ; + end nand_3 ; + + function nand_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 ) ; + return result ; + end nand_4 ; + + function nand_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 ) ; + return result ; + end nand_5 ; + + function nand_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 ) ; + return result ; + end nand_6 ; + + function nand_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6) ; + return result ; + end nand_7 ; + + function nand_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nand_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 and in1 and in2 and in3 and in4 and in5 and in6 and in7 ) ; + return result ; + end nand_8 ; + + function nor_2 + (in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_2 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 ) ; + return result ; + end nor_2 ; + + function nor_3 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_3 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 ) ; + return result ; + end nor_3 ; + + function nor_4 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_4 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 ) ; + return result ; + end nor_4 ; + + function nor_5 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_5 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 ) ; + return result ; + end nor_5 ; + + function nor_6 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_6 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 ) ; + return result ; + end nor_6 ; + + function nor_7 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_7 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 ) ; + return result ; + end nor_7 ; + + function nor_8 + (in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function nor_8 + (in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector (0 to in0'length-1); + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := not( in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7 ) ; + return result ; + end nor_8 ; + + function tie_0 + -- synopsys translate_off + (btr : in string :=""; + blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '0'; + return result; + end tie_0; + + function vector_tie_0 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '0'; + end loop; + return result; + end vector_tie_0; + + function tie_1 + -- synopsys translate_off + (btr : in string :="" + ;blkdata : in string :="" + ) + -- synopsys translate_on + return std_ulogic + is + variable result : std_ulogic ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + result := '1'; + return result; + end tie_1; + + function vector_tie_1 + (width : integer := 1 + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_ulogic_vector + is + variable result : std_ulogic_vector(0 to width-1) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + for i in 0 to width-1 loop + result(i) := '1'; + end loop; + return result; + end vector_tie_1; + + function decode( code : std_ulogic_vector ) return std_ulogic_vector is + variable result : std_ulogic_vector(0 to (2**(code'length)-1)) := (others => '0'); + begin + result := (others => '0'); + result( tconv( code ) ) := '1'; + for i in code'low to code'high loop + if code(i) = 'U' then + result := (others => 'U'); + end if; + end loop; + for i in code'low to code'high loop + if code(i) = 'X' then + result := (others => 'X'); + end if; + end loop; + return result; + end decode; + + function decode_2to4 + (code : std_ulogic_vector(0 to 1) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_4 + is + variable result : std_ulogic_vector(0 to 3) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "00" => result := "1000"; + when "01" => result := "0100"; + when "10" => result := "0010"; + when "11" => result := "0001"; + when others => result := "XXXX"; + end case; + return result; + end decode_2to4; + + function decode_3to8 + (code : std_ulogic_vector(0 to 2) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_8 + is + variable result : std_ulogic_vector(0 to 7) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "000" => result := "10000000"; + when "001" => result := "01000000"; + when "010" => result := "00100000"; + when "011" => result := "00010000"; + when "100" => result := "00001000"; + when "101" => result := "00000100"; + when "110" => result := "00000010"; + when "111" => result := "00000001"; + when others => result := "XXXXXXXX"; + end case; + return result; + end decode_3to8; + + function decode_4to16 + (code : std_ulogic_vector(0 to 3) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_16 + is + variable result : std_ulogic_vector(0 to 15) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + case code is + when "0000" => result := "1000000000000000"; + when "0001" => result := "0100000000000000"; + when "0010" => result := "0010000000000000"; + when "0011" => result := "0001000000000000"; + when "0100" => result := "0000100000000000"; + when "0101" => result := "0000010000000000"; + when "0110" => result := "0000001000000000"; + when "0111" => result := "0000000100000000"; + when "1000" => result := "0000000010000000"; + when "1001" => result := "0000000001000000"; + when "1010" => result := "0000000000100000"; + when "1011" => result := "0000000000010000"; + when "1100" => result := "0000000000001000"; + when "1101" => result := "0000000000000100"; + when "1110" => result := "0000000000000010"; + when "1111" => result := "0000000000000001"; + when others => result := "XXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_4to16; + + function decode_5to32 + (code : std_ulogic_vector(0 to 4) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_32 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 31) ; + begin + case code is + when "00000" => result := "10000000000000000000000000000000"; + when "00001" => result := "01000000000000000000000000000000"; + when "00010" => result := "00100000000000000000000000000000"; + when "00011" => result := "00010000000000000000000000000000"; + when "00100" => result := "00001000000000000000000000000000"; + when "00101" => result := "00000100000000000000000000000000"; + when "00110" => result := "00000010000000000000000000000000"; + when "00111" => result := "00000001000000000000000000000000"; + when "01000" => result := "00000000100000000000000000000000"; + when "01001" => result := "00000000010000000000000000000000"; + when "01010" => result := "00000000001000000000000000000000"; + when "01011" => result := "00000000000100000000000000000000"; + when "01100" => result := "00000000000010000000000000000000"; + when "01101" => result := "00000000000001000000000000000000"; + when "01110" => result := "00000000000000100000000000000000"; + when "01111" => result := "00000000000000010000000000000000"; + when "10000" => result := "00000000000000001000000000000000"; + when "10001" => result := "00000000000000000100000000000000"; + when "10010" => result := "00000000000000000010000000000000"; + when "10011" => result := "00000000000000000001000000000000"; + when "10100" => result := "00000000000000000000100000000000"; + when "10101" => result := "00000000000000000000010000000000"; + when "10110" => result := "00000000000000000000001000000000"; + when "10111" => result := "00000000000000000000000100000000"; + when "11000" => result := "00000000000000000000000010000000"; + when "11001" => result := "00000000000000000000000001000000"; + when "11010" => result := "00000000000000000000000000100000"; + when "11011" => result := "00000000000000000000000000010000"; + when "11100" => result := "00000000000000000000000000001000"; + when "11101" => result := "00000000000000000000000000000100"; + when "11110" => result := "00000000000000000000000000000010"; + when "11111" => result := "00000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_5to32; + + function decode_6to64 + (code : std_ulogic_vector(0 to 5) + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + return std_return_64 + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to 63) ; + begin + case code is + when "000000" => result := "1000000000000000000000000000000000000000000000000000000000000000"; + when "000001" => result := "0100000000000000000000000000000000000000000000000000000000000000"; + when "000010" => result := "0010000000000000000000000000000000000000000000000000000000000000"; + when "000011" => result := "0001000000000000000000000000000000000000000000000000000000000000"; + when "000100" => result := "0000100000000000000000000000000000000000000000000000000000000000"; + when "000101" => result := "0000010000000000000000000000000000000000000000000000000000000000"; + when "000110" => result := "0000001000000000000000000000000000000000000000000000000000000000"; + when "000111" => result := "0000000100000000000000000000000000000000000000000000000000000000"; + when "001000" => result := "0000000010000000000000000000000000000000000000000000000000000000"; + when "001001" => result := "0000000001000000000000000000000000000000000000000000000000000000"; + when "001010" => result := "0000000000100000000000000000000000000000000000000000000000000000"; + when "001011" => result := "0000000000010000000000000000000000000000000000000000000000000000"; + when "001100" => result := "0000000000001000000000000000000000000000000000000000000000000000"; + when "001101" => result := "0000000000000100000000000000000000000000000000000000000000000000"; + when "001110" => result := "0000000000000010000000000000000000000000000000000000000000000000"; + when "001111" => result := "0000000000000001000000000000000000000000000000000000000000000000"; + when "010000" => result := "0000000000000000100000000000000000000000000000000000000000000000"; + when "010001" => result := "0000000000000000010000000000000000000000000000000000000000000000"; + when "010010" => result := "0000000000000000001000000000000000000000000000000000000000000000"; + when "010011" => result := "0000000000000000000100000000000000000000000000000000000000000000"; + when "010100" => result := "0000000000000000000010000000000000000000000000000000000000000000"; + when "010101" => result := "0000000000000000000001000000000000000000000000000000000000000000"; + when "010110" => result := "0000000000000000000000100000000000000000000000000000000000000000"; + when "010111" => result := "0000000000000000000000010000000000000000000000000000000000000000"; + when "011000" => result := "0000000000000000000000001000000000000000000000000000000000000000"; + when "011001" => result := "0000000000000000000000000100000000000000000000000000000000000000"; + when "011010" => result := "0000000000000000000000000010000000000000000000000000000000000000"; + when "011011" => result := "0000000000000000000000000001000000000000000000000000000000000000"; + when "011100" => result := "0000000000000000000000000000100000000000000000000000000000000000"; + when "011101" => result := "0000000000000000000000000000010000000000000000000000000000000000"; + when "011110" => result := "0000000000000000000000000000001000000000000000000000000000000000"; + when "011111" => result := "0000000000000000000000000000000100000000000000000000000000000000"; + when "100000" => result := "0000000000000000000000000000000010000000000000000000000000000000"; + when "100001" => result := "0000000000000000000000000000000001000000000000000000000000000000"; + when "100010" => result := "0000000000000000000000000000000000100000000000000000000000000000"; + when "100011" => result := "0000000000000000000000000000000000010000000000000000000000000000"; + when "100100" => result := "0000000000000000000000000000000000001000000000000000000000000000"; + when "100101" => result := "0000000000000000000000000000000000000100000000000000000000000000"; + when "100110" => result := "0000000000000000000000000000000000000010000000000000000000000000"; + when "100111" => result := "0000000000000000000000000000000000000001000000000000000000000000"; + when "101000" => result := "0000000000000000000000000000000000000000100000000000000000000000"; + when "101001" => result := "0000000000000000000000000000000000000000010000000000000000000000"; + when "101010" => result := "0000000000000000000000000000000000000000001000000000000000000000"; + when "101011" => result := "0000000000000000000000000000000000000000000100000000000000000000"; + when "101100" => result := "0000000000000000000000000000000000000000000010000000000000000000"; + when "101101" => result := "0000000000000000000000000000000000000000000001000000000000000000"; + when "101110" => result := "0000000000000000000000000000000000000000000000100000000000000000"; + when "101111" => result := "0000000000000000000000000000000000000000000000010000000000000000"; + when "110000" => result := "0000000000000000000000000000000000000000000000001000000000000000"; + when "110001" => result := "0000000000000000000000000000000000000000000000000100000000000000"; + when "110010" => result := "0000000000000000000000000000000000000000000000000010000000000000"; + when "110011" => result := "0000000000000000000000000000000000000000000000000001000000000000"; + when "110100" => result := "0000000000000000000000000000000000000000000000000000100000000000"; + when "110101" => result := "0000000000000000000000000000000000000000000000000000010000000000"; + when "110110" => result := "0000000000000000000000000000000000000000000000000000001000000000"; + when "110111" => result := "0000000000000000000000000000000000000000000000000000000100000000"; + when "111000" => result := "0000000000000000000000000000000000000000000000000000000010000000"; + when "111001" => result := "0000000000000000000000000000000000000000000000000000000001000000"; + when "111010" => result := "0000000000000000000000000000000000000000000000000000000000100000"; + when "111011" => result := "0000000000000000000000000000000000000000000000000000000000010000"; + when "111100" => result := "0000000000000000000000000000000000000000000000000000000000001000"; + when "111101" => result := "0000000000000000000000000000000000000000000000000000000000000100"; + when "111110" => result := "0000000000000000000000000000000000000000000000000000000000000010"; + when "111111" => result := "0000000000000000000000000000000000000000000000000000000000000001"; + when others => result := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end case; + return result; + end decode_6to64; + +-- full adder function + procedure full_add + (add_1 : in std_ulogic ; + add_2 : in std_ulogic ; + cryin : in std_ulogic ; + signal sum : out std_ulogic ; + signal carry : out std_ulogic + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + sum <= add_1 xor add_2 xor cryin; + carry <= (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + end full_add; + + procedure full_add + (add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + cryin : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic_vector + -- synopsys translate_off + ;btr : in string :="" + ;blkdata : in string :="" + -- synopsys translate_on + ) + is + variable sum_result : std_ulogic_vector(sum'range) ; + variable carry_result : std_ulogic_vector(carry'range) ; + -- synopsys translate_off + variable block_data : string(1 to 1) ; + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & btr & "/" & + blkdata ; + -- synopsys translate_on + begin + -- synopsys translate_off + assert (add_1'length = add_2'length) + report "Addends of Full_Add are not the same length." + severity error; + assert (add_1'length = cryin'length) and (add_2'length = cryin'length) + report "Addends of Full_Add are not the same length as the CryIn." + severity error; + -- synopsys translate_on + sum_result := add_1 xor add_2 xor cryin; + carry_result := (add_1 and add_2) or + (add_1 and cryin) or + (add_2 and cryin); + sum <= sum_result ; + carry <= carry_result ; + end full_add; + + -- Ripple adder function + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ; + signal carry : out std_ulogic ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(0 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 1 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + sum <= result ; + carry <= c(c'left) ; + end ripple_adder ; + + procedure ripple_adder + ( add_1 : in std_ulogic_vector ; + add_2 : in std_ulogic_vector ; + signal sum : out std_ulogic_vector ) + is + -- Synopsys translate_off + attribute unroll_loop : boolean; + attribute unroll_loop of ripple : label is true; + -- Synopsys translate_on + variable a : std_ulogic_vector(1 to add_1'length) ; + variable b : std_ulogic_vector(1 to add_2'length) ; + variable c : std_ulogic_vector(1 to add_1'length) ; + variable result : std_ulogic_vector(1 to add_1'length) ; + begin + a := add_1; + b := add_2; + c(c'right) := '0' ; + ripple:for i in result'right downto 2 loop + c(i-1) := ( c(i) and a(i) ) or + ( c(i) and b(i) ) or + ( a(i) and b(i) ) ; + result(i) := a(i) xor b(i) xor c(i) ; + end loop ; + result(1) := a(1) xor b(1) xor c(1) ; + sum <= result ; + end ripple_adder ; + + -- Dot Functions + function dot_and + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end dot_and ; + + function dot_or + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '0'; + for i in in0'range loop + result := in0(i) or result ; + end loop ; + return result; + end dot_or ; + + function clock_tree_dot + (in0 : std_ulogic_vector ) + return std_ulogic + is + variable result : std_ulogic ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + + function clock_tree_dot + (in0 : bit_vector ) + return bit + is + variable result : bit ; + begin + result := '1'; + for i in in0'range loop + result := in0(i) and result ; + end loop ; + return result; + end clock_tree_dot ; + +end std_ulogic_function_support; + diff --git a/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl index 130997f..19cfbfa 100644 --- a/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl @@ -1,1517 +1,1517 @@ ---*************************************************************************** --- Copyright 2020 International Business Machines --- --- Licensed under the Apache License, Version 2.0 (the “License”); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- http://www.apache.org/licenses/LICENSE-2.0 --- --- The patent license granted to you in Section 3 of the License, as applied --- to the “Work,” hereby includes implementations of the Work in physical form. --- --- Unless required by applicable law or agreed to in writing, the reference design --- distributed under the License is distributed on an “AS IS” BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ---*************************************************************************** -library ibm,ieee ; -use ieee.std_logic_1164.all ; -use ibm.std_ulogic_support.all; - -package std_ulogic_mux_support is - - -- Multiplexor/Selector Functions - function mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of mux_2to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_2to1 : function is 1; - attribute pin_bit_information of mux_2to1 : function is - (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of mux_4to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_4to1 : function is 1; - attribute pin_bit_information of mux_4to1 : function is - (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of mux_8to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_8to1 : function is 1; - attribute pin_bit_information of mux_8to1 : function is - (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), - 10 => (" ","PASS "," "," "), - 11 => (" ","PASS "," "," "), - 12 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_2to1 : function is 1; - attribute pin_bit_information of not_mux_2to1 : function is - (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","PASS "," "," "), - 5 => (" ","PASS "," "," "), - 6 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_4to1 : function is 1; - attribute pin_bit_information of not_mux_4to1 : function is - (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","PASS "," "," "), - 7 => (" ","PASS "," "," "), - 8 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_8to1 : function is 1; - attribute pin_bit_information of not_mux_8to1 : function is - (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), - 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), - 10 => (" ","PASS "," "," "), - 11 => (" ","PASS "," "," "), - 12 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - -- Primitive selector input functions - function select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of select_1of2 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of2 : function is 1; - attribute pin_bit_information of select_1of2 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of select_1of3 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of3 : function is 1; - attribute pin_bit_information of select_1of3 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of select_1of4 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of4 : function is 1; - attribute pin_bit_information of select_1of4 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic ; - gate4 : std_ulogic ; - in4 : std_ulogic ; - gate5 : std_ulogic ; - in5 : std_ulogic ; - gate6 : std_ulogic ; - in6 : std_ulogic ; - gate7 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector ; - gate4 : std_ulogic ; - in4 : std_ulogic_vector ; - gate5 : std_ulogic ; - in5 : std_ulogic_vector ; - gate6 : std_ulogic ; - in6 : std_ulogic_vector ; - gate7 : std_ulogic ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of select_1of8 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of8 : function is 1; - attribute pin_bit_information of select_1of8 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), - 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), - 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), - 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), - 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), - 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), - 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), - 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), - 17 => (" ","PASS "," "," "), - 18 => (" ","PASS "," "," "), - 19 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of2 : function is 1; - attribute pin_bit_information of not_select_1of2 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","PASS "," "," "), - 6 => (" ","PASS "," "," "), - 7 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of3 : function is 1; - attribute PIN_BIT_INFORMATION of not_select_1of3 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","PASS "," "," "), - 8 => (" ","PASS "," "," "), - 9 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of4 : function is 1; - attribute pin_bit_information of not_select_1of4 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","PASS "," "," "), - 10 => (" ","PASS "," "," "), - 11 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - - function not_select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic ; - gate4 : std_ulogic ; - in4 : std_ulogic ; - gate5 : std_ulogic ; - in5 : std_ulogic ; - gate6 : std_ulogic ; - in6 : std_ulogic ; - gate7 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic ; - - function not_select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector ; - gate4 : std_ulogic ; - in4 : std_ulogic_vector ; - gate5 : std_ulogic ; - in5 : std_ulogic_vector ; - gate6 : std_ulogic ; - in6 : std_ulogic_vector ; - gate7 : std_ulogic ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector ; - -- synopsys translate_off - attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of8 : function is 1; - attribute pin_bit_information of not_select_1of8 : function is - (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), - 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), - 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), - 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), - 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), - 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), - 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), - 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), - 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), - 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), - 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), - 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), - 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), - 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), - 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), - 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), - 17 => (" ","PASS "," "," "), - 18 => (" ","PASS "," "," "), - 19 => (" ","INV ","SAME","PIN_BIT_VECTOR")); - -- synopsys translate_on - -end std_ulogic_mux_support; - --- The Source code for this program is not published or otherwise -package body std_ulogic_mux_support is - - -- Multiplexor/Selector Functions - function mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when '0' => result := in0; - when '1' => result := in1; - when others => result := 'X'; - end case; - return result; - end mux_2to1 ; - - function mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when '0' => result := in0; - when '1' => result := in1; - when others => result := (others => 'X'); - end case; - return result; - end mux_2to1 ; - - function mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when "00" => result := in0; - when "01" => result := in1; - when "10" => result := in2; - when "11" => result := in3; - when others => result := 'X'; - end case; - return result; - end mux_4to1 ; - - function mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when "00" => result := in0; - when "01" => result := in1; - when "10" => result := in2; - when "11" => result := in3; - when others => result := (others => 'X'); - end case; - return result; - end mux_4to1 ; - - function mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when "000" => result := in0; - when "001" => result := in1; - when "010" => result := in2; - when "011" => result := in3; - when "100" => result := in4; - when "101" => result := in5; - when "110" => result := in6; - when "111" => result := in7; - when others => result := 'X'; - end case; - return result; - end mux_8to1 ; - - function mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when "000" => result := in0; - when "001" => result := in1; - when "010" => result := in2; - when "011" => result := in3; - when "100" => result := in4; - when "101" => result := in5; - when "110" => result := in6; - when "111" => result := in7; - when others => result := (others => 'X'); - end case; - return result; - end mux_8to1 ; - - -- Inverted Multiplexor Selector/Functions - function not_mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when '0' => result := not in0; - when '1' => result := not in1; - when others => result := 'X'; - end case; - return result; - end not_mux_2to1 ; - - function not_mux_2to1 - (code : std_ulogic ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when '0' => result := not in0; - when '1' => result := not in1; - when others => result := (others => 'X'); - end case; - return result; - end not_mux_2to1 ; - - function not_mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when "00" => result := not in0; - when "01" => result := not in1; - when "10" => result := not in2; - when "11" => result := not in3; - when others => result := 'X'; - end case; - return result; - end not_mux_4to1 ; - - function not_mux_4to1 - (code : std_ulogic_vector(0 to 1) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when "00" => result := not in0; - when "01" => result := not in1; - when "10" => result := not in2; - when "11" => result := not in3; - when others => result := (others => 'X'); - end case; - return result; - end not_mux_4to1 ; - - function not_mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic ; - in1 : std_ulogic ; - in2 : std_ulogic ; - in3 : std_ulogic ; - in4 : std_ulogic ; - in5 : std_ulogic ; - in6 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic; - begin - case code is - when "000" => result := not in0; - when "001" => result := not in1; - when "010" => result := not in2; - when "011" => result := not in3; - when "100" => result := not in4; - when "101" => result := not in5; - when "110" => result := not in6; - when "111" => result := not in7; - when others => result := 'X'; - end case; - return result; - end not_mux_8to1 ; - - function not_mux_8to1 - (code : std_ulogic_vector(0 to 2) ; - in0 : std_ulogic_vector ; - in1 : std_ulogic_vector ; - in2 : std_ulogic_vector ; - in3 : std_ulogic_vector ; - in4 : std_ulogic_vector ; - in5 : std_ulogic_vector ; - in6 : std_ulogic_vector ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - case code is - when "000" => result := not in0; - when "001" => result := not in1; - when "010" => result := not in2; - when "011" => result := not in3; - when "100" => result := not in4; - when "101" => result := not in5; - when "110" => result := not in6; - when "111" => result := not in7; - when others => result := (others => 'X'); - end case; - return result; - end not_mux_8to1 ; - - -- Vectored primitive selector input functions - function select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ); - return result ; - end select_1of2 ; - - function select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector(0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ); - return result ; - end select_1of2 ; - - function select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) ; - return result ; - end select_1of3 ; - - function select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in1'length-1 => gate2 ) and in2 ); - return result ; - end select_1of3 ; - - function select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ); - return result ; - end select_1of4 ; - - function select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; - return result ; - end select_1of4 ; - - function select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic ; - gate4 : std_ulogic ; - in4 : std_ulogic ; - gate5 : std_ulogic ; - in5 : std_ulogic ; - gate6 : std_ulogic ; - in6 : std_ulogic ; - gate7 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ) or - ( gate4 and in4 ) or - ( gate5 and in5 ) or - ( gate6 and in6 ) or - ( gate7 and in7 ) ; - return result ; - end select_1of8 ; - - function select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector ; - gate4 : std_ulogic ; - in4 : std_ulogic_vector ; - gate5 : std_ulogic ; - in5 : std_ulogic_vector ; - gate6 : std_ulogic ; - in6 : std_ulogic_vector ; - gate7 : std_ulogic ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) or - ( ( 0 to in4'length-1 => gate4 ) and in4 ) or - ( ( 0 to in5'length-1 => gate5 ) and in5 ) or - ( ( 0 to in6'length-1 => gate6 ) and in6 ) or - ( ( 0 to in7'length-1 => gate7 ) and in7 ) ; - return result ; - end select_1of8 ; - - function not_select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) ) ; - return result ; - end not_select_1of2 ; - - function not_select_1of2 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) ) ; - return result ; - end not_select_1of2 ; - - function not_select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) ) ; - return result ; - end not_select_1of3 ; - - function not_select_1of3 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in1'length-1 => gate2 ) and in2 ) ) ; - return result ; - end not_select_1of3 ; - - function not_select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ) ) ; - return result ; - end not_select_1of4 ; - - function not_select_1of4 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; - return result ; - end not_select_1of4 ; - - function not_select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic ; - gate1 : std_ulogic ; - in1 : std_ulogic ; - gate2 : std_ulogic ; - in2 : std_ulogic ; - gate3 : std_ulogic ; - in3 : std_ulogic ; - gate4 : std_ulogic ; - in4 : std_ulogic ; - gate5 : std_ulogic ; - in5 : std_ulogic ; - gate6 : std_ulogic ; - in6 : std_ulogic ; - gate7 : std_ulogic ; - in7 : std_ulogic - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic ; - begin - result := not( ( gate0 and in0 ) or - ( gate1 and in1 ) or - ( gate2 and in2 ) or - ( gate3 and in3 ) or - ( gate4 and in4 ) or - ( gate5 and in5 ) or - ( gate6 and in6 ) or - ( gate7 and in7 ) ) ; - return result ; - end not_select_1of8 ; - - function not_select_1of8 - (gate0 : std_ulogic ; - in0 : std_ulogic_vector ; - gate1 : std_ulogic ; - in1 : std_ulogic_vector ; - gate2 : std_ulogic ; - in2 : std_ulogic_vector ; - gate3 : std_ulogic ; - in3 : std_ulogic_vector ; - gate4 : std_ulogic ; - in4 : std_ulogic_vector ; - gate5 : std_ulogic ; - in5 : std_ulogic_vector ; - gate6 : std_ulogic ; - in6 : std_ulogic_vector ; - gate7 : std_ulogic ; - in7 : std_ulogic_vector - -- synopsys translate_off - ;btr : string := "" - ;blkdata : string := "" - -- synopsys translate_on - ) return std_ulogic_vector - is - variable block_data : string(1 to 1) ; - -- synopsys translate_off - attribute dynamic_block_data of block_data : variable is - "CUE_BTR=/" & BTR & "/" & - BLKDATA ; - -- synopsys translate_on - variable result : std_ulogic_vector (0 to in0'length-1); - begin - result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or - ( ( 0 to in1'length-1 => gate1 ) and in1 ) or - ( ( 0 to in2'length-1 => gate2 ) and in2 ) or - ( ( 0 to in3'length-1 => gate3 ) and in3 ) or - ( ( 0 to in4'length-1 => gate4 ) and in4 ) or - ( ( 0 to in5'length-1 => gate5 ) and in5 ) or - ( ( 0 to in6'length-1 => gate6 ) and in6 ) or - ( ( 0 to in7'length-1 => gate7 ) and in7 ) ) ; - return result ; - end not_select_1of8 ; - -end std_ulogic_mux_support; +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ibm,ieee ; +use ieee.std_logic_1164.all ; +use ibm.std_ulogic_support.all; + +package std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_2to1 : function is 1; + attribute pin_bit_information of mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_4to1 : function is 1; + attribute pin_bit_information of mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of mux_8to1 : function is 1; + attribute pin_bit_information of mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_2to1 : function is 1; + attribute pin_bit_information of not_mux_2to1 : function is + (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","PASS "," "," "), + 5 => (" ","PASS "," "," "), + 6 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_4to1 : function is 1; + attribute pin_bit_information of not_mux_4to1 : function is + (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","PASS "," "," "), + 7 => (" ","PASS "," "," "), + 8 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ; + attribute recursive_synthesis of not_mux_8to1 : function is 1; + attribute pin_bit_information of not_mux_8to1 : function is + (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 4 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 6 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 8 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 10 => (" ","PASS "," "," "), + 11 => (" ","PASS "," "," "), + 12 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + -- Primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of2 : function is 1; + attribute pin_bit_information of select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of3 : function is 1; + attribute pin_bit_information of select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of4 : function is 1; + attribute pin_bit_information of select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of select_1of8 : function is 1; + attribute pin_bit_information of select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","OUT ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of2 : function is 1; + attribute pin_bit_information of not_select_1of2 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","PASS "," "," "), + 6 => (" ","PASS "," "," "), + 7 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of3 : function is 1; + attribute PIN_BIT_INFORMATION of not_select_1of3 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","PASS "," "," "), + 8 => (" ","PASS "," "," "), + 9 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of4 : function is 1; + attribute pin_bit_information of not_select_1of4 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","PASS "," "," "), + 10 => (" ","PASS "," "," "), + 11 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector ; + -- synopsys translate_off + attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ; + attribute recursive_synthesis of not_select_1of8 : function is 1; + attribute pin_bit_information of not_select_1of8 : function is + (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), + 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), + 3 => (" ","S1 ","SAME","PIN_BIT_SCALAR"), + 4 => (" ","D1 ","SAME","PIN_BIT_VECTOR"), + 5 => (" ","S2 ","SAME","PIN_BIT_SCALAR"), + 6 => (" ","D2 ","SAME","PIN_BIT_VECTOR"), + 7 => (" ","S3 ","SAME","PIN_BIT_SCALAR"), + 8 => (" ","D3 ","SAME","PIN_BIT_VECTOR"), + 9 => (" ","S4 ","SAME","PIN_BIT_SCALAR"), + 10 => (" ","D4 ","SAME","PIN_BIT_VECTOR"), + 11 => (" ","S5 ","SAME","PIN_BIT_SCALAR"), + 12 => (" ","D5 ","SAME","PIN_BIT_VECTOR"), + 13 => (" ","S6 ","SAME","PIN_BIT_SCALAR"), + 14 => (" ","D6 ","SAME","PIN_BIT_VECTOR"), + 15 => (" ","S7 ","SAME","PIN_BIT_SCALAR"), + 16 => (" ","D7 ","SAME","PIN_BIT_VECTOR"), + 17 => (" ","PASS "," "," "), + 18 => (" ","PASS "," "," "), + 19 => (" ","INV ","SAME","PIN_BIT_VECTOR")); + -- synopsys translate_on + +end std_ulogic_mux_support; + +-- The Source code for this program is not published or otherwise +package body std_ulogic_mux_support is + + -- Multiplexor/Selector Functions + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := 'X'; + end case; + return result; + end mux_2to1 ; + + function mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := in0; + when '1' => result := in1; + when others => result := (others => 'X'); + end case; + return result; + end mux_2to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := 'X'; + end case; + return result; + end mux_4to1 ; + + function mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := in0; + when "01" => result := in1; + when "10" => result := in2; + when "11" => result := in3; + when others => result := (others => 'X'); + end case; + return result; + end mux_4to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := 'X'; + end case; + return result; + end mux_8to1 ; + + function mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := in0; + when "001" => result := in1; + when "010" => result := in2; + when "011" => result := in3; + when "100" => result := in4; + when "101" => result := in5; + when "110" => result := in6; + when "111" => result := in7; + when others => result := (others => 'X'); + end case; + return result; + end mux_8to1 ; + + -- Inverted Multiplexor Selector/Functions + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := 'X'; + end case; + return result; + end not_mux_2to1 ; + + function not_mux_2to1 + (code : std_ulogic ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when '0' => result := not in0; + when '1' => result := not in1; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_2to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := 'X'; + end case; + return result; + end not_mux_4to1 ; + + function not_mux_4to1 + (code : std_ulogic_vector(0 to 1) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "00" => result := not in0; + when "01" => result := not in1; + when "10" => result := not in2; + when "11" => result := not in3; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_4to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic ; + in1 : std_ulogic ; + in2 : std_ulogic ; + in3 : std_ulogic ; + in4 : std_ulogic ; + in5 : std_ulogic ; + in6 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic; + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := 'X'; + end case; + return result; + end not_mux_8to1 ; + + function not_mux_8to1 + (code : std_ulogic_vector(0 to 2) ; + in0 : std_ulogic_vector ; + in1 : std_ulogic_vector ; + in2 : std_ulogic_vector ; + in3 : std_ulogic_vector ; + in4 : std_ulogic_vector ; + in5 : std_ulogic_vector ; + in6 : std_ulogic_vector ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + case code is + when "000" => result := not in0; + when "001" => result := not in1; + when "010" => result := not in2; + when "011" => result := not in3; + when "100" => result := not in4; + when "101" => result := not in5; + when "110" => result := not in6; + when "111" => result := not in7; + when others => result := (others => 'X'); + end case; + return result; + end not_mux_8to1 ; + + -- Vectored primitive selector input functions + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ); + return result ; + end select_1of2 ; + + function select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector(0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ); + return result ; + end select_1of2 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ; + return result ; + end select_1of3 ; + + function select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ); + return result ; + end select_1of3 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ); + return result ; + end select_1of4 ; + + function select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ; + return result ; + end select_1of4 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ; + return result ; + end select_1of8 ; + + function select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ; + return result ; + end select_1of8 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of2 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) ) ; + return result ; + end not_select_1of2 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of3 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in1'length-1 => gate2 ) and in2 ) ) ; + return result ; + end not_select_1of3 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of4 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) ) ; + return result ; + end not_select_1of4 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic ; + gate1 : std_ulogic ; + in1 : std_ulogic ; + gate2 : std_ulogic ; + in2 : std_ulogic ; + gate3 : std_ulogic ; + in3 : std_ulogic ; + gate4 : std_ulogic ; + in4 : std_ulogic ; + gate5 : std_ulogic ; + in5 : std_ulogic ; + gate6 : std_ulogic ; + in6 : std_ulogic ; + gate7 : std_ulogic ; + in7 : std_ulogic + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic ; + begin + result := not( ( gate0 and in0 ) or + ( gate1 and in1 ) or + ( gate2 and in2 ) or + ( gate3 and in3 ) or + ( gate4 and in4 ) or + ( gate5 and in5 ) or + ( gate6 and in6 ) or + ( gate7 and in7 ) ) ; + return result ; + end not_select_1of8 ; + + function not_select_1of8 + (gate0 : std_ulogic ; + in0 : std_ulogic_vector ; + gate1 : std_ulogic ; + in1 : std_ulogic_vector ; + gate2 : std_ulogic ; + in2 : std_ulogic_vector ; + gate3 : std_ulogic ; + in3 : std_ulogic_vector ; + gate4 : std_ulogic ; + in4 : std_ulogic_vector ; + gate5 : std_ulogic ; + in5 : std_ulogic_vector ; + gate6 : std_ulogic ; + in6 : std_ulogic_vector ; + gate7 : std_ulogic ; + in7 : std_ulogic_vector + -- synopsys translate_off + ;btr : string := "" + ;blkdata : string := "" + -- synopsys translate_on + ) return std_ulogic_vector + is + variable block_data : string(1 to 1) ; + -- synopsys translate_off + attribute dynamic_block_data of block_data : variable is + "CUE_BTR=/" & BTR & "/" & + BLKDATA ; + -- synopsys translate_on + variable result : std_ulogic_vector (0 to in0'length-1); + begin + result := not( ( ( 0 to in0'length-1 => gate0 ) and in0 ) or + ( ( 0 to in1'length-1 => gate1 ) and in1 ) or + ( ( 0 to in2'length-1 => gate2 ) and in2 ) or + ( ( 0 to in3'length-1 => gate3 ) and in3 ) or + ( ( 0 to in4'length-1 => gate4 ) and in4 ) or + ( ( 0 to in5'length-1 => gate5 ) and in5 ) or + ( ( 0 to in6'length-1 => gate6 ) and in6 ) or + ( ( 0 to in7'length-1 => gate7 ) and in7 ) ) ; + return result ; + end not_select_1of8 ; + +end std_ulogic_mux_support; diff --git a/rel/src/vhdl/ibm/std_ulogic_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_support.vhdl index fd7d1b6..2bc8f92 100644 --- a/rel/src/vhdl/ibm/std_ulogic_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_support.vhdl @@ -1,2678 +1,2678 @@ ---*************************************************************************** --- Copyright 2020 International Business Machines --- --- Licensed under the Apache License, Version 2.0 (the “License”); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- http://www.apache.org/licenses/LICENSE-2.0 --- --- The patent license granted to you in Section 3 of the License, as applied --- to the “Work,” hereby includes implementations of the Work in physical form. --- --- Unless required by applicable law or agreed to in writing, the reference design --- distributed under the License is distributed on an “AS IS” BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ---*************************************************************************** -library ieee, ibm ; -use ieee.std_logic_1164.all ; -use ieee.numeric_std.all ; - -package std_ulogic_support is - - attribute like_builtin: boolean; - attribute dc_allow: boolean; - attribute type_convert: boolean; - attribute recursive_synthesis: boolean; - attribute functionality: string; - attribute btr_name: string; - attribute block_data: string; - type pbi_el_t is array(0 to 3) of string; - type pbi_t is array(integer range <>) of pbi_el_t; - attribute pin_bit_information: pbi_t; - attribute dynamic_block_data: string; - - type base_t is ( bin, oct, dec, hex ); - - ------------------------------------------------------------------- - -- Overloaded Relational Operator that can return std_ulogic - ------------------------------------------------------------------- - function "=" ( l,r : integer ) return std_ulogic; - function "/=" ( l,r : integer ) return std_ulogic; - function ">" ( l,r : integer ) return std_ulogic; - function ">=" ( l,r : integer ) return std_ulogic; - function "<" ( l,r : integer ) return std_ulogic; - function "<=" ( l,r : integer ) return std_ulogic; - - function "=" ( l,r : std_ulogic ) return std_ulogic; - function "/=" ( l,r : std_ulogic ) return std_ulogic; - function ">" ( l,r : std_ulogic ) return std_ulogic; - function ">=" ( l,r : std_ulogic ) return std_ulogic; - function "<" ( l,r : std_ulogic ) return std_ulogic; - function "<=" ( l,r : std_ulogic ) return std_ulogic; - - function "=" ( l, r : std_ulogic_vector ) return std_ulogic; - function "/=" ( l, r : std_ulogic_vector ) return std_ulogic; - function ">" ( l, r : std_ulogic_vector ) return std_ulogic; - function ">=" ( l, r : std_ulogic_vector ) return std_ulogic; - function "<" ( l, r : std_ulogic_vector ) return std_ulogic; - function "<=" ( l, r : std_ulogic_vector ) return std_ulogic; --- synopsys translate_off - attribute like_builtin of "=" :function is true; - attribute like_builtin of "/=" :function is true; - attribute like_builtin of ">" :function is true; - attribute like_builtin of ">=" :function is true; - attribute like_builtin of "<" :function is true; - attribute like_builtin of "<=" :function is true; --- Synopsys translate_on - ------------------------------------------------------------------- - -- Relational Functions that can return Boolean - ------------------------------------------------------------------- - function eq( l,r : std_ulogic ) return boolean; - function ne( l,r : std_ulogic ) return boolean; - function gt( l,r : std_ulogic ) return boolean; - function ge( l,r : std_ulogic ) return boolean; - function lt( l,r : std_ulogic ) return boolean; - function le( l,r : std_ulogic ) return boolean; - - ------------------------------------------------------------------- - -- Relational Functions that can return std_ulogic - ------------------------------------------------------------------- - - function eq( l,r : std_ulogic ) return std_ulogic; - function ne( l,r : std_ulogic ) return std_ulogic; - function gt( l,r : std_ulogic ) return std_ulogic; - function ge( l,r : std_ulogic ) return std_ulogic; - function lt( l,r : std_ulogic ) return std_ulogic; - function le( l,r : std_ulogic ) return std_ulogic; - - ------------------------------------------------------------------- - -- Vectorized Relational Functions - ------------------------------------------------------------------- - - function eq( l,r : std_ulogic_vector ) return boolean; - function ne( l,r : std_ulogic_vector ) return boolean; - function gt( l,r : std_ulogic_vector ) return boolean; - function ge( l,r : std_ulogic_vector ) return boolean; - function lt( l,r : std_ulogic_vector ) return boolean; - function le( l,r : std_ulogic_vector ) return boolean; - - function eq( l,r : std_ulogic_vector ) return std_ulogic; - function ne( l,r : std_ulogic_vector ) return std_ulogic; - function gt( l,r : std_ulogic_vector ) return std_ulogic; - function ge( l,r : std_ulogic_vector ) return std_ulogic; - function lt( l,r : std_ulogic_vector ) return std_ulogic; - function le( l,r : std_ulogic_vector ) return std_ulogic; --- Synopsys translate_off - attribute functionality of eq : function is "="; - attribute functionality of ne : function is "/="; - attribute functionality of gt : function is ">"; - attribute functionality of ge : function is ">="; - attribute functionality of lt : function is "<"; - attribute functionality of le : function is "<="; - - attribute dc_allow of eq : function is true; - attribute dc_allow of ne : function is true; --- Synopsys translate_on - - ------------------------------------------------------------------- - -- Type Conversion Functions - ------------------------------------------------------------------- - - -- Boolean conversion to other types - function tconv( b : boolean ) return bit; - function tconv( b : boolean ) return std_ulogic; --- Synopsys translate_off - function tconv( b : boolean ) return string; --- Synopsys translate_on - - -- Bit to other types - function tconv( b : bit ) return boolean; - function tconv( b : bit ) return integer; - function tconv( b : bit ) return std_ulogic; --- Synopsys translate_off - function tconv( b : bit ) return character; - function tconv( b : bit ) return string; --- Synopsys translate_on - - -- Bit_vector to other types - function tconv( b : bit_vector ) return integer; - function tconv( b : bit_vector ) return std_ulogic_vector; --- function tconv( b : bit_vector ) return std_logic_vector; --- synopsys translate_off - function tconv( b : bit_vector ) return string; - function tconv( b : bit_vector; base : base_t ) return string; --- synopsys translate_on - - -- Integer conversion to other types - function tconv( n : integer; w: positive ) return bit_vector ; - function tconv( n : integer; w: positive ) return std_ulogic_vector ; --- synopsys translate_off - function tconv( n : integer; w: positive ) return string ; - function tconv( n : integer ) return string ; --- synopsys translate_on - --- Synopsys translate_off - -- String conversion to other types - function tconv( s : string ) return integer ; - function tconv( s : string; base : base_t ) return integer ; - function tconv( s : string ) return bit ; - function tconv( s : string ) return bit_vector ; - function tconv( s : string; base : base_t ) return bit_vector ; - function tconv( s : string ) return std_ulogic ; - function tconv( s : string ) return std_ulogic_vector ; - function tconv( s : string; base : base_t ) return std_ulogic_vector ; --- Synopsys translate_on - - -- Std_uLogic to other types - function tconv( s : std_ulogic ) return boolean; - function tconv( s : std_ulogic ) return bit; - function tconv( s : std_ulogic ) return integer; - function tconv( s : std_ulogic ) return std_ulogic_vector; --- synopsys translate_off - function tconv( s : std_ulogic ) return character; - function tconv( s : std_ulogic ) return string; --- synopsys translate_on - - -- std_ulogic_vector to other types - function tconv( s : std_ulogic_vector ) return bit_vector; - function tconv( s : std_ulogic_vector ) return std_logic_vector; - function tconv( s : std_ulogic_vector ) return integer; - function tconv( s : std_ulogic_vector ) return std_ulogic; --- synopsys translate_off - function tconv( s : std_ulogic_vector ) return string; - function tconv( s : std_ulogic_vector; base : base_t ) return string; --- synopsys translate_on - - -- std_logic_vector to other types --- function tconv( s : std_logic_vector ) return bit_vector; --- function tconv( s : std_logic_vector ) return std_ulogic_vector; --- function tconv( s : std_logic_vector ) return integer; --- synopsys translate_off --- function tconv( s : std_logic_vector ) return string; --- function tconv( s : std_logic_vector; base : base_t ) return string; --- synopsys translate_on - --- synopsys translate_off - function hexstring( d : std_ulogic_vector ) return string ; - function octstring( d : std_ulogic_vector ) return string ; - function bitstring( d : std_ulogic_vector ) return string ; --- synopsys translate_on - - ------------------------------------------------------------------- - -- HIS ATTRIBUTEs for Type Conversion Functions - ------------------------------------------------------------------- --- Synopsys translate_off - attribute type_convert of tconv : function is true; - - ------------------------------------------------------------------- - -- synthesis ATTRIBUTEs for Type Conversion Functions - ------------------------------------------------------------------- - - attribute btr_name of tconv : function is "PASS"; - attribute pin_bit_information of tconv : function is - (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), - 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); --- Synopsys translate_on - - --============================================================================ - -- Match Functions - --============================================================================ - - function std_match (l, r: std_ulogic) return std_ulogic; - function std_match (l, r: std_ulogic_vector) return std_ulogic; - --- Synopsys translate_off - attribute functionality of std_match : function is "="; - attribute dc_allow of std_match : function is true; --- Synopsys translate_on ---============================================================== - -- Shift and Rotate Functions ---============================================================== - - -- Id: S.1 - function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: Performs a shift-left on an std_ulogic_vector vector COUNT times. - -- The vacated positions are filled with '0'. - -- The COUNT leftmost elements are lost. - - -- Id: S.2 - function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: Performs a shift-right on an std_ulogic_vector vector COUNT times. - -- The vacated positions are filled with '0'. - -- The COUNT rightmost elements are lost. - - -- Id: S.5 - function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: Performs a rotate-left of an std_ulogic_vector vector COUNT times. - - -- Id: S.6 - function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: Performs a rotate-right of an std_ulogic_vector vector COUNT times. - - -- Id: S.9 - function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: SHIFT_LEFT(ARG, COUNT) - - -- Id: S.11 - function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: SHIFT_RIGHT(ARG, COUNT) - - -- Id: S.13 - function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: ROTATE_LEFT(ARG, COUNT) - - -- Id: S.15 - function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; - -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) - -- Result: ROTATE_RIGHT(ARG, COUNT) - --=========================================================== - --End shift and rotate functions............................. - --=========================================================== -end std_ulogic_support ; - -package body std_ulogic_support is - - ------------------------------------------------------------------- - -- Look Up tables for operator overloading - ------------------------------------------------------------------- - -- Types used for overloaded operator lookup tables - ------------------------------------------------------------------- - --- Synopsys synthesis_off - type std_ulogic_to_character_type is array( std_ulogic ) of character; - - constant std_ulogic_to_character : std_ulogic_to_character_type := - ( 'U','X','0','1','Z','W','L','H','-'); - - type stdlogic_2d is array ( std_ulogic, std_ulogic ) of std_ulogic; - type b_stdlogic_2d is array ( std_ulogic, std_ulogic ) of boolean; --- Synopsys synthesis_on - ------------------------------------------------------------------- - -- Logic operation lookup tables - ------------------------------------------------------------------- --- Synopsys synthesis_off - -- LessThan Logic Operator - - constant lt_table : stdlogic_2D := ( - -- RHS U X 0 1 Z W L H - | - -- LHS ---------------------------------------------------+--- - ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X - ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W - ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - - others=>(others=>'-') - ); - - constant b_lt_table : b_stdlogic_2D := ( - 'U'=>( others=>false ), - 'X'=>( others=>false ), - '0'=>( '1'=>true, 'H'=>true, others=>false ), - '1'=>( others=>false ), - 'Z'=>( others=>false ), - 'W'=>( others=>false ), - 'L'=>( '1'=>true, 'H'=>true, others=>false ), - 'H'=>( others=>false ), - '-'=>( others=>false ), - others=>( others=>false ) - ); - - -- LessThanorEqual Logic Operator - - constant le_table : stdlogic_2D := ( - -- RHS U X 0 1 Z W L H - | - -- LHS ---------------------------------------------------+--- - ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X - ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 0 - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W - ( 'U', 'X', '1', '1', 'X', 'X', '0', '1', 'X' ), -- | L - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - - others=>(others=>'-') - ); - - constant b_le_table : b_stdlogic_2D := ( - -- RHS => - 0 U X 1 Z W L H - -- LHS -------------------------------------------------------------------------------------------------- - 'U'=>( others=>false ), - 'X'=>( others=>false ), - '0'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), - '1'=>( '1'=>true, 'H'=>true, others=>false ), - 'Z'=>( others=>false ), - 'W'=>( others=>false ), - 'L'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), - 'H'=>( '1'=>true, 'H'=>true, others=>false ), - '-'=>( others=>false ), - others=>( others=>false ) - ); - - -- GreaterThan Logic Operator - - constant gt_table : stdlogic_2D := ( - -- RHS U X 0 1 Z W L H - | - -- LHS ---------------------------------------------------+--- - ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 - ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W - ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L - ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - - others=>(others=>'-') - ); - - constant b_gt_table : b_stdlogic_2D := ( - -- LHS => ( RHS ) - 'U'=>( others=>false ), - 'X'=>( others=>false ), - '0'=>( others=>false ), - '1'=>( '0'=>true, 'L'=>true, others=>false ), - 'Z'=>( others=>false ), - 'W'=>( others=>false ), - 'L'=>( others=>false ), - 'H'=>( '0'=>true, 'L'=>true, others=>false ), - '-'=>( others=>false ), - others=>(others=>false)); - - -- GreaterThanorEqual Logic Operator - - constant ge_table : stdlogic_2D := ( - -- RHS U X 0 1 Z W L H - | - -- LHS ---------------------------------------------------+--- - ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X - ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 - ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 1 - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W - ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L - ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | H - ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - - others=>(others=>'-') - ); - - constant b_ge_table : b_stdlogic_2D := ( - -- RHS => - 0 U X 1 Z W L H - -- LHS -------------------------------------------------------------------------------------------------- - 'U'=>( others=>false ), - 'X'=>( others=>false ), - '0'=>( '0'=>true, 'L'=>true, others=>false ), - '1'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), - 'Z'=>( others=>false ), - 'W'=>( others=>false ), - 'L'=>( '0'=>true, 'L'=>true, others=>false ), - 'H'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), - '-'=>( others=>false ), - others=>( others=>false ) - ); --- Synopsys synthesis_on - - ------------------------------------------------------------------- - -- Relational Functions returning Boolean - ------------------------------------------------------------------- - - function eq( l,r : std_ulogic ) return boolean is - begin - return std_match( l, r ); - end eq; - - function ne( l,r : std_ulogic ) return boolean is - begin - return not( std_match( l, r ) ); - end ne; - - function gt( l,r : std_ulogic ) return boolean is - variable result : boolean; - -- pragma built_in SYN_GT - begin - -- Synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := b_gt_table( l, r ); - -- Synopsys translate_on - return result; - end gt; - - function ge( l,r : std_ulogic ) return boolean is - variable result : boolean; - -- pragma built_in SYN_GEQ - begin - -- synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := b_ge_table( l, r ); - -- synopsys translate_on - return result; - end ge; - - function lt( l,r : std_ulogic ) return boolean is - variable result : boolean; - -- pragma built_in SYN_LT - begin - -- synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := b_lt_table( l, r ); - -- synopsys translate_on - return result; - end lt; - - function le( l,r : std_ulogic ) return boolean is - variable result : boolean; - -- pragma built_in SYN_LEQ - begin - -- synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := b_le_table( l, r ); - -- synopsys translate_on - return result; - end le; - - ------------------------------------------------------------------- - -- Relational Functions returning std_ulogic - ------------------------------------------------------------------- - - function eq( l,r : std_ulogic ) return std_ulogic is - begin - return std_match( l, r ); - end eq; - - function ne( l,r : std_ulogic ) return std_ulogic is - begin - return not std_match( l, r ) ; - end ne; - - function gt( l,r : std_ulogic ) return std_ulogic is - variable result : std_ulogic; - -- pragma built_in SYN_GT - begin - -- Synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := gt_table( l, r ); - -- synopsys translate_on - return result; - end gt; - - function ge( l,r : std_ulogic ) return std_ulogic is - variable result : std_ulogic; - -- pragma built_in SYN_GEQ - begin - -- Synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := ge_table( l, r ); - -- Synopsys translate_on - return result; - end ge; - - function lt( l,r : std_ulogic ) return std_ulogic is - variable result : std_ulogic; - -- pragma built_in SYN_LT - begin - -- Synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := lt_table( l, r ); - -- Synopsys translate_on - return result; - end lt; - - function le( l,r : std_ulogic ) return std_ulogic is - variable result : std_ulogic; - -- pragma built_in SYN_LEQ - begin - -- Synopsys translate_off - assert ( l /= '-' ) and ( r /= '-' ) - report "Invalid dont_care in relational function" - severity error; - result := le_table( l, r ); - -- Synopsys translate_on - return result; - end le; - - -- - -- utility function get rid of most meta values - -- - function to_x01d( d : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_FEED_THRU - variable result : std_ulogic; - begin - -- Synopsys translate_off - case d is - when '0' | 'L' => result := '0'; - when '1' | 'H' => result := '1'; - when '-' => result := '-'; - when others => result := 'X'; - end case; - -- Synopsys translate_on - return result; - end to_x01d; - - ------------------------------------------------------------------- - -- Vectored Relational Functions returning Boolean - ------------------------------------------------------------------- - function eq( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := std_match(l,r); - return result; - end eq; - - --------------------------------------------------------------------- - function ne( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := not std_match(l,r); - return result; - end ne; - - ------------------------------------------------------------------- - function gt( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := unsigned(l) > unsigned(r); - return result; - end gt; - - ------------------------------------------------------------------- - function ge( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := unsigned(l) >= unsigned(r); - return result; - end ge; - - ------------------------------------------------------------------- - function lt( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := unsigned(l) < unsigned(r); - return result; - end lt; - - ------------------------------------------------------------------- - function le( l,r : std_ulogic_vector) return boolean is - variable result : boolean ; - begin - result := unsigned(l) <= unsigned(r); - return result; - end le; - - ------------------------------------------------------------------- - -- vectored relational functions returning std_ulogic - ------------------------------------------------------------------- - function eq( l,r : std_ulogic_vector) return std_ulogic is - variable result : std_ulogic ; - begin - result := std_match( l, r ) ; - --result := (l ?= r); - return result; - end eq; - --------------------------------------------------------------------- - function ne( l,r : std_ulogic_vector) return std_ulogic is - variable result :std_ulogic ; - begin - result := not std_match( l, r ) ; - --result := not (l ?= r); - return result; - end ne; - - ------------------------------------------------------------------- - function gt( l,r : std_ulogic_vector) return std_ulogic is - variable result : boolean ; - -- pragma built_in SYN_GT - begin - result := unsigned(l) > unsigned(r); - if (result = true ) then - return '1' ; - else - return '0'; - end if ; - end gt; - - ------------------------------------------------------------------- - function ge( l,r : std_ulogic_vector) return std_ulogic is - variable result : boolean ; - -- pragma built_in SYN_GEQ - begin - result := unsigned(l) >= unsigned(r); - if (result = true ) then - return '1' ; - else - return '0'; - end if ; - end ge; - - ------------------------------------------------------------------- - function lt( l,r : std_ulogic_vector) return std_ulogic is - variable result : boolean ; - -- pragma built_in SYN_LT - begin - result := unsigned(l) < unsigned(r); - if (result = true ) then - return '1' ; - else - return '0'; - end if ; - end lt; - - ------------------------------------------------------------------- - function le( l,r : std_ulogic_vector) return std_ulogic is - variable result : boolean ; - -- pragma built_in SYN_LEQ - begin - result := unsigned(l) <= unsigned(r); - if (result = true ) then - return '1' ; - else - return '0'; - end if ; - end le; - - ------------------------------------------------------------------- - -- Type Conversion Functions - ------------------------------------------------------------------- - ------------------------------------------------------------------- - -- Boolean Conversions - ------------------------------------------------------------------- - function tconv ( b : boolean ) return bit is - -- pragma built_in SYN_FEED_THRU - begin - case b is - when false => return('0'); - when true => return('1'); - end case; - end tconv ; - --- Synopsys translate_off - function tconv ( b : boolean ) return string is - begin - case b is - when false => return("FALSE"); - when true => return("TRUE"); - end case; - end tconv ; --- Synopsys translate_on - - function tconv ( b : boolean ) return std_ulogic is - -- pragma built_in SYN_FEED_THRU - begin - case b is - when false => return('0'); - when true => return('1'); - end case; - end tconv ; - - ------------------------------------------------------------------- - -- Bit Conversions - ------------------------------------------------------------------- - function tconv ( b : bit ) return boolean is - -- pragma built_in SYN_FEED_THRU - begin - case b is - when '0' => return(false); - when '1' => return(true); - end case; - end tconv ; - --- Synopsys translate_off - function tconv ( b : bit ) return character is - begin - case b is - when '0' => return('0'); - when '1' => return('1'); - end case; - end tconv ; - - function tconv ( b : bit ) return string is - begin - case b is - when '0' => return("0"); - when '1' => return("1"); - end case; - end tconv ; --- Synopsys translate_on - - function tconv ( b : bit ) return integer is - -- pragma built_in SYN_UNSIGNED_TO_INTEGER - begin - case b is - when '0' => return(0); - when '1' => return(1); - end case; - end tconv ; - - function tconv ( b : bit ) return std_ulogic is - -- pragma built_in SYN_FEED_THRU - begin - case b is - when '0' => return('0'); - when '1' => return('1'); - end case; - end tconv ; - - ------------------------------------------------------------------- - -- Bit_vector Conversions - ------------------------------------------------------------------- - function tconv ( b : bit_vector ) return integer is - variable int_result : integer ; - variable int_exp : integer ; - variable new_value : bit_vector(1 to b'length); - -- pragma built_in SYN_UNSIGNED_TO_INTEGER - begin - -- Synopsys translate_off - int_result := 0; - int_exp := 0; - new_value := b; - for i in new_value'length to 1 loop - if b(i)='1' then - int_result := int_result + (2**int_exp); - end if; - int_exp := int_exp + 1; - end loop; - -- synopsys translate_on - return int_result; - end tconv ; - --- Synopsys translate_off - function tconv ( b : bit_vector ) return string is - alias sv : bit_vector ( 1 to b'length ) is b; - variable result : string ( 1 to b'length ); - begin - result := (others => '0'); - for i in result'range loop - case sv(i) is - when '0' => result(i) := '0'; - when '1' => result(i) := '1'; - end case; - end loop; - return result; - end tconv ; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( b : bit_vector; base : base_t ) return string is - alias sv : bit_vector ( 1 to b'length ) is b; - variable result : string ( 1 to b'length ); - variable start : positive; - variable extra : natural; - variable resultlength : positive; - subtype bv is bit_vector( 1 to 1 ); - subtype qv is bit_vector( 1 to 2 ); - subtype ov is bit_vector( 1 to 3 ); - subtype hv is bit_vector( 1 to 4 ); - begin - case base is - when bin => - resultlength := sv'length; - start := 1; - for i in start to resultlength loop - case sv( i ) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - end case; - end loop; - - when oct => - extra := sv'length rem ov'length; - case extra is - when 0 => - resultlength := b'length/ov'length; - start := 1; - when 1 => - resultlength := ( b'length/ov'length ) + 1; - start := 2; - case sv( 1 ) is - when '0' => result( 1 ) := '0'; - when '1' => result( 1 ) := '1'; - end case; - when 2 => - resultlength := ( b'length/ov'length ) + 1; - start := 2; - case qv'( sv( 1 to 2 ) ) is - when "00" => result( 1 ) := '0'; - when "01" => result( 1 ) := '1'; - when "10" => result( 1 ) := '2'; - when "11" => result( 1 ) := '3'; - end case; - when others => - assert false report "TCONV fatal condition" severity failure; - end case; - - for i in 0 to resultLength - start loop - case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is - when "000" => result( i+start ) := '0'; - when "001" => result( i+start ) := '1'; - when "010" => result( i+start ) := '2'; - when "011" => result( i+start ) := '3'; - when "100" => result( i+start ) := '4'; - when "101" => result( i+start ) := '5'; - when "110" => result( i+start ) := '6'; - when "111" => result( i+start ) := '7'; - when others => result( i+start ) := '.'; - end case; - end loop; - - when hex => - extra := b'length rem hv'length; - case extra is - when 0 => - resultLength := b'length/hv'length; - start := 1; - when 1 => - resultLength := ( b'length/hv'length ) + 1; - start := 2; - case sv( 1 ) is - when '0' => result( 1 ) := '0'; - when '1' => result( 1 ) := '1'; - end case; - when 2 => - resultLength := ( b'length/hv'length ) + 1; - start := 2; - case qv'( sv( 1 to 2 ) ) is - when "00" => result( 1 ) := '0'; - when "01" => result( 1 ) := '1'; - when "10" => result( 1 ) := '2'; - when "11" => result( 1 ) := '3'; - end case; - when 3 => - resultLength := ( b'length/hv'length ) + 1; - start := 2; - case ov'( sv( 1 to 3 ) ) is - when o"0" => result( 1 ) := '0'; - when o"1" => result( 1 ) := '1'; - when o"2" => result( 1 ) := '2'; - when o"3" => result( 1 ) := '3'; - when o"4" => result( 1 ) := '4'; - when o"5" => result( 1 ) := '5'; - when o"6" => result( 1 ) := '6'; - when o"7" => result( 1 ) := '7'; - end case; - when others => - assert false report "TCONV fatal condition" severity failure; - end case; - - for i in 0 to resultLength - start loop - case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is - when "0000" => result( i+start ) := '0'; - when "0001" => result( i+start ) := '1'; - when "0010" => result( i+start ) := '2'; - when "0011" => result( i+start ) := '3'; - when "0100" => result( i+start ) := '4'; - when "0101" => result( i+start ) := '5'; - when "0110" => result( i+start ) := '6'; - when "0111" => result( i+start ) := '7'; - when "1000" => result( i+start ) := '8'; - when "1001" => result( i+start ) := '9'; - when "1010" => result( i+start ) := 'A'; - when "1011" => result( i+start ) := 'B'; - when "1100" => result( i+start ) := 'C'; - when "1101" => result( i+start ) := 'D'; - when "1110" => result( i+start ) := 'E'; - when "1111" => result( i+start ) := 'F'; - when others => result( i+start ) := '.'; - end case; - end loop; - - when others => - assert false report "Unsupported base passed." severity warning; - - end case; - - return result( 1 to resultLength ); - end tconv ; --- Synopsys translate_on - - function tconv ( b : bit_vector ) return std_ulogic_vector is - alias sv : bit_vector ( 1 to b'length ) is b; - variable result : std_ulogic_vector ( 1 to b'length ); - -- pragma built_in SYN_FEED_THRU - begin - for i in result'range loop - case sv(i) is - when '0' => result(i) := '0'; - when '1' => result(i) := '1'; - end case; - end loop; - return result; - end tconv ; - - --function tconv ( b : bit_vector ) return std_logic_vector is - -- alias sv : bit_vector ( 1 to b'length ) is b; - -- variable result : std_logic_vector ( 1 to b'length ); - ---- pragma built_in SYN_FEED_THRU - --begin - -- for i in result'range loop - -- case sv(i) is - -- when '0' => result(i) := '0'; - -- when '1' => result(i) := '1'; - -- end case; - -- end loop; - -- return result; - --end tconv ; - - ------------------------------------------------------------------- - -- Integer conversion to other types - ------------------------------------------------------------------- - function tconv ( n : integer;w : positive) return bit_vector is - variable result : bit_vector(w-1 downto 0) ; - variable ib : integer; - variable test : integer; - -- pragma built_in SYN_INTEGER_TO_UNSIGNED - begin - if n < 0 then - result := (others => '0'); - else - ib := n; - result := (others => '0'); - for i in result'reverse_range loop - exit when ib = 0; - test := ib rem 2; - if test = 1 then - result(i) := '1'; - else - result(i) := '0'; - end if; - ib := ib / 2; - end loop; - end if; - -- synopsys translate_off - assert n >= 0 - report "tconv: n < 0 is not permitted" - severity warning; - assert ib = 0 - report "tconv: integer overflows requested result width" - severity warning; - -- synopsys translate_on - return result; - end tconv; - - function tconv ( n : integer; w : positive) return std_ulogic_vector is - variable result : std_ulogic_vector(w-1 downto 0) ; - variable ib : integer; - variable test : integer; - -- pragma built_in SYN_INTEGER_TO_UNSIGNED - begin - if n < 0 then - result := (others => 'X'); - else - ib := n; - result := (others => '0'); - for i in result'reverse_range loop - exit when ib = 0; - test := ib rem 2; - if test = 1 then - result(i) := '1'; - else - result(i) := '0'; - end if; - ib := ib / 2; - end loop; - end if; - -- Synopsys translate_off - assert n >= 0 - report "tconv: n < 0 is not permitted" - severity warning; - assert ib = 0 - report "tconv: integer overflows requested result width" - severity warning; - -- Synopsys translate_on - return result; - end tconv; - --- Synopsys translate_off - function tconv ( n : integer; w : positive ) return string is - subtype digit is integer range 0 to 9; - variable result : string( 1 to w ) ; - variable ib : integer; - variable msd : integer; - variable sign : character := '-'; - variable test : digit; - begin - ib := abs n; - for i in result'reverse_range loop - test := ib rem 10; - - case test is - when 0 => result(i) := '0'; - when 1 => result(i) := '1'; - when 2 => result(i) := '2'; - when 3 => result(i) := '3'; - when 4 => result(i) := '4'; - when 5 => result(i) := '5'; - when 6 => result(i) := '6'; - when 7 => result(i) := '7'; - when 8 => result(i) := '8'; - when 9 => result(i) := '9'; - end case; - - ib := ib / 10; - - exit when ib = 0; - end loop; - - if ib < 0 then - result(1) := sign; - end if; - - assert - not( ( ( ib < 0 ) and ( ( abs ib ) > ( 10**(w-1) - 1 ) ) ) or - ( ( ib >= 0 ) and ( ib > ( 10**w - 1 ) ) ) ) - report "tconv: integer overflows requested result width" - severity warning; - - return result; - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( n : integer) return string is - subtype digit is integer range 0 to 9; - variable result : string( 1 to 10 ) ; - variable ib : integer; - variable msd : integer; - variable sign : character := '-'; - variable test : digit; - begin - ib := abs n ; - for i in result'reverse_range loop - test := ib rem 10; - case test is - when 0 => result(i) := '0'; - when 1 => result(i) := '1'; - when 2 => result(i) := '2'; - when 3 => result(i) := '3'; - when 4 => result(i) := '4'; - when 5 => result(i) := '5'; - when 6 => result(i) := '6'; - when 7 => result(i) := '7'; - when 8 => result(i) := '8'; - when 9 => result(i) := '9'; - end case; - ib := ib / 10; - if ib = 0 then - msd := i; - exit; - end if; - end loop; - if ib < 0 then - return sign & result(msd to 10); - else - return result(msd to 10); - end if; - end tconv; --- Synopsys translate_on - - ------------------------------------------------------------------- - -- String conversion to other types - ------------------------------------------------------------------- --- Synopsys translate_off - function TConv ( s : string ) return integer is - variable result : integer ; - alias si : string( s'length downto 1 ) is s; - variable invalid : boolean ; - begin - invalid := false ; - for i in si'range loop - case si( i ) is - when '0' => null; - when '1' => result := result + 10 ** ( i - 1 ) ; - when '2' => result := result + 2 * 10 ** ( i - 1 ) ; - when '3' => result := result + 3 * 10 ** ( i - 1 ) ; - when '4' => result := result + 4 * 10 ** ( i - 1 ) ; - when '5' => result := result + 5 * 10 ** ( i - 1 ) ; - when '6' => result := result + 6 * 10 ** ( i - 1 ) ; - when '7' => result := result + 7 * 10 ** ( i - 1 ) ; - when '8' => result := result + 8 * 10 ** ( i - 1 ) ; - when '9' => result := result + 9 * 10 ** ( i - 1 ) ; - when others => invalid := true; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 thru 9" & - "; treating invalid characters as 0's" - severity warning; - return result; - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string; base : base_t ) return integer is - alias sv : string ( s'length downto 1 ) is s; - variable result : integer ; - variable invalid : boolean ; - variable vc_len : integer ; - variable validchars : string(1 to 20) := "0 thru 9 or A thru F"; - begin - invalid := false ; - case base is - when bin => - vc_len := 6; - validchars(1 to 6) := "0 or 1"; - for i in sv'range loop - case sv( i ) is - when '0' => null; - when '1' => result := result + 2 ** ( i - 1 ) ; - when others => invalid := true; - end case; - end loop; - - when oct => - vc_len := 8; - validchars(1 to 8) := "0 thru 7"; - for i in sv'range loop - case sv( i ) is - when '0' => null; - when '1' => result := result + 8 ** ( i - 1 ) ; - when '2' => result := result + 2 * 8 ** ( i - 1 ) ; - when '3' => result := result + 3 * 8 ** ( i - 1 ) ; - when '4' => result := result + 4 * 8 ** ( i - 1 ) ; - when '5' => result := result + 5 * 8 ** ( i - 1 ) ; - when '6' => result := result + 6 * 8 ** ( i - 1 ) ; - when '7' => result := result + 7 * 8 ** ( i - 1 ) ; - when others => invalid := true; - end case; - end loop; - - when dec => - vc_len := 8; - validchars(1 to 8) := "0 thru 9"; - for i in sv'range loop - case sv( i ) is - when '0' => null; - when '1' => result := result + 10 ** ( i - 1 ) ; - when '2' => result := result + 2 * 10 ** ( i - 1 ) ; - when '3' => result := result + 3 * 10 ** ( i - 1 ) ; - when '4' => result := result + 4 * 10 ** ( i - 1 ) ; - when '5' => result := result + 5 * 10 ** ( i - 1 ) ; - when '6' => result := result + 6 * 10 ** ( i - 1 ) ; - when '7' => result := result + 7 * 10 ** ( i - 1 ) ; - when '8' => result := result + 8 * 10 ** ( i - 1 ) ; - when '9' => result := result + 9 * 10 ** ( i - 1 ) ; - when others => invalid := true; - end case; - end loop; - - when hex => - for i in sv'range loop - case sv( i ) is - when '0' => null; - when '1' => result := result + 16 ** ( i - 1 ) ; - when '2' => result := result + 2 * 16 ** ( i - 1 ) ; - when '3' => result := result + 3 * 16 ** ( i - 1 ) ; - when '4' => result := result + 4 * 16 ** ( i - 1 ) ; - when '5' => result := result + 5 * 16 ** ( i - 1 ) ; - when '6' => result := result + 6 * 16 ** ( i - 1 ) ; - when '7' => result := result + 7 * 16 ** ( i - 1 ) ; - when '8' => result := result + 8 * 16 ** ( i - 1 ) ; - when '9' => result := result + 9 * 16 ** ( i - 1 ) ; - when 'A' | 'a' => result := result + 10 * 16 ** ( i - 1 ) ; - when 'B' | 'b' => result := result + 11 * 16 ** ( i - 1 ) ; - when 'C' | 'c' => result := result + 12 * 16 ** ( i - 1 ) ; - when 'D' | 'd' => result := result + 13 * 16 ** ( i - 1 ) ; - when 'E' | 'e' => result := result + 14 * 16 ** ( i - 1 ) ; - when 'F' | 'f' => result := result + 15 * 16 ** ( i - 1 ) ; - when others => invalid := true; - end case; - end loop; - - when others => - assert false report "Unsupported base passed." severity warning; - - end case; - - assert not invalid - report "String contained characters other than " & - validchars(1 to vc_len) & "; treating invalid characters as 0's" - severity warning; - - return result; - end; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string ) return bit is - variable result : bit; - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - assert s'length = 1 - report "String conversion to bit longer that 1 character" - severity warning; - case si(1) is - when '0' => result := '0'; - when '1' => result := '1'; - when others => - invalid := true; - result := '0'; - end case; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treating invalid characters as 0's" - severity warning; - return result; - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string ) return bit_vector is - variable result : bit_vector( 1 to s'length ); - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - for i in si'range loop - case si(i) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - when others => - invalid := true; - result( i ) := '0'; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treating invalid characters as 0's" - severity warning; - return result( 1 to result'length ); - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string; base : base_t ) return bit_vector is - variable result : bit_vector( 1 to 4*s'length ); - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - case base is - when bin => - for i in si'range loop - case si(i) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - when others => - invalid := true; - result( i ) := '0'; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treated invalid characters as 0's" - severity warning; - return result(1 to s'length) ; - - when oct => - for i in si'range loop - case si(i) is - when '0' => result( (3*i)-2 to 3*i ) := o"0"; - when '1' => result( (3*i)-2 to 3*i ) := o"1"; - when '2' => result( (3*i)-2 to 3*i ) := o"2"; - when '3' => result( (3*i)-2 to 3*i ) := o"3"; - when '4' => result( (3*i)-2 to 3*i ) := o"4"; - when '5' => result( (3*i)-2 to 3*i ) := o"5"; - when '6' => result( (3*i)-2 to 3*i ) := o"6"; - when '7' => result( (3*i)-2 to 3*i ) := o"7"; - when others => - invalid := true; - result( (3*i)-2 to 3*i ) := o"0"; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 through 7; " & - "treated invalid characters as 0's" - severity warning; - return result( 1 to 3*s'length ); - - when hex => - for i in si'range loop - case si(i) is - when '0' => result( (4*i)-3 to 4*i ) := x"0"; - when '1' => result( (4*i)-3 to 4*i ) := x"1"; - when '2' => result( (4*i)-3 to 4*i ) := x"2"; - when '3' => result( (4*i)-3 to 4*i ) := x"3"; - when '4' => result( (4*i)-3 to 4*i ) := x"4"; - when '5' => result( (4*i)-3 to 4*i ) := x"5"; - when '6' => result( (4*i)-3 to 4*i ) := x"6"; - when '7' => result( (4*i)-3 to 4*i ) := x"7"; - when '8' => result( (4*i)-3 to 4*i ) := x"8"; - when '9' => result( (4*i)-3 to 4*i ) := x"9"; - when 'A' | 'a' => result( (4*i)-3 to 4*i ) := x"A"; - when 'B' | 'b' => result( (4*i)-3 to 4*i ) := x"B"; - when 'C' | 'c' => result( (4*i)-3 to 4*i ) := x"C"; - when 'D' | 'd' => result( (4*i)-3 to 4*i ) := x"D"; - when 'E' | 'e' => result( (4*i)-3 to 4*i ) := x"E"; - when 'F' | 'f' => result( (4*i)-3 to 4*i ) := x"F"; - when others => - invalid := true; - result( (4*i)-3 to 4*i ) := x"0"; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 through 9 or " & - "A through F; " & - "treated invalid characters as 0's" - severity warning; - return result( 1 to 4*s'length ); - - when others => - assert false report "Unsupported base passed." severity warning; - return result ; - - end case; - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string ) return std_ulogic is - variable result : std_ulogic; - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - assert s'length = 1 - report "String conversion to bit longer that 1 character" - severity warning; - case si(1) is - when '0' => result := '0'; - when '1' => result := '1'; - when others => - invalid := true; - result := 'X'; - end case; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treating invalid characters as X's" - severity warning; - return result; - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string ) return std_ulogic_vector is - variable result : std_ulogic_vector( 1 to s'length ); - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - for i in si'range loop - case si(i) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - when others => - invalid := true; - result( i ) := 'X'; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treating invalid characters as X's" - severity warning; - return result( 1 to result'length ); - end tconv; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : string; base : base_t ) return std_ulogic_vector is - variable result : std_ulogic_vector( 1 to 4*s'length ); - alias si : string( 1 to s'length ) is s; - variable invalid : boolean := false; - begin - case base is - when bin => - for i in si'range loop - case si(i) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - when others => - invalid := true; - result( i ) := '0'; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 or 1; " & - "treated invalid characters as 0's" - severity warning; - return result(1 to s'length) ; - - when oct => - for i in si'range loop - case si(i) is - when '0' => result( (3*i)-2 to 3*i ) := "000"; - when '1' => result( (3*i)-2 to 3*i ) := "001"; - when '2' => result( (3*i)-2 to 3*i ) := "010"; - when '3' => result( (3*i)-2 to 3*i ) := "011"; - when '4' => result( (3*i)-2 to 3*i ) := "100"; - when '5' => result( (3*i)-2 to 3*i ) := "101"; - when '6' => result( (3*i)-2 to 3*i ) := "110"; - when '7' => result( (3*i)-2 to 3*i ) := "111"; - when others => - invalid := true; - result( (3*i)-2 to 3*i ) := "XXX"; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 through 7; " & - "treated invalid characters as X's" - severity warning; - return result( 1 to 3*s'length ); - - when hex => - for i in si'range loop - case si(i) is - when '0' => result( (4*i)-3 to 4*i ) := "0000"; - when '1' => result( (4*i)-3 to 4*i ) := "0001"; - when '2' => result( (4*i)-3 to 4*i ) := "0010"; - when '3' => result( (4*i)-3 to 4*i ) := "0011"; - when '4' => result( (4*i)-3 to 4*i ) := "0100"; - when '5' => result( (4*i)-3 to 4*i ) := "0101"; - when '6' => result( (4*i)-3 to 4*i ) := "0110"; - when '7' => result( (4*i)-3 to 4*i ) := "0111"; - when '8' => result( (4*i)-3 to 4*i ) := "1000"; - when '9' => result( (4*i)-3 to 4*i ) := "1001"; - when 'A' | 'a' => result( (4*i)-3 to 4*i ) := "1010"; - when 'B' | 'b' => result( (4*i)-3 to 4*i ) := "1011"; - when 'C' | 'c' => result( (4*i)-3 to 4*i ) := "1100"; - when 'D' | 'd' => result( (4*i)-3 to 4*i ) := "1101"; - when 'E' | 'e' => result( (4*i)-3 to 4*i ) := "1110"; - when 'F' | 'f' => result( (4*i)-3 to 4*i ) := "1111"; - when others => - invalid := true; - result( (4*i)-3 to 4*i ) := "XXXX"; - end case; - end loop; - assert not invalid - report "String contained characters other than 0 through 9 or " & - "A through F; " & - "treated invalid characters as X's" - severity warning; - return result( 1 to 4*s'length ); - - when others => - assert false report "Unsupported base passed." severity warning; - return result ; - - end case; - end tconv; --- Synopsys translate_on - - ------------------------------------------------------------------- - -- Std_uLogic Conversions - ------------------------------------------------------------------- - function tconv ( s : std_ulogic ) return boolean is - -- pragma built_in SYN_FEED_THRU - begin - case s is - when '0' => return(false); - when '1' => return(true); - when 'L' => return(false); - when 'H' => return(true); - when others => return(false); - end case; - end; - - function tconv ( s : std_ulogic ) return bit is - -- pragma built_in SYN_FEED_THRU - begin - case s is - when '0' => return('0'); - when '1' => return('1'); - when 'L' => return('0'); - when 'H' => return('1'); - when others => return('0'); - end case; - end; - --- Synopsys translate_off - function tconv ( s : std_ulogic ) return character is - begin - case s is - when '0' => return('0'); - when 'L' => return('L'); - when '1' => return('1'); - when 'H' => return('H'); - when 'U' => return('U'); - when 'W' => return('W'); - when '-' => return('-'); - when 'Z' => return('Z'); - when others => return('X'); - end case; - end; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : std_ulogic ) return string is - begin - case s is - when '0' => return("0"); - when 'L' => return("L"); - when '1' => return("1"); - when 'H' => return("H"); - when 'U' => return("U"); - when 'W' => return("W"); - when '-' => return("-"); - when 'Z' => return("Z"); - when others => return("X"); - end case; - end; --- Synopsys translate_on - - function tconv ( s : std_ulogic ) return integer is - -- pragma built_in SYN_UNSIGNED_TO_INTEGER - begin - case s is - when '0' => return(0); - when 'L' => return(0); - when '1' => return(1); - when 'H' => return(1); - when 'U' => return(0); - when 'W' => return(0); - when '-' => return(0); - when 'Z' => return(0); - when others => return(0); - end case; - end; - - function tconv ( s : std_ulogic ) return std_ulogic_vector is - -- pragma built_in SYN_FEED_THRU - begin - case s is - when '0' => return("0"); - when 'L' => return("L"); - when '1' => return("1"); - when 'H' => return("H"); - when 'U' => return("U"); - when 'W' => return("W"); - when '-' => return("-"); - when 'Z' => return("Z"); - when others => return("X"); - end case; - end; - - ------------------------------------------------------------------- - -- std_ulogic_vector Conversions - ------------------------------------------------------------------- - function tconv ( s : std_ulogic_vector ) return bit_vector is - alias sv : std_ulogic_vector ( 1 to s'length ) is s; - variable result : bit_vector ( 1 to s'length ) ; - -- pragma built_in SYN_FEED_THRU - begin - for i in result'range loop - case sv(i) is - when '0' => result(i) := '0'; - when '1' => result(i) := '1'; - when 'L' => result(i) := '0'; - when 'H' => result(i) := '1'; - when others => result(i) := '0'; - end case; - end loop; - return result; - end; - - function tconv ( s : std_ulogic_vector ) return std_logic_vector is - alias sv : std_ulogic_vector ( 1 to s'length ) is s; - variable result : std_logic_vector ( 1 to s'length ) := (others => 'X'); - -- pragma built_in SYN_FEED_THRU - begin - for i in result'range loop - case sv(i) is - when '0' => result(i) := '0'; - when '1' => result(i) := '1'; - when 'L' => result(i) := '0'; - when 'H' => result(i) := '1'; - when 'W' => result(i) := 'W'; - when '-' => result(i) := '-'; - when 'U' => result(i) := 'U'; - when 'X' => result(i) := 'X'; - when 'Z' => result(i) := 'Z'; - end case; - end loop; - return result; - end; - - function tconv ( s : std_ulogic_vector ) return integer is - variable int_result : integer ; - variable int_exp : integer ; - variable new_value : std_ulogic_vector(1 to s'length) ; - variable invalid : boolean ; - -- pragma built_in SYN_UNSIGNED_TO_INTEGER - begin - -- Synopsys translate_off - int_result := 0; - int_exp := 0; - invalid := false ; - new_value := s ; - for i in new_value'length downto 1 loop - case new_value(i) is - when '1' => int_result := int_result + (2**int_exp); - when '0' => null; - when others => - invalid := true; - end case; - int_exp := int_exp + 1; - end loop; - assert not invalid - report "The std_ulogic_Vector input contained values " & - "other than '0' and '1'. They were treated as zeroes." - severity warning; - -- Synopsys translate_on - return int_result; - end tconv ; - --- Synopsys translate_off - function tconv ( s : std_ulogic_vector ) return string is - alias sv : std_ulogic_vector ( 1 to s'length ) is s; - variable result : string ( 1 to s'length ) := (others => 'X'); - begin - for i in result'range loop - case sv(i) is - when '0' => result(i) := '0'; - when 'L' => result(i) := 'L'; - when '1' => result(i) := '1'; - when 'H' => result(i) := 'H'; - when 'U' => result(i) := 'U'; - when '-' => result(i) := '-'; - when 'W' => result(i) := 'W'; - when 'Z' => result(i) := 'Z'; - when others => result(i) := 'X'; - end case; - end loop; - return result; - end; --- Synopsys translate_on - --- Synopsys translate_off - function tconv ( s : std_ulogic_vector; base : base_t ) return string is - alias sv : std_ulogic_vector ( 1 to s'length ) is s; - variable result : string ( 1 to s'length ); - variable start : positive; - variable extra : natural; - variable resultLength : positive; - subtype bv is std_ulogic_vector( 1 to 1 ); - subtype qv is std_ulogic_vector( 1 to 2 ); - subtype ov is std_ulogic_vector( 1 to 3 ); - subtype hv is std_ulogic_vector( 1 to 4 ); - begin - case base is - when bin => - resultLength := sv'length; - start := 1; - for i in start to resultLength loop - case sv( i ) is - when '0' => result( i ) := '0'; - when '1' => result( i ) := '1'; - when 'X' => result( i ) := 'X'; - when 'L' => result( i ) := 'L'; - when 'H' => result( i ) := 'H'; - when 'W' => result( i ) := 'W'; - when '-' => result( i ) := '-'; - when 'U' => result( i ) := 'U'; - when 'Z' => result( i ) := 'Z'; - end case; - end loop; - - when oct => - extra := sv'length rem ov'length; - case extra is - when 0 => - resultLength := s'length/ov'length; - start := 1; - when 1 => - resultLength := ( s'length/ov'length ) + 1; - start := 2; - case sv( 1 ) is - when '0' => result( 1 ) := '0'; - when '1' => result( 1 ) := '1'; - when '-' => result( 1 ) := '-'; - when 'X' => result( 1 ) := 'X'; - when 'U' => result( 1 ) := 'U'; - when 'Z' => result( 1 ) := 'Z'; - when others => result( 1 ) := '.'; - end case; - when 2 => - resultLength := ( s'length/ov'length ) + 1; - start := 2; - case qv'( sv( 1 to 2 ) ) is - when "00" => result( 1 ) := '0'; - when "01" => result( 1 ) := '1'; - when "10" => result( 1 ) := '2'; - when "11" => result( 1 ) := '3'; - when "--" => result( 1 ) := '-'; - when "XX" => result( 1 ) := 'X'; - when "UU" => result( 1 ) := 'U'; - when "ZZ" => result( 1 ) := 'Z'; - when others => result( 1 ) := '.'; - end case; - when others => - assert false report "TCONV fatal condition" severity failure; - end case; - - for i in 0 to resultLength - start loop - case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is - when "000" => result( i+start ) := '0'; - when "001" => result( i+start ) := '1'; - when "010" => result( i+start ) := '2'; - when "011" => result( i+start ) := '3'; - when "100" => result( i+start ) := '4'; - when "101" => result( i+start ) := '5'; - when "110" => result( i+start ) := '6'; - when "111" => result( i+start ) := '7'; - when "---" => result( i+start ) := '-'; - when "XXX" => result( i+start ) := 'X'; - when "UUU" => result( i+start ) := 'U'; - when "ZZZ" => result( i+start ) := 'Z'; - when others => result( i+start ) := '.'; - end case; - end loop; - - when hex => - extra := s'length rem hv'length; - case extra is - when 0 => - resultLength := s'length/hv'length; - start := 1; - when 1 => - resultLength := ( s'length/hv'length ) + 1; - start := 2; - case sv( 1 ) is - when '0' => result( 1 ) := '0'; - when '1' => result( 1 ) := '1'; - when '-' => result( 1 ) := '-'; - when 'X' => result( 1 ) := 'X'; - when 'U' => result( 1 ) := 'U'; - when 'Z' => result( 1 ) := 'Z'; - when others => result( 1 ) := '.'; - end case; - when 2 => - resultLength := ( s'length/hv'length ) + 1; - start := 2; - case qv'( sv( 1 to 2 ) ) is - when "00" => result( 1 ) := '0'; - when "01" => result( 1 ) := '1'; - when "10" => result( 1 ) := '2'; - when "11" => result( 1 ) := '3'; - when "--" => result( 1 ) := '-'; - when "XX" => result( 1 ) := 'X'; - when "UU" => result( 1 ) := 'U'; - when "ZZ" => result( 1 ) := 'Z'; - when others => result( 1 ) := '.'; - end case; - when 3 => - resultLength := ( s'length/hv'length ) + 1; - start := 2; - case ov'( sv( 1 to 3 ) ) is - when "000" => result( 1 ) := '0'; - when "001" => result( 1 ) := '1'; - when "010" => result( 1 ) := '2'; - when "011" => result( 1 ) := '3'; - when "100" => result( 1 ) := '4'; - when "101" => result( 1 ) := '5'; - when "110" => result( 1 ) := '6'; - when "111" => result( 1 ) := '7'; - when "---" => result( 1 ) := '-'; - when "XXX" => result( 1 ) := 'X'; - when "UUU" => result( 1 ) := 'U'; - when "ZZZ" => result( 1 ) := 'Z'; - when others => result( 1 ) := '.'; - end case; - when others => - assert false report "TCONV fatal condition" severity failure; - end case; - - for i in 0 to resultLength - start loop - case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is - when "0000" => result( i+start ) := '0'; - when "0001" => result( i+start ) := '1'; - when "0010" => result( i+start ) := '2'; - when "0011" => result( i+start ) := '3'; - when "0100" => result( i+start ) := '4'; - when "0101" => result( i+start ) := '5'; - when "0110" => result( i+start ) := '6'; - when "0111" => result( i+start ) := '7'; - when "1000" => result( i+start ) := '8'; - when "1001" => result( i+start ) := '9'; - when "1010" => result( i+start ) := 'A'; - when "1011" => result( i+start ) := 'B'; - when "1100" => result( i+start ) := 'C'; - when "1101" => result( i+start ) := 'D'; - when "1110" => result( i+start ) := 'E'; - when "1111" => result( i+start ) := 'F'; - when "----" => result( i+start ) := '-'; - when "XXXX" => result( i+start ) := 'X'; - when "UUUU" => result( i+start ) := 'U'; - when "ZZZZ" => result( i+start ) := 'Z'; - when others => result( i+start ) := '.'; - end case; - end loop; - - when others => - assert false report "Unsupported base passed." severity warning; - end case; - return result( 1 to resultLength ); - end; --- Synopsys translate_on - - function tconv ( s : std_ulogic_vector ) return std_ulogic is - alias sv : std_ulogic_vector( 1 to s'length ) is s; - variable result : std_ulogic; - -- pragma built_in SYN_FEED_THRU - begin - case sv(s'length) is - when '0' => return('0'); - when 'L' => return('L'); - when '1' => return('1'); - when 'H' => return('H'); - when 'U' => return('U'); - when 'W' => return('W'); - when '-' => return('-'); - when 'Z' => return('Z'); - when others => return('X'); - end case; - end; - - ------------------------------------------------------------------- - -- std_logic_vector Conversions - ------------------------------------------------------------------- - --function tconv ( s : std_logic_vector ) return bit_vector is - -- alias sv : std_logic_vector ( 1 to s'length ) is s; - -- variable result : bit_vector ( 1 to s'length ) := (others => '0'); - ---- pragma built_in SYN_FEED_THRU - --begin - -- for i in result'range loop - -- case sv(i) is - -- when '0' => result(i) := '0'; - -- when '1' => result(i) := '1'; - -- when 'L' => result(i) := '0'; - -- when 'H' => result(i) := '1'; - -- when others => result(i) := '0'; - -- end case; - -- end loop; - -- return result; - --end; - - --function tconv ( s : std_logic_vector ) return std_ulogic_vector is - -- alias sv : std_logic_vector ( 1 to s'length ) is s; - -- variable result : std_ulogic_vector ( 1 to s'length ) := (others => 'X'); - ---- pragma built_in SYN_FEED_THRU - --begin - -- for i in result'range loop - -- case sv(i) is - -- when '0' => result(i) := '0'; - -- when '1' => result(i) := '1'; - -- when 'L' => result(i) := '0'; - -- when 'H' => result(i) := '1'; - -- when 'W' => result(i) := 'W'; - -- when '-' => result(i) := '-'; - -- when 'U' => result(i) := 'U'; - -- when 'X' => result(i) := 'X'; - -- when 'Z' => result(i) := 'Z'; - -- end case; - -- end loop; - -- return result; - --end; - - --function tconv ( s : std_logic_vector ) return integer is - -- variable int_result : integer := 0; - -- variable int_exp : integer := 0; - -- alias new_value : std_logic_vector(1 to s'length) is s ; - -- variable invalid : boolean := false; - ---- pragma built_in SYN_UNSIGNED_TO_INTEGER - --begin - ---- Synopsys translate_off - -- for i in new_value'length downto 1 loop - -- case new_value(i) is - -- when '1' => int_result := int_result + (2**int_exp); - -- when '0' => null; - -- when others => - -- invalid := true; - -- end case; - -- int_exp := int_exp + 1; - -- end loop; - -- assert not invalid - -- report "The std_logic_Vector input contained values " & - -- "other than '0' and '1'. They were treated as zeroes." - -- severity warning; - ---- Synopsys translate_on - -- return int_result; - --end tconv ; - --- Synopsys translate_off - --function tconv ( s : std_logic_vector ) return string is - -- alias sv : std_logic_vector ( 1 to s'length ) is s; - -- variable result : string ( 1 to s'length ) := (others => 'X'); - --begin - -- for i in result'range loop - -- case sv(i) is - -- when '0' => result(i) := '0'; - -- when 'L' => result(i) := 'L'; - -- when '1' => result(i) := '1'; - -- when 'H' => result(i) := 'H'; - -- when 'U' => result(i) := 'U'; - -- when '-' => result(i) := '-'; - -- when 'W' => result(i) := 'W'; - -- when 'Z' => result(i) := 'Z'; - -- when others => result(i) := 'X'; - -- end case; - -- end loop; - -- return result; - --end; --- Synopsys translate_on - --- Synopsys translate_off - --function tconv ( s : std_logic_vector; base : base_t ) return string is - -- alias sv : std_logic_vector ( 1 to s'length ) is s; - -- variable result : string ( 1 to s'length ); - -- variable start : positive; - -- variable extra : natural; - -- variable resultlength : positive; - -- subtype bv is std_logic_vector( 1 to 1 ); - -- subtype qv is std_logic_vector( 1 to 2 ); - -- subtype ov is std_logic_vector( 1 to 3 ); - -- subtype hv is std_logic_vector( 1 to 4 ); - --begin - -- case base is - -- when bin => - -- resultLength := sv'length; - -- start := 1; - -- for i in start to resultLength loop - -- case sv( i ) is - -- when '0' => result( i ) := '0'; - -- when '1' => result( i ) := '1'; - -- when 'X' => result( i ) := 'X'; - -- when 'L' => result( i ) := 'L'; - -- when 'H' => result( i ) := 'H'; - -- when 'W' => result( i ) := 'W'; - -- when '-' => result( i ) := '-'; - -- when 'U' => result( i ) := 'U'; - -- when 'Z' => result( i ) := 'Z'; - -- end case; - -- end loop; - - -- when oct => - -- extra := sv'length rem ov'length; - -- case extra is - -- when 0 => - -- resultLength := s'length/ov'length; - -- start := 1; - -- when 1 => - -- resultLength := ( s'length/ov'length ) + 1; - -- start := 2; - -- case sv( 1 ) is - -- when '0' => result( 1 ) := '0'; - -- when '1' => result( 1 ) := '1'; - -- when '-' => result( 1 ) := '-'; - -- when 'X' => result( 1 ) := 'X'; - -- when 'U' => result( 1 ) := 'U'; - -- when 'Z' => result( 1 ) := 'Z'; - -- when others => result( 1 ) := '.'; - -- end case; - -- when 2 => - -- resultLength := ( s'length/ov'length ) + 1; - -- start := 2; - -- case qv'( sv( 1 to 2 ) ) is - -- when "00" => result( 1 ) := '0'; - -- when "01" => result( 1 ) := '1'; - -- when "10" => result( 1 ) := '2'; - -- when "11" => result( 1 ) := '3'; - -- when "--" => result( 1 ) := '-'; - -- when "XX" => result( 1 ) := 'X'; - -- when "UU" => result( 1 ) := 'U'; - -- when "ZZ" => result( 1 ) := 'Z'; - -- when others => result( 1 ) := '.'; - -- end case; - -- when others => - -- assert false report "TCONV fatal condition" severity failure; - -- end case; - - -- for i in 0 to resultLength - start loop - -- case ov'( sv( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is - -- when "000" => result( i+start ) := '0'; - -- when "001" => result( i+start ) := '1'; - -- when "010" => result( i+start ) := '2'; - -- when "011" => result( i+start ) := '3'; - -- when "100" => result( i+start ) := '4'; - -- when "101" => result( i+start ) := '5'; - -- when "110" => result( i+start ) := '6'; - -- when "111" => result( i+start ) := '7'; - -- when "---" => result( i+start ) := '-'; - -- when "XXX" => result( i+start ) := 'X'; - -- when "UUU" => result( i+start ) := 'U'; - -- when "ZZZ" => result( i+start ) := 'Z'; - -- when others => result( i+start ) := '.'; - -- end case; - -- end loop; - - -- when hex => - -- extra := s'length rem hv'length; - -- case extra is - -- when 0 => - -- resultLength := s'length/hv'length; - -- start := 1; - -- when 1 => - -- resultLength := ( s'length/hv'length ) + 1; - -- start := 2; - -- case sv( 1 ) is - -- when '0' => result( 1 ) := '0'; - -- when '1' => result( 1 ) := '1'; - -- when '-' => result( 1 ) := '-'; - -- when 'X' => result( 1 ) := 'X'; - -- when 'U' => result( 1 ) := 'U'; - -- when 'Z' => result( 1 ) := 'Z'; - -- when others => result( 1 ) := '.'; - -- end case; - -- when 2 => - -- resultLength := ( s'length/hv'length ) + 1; - -- start := 2; - -- case qv'( sv( 1 to 2 ) ) is - -- when "00" => result( 1 ) := '0'; - -- when "01" => result( 1 ) := '1'; - -- when "10" => result( 1 ) := '2'; - -- when "11" => result( 1 ) := '3'; - -- when "--" => result( 1 ) := '-'; - -- when "XX" => result( 1 ) := 'X'; - -- when "UU" => result( 1 ) := 'U'; - -- when "ZZ" => result( 1 ) := 'Z'; - -- when others => result( 1 ) := '.'; - -- end case; - -- when 3 => - -- resultLength := ( s'length/hv'length ) + 1; - -- start := 2; - -- case ov'( sv( 1 to 3 ) ) is - -- when "000" => result( 1 ) := '0'; - -- when "001" => result( 1 ) := '1'; - -- when "010" => result( 1 ) := '2'; - -- when "011" => result( 1 ) := '3'; - -- when "100" => result( 1 ) := '4'; - -- when "101" => result( 1 ) := '5'; - -- when "110" => result( 1 ) := '6'; - -- when "111" => result( 1 ) := '7'; - -- when "---" => result( 1 ) := '-'; - -- when "XXX" => result( 1 ) := 'X'; - -- when "UUU" => result( 1 ) := 'U'; - -- when "ZZZ" => result( 1 ) := 'Z'; - -- when others => result( 1 ) := '.'; - -- end case; - -- when others => - -- assert false report "TCONV fatal condition" severity failure; - -- end case; - - -- for i in 0 to resultLength - start loop - -- case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is - -- when "0000" => result( i+start ) := '0'; - -- when "0001" => result( i+start ) := '1'; - -- when "0010" => result( i+start ) := '2'; - -- when "0011" => result( i+start ) := '3'; - -- when "0100" => result( i+start ) := '4'; - -- when "0101" => result( i+start ) := '5'; - -- when "0110" => result( i+start ) := '6'; - -- when "0111" => result( i+start ) := '7'; - -- when "1000" => result( i+start ) := '8'; - -- when "1001" => result( i+start ) := '9'; - -- when "1010" => result( i+start ) := 'A'; - -- when "1011" => result( i+start ) := 'B'; - -- when "1100" => result( i+start ) := 'C'; - -- when "1101" => result( i+start ) := 'D'; - -- when "1110" => result( i+start ) := 'E'; - -- when "1111" => result( i+start ) := 'F'; - -- when "----" => result( i+start ) := '-'; - -- when "XXXX" => result( i+start ) := 'X'; - -- when "UUUU" => result( i+start ) := 'U'; - -- when "ZZZZ" => result( i+start ) := 'Z'; - -- when others => result( i+start ) := '.'; - -- end case; - -- end loop; - - -- when others => - -- assert false report "Unsupported base passed." severity warning; - -- end case; - -- return result( 1 to resultLength ); - --end; --- Synopsys translate_on - --- Synopsys translate_off - function hexstring( d : std_ulogic_vector ) return string is - variable nd : - Std_Ulogic_vector( 0 to ((d'length + (4 - (d'length mod 4))) - 1) ) := ( others => '0' ); - variable r : string(1 to (nd'length/4)); - variable hexsize : integer; - variable offset : integer; - subtype iv4 is Std_Ulogic_vector(1 to 4); - begin - - offset := d'length mod 4; - - if offset = 0 then - hexsize := d'length / 4; - nd( 0 to d'length - 1 ) := d; - else - hexsize := nd'length / 4; - nd( ( nd'left + (4 - offset) ) to nd'right ) := d; - end if; - - for i in 0 to hexsize - 1 loop - - case iv4( nd( ( i * 4 ) to ( ( i * 4 ) + 3 ) ) ) is - when "0000" => r(i + 1) := '0'; - when "0001" => r(i + 1) := '1'; - when "0010" => r(i + 1) := '2'; - when "0011" => r(i + 1) := '3'; - when "0100" => r(i + 1) := '4'; - when "0101" => r(i + 1) := '5'; - when "0110" => r(i + 1) := '6'; - when "0111" => r(i + 1) := '7'; - when "1000" => r(i + 1) := '8'; - when "1001" => r(i + 1) := '9'; - when "1010" => r(i + 1) := 'A'; - when "1011" => r(i + 1) := 'B'; - when "1100" => r(i + 1) := 'C'; - when "1101" => r(i + 1) := 'D'; - when "1110" => r(i + 1) := 'E'; - when "1111" => r(i + 1) := 'F'; - when "----" => r(i + 1) := '-'; - when "XXXX" => r(i + 1) := 'X'; - when "UUUU" => r(i + 1) := 'U'; - when "ZZZZ" => r(i + 1) := 'Z'; - when others => r(i + 1) := '.'; - end case; - - end loop; - - return r(1 to hexsize); - end hexstring; --- Synopsys translate_on - --- Synopsys translate_off - function octstring( d : std_ulogic_vector ) return string is - variable nd : - Std_Ulogic_vector( 0 to ((d'length + (3 - (d'length mod 3))) - 1) ) := ( others => '0' ); - variable offset : integer; - variable r : string(1 to (nd'length/3)); - variable octsize : integer; - subtype iv3 is Std_Ulogic_vector(1 to 3); - begin - - offset := d'length mod 3; - - if offset = 0 then - octsize := d'length / 3; - nd( 0 to d'length - 1 ) := d; - else - octsize := nd'length / 3; - nd( ( nd'left + (3 - offset) ) to nd'right ) := d; - end if; - - for i in 0 to octsize - 1 loop - - case iv3( nd( ( i * 3 ) to ( ( i * 3 ) + 2 ) ) ) is - when "000" => r(i + 1) := '0'; - when "001" => r(i + 1) := '1'; - when "010" => r(i + 1) := '2'; - when "011" => r(i + 1) := '3'; - when "100" => r(i + 1) := '4'; - when "101" => r(i + 1) := '5'; - when "110" => r(i + 1) := '6'; - when "111" => r(i + 1) := '7'; - when "---" => r(i + 1) := '-'; - when "XXX" => r(i + 1) := 'X'; - when "UUU" => r(i + 1) := 'U'; - when "ZZZ" => r(i + 1) := 'Z'; - when others => r(i + 1) := '.'; - end case; - - end loop; - - return r; - end octstring; --- Synopsys translate_on - --- Synopsys translate_off - function bitstring( d : std_ulogic_vector ) return string is - variable nd : - Std_Ulogic_vector(0 to ( d'length - 1 ) ) := ( others => '0' ); - variable r : string(1 to (nd'length)); - begin - nd := d; - for i in nd'range loop - r(i + 1) := std_ulogic_to_character( nd(i) ); - end loop; - return r; - end bitstring; --- Synopsys translate_on - - ------------------------------------------------------------------- - -- Std_Match functions - ------------------------------------------------------------------- - constant no_warning: boolean := false; -- default to emit warnings - - -- Id: M.1a - function std_match (l, r: std_ulogic) return std_ulogic is - begin - if (l ?= r) then - return '1' ; - else - return '0' ; - end if ; - end std_match; - - -- Id: M.4b - function std_match (l, r: std_ulogic_vector) return std_ulogic is - variable result : boolean ; - begin - if (l ?= r) then - return '1' ; - else - return '0' ; - end if; - end std_match; - - ------------------------------------------------------------------- - -- Overloaded Relational Operators returning std_ulogic - ------------------------------------------------------------------- - function "=" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_EQL - begin - if (l - r) = 0 then - return ('1'); - else - return ('0'); - end if ; - end "="; - - function "/=" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_NEQ - begin - if (l - r) = 0 then - return ('0'); - else - return ('1'); - end if ; - end "/="; - - function ">" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_GT - begin - if (l - r) > 0 then - return ('1'); - else - return ('0'); - end if ; - end ">"; - - function ">=" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_GEQ - begin - if (l - r) >= 0 then - return ('1'); - else - return ('0'); - end if ; - end ">="; - - function "<" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_LT - begin - if (r - l) > 0 then - return ('1'); - else - return ('0'); - end if ; - end "<"; - - function "<=" ( l,r : integer ) return std_ulogic is - -- pragma built_in SYN_LEQ - begin - if (r - l) >= 0 then - return ('1'); - else - return ('0'); - end if ; - end "<="; - - ------------------------------------------------------------------- - -- Overloaded Relational Operators returning STD_uLogic - ------------------------------------------------------------------- - function "=" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_EQL - begin - return ( tconv( l = r ) ); - end "="; - - function "/=" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_NEQ - begin - return ( tconv( l /= r ) ); - end "/="; - - function ">" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_GT - begin - return ( tconv( l > r ) ); - end ">"; - - function ">=" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_GEQ - begin - return ( tconv( l >= r ) ); - end ">="; - - function "<" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_LT - begin - return ( tconv( l < r ) ); - end "<"; - - function "<=" ( l,r : std_ulogic ) return std_ulogic is - -- pragma built_in SYN_LEQ - begin - return ( tconv( l <= r ) ); - end "<="; - - ------------------------------------------------------------------- - -- Overloaded Relational Operators returning STD_uLogic - ------------------------------------------------------------------- - - function "=" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_EQL - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the = " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l = r ) ); - end "="; - - ------------------------------------------------------------------- - function "/=" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_NEQ - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the /= " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l /= r ) ); - end "/="; - - ------------------------------------------------------------------- - function ">" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_GT - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the > " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l > r ) ); - end ">"; - - ------------------------------------------------------------------- - function ">=" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_GEQ - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the >= " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l >= r ) ); - end ">="; - - ------------------------------------------------------------------- - function "<" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_LT - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the < " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l < r ) ); - end "<"; - - ------------------------------------------------------------------- - function "<=" ( l,r : std_ulogic_vector) return std_ulogic is - -- pragma built_in SYN_LEQ - begin - -- Synopsys translate_off - if l'length /= r'length then - assert false - report "The bit lengths of the two inputs to the <= " & - "operator are unequal. " - severity error; - return '0' ; - end if ; - -- Synopsys translate_on - return ( tconv( l <= r ) ); - end "<="; - ---============================================================== - -- Shift and Rotate Functions ---============================================================== -----------Local Subprograms - shift/rotate ops------------------- - -- Synopsys translate_off - constant NAU: std_ulogic_vector(0 downto 1) := (others => '0'); - -- Synopsys translate_on - - function xsll (arg: std_ulogic_vector; count: natural) return std_ulogic_vector - is - constant arg_l: integer := arg'length-1; - alias xarg: std_ulogic_vector(arg_l downto 0) is arg; - variable result: std_ulogic_vector(arg_l downto 0) ; - -- pragma built_in SYN_SLLU - begin - result := (others => '0'); - if count <= arg_l then - result(arg_l downto count) := xarg(arg_l-count downto 0); - end if; - return result; - end xsll; - - function xsrl (arg: std_ulogic_vector; count: natural) return std_ulogic_vector - is - constant arg_l: integer := arg'length-1; - alias xarg: std_ulogic_vector(arg_l downto 0) is arg; - variable result: std_ulogic_vector(arg_l downto 0) ; - -- pragma built_in SYN_SRLU - begin - result := (others => '0'); - if count <= arg_l then - result(arg_l-count downto 0) := xarg(arg_l downto count); - end if; - return result; - end xsrl; - - function xsra (arg: std_ulogic_vector; count: natural) return std_ulogic_vector - is - constant arg_l: integer := arg'length-1; - alias xarg: std_ulogic_vector(arg_l downto 0) is arg; - variable result: std_ulogic_vector(arg_l downto 0); - variable xcount: natural ; - -- pragma built_in SYN_SHR - begin - xcount := count; - if ((arg'length <= 1) or (xcount = 0)) then return arg; - else - if (xcount > arg_l) then xcount := arg_l; - end if; - result(arg_l-xcount downto 0) := xarg(arg_l downto xcount); - result(arg_l downto (arg_l - xcount + 1)) := (others => xarg(arg_l)); - end if; - return result; - end xsra; - - function xrol (arg: std_ulogic_vector; count: natural) return std_ulogic_vector - is - constant arg_l: integer := arg'length-1; - alias xarg: std_ulogic_vector(arg_l downto 0) is arg; - variable result: std_ulogic_vector(arg_l downto 0) ; - variable countm: integer; - -- pragma built_in SYN_ROLU - begin - result := xarg; - countm := count mod (arg_l + 1); - if countm /= 0 then - result(arg_l downto countm) := xarg(arg_l-countm downto 0); - result(countm-1 downto 0) := xarg(arg_l downto arg_l-countm+1); - end if; - return result; - end xrol; - - function xror (arg: std_ulogic_vector; count: natural) return std_ulogic_vector - is - constant arg_l: integer := arg'length-1; - alias xarg: std_ulogic_vector(arg_l downto 0) is arg; - variable result: std_ulogic_vector(arg_l downto 0) ; - variable countm: integer; - -- pragma built_in SYN_RORU - begin - countm := count mod (arg_l + 1); - result := xarg; - if countm /= 0 then - result(arg_l-countm downto 0) := xarg(arg_l downto countm); - result(arg_l downto arg_l-countm+1) := xarg(countm-1 downto 0); - end if; - return result; - end xror; - ---=================================================================== - - -- Id: S.1 - function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is - -- pragma built_in SYN_SLLU - begin - -- Synopsys translate_off - if (arg'length < 1) then return NAU; - end if; - -- Synopsys translate_on - return std_ulogic_vector( xsll( std_ulogic_vector(arg), count ) ); - end shift_left; - - -- Id: S.2 - function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is - -- pragma built_in SYN_SRLU - begin - -- Synopsys translate_off - if (arg'length < 1) then return NAU; - end if; - -- Synopsys translate_on - return std_ulogic_vector( xsrl( std_ulogic_vector(arg), count ) ); - end shift_right; - - - -- Id: S.5 - function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is - -- pragma built_in SYN_ROLU - begin - -- Synopsys translate_off - if (arg'length < 1) then return NAU; - end if; - -- Synopsys translate_on - return std_ulogic_vector( xrol( std_ulogic_vector(arg), count ) ); - end rotate_left; - - -- Id: S.6 - function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is - -- pragma built_in SYN_RORU - begin - -- Synopsys translate_off - if (arg'length < 1) then return NAU; - end if; - -- Synopsys translate_on - return std_ulogic_vector( xror( std_ulogic_vector(arg), count ) ); - end rotate_right; - - -- Id: S.9 - function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is - -- pragma built_in SYN_SLL - begin - if (count >= 0) then - return shift_left(arg, count); - else - return shift_right(arg, -count); - end if; - end "sll"; - - -- Id: S.11 - function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is - -- pragma built_in SYN_SRL - begin - if (count >= 0) then - return shift_right(arg, count); - else - return shift_left(arg, -count); - end if; - end "srl"; - - -- Id: S.13 - function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is - -- pragma built_in SYN_ROL - begin - if (count >= 0) then - return rotate_left(arg, count); - else - return rotate_right(arg, -count); - end if; - end "rol"; - - -- Id: S.15 - function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is - -- pragma built_in SYN_ROR - begin - if (count >= 0) then - return rotate_right(arg, count); - else - return rotate_left(arg, -count); - end if; - end "ror"; - ---============================================================== - --End Shift and Rotate Functions ---============================================================== - -end std_ulogic_support ; - +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library ieee, ibm ; +use ieee.std_logic_1164.all ; +use ieee.numeric_std.all ; + +package std_ulogic_support is + + attribute like_builtin: boolean; + attribute dc_allow: boolean; + attribute type_convert: boolean; + attribute recursive_synthesis: boolean; + attribute functionality: string; + attribute btr_name: string; + attribute block_data: string; + type pbi_el_t is array(0 to 3) of string; + type pbi_t is array(integer range <>) of pbi_el_t; + attribute pin_bit_information: pbi_t; + attribute dynamic_block_data: string; + + type base_t is ( bin, oct, dec, hex ); + + ------------------------------------------------------------------- + -- Overloaded Relational Operator that can return std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic; + function "/=" ( l,r : integer ) return std_ulogic; + function ">" ( l,r : integer ) return std_ulogic; + function ">=" ( l,r : integer ) return std_ulogic; + function "<" ( l,r : integer ) return std_ulogic; + function "<=" ( l,r : integer ) return std_ulogic; + + function "=" ( l,r : std_ulogic ) return std_ulogic; + function "/=" ( l,r : std_ulogic ) return std_ulogic; + function ">" ( l,r : std_ulogic ) return std_ulogic; + function ">=" ( l,r : std_ulogic ) return std_ulogic; + function "<" ( l,r : std_ulogic ) return std_ulogic; + function "<=" ( l,r : std_ulogic ) return std_ulogic; + + function "=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "/=" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">" ( l, r : std_ulogic_vector ) return std_ulogic; + function ">=" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<" ( l, r : std_ulogic_vector ) return std_ulogic; + function "<=" ( l, r : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + attribute like_builtin of "=" :function is true; + attribute like_builtin of "/=" :function is true; + attribute like_builtin of ">" :function is true; + attribute like_builtin of ">=" :function is true; + attribute like_builtin of "<" :function is true; + attribute like_builtin of "<=" :function is true; +-- Synopsys translate_on + ------------------------------------------------------------------- + -- Relational Functions that can return Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic ) return boolean; + function ne( l,r : std_ulogic ) return boolean; + function gt( l,r : std_ulogic ) return boolean; + function ge( l,r : std_ulogic ) return boolean; + function lt( l,r : std_ulogic ) return boolean; + function le( l,r : std_ulogic ) return boolean; + + ------------------------------------------------------------------- + -- Relational Functions that can return std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic; + function ne( l,r : std_ulogic ) return std_ulogic; + function gt( l,r : std_ulogic ) return std_ulogic; + function ge( l,r : std_ulogic ) return std_ulogic; + function lt( l,r : std_ulogic ) return std_ulogic; + function le( l,r : std_ulogic ) return std_ulogic; + + ------------------------------------------------------------------- + -- Vectorized Relational Functions + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic_vector ) return boolean; + function ne( l,r : std_ulogic_vector ) return boolean; + function gt( l,r : std_ulogic_vector ) return boolean; + function ge( l,r : std_ulogic_vector ) return boolean; + function lt( l,r : std_ulogic_vector ) return boolean; + function le( l,r : std_ulogic_vector ) return boolean; + + function eq( l,r : std_ulogic_vector ) return std_ulogic; + function ne( l,r : std_ulogic_vector ) return std_ulogic; + function gt( l,r : std_ulogic_vector ) return std_ulogic; + function ge( l,r : std_ulogic_vector ) return std_ulogic; + function lt( l,r : std_ulogic_vector ) return std_ulogic; + function le( l,r : std_ulogic_vector ) return std_ulogic; +-- Synopsys translate_off + attribute functionality of eq : function is "="; + attribute functionality of ne : function is "/="; + attribute functionality of gt : function is ">"; + attribute functionality of ge : function is ">="; + attribute functionality of lt : function is "<"; + attribute functionality of le : function is "<="; + + attribute dc_allow of eq : function is true; + attribute dc_allow of ne : function is true; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + + -- Boolean conversion to other types + function tconv( b : boolean ) return bit; + function tconv( b : boolean ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : boolean ) return string; +-- Synopsys translate_on + + -- Bit to other types + function tconv( b : bit ) return boolean; + function tconv( b : bit ) return integer; + function tconv( b : bit ) return std_ulogic; +-- Synopsys translate_off + function tconv( b : bit ) return character; + function tconv( b : bit ) return string; +-- Synopsys translate_on + + -- Bit_vector to other types + function tconv( b : bit_vector ) return integer; + function tconv( b : bit_vector ) return std_ulogic_vector; +-- function tconv( b : bit_vector ) return std_logic_vector; +-- synopsys translate_off + function tconv( b : bit_vector ) return string; + function tconv( b : bit_vector; base : base_t ) return string; +-- synopsys translate_on + + -- Integer conversion to other types + function tconv( n : integer; w: positive ) return bit_vector ; + function tconv( n : integer; w: positive ) return std_ulogic_vector ; +-- synopsys translate_off + function tconv( n : integer; w: positive ) return string ; + function tconv( n : integer ) return string ; +-- synopsys translate_on + +-- Synopsys translate_off + -- String conversion to other types + function tconv( s : string ) return integer ; + function tconv( s : string; base : base_t ) return integer ; + function tconv( s : string ) return bit ; + function tconv( s : string ) return bit_vector ; + function tconv( s : string; base : base_t ) return bit_vector ; + function tconv( s : string ) return std_ulogic ; + function tconv( s : string ) return std_ulogic_vector ; + function tconv( s : string; base : base_t ) return std_ulogic_vector ; +-- Synopsys translate_on + + -- Std_uLogic to other types + function tconv( s : std_ulogic ) return boolean; + function tconv( s : std_ulogic ) return bit; + function tconv( s : std_ulogic ) return integer; + function tconv( s : std_ulogic ) return std_ulogic_vector; +-- synopsys translate_off + function tconv( s : std_ulogic ) return character; + function tconv( s : std_ulogic ) return string; +-- synopsys translate_on + + -- std_ulogic_vector to other types + function tconv( s : std_ulogic_vector ) return bit_vector; + function tconv( s : std_ulogic_vector ) return std_logic_vector; + function tconv( s : std_ulogic_vector ) return integer; + function tconv( s : std_ulogic_vector ) return std_ulogic; +-- synopsys translate_off + function tconv( s : std_ulogic_vector ) return string; + function tconv( s : std_ulogic_vector; base : base_t ) return string; +-- synopsys translate_on + + -- std_logic_vector to other types +-- function tconv( s : std_logic_vector ) return bit_vector; +-- function tconv( s : std_logic_vector ) return std_ulogic_vector; +-- function tconv( s : std_logic_vector ) return integer; +-- synopsys translate_off +-- function tconv( s : std_logic_vector ) return string; +-- function tconv( s : std_logic_vector; base : base_t ) return string; +-- synopsys translate_on + +-- synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string ; + function octstring( d : std_ulogic_vector ) return string ; + function bitstring( d : std_ulogic_vector ) return string ; +-- synopsys translate_on + + ------------------------------------------------------------------- + -- HIS ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- +-- Synopsys translate_off + attribute type_convert of tconv : function is true; + + ------------------------------------------------------------------- + -- synthesis ATTRIBUTEs for Type Conversion Functions + ------------------------------------------------------------------- + + attribute btr_name of tconv : function is "PASS"; + attribute pin_bit_information of tconv : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); +-- Synopsys translate_on + + --============================================================================ + -- Match Functions + --============================================================================ + + function std_match (l, r: std_ulogic) return std_ulogic; + function std_match (l, r: std_ulogic_vector) return std_ulogic; + +-- Synopsys translate_off + attribute functionality of std_match : function is "="; + attribute dc_allow of std_match : function is true; +-- Synopsys translate_on +--============================================================== + -- Shift and Rotate Functions +--============================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-left on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT leftmost elements are lost. + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a shift-right on an std_ulogic_vector vector COUNT times. + -- The vacated positions are filled with '0'. + -- The COUNT rightmost elements are lost. + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-left of an std_ulogic_vector vector COUNT times. + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: Performs a rotate-right of an std_ulogic_vector vector COUNT times. + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_LEFT(ARG, COUNT) + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: SHIFT_RIGHT(ARG, COUNT) + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_LEFT(ARG, COUNT) + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector; + -- Result subtype: std_ulogic_vector(ARG'LENGTH-1 downto 0) + -- Result: ROTATE_RIGHT(ARG, COUNT) + --=========================================================== + --End shift and rotate functions............................. + --=========================================================== +end std_ulogic_support ; + +package body std_ulogic_support is + + ------------------------------------------------------------------- + -- Look Up tables for operator overloading + ------------------------------------------------------------------- + -- Types used for overloaded operator lookup tables + ------------------------------------------------------------------- + +-- Synopsys synthesis_off + type std_ulogic_to_character_type is array( std_ulogic ) of character; + + constant std_ulogic_to_character : std_ulogic_to_character_type := + ( 'U','X','0','1','Z','W','L','H','-'); + + type stdlogic_2d is array ( std_ulogic, std_ulogic ) of std_ulogic; + type b_stdlogic_2d is array ( std_ulogic, std_ulogic ) of boolean; +-- Synopsys synthesis_on + ------------------------------------------------------------------- + -- Logic operation lookup tables + ------------------------------------------------------------------- +-- Synopsys synthesis_off + -- LessThan Logic Operator + + constant lt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_lt_table : b_stdlogic_2D := ( + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '1'=>true, 'H'=>true, others=>false ), + '1'=>( others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '1'=>true, 'H'=>true, others=>false ), + 'H'=>( others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- LessThanorEqual Logic Operator + + constant le_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 0 + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '1', 'X', 'X', '0', '1', 'X' ), -- | L + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_le_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '1'=>( '1'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'H'=>( '1'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); + + -- GreaterThan Logic Operator + + constant gt_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_gt_table : b_stdlogic_2D := ( + -- LHS => ( RHS ) + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( others=>false ), + '1'=>( '0'=>true, 'L'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( others=>false ), + 'H'=>( '0'=>true, 'L'=>true, others=>false ), + '-'=>( others=>false ), + others=>(others=>false)); + + -- GreaterThanorEqual Logic Operator + + constant ge_table : stdlogic_2D := ( + -- RHS U X 0 1 Z W L H - | + -- LHS ---------------------------------------------------+--- + ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | 1 + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W + ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L + ( 'U', 'X', '1', '1', 'X', 'X', '1', '1', 'X' ), -- | H + ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | - + others=>(others=>'-') + ); + + constant b_ge_table : b_stdlogic_2D := ( + -- RHS => - 0 U X 1 Z W L H + -- LHS -------------------------------------------------------------------------------------------------- + 'U'=>( others=>false ), + 'X'=>( others=>false ), + '0'=>( '0'=>true, 'L'=>true, others=>false ), + '1'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + 'Z'=>( others=>false ), + 'W'=>( others=>false ), + 'L'=>( '0'=>true, 'L'=>true, others=>false ), + 'H'=>( '0'=>true, '1'=>true, 'L'=>true, 'H'=>true, others=>false ), + '-'=>( others=>false ), + others=>( others=>false ) + ); +-- Synopsys synthesis_on + + ------------------------------------------------------------------- + -- Relational Functions returning Boolean + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return boolean is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return boolean is + begin + return not( std_match( l, r ) ); + end ne; + + function gt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_gt_table( l, r ); + -- Synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_GEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_ge_table( l, r ); + -- synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LT + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_lt_table( l, r ); + -- synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return boolean is + variable result : boolean; + -- pragma built_in SYN_LEQ + begin + -- synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := b_le_table( l, r ); + -- synopsys translate_on + return result; + end le; + + ------------------------------------------------------------------- + -- Relational Functions returning std_ulogic + ------------------------------------------------------------------- + + function eq( l,r : std_ulogic ) return std_ulogic is + begin + return std_match( l, r ); + end eq; + + function ne( l,r : std_ulogic ) return std_ulogic is + begin + return not std_match( l, r ) ; + end ne; + + function gt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := gt_table( l, r ); + -- synopsys translate_on + return result; + end gt; + + function ge( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := ge_table( l, r ); + -- Synopsys translate_on + return result; + end ge; + + function lt( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := lt_table( l, r ); + -- Synopsys translate_on + return result; + end lt; + + function le( l,r : std_ulogic ) return std_ulogic is + variable result : std_ulogic; + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + assert ( l /= '-' ) and ( r /= '-' ) + report "Invalid dont_care in relational function" + severity error; + result := le_table( l, r ); + -- Synopsys translate_on + return result; + end le; + + -- + -- utility function get rid of most meta values + -- + function to_x01d( d : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + variable result : std_ulogic; + begin + -- Synopsys translate_off + case d is + when '0' | 'L' => result := '0'; + when '1' | 'H' => result := '1'; + when '-' => result := '-'; + when others => result := 'X'; + end case; + -- Synopsys translate_on + return result; + end to_x01d; + + ------------------------------------------------------------------- + -- Vectored Relational Functions returning Boolean + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := std_match(l,r); + return result; + end eq; + + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := not std_match(l,r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) > unsigned(r); + return result; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) >= unsigned(r); + return result; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) < unsigned(r); + return result; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return boolean is + variable result : boolean ; + begin + result := unsigned(l) <= unsigned(r); + return result; + end le; + + ------------------------------------------------------------------- + -- vectored relational functions returning std_ulogic + ------------------------------------------------------------------- + function eq( l,r : std_ulogic_vector) return std_ulogic is + variable result : std_ulogic ; + begin + result := std_match( l, r ) ; + --result := (l ?= r); + return result; + end eq; + --------------------------------------------------------------------- + function ne( l,r : std_ulogic_vector) return std_ulogic is + variable result :std_ulogic ; + begin + result := not std_match( l, r ) ; + --result := not (l ?= r); + return result; + end ne; + + ------------------------------------------------------------------- + function gt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GT + begin + result := unsigned(l) > unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end gt; + + ------------------------------------------------------------------- + function ge( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_GEQ + begin + result := unsigned(l) >= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end ge; + + ------------------------------------------------------------------- + function lt( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LT + begin + result := unsigned(l) < unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end lt; + + ------------------------------------------------------------------- + function le( l,r : std_ulogic_vector) return std_ulogic is + variable result : boolean ; + -- pragma built_in SYN_LEQ + begin + result := unsigned(l) <= unsigned(r); + if (result = true ) then + return '1' ; + else + return '0'; + end if ; + end le; + + ------------------------------------------------------------------- + -- Type Conversion Functions + ------------------------------------------------------------------- + ------------------------------------------------------------------- + -- Boolean Conversions + ------------------------------------------------------------------- + function tconv ( b : boolean ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : boolean ) return string is + begin + case b is + when false => return("FALSE"); + when true => return("TRUE"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : boolean ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when false => return('0'); + when true => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit Conversions + ------------------------------------------------------------------- + function tconv ( b : bit ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return(false); + when '1' => return(true); + end case; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit ) return character is + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + function tconv ( b : bit ) return string is + begin + case b is + when '0' => return("0"); + when '1' => return("1"); + end case; + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case b is + when '0' => return(0); + when '1' => return(1); + end case; + end tconv ; + + function tconv ( b : bit ) return std_ulogic is + -- pragma built_in SYN_FEED_THRU + begin + case b is + when '0' => return('0'); + when '1' => return('1'); + end case; + end tconv ; + + ------------------------------------------------------------------- + -- Bit_vector Conversions + ------------------------------------------------------------------- + function tconv ( b : bit_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : bit_vector(1 to b'length); + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + new_value := b; + for i in new_value'length to 1 loop + if b(i)='1' then + int_result := int_result + (2**int_exp); + end if; + int_exp := int_exp + 1; + end loop; + -- synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( b : bit_vector ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + begin + result := (others => '0'); + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( b : bit_vector; base : base_t ) return string is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : string ( 1 to b'length ); + variable start : positive; + variable extra : natural; + variable resultlength : positive; + subtype bv is bit_vector( 1 to 1 ); + subtype qv is bit_vector( 1 to 2 ); + subtype ov is bit_vector( 1 to 3 ); + subtype hv is bit_vector( 1 to 4 ); + begin + case base is + when bin => + resultlength := sv'length; + start := 1; + for i in start to resultlength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultlength := b'length/ov'length; + start := 1; + when 1 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultlength := ( b'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := b'length rem hv'length; + case extra is + when 0 => + resultLength := b'length/hv'length; + start := 1; + when 1 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + end case; + when 2 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + end case; + when 3 => + resultLength := ( b'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when o"0" => result( 1 ) := '0'; + when o"1" => result( 1 ) := '1'; + when o"2" => result( 1 ) := '2'; + when o"3" => result( 1 ) := '3'; + when o"4" => result( 1 ) := '4'; + when o"5" => result( 1 ) := '5'; + when o"6" => result( 1 ) := '6'; + when o"7" => result( 1 ) := '7'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + return result( 1 to resultLength ); + end tconv ; +-- Synopsys translate_on + + function tconv ( b : bit_vector ) return std_ulogic_vector is + alias sv : bit_vector ( 1 to b'length ) is b; + variable result : std_ulogic_vector ( 1 to b'length ); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + end case; + end loop; + return result; + end tconv ; + + --function tconv ( b : bit_vector ) return std_logic_vector is + -- alias sv : bit_vector ( 1 to b'length ) is b; + -- variable result : std_logic_vector ( 1 to b'length ); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- end case; + -- end loop; + -- return result; + --end tconv ; + + ------------------------------------------------------------------- + -- Integer conversion to other types + ------------------------------------------------------------------- + function tconv ( n : integer;w : positive) return bit_vector is + variable result : bit_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => '0'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- synopsys translate_on + return result; + end tconv; + + function tconv ( n : integer; w : positive) return std_ulogic_vector is + variable result : std_ulogic_vector(w-1 downto 0) ; + variable ib : integer; + variable test : integer; + -- pragma built_in SYN_INTEGER_TO_UNSIGNED + begin + if n < 0 then + result := (others => 'X'); + else + ib := n; + result := (others => '0'); + for i in result'reverse_range loop + exit when ib = 0; + test := ib rem 2; + if test = 1 then + result(i) := '1'; + else + result(i) := '0'; + end if; + ib := ib / 2; + end loop; + end if; + -- Synopsys translate_off + assert n >= 0 + report "tconv: n < 0 is not permitted" + severity warning; + assert ib = 0 + report "tconv: integer overflows requested result width" + severity warning; + -- Synopsys translate_on + return result; + end tconv; + +-- Synopsys translate_off + function tconv ( n : integer; w : positive ) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to w ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n; + for i in result'reverse_range loop + test := ib rem 10; + + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + + ib := ib / 10; + + exit when ib = 0; + end loop; + + if ib < 0 then + result(1) := sign; + end if; + + assert + not( ( ( ib < 0 ) and ( ( abs ib ) > ( 10**(w-1) - 1 ) ) ) or + ( ( ib >= 0 ) and ( ib > ( 10**w - 1 ) ) ) ) + report "tconv: integer overflows requested result width" + severity warning; + + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( n : integer) return string is + subtype digit is integer range 0 to 9; + variable result : string( 1 to 10 ) ; + variable ib : integer; + variable msd : integer; + variable sign : character := '-'; + variable test : digit; + begin + ib := abs n ; + for i in result'reverse_range loop + test := ib rem 10; + case test is + when 0 => result(i) := '0'; + when 1 => result(i) := '1'; + when 2 => result(i) := '2'; + when 3 => result(i) := '3'; + when 4 => result(i) := '4'; + when 5 => result(i) := '5'; + when 6 => result(i) := '6'; + when 7 => result(i) := '7'; + when 8 => result(i) := '8'; + when 9 => result(i) := '9'; + end case; + ib := ib / 10; + if ib = 0 then + msd := i; + exit; + end if; + end loop; + if ib < 0 then + return sign & result(msd to 10); + else + return result(msd to 10); + end if; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- String conversion to other types + ------------------------------------------------------------------- +-- Synopsys translate_off + function TConv ( s : string ) return integer is + variable result : integer ; + alias si : string( s'length downto 1 ) is s; + variable invalid : boolean ; + begin + invalid := false ; + for i in si'range loop + case si( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 thru 9" & + "; treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return integer is + alias sv : string ( s'length downto 1 ) is s; + variable result : integer ; + variable invalid : boolean ; + variable vc_len : integer ; + variable validchars : string(1 to 20) := "0 thru 9 or A thru F"; + begin + invalid := false ; + case base is + when bin => + vc_len := 6; + validchars(1 to 6) := "0 or 1"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 2 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when oct => + vc_len := 8; + validchars(1 to 8) := "0 thru 7"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 8 ** ( i - 1 ) ; + when '2' => result := result + 2 * 8 ** ( i - 1 ) ; + when '3' => result := result + 3 * 8 ** ( i - 1 ) ; + when '4' => result := result + 4 * 8 ** ( i - 1 ) ; + when '5' => result := result + 5 * 8 ** ( i - 1 ) ; + when '6' => result := result + 6 * 8 ** ( i - 1 ) ; + when '7' => result := result + 7 * 8 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when dec => + vc_len := 8; + validchars(1 to 8) := "0 thru 9"; + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 10 ** ( i - 1 ) ; + when '2' => result := result + 2 * 10 ** ( i - 1 ) ; + when '3' => result := result + 3 * 10 ** ( i - 1 ) ; + when '4' => result := result + 4 * 10 ** ( i - 1 ) ; + when '5' => result := result + 5 * 10 ** ( i - 1 ) ; + when '6' => result := result + 6 * 10 ** ( i - 1 ) ; + when '7' => result := result + 7 * 10 ** ( i - 1 ) ; + when '8' => result := result + 8 * 10 ** ( i - 1 ) ; + when '9' => result := result + 9 * 10 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when hex => + for i in sv'range loop + case sv( i ) is + when '0' => null; + when '1' => result := result + 16 ** ( i - 1 ) ; + when '2' => result := result + 2 * 16 ** ( i - 1 ) ; + when '3' => result := result + 3 * 16 ** ( i - 1 ) ; + when '4' => result := result + 4 * 16 ** ( i - 1 ) ; + when '5' => result := result + 5 * 16 ** ( i - 1 ) ; + when '6' => result := result + 6 * 16 ** ( i - 1 ) ; + when '7' => result := result + 7 * 16 ** ( i - 1 ) ; + when '8' => result := result + 8 * 16 ** ( i - 1 ) ; + when '9' => result := result + 9 * 16 ** ( i - 1 ) ; + when 'A' | 'a' => result := result + 10 * 16 ** ( i - 1 ) ; + when 'B' | 'b' => result := result + 11 * 16 ** ( i - 1 ) ; + when 'C' | 'c' => result := result + 12 * 16 ** ( i - 1 ) ; + when 'D' | 'd' => result := result + 13 * 16 ** ( i - 1 ) ; + when 'E' | 'e' => result := result + 14 * 16 ** ( i - 1 ) ; + when 'F' | 'f' => result := result + 15 * 16 ** ( i - 1 ) ; + when others => invalid := true; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + + end case; + + assert not invalid + report "String contained characters other than " & + validchars(1 to vc_len) & "; treating invalid characters as 0's" + severity warning; + + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit is + variable result : bit; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := '0'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return bit_vector is + variable result : bit_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as 0's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return bit_vector is + variable result : bit_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := o"0"; + when '1' => result( (3*i)-2 to 3*i ) := o"1"; + when '2' => result( (3*i)-2 to 3*i ) := o"2"; + when '3' => result( (3*i)-2 to 3*i ) := o"3"; + when '4' => result( (3*i)-2 to 3*i ) := o"4"; + when '5' => result( (3*i)-2 to 3*i ) := o"5"; + when '6' => result( (3*i)-2 to 3*i ) := o"6"; + when '7' => result( (3*i)-2 to 3*i ) := o"7"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := o"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := x"0"; + when '1' => result( (4*i)-3 to 4*i ) := x"1"; + when '2' => result( (4*i)-3 to 4*i ) := x"2"; + when '3' => result( (4*i)-3 to 4*i ) := x"3"; + when '4' => result( (4*i)-3 to 4*i ) := x"4"; + when '5' => result( (4*i)-3 to 4*i ) := x"5"; + when '6' => result( (4*i)-3 to 4*i ) := x"6"; + when '7' => result( (4*i)-3 to 4*i ) := x"7"; + when '8' => result( (4*i)-3 to 4*i ) := x"8"; + when '9' => result( (4*i)-3 to 4*i ) := x"9"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := x"A"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := x"B"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := x"C"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := x"D"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := x"E"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := x"F"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := x"0"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as 0's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic is + variable result : std_ulogic; + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + assert s'length = 1 + report "String conversion to bit longer that 1 character" + severity warning; + case si(1) is + when '0' => result := '0'; + when '1' => result := '1'; + when others => + invalid := true; + result := 'X'; + end case; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result; + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := 'X'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treating invalid characters as X's" + severity warning; + return result( 1 to result'length ); + end tconv; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : string; base : base_t ) return std_ulogic_vector is + variable result : std_ulogic_vector( 1 to 4*s'length ); + alias si : string( 1 to s'length ) is s; + variable invalid : boolean := false; + begin + case base is + when bin => + for i in si'range loop + case si(i) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when others => + invalid := true; + result( i ) := '0'; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 or 1; " & + "treated invalid characters as 0's" + severity warning; + return result(1 to s'length) ; + + when oct => + for i in si'range loop + case si(i) is + when '0' => result( (3*i)-2 to 3*i ) := "000"; + when '1' => result( (3*i)-2 to 3*i ) := "001"; + when '2' => result( (3*i)-2 to 3*i ) := "010"; + when '3' => result( (3*i)-2 to 3*i ) := "011"; + when '4' => result( (3*i)-2 to 3*i ) := "100"; + when '5' => result( (3*i)-2 to 3*i ) := "101"; + when '6' => result( (3*i)-2 to 3*i ) := "110"; + when '7' => result( (3*i)-2 to 3*i ) := "111"; + when others => + invalid := true; + result( (3*i)-2 to 3*i ) := "XXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 7; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 3*s'length ); + + when hex => + for i in si'range loop + case si(i) is + when '0' => result( (4*i)-3 to 4*i ) := "0000"; + when '1' => result( (4*i)-3 to 4*i ) := "0001"; + when '2' => result( (4*i)-3 to 4*i ) := "0010"; + when '3' => result( (4*i)-3 to 4*i ) := "0011"; + when '4' => result( (4*i)-3 to 4*i ) := "0100"; + when '5' => result( (4*i)-3 to 4*i ) := "0101"; + when '6' => result( (4*i)-3 to 4*i ) := "0110"; + when '7' => result( (4*i)-3 to 4*i ) := "0111"; + when '8' => result( (4*i)-3 to 4*i ) := "1000"; + when '9' => result( (4*i)-3 to 4*i ) := "1001"; + when 'A' | 'a' => result( (4*i)-3 to 4*i ) := "1010"; + when 'B' | 'b' => result( (4*i)-3 to 4*i ) := "1011"; + when 'C' | 'c' => result( (4*i)-3 to 4*i ) := "1100"; + when 'D' | 'd' => result( (4*i)-3 to 4*i ) := "1101"; + when 'E' | 'e' => result( (4*i)-3 to 4*i ) := "1110"; + when 'F' | 'f' => result( (4*i)-3 to 4*i ) := "1111"; + when others => + invalid := true; + result( (4*i)-3 to 4*i ) := "XXXX"; + end case; + end loop; + assert not invalid + report "String contained characters other than 0 through 9 or " & + "A through F; " & + "treated invalid characters as X's" + severity warning; + return result( 1 to 4*s'length ); + + when others => + assert false report "Unsupported base passed." severity warning; + return result ; + + end case; + end tconv; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_uLogic Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic ) return boolean is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return(false); + when '1' => return(true); + when 'L' => return(false); + when 'H' => return(true); + when others => return(false); + end case; + end; + + function tconv ( s : std_ulogic ) return bit is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return('0'); + when '1' => return('1'); + when 'L' => return('0'); + when 'H' => return('1'); + when others => return('0'); + end case; + end; + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return character is + begin + case s is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic ) return string is + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic ) return integer is + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + case s is + when '0' => return(0); + when 'L' => return(0); + when '1' => return(1); + when 'H' => return(1); + when 'U' => return(0); + when 'W' => return(0); + when '-' => return(0); + when 'Z' => return(0); + when others => return(0); + end case; + end; + + function tconv ( s : std_ulogic ) return std_ulogic_vector is + -- pragma built_in SYN_FEED_THRU + begin + case s is + when '0' => return("0"); + when 'L' => return("L"); + when '1' => return("1"); + when 'H' => return("H"); + when 'U' => return("U"); + when 'W' => return("W"); + when '-' => return("-"); + when 'Z' => return("Z"); + when others => return("X"); + end case; + end; + + ------------------------------------------------------------------- + -- std_ulogic_vector Conversions + ------------------------------------------------------------------- + function tconv ( s : std_ulogic_vector ) return bit_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : bit_vector ( 1 to s'length ) ; + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when others => result(i) := '0'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return std_logic_vector is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : std_logic_vector ( 1 to s'length ) := (others => 'X'); + -- pragma built_in SYN_FEED_THRU + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when '1' => result(i) := '1'; + when 'L' => result(i) := '0'; + when 'H' => result(i) := '1'; + when 'W' => result(i) := 'W'; + when '-' => result(i) := '-'; + when 'U' => result(i) := 'U'; + when 'X' => result(i) := 'X'; + when 'Z' => result(i) := 'Z'; + end case; + end loop; + return result; + end; + + function tconv ( s : std_ulogic_vector ) return integer is + variable int_result : integer ; + variable int_exp : integer ; + variable new_value : std_ulogic_vector(1 to s'length) ; + variable invalid : boolean ; + -- pragma built_in SYN_UNSIGNED_TO_INTEGER + begin + -- Synopsys translate_off + int_result := 0; + int_exp := 0; + invalid := false ; + new_value := s ; + for i in new_value'length downto 1 loop + case new_value(i) is + when '1' => int_result := int_result + (2**int_exp); + when '0' => null; + when others => + invalid := true; + end case; + int_exp := int_exp + 1; + end loop; + assert not invalid + report "The std_ulogic_Vector input contained values " & + "other than '0' and '1'. They were treated as zeroes." + severity warning; + -- Synopsys translate_on + return int_result; + end tconv ; + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ) := (others => 'X'); + begin + for i in result'range loop + case sv(i) is + when '0' => result(i) := '0'; + when 'L' => result(i) := 'L'; + when '1' => result(i) := '1'; + when 'H' => result(i) := 'H'; + when 'U' => result(i) := 'U'; + when '-' => result(i) := '-'; + when 'W' => result(i) := 'W'; + when 'Z' => result(i) := 'Z'; + when others => result(i) := 'X'; + end case; + end loop; + return result; + end; +-- Synopsys translate_on + +-- Synopsys translate_off + function tconv ( s : std_ulogic_vector; base : base_t ) return string is + alias sv : std_ulogic_vector ( 1 to s'length ) is s; + variable result : string ( 1 to s'length ); + variable start : positive; + variable extra : natural; + variable resultLength : positive; + subtype bv is std_ulogic_vector( 1 to 1 ); + subtype qv is std_ulogic_vector( 1 to 2 ); + subtype ov is std_ulogic_vector( 1 to 3 ); + subtype hv is std_ulogic_vector( 1 to 4 ); + begin + case base is + when bin => + resultLength := sv'length; + start := 1; + for i in start to resultLength loop + case sv( i ) is + when '0' => result( i ) := '0'; + when '1' => result( i ) := '1'; + when 'X' => result( i ) := 'X'; + when 'L' => result( i ) := 'L'; + when 'H' => result( i ) := 'H'; + when 'W' => result( i ) := 'W'; + when '-' => result( i ) := '-'; + when 'U' => result( i ) := 'U'; + when 'Z' => result( i ) := 'Z'; + end case; + end loop; + + when oct => + extra := sv'length rem ov'length; + case extra is + when 0 => + resultLength := s'length/ov'length; + start := 1; + when 1 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/ov'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case ov'( SV( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + when "000" => result( i+start ) := '0'; + when "001" => result( i+start ) := '1'; + when "010" => result( i+start ) := '2'; + when "011" => result( i+start ) := '3'; + when "100" => result( i+start ) := '4'; + when "101" => result( i+start ) := '5'; + when "110" => result( i+start ) := '6'; + when "111" => result( i+start ) := '7'; + when "---" => result( i+start ) := '-'; + when "XXX" => result( i+start ) := 'X'; + when "UUU" => result( i+start ) := 'U'; + when "ZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when hex => + extra := s'length rem hv'length; + case extra is + when 0 => + resultLength := s'length/hv'length; + start := 1; + when 1 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case sv( 1 ) is + when '0' => result( 1 ) := '0'; + when '1' => result( 1 ) := '1'; + when '-' => result( 1 ) := '-'; + when 'X' => result( 1 ) := 'X'; + when 'U' => result( 1 ) := 'U'; + when 'Z' => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 2 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case qv'( sv( 1 to 2 ) ) is + when "00" => result( 1 ) := '0'; + when "01" => result( 1 ) := '1'; + when "10" => result( 1 ) := '2'; + when "11" => result( 1 ) := '3'; + when "--" => result( 1 ) := '-'; + when "XX" => result( 1 ) := 'X'; + when "UU" => result( 1 ) := 'U'; + when "ZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when 3 => + resultLength := ( s'length/hv'length ) + 1; + start := 2; + case ov'( sv( 1 to 3 ) ) is + when "000" => result( 1 ) := '0'; + when "001" => result( 1 ) := '1'; + when "010" => result( 1 ) := '2'; + when "011" => result( 1 ) := '3'; + when "100" => result( 1 ) := '4'; + when "101" => result( 1 ) := '5'; + when "110" => result( 1 ) := '6'; + when "111" => result( 1 ) := '7'; + when "---" => result( 1 ) := '-'; + when "XXX" => result( 1 ) := 'X'; + when "UUU" => result( 1 ) := 'U'; + when "ZZZ" => result( 1 ) := 'Z'; + when others => result( 1 ) := '.'; + end case; + when others => + assert false report "TCONV fatal condition" severity failure; + end case; + + for i in 0 to resultLength - start loop + case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + when "0000" => result( i+start ) := '0'; + when "0001" => result( i+start ) := '1'; + when "0010" => result( i+start ) := '2'; + when "0011" => result( i+start ) := '3'; + when "0100" => result( i+start ) := '4'; + when "0101" => result( i+start ) := '5'; + when "0110" => result( i+start ) := '6'; + when "0111" => result( i+start ) := '7'; + when "1000" => result( i+start ) := '8'; + when "1001" => result( i+start ) := '9'; + when "1010" => result( i+start ) := 'A'; + when "1011" => result( i+start ) := 'B'; + when "1100" => result( i+start ) := 'C'; + when "1101" => result( i+start ) := 'D'; + when "1110" => result( i+start ) := 'E'; + when "1111" => result( i+start ) := 'F'; + when "----" => result( i+start ) := '-'; + when "XXXX" => result( i+start ) := 'X'; + when "UUUU" => result( i+start ) := 'U'; + when "ZZZZ" => result( i+start ) := 'Z'; + when others => result( i+start ) := '.'; + end case; + end loop; + + when others => + assert false report "Unsupported base passed." severity warning; + end case; + return result( 1 to resultLength ); + end; +-- Synopsys translate_on + + function tconv ( s : std_ulogic_vector ) return std_ulogic is + alias sv : std_ulogic_vector( 1 to s'length ) is s; + variable result : std_ulogic; + -- pragma built_in SYN_FEED_THRU + begin + case sv(s'length) is + when '0' => return('0'); + when 'L' => return('L'); + when '1' => return('1'); + when 'H' => return('H'); + when 'U' => return('U'); + when 'W' => return('W'); + when '-' => return('-'); + when 'Z' => return('Z'); + when others => return('X'); + end case; + end; + + ------------------------------------------------------------------- + -- std_logic_vector Conversions + ------------------------------------------------------------------- + --function tconv ( s : std_logic_vector ) return bit_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : bit_vector ( 1 to s'length ) := (others => '0'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when others => result(i) := '0'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return std_ulogic_vector is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : std_ulogic_vector ( 1 to s'length ) := (others => 'X'); + ---- pragma built_in SYN_FEED_THRU + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when '1' => result(i) := '1'; + -- when 'L' => result(i) := '0'; + -- when 'H' => result(i) := '1'; + -- when 'W' => result(i) := 'W'; + -- when '-' => result(i) := '-'; + -- when 'U' => result(i) := 'U'; + -- when 'X' => result(i) := 'X'; + -- when 'Z' => result(i) := 'Z'; + -- end case; + -- end loop; + -- return result; + --end; + + --function tconv ( s : std_logic_vector ) return integer is + -- variable int_result : integer := 0; + -- variable int_exp : integer := 0; + -- alias new_value : std_logic_vector(1 to s'length) is s ; + -- variable invalid : boolean := false; + ---- pragma built_in SYN_UNSIGNED_TO_INTEGER + --begin + ---- Synopsys translate_off + -- for i in new_value'length downto 1 loop + -- case new_value(i) is + -- when '1' => int_result := int_result + (2**int_exp); + -- when '0' => null; + -- when others => + -- invalid := true; + -- end case; + -- int_exp := int_exp + 1; + -- end loop; + -- assert not invalid + -- report "The std_logic_Vector input contained values " & + -- "other than '0' and '1'. They were treated as zeroes." + -- severity warning; + ---- Synopsys translate_on + -- return int_result; + --end tconv ; + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ) := (others => 'X'); + --begin + -- for i in result'range loop + -- case sv(i) is + -- when '0' => result(i) := '0'; + -- when 'L' => result(i) := 'L'; + -- when '1' => result(i) := '1'; + -- when 'H' => result(i) := 'H'; + -- when 'U' => result(i) := 'U'; + -- when '-' => result(i) := '-'; + -- when 'W' => result(i) := 'W'; + -- when 'Z' => result(i) := 'Z'; + -- when others => result(i) := 'X'; + -- end case; + -- end loop; + -- return result; + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + --function tconv ( s : std_logic_vector; base : base_t ) return string is + -- alias sv : std_logic_vector ( 1 to s'length ) is s; + -- variable result : string ( 1 to s'length ); + -- variable start : positive; + -- variable extra : natural; + -- variable resultlength : positive; + -- subtype bv is std_logic_vector( 1 to 1 ); + -- subtype qv is std_logic_vector( 1 to 2 ); + -- subtype ov is std_logic_vector( 1 to 3 ); + -- subtype hv is std_logic_vector( 1 to 4 ); + --begin + -- case base is + -- when bin => + -- resultLength := sv'length; + -- start := 1; + -- for i in start to resultLength loop + -- case sv( i ) is + -- when '0' => result( i ) := '0'; + -- when '1' => result( i ) := '1'; + -- when 'X' => result( i ) := 'X'; + -- when 'L' => result( i ) := 'L'; + -- when 'H' => result( i ) := 'H'; + -- when 'W' => result( i ) := 'W'; + -- when '-' => result( i ) := '-'; + -- when 'U' => result( i ) := 'U'; + -- when 'Z' => result( i ) := 'Z'; + -- end case; + -- end loop; + + -- when oct => + -- extra := sv'length rem ov'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/ov'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/ov'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case ov'( sv( (ov'length*i)+(extra+1) to (ov'length*i)+(extra+3) ) ) is + -- when "000" => result( i+start ) := '0'; + -- when "001" => result( i+start ) := '1'; + -- when "010" => result( i+start ) := '2'; + -- when "011" => result( i+start ) := '3'; + -- when "100" => result( i+start ) := '4'; + -- when "101" => result( i+start ) := '5'; + -- when "110" => result( i+start ) := '6'; + -- when "111" => result( i+start ) := '7'; + -- when "---" => result( i+start ) := '-'; + -- when "XXX" => result( i+start ) := 'X'; + -- when "UUU" => result( i+start ) := 'U'; + -- when "ZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when hex => + -- extra := s'length rem hv'length; + -- case extra is + -- when 0 => + -- resultLength := s'length/hv'length; + -- start := 1; + -- when 1 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case sv( 1 ) is + -- when '0' => result( 1 ) := '0'; + -- when '1' => result( 1 ) := '1'; + -- when '-' => result( 1 ) := '-'; + -- when 'X' => result( 1 ) := 'X'; + -- when 'U' => result( 1 ) := 'U'; + -- when 'Z' => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 2 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case qv'( sv( 1 to 2 ) ) is + -- when "00" => result( 1 ) := '0'; + -- when "01" => result( 1 ) := '1'; + -- when "10" => result( 1 ) := '2'; + -- when "11" => result( 1 ) := '3'; + -- when "--" => result( 1 ) := '-'; + -- when "XX" => result( 1 ) := 'X'; + -- when "UU" => result( 1 ) := 'U'; + -- when "ZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when 3 => + -- resultLength := ( s'length/hv'length ) + 1; + -- start := 2; + -- case ov'( sv( 1 to 3 ) ) is + -- when "000" => result( 1 ) := '0'; + -- when "001" => result( 1 ) := '1'; + -- when "010" => result( 1 ) := '2'; + -- when "011" => result( 1 ) := '3'; + -- when "100" => result( 1 ) := '4'; + -- when "101" => result( 1 ) := '5'; + -- when "110" => result( 1 ) := '6'; + -- when "111" => result( 1 ) := '7'; + -- when "---" => result( 1 ) := '-'; + -- when "XXX" => result( 1 ) := 'X'; + -- when "UUU" => result( 1 ) := 'U'; + -- when "ZZZ" => result( 1 ) := 'Z'; + -- when others => result( 1 ) := '.'; + -- end case; + -- when others => + -- assert false report "TCONV fatal condition" severity failure; + -- end case; + + -- for i in 0 to resultLength - start loop + -- case hv'( SV( (hv'length*i)+(extra+1) to (hv'length*i)+(extra+4) ) ) is + -- when "0000" => result( i+start ) := '0'; + -- when "0001" => result( i+start ) := '1'; + -- when "0010" => result( i+start ) := '2'; + -- when "0011" => result( i+start ) := '3'; + -- when "0100" => result( i+start ) := '4'; + -- when "0101" => result( i+start ) := '5'; + -- when "0110" => result( i+start ) := '6'; + -- when "0111" => result( i+start ) := '7'; + -- when "1000" => result( i+start ) := '8'; + -- when "1001" => result( i+start ) := '9'; + -- when "1010" => result( i+start ) := 'A'; + -- when "1011" => result( i+start ) := 'B'; + -- when "1100" => result( i+start ) := 'C'; + -- when "1101" => result( i+start ) := 'D'; + -- when "1110" => result( i+start ) := 'E'; + -- when "1111" => result( i+start ) := 'F'; + -- when "----" => result( i+start ) := '-'; + -- when "XXXX" => result( i+start ) := 'X'; + -- when "UUUU" => result( i+start ) := 'U'; + -- when "ZZZZ" => result( i+start ) := 'Z'; + -- when others => result( i+start ) := '.'; + -- end case; + -- end loop; + + -- when others => + -- assert false report "Unsupported base passed." severity warning; + -- end case; + -- return result( 1 to resultLength ); + --end; +-- Synopsys translate_on + +-- Synopsys translate_off + function hexstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (4 - (d'length mod 4))) - 1) ) := ( others => '0' ); + variable r : string(1 to (nd'length/4)); + variable hexsize : integer; + variable offset : integer; + subtype iv4 is Std_Ulogic_vector(1 to 4); + begin + + offset := d'length mod 4; + + if offset = 0 then + hexsize := d'length / 4; + nd( 0 to d'length - 1 ) := d; + else + hexsize := nd'length / 4; + nd( ( nd'left + (4 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to hexsize - 1 loop + + case iv4( nd( ( i * 4 ) to ( ( i * 4 ) + 3 ) ) ) is + when "0000" => r(i + 1) := '0'; + when "0001" => r(i + 1) := '1'; + when "0010" => r(i + 1) := '2'; + when "0011" => r(i + 1) := '3'; + when "0100" => r(i + 1) := '4'; + when "0101" => r(i + 1) := '5'; + when "0110" => r(i + 1) := '6'; + when "0111" => r(i + 1) := '7'; + when "1000" => r(i + 1) := '8'; + when "1001" => r(i + 1) := '9'; + when "1010" => r(i + 1) := 'A'; + when "1011" => r(i + 1) := 'B'; + when "1100" => r(i + 1) := 'C'; + when "1101" => r(i + 1) := 'D'; + when "1110" => r(i + 1) := 'E'; + when "1111" => r(i + 1) := 'F'; + when "----" => r(i + 1) := '-'; + when "XXXX" => r(i + 1) := 'X'; + when "UUUU" => r(i + 1) := 'U'; + when "ZZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r(1 to hexsize); + end hexstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function octstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector( 0 to ((d'length + (3 - (d'length mod 3))) - 1) ) := ( others => '0' ); + variable offset : integer; + variable r : string(1 to (nd'length/3)); + variable octsize : integer; + subtype iv3 is Std_Ulogic_vector(1 to 3); + begin + + offset := d'length mod 3; + + if offset = 0 then + octsize := d'length / 3; + nd( 0 to d'length - 1 ) := d; + else + octsize := nd'length / 3; + nd( ( nd'left + (3 - offset) ) to nd'right ) := d; + end if; + + for i in 0 to octsize - 1 loop + + case iv3( nd( ( i * 3 ) to ( ( i * 3 ) + 2 ) ) ) is + when "000" => r(i + 1) := '0'; + when "001" => r(i + 1) := '1'; + when "010" => r(i + 1) := '2'; + when "011" => r(i + 1) := '3'; + when "100" => r(i + 1) := '4'; + when "101" => r(i + 1) := '5'; + when "110" => r(i + 1) := '6'; + when "111" => r(i + 1) := '7'; + when "---" => r(i + 1) := '-'; + when "XXX" => r(i + 1) := 'X'; + when "UUU" => r(i + 1) := 'U'; + when "ZZZ" => r(i + 1) := 'Z'; + when others => r(i + 1) := '.'; + end case; + + end loop; + + return r; + end octstring; +-- Synopsys translate_on + +-- Synopsys translate_off + function bitstring( d : std_ulogic_vector ) return string is + variable nd : + Std_Ulogic_vector(0 to ( d'length - 1 ) ) := ( others => '0' ); + variable r : string(1 to (nd'length)); + begin + nd := d; + for i in nd'range loop + r(i + 1) := std_ulogic_to_character( nd(i) ); + end loop; + return r; + end bitstring; +-- Synopsys translate_on + + ------------------------------------------------------------------- + -- Std_Match functions + ------------------------------------------------------------------- + constant no_warning: boolean := false; -- default to emit warnings + + -- Id: M.1a + function std_match (l, r: std_ulogic) return std_ulogic is + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if ; + end std_match; + + -- Id: M.4b + function std_match (l, r: std_ulogic_vector) return std_ulogic is + variable result : boolean ; + begin + if (l ?= r) then + return '1' ; + else + return '0' ; + end if; + end std_match; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning std_ulogic + ------------------------------------------------------------------- + function "=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + if (l - r) = 0 then + return ('1'); + else + return ('0'); + end if ; + end "="; + + function "/=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + if (l - r) = 0 then + return ('0'); + else + return ('1'); + end if ; + end "/="; + + function ">" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GT + begin + if (l - r) > 0 then + return ('1'); + else + return ('0'); + end if ; + end ">"; + + function ">=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + if (l - r) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end ">="; + + function "<" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LT + begin + if (r - l) > 0 then + return ('1'); + else + return ('0'); + end if ; + end "<"; + + function "<=" ( l,r : integer ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + if (r - l) >= 0 then + return ('1'); + else + return ('0'); + end if ; + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + function "=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_EQL + begin + return ( tconv( l = r ) ); + end "="; + + function "/=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + return ( tconv( l /= r ) ); + end "/="; + + function ">" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GT + begin + return ( tconv( l > r ) ); + end ">"; + + function ">=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + return ( tconv( l >= r ) ); + end ">="; + + function "<" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LT + begin + return ( tconv( l < r ) ); + end "<"; + + function "<=" ( l,r : std_ulogic ) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + return ( tconv( l <= r ) ); + end "<="; + + ------------------------------------------------------------------- + -- Overloaded Relational Operators returning STD_uLogic + ------------------------------------------------------------------- + + function "=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_EQL + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the = " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l = r ) ); + end "="; + + ------------------------------------------------------------------- + function "/=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_NEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the /= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l /= r ) ); + end "/="; + + ------------------------------------------------------------------- + function ">" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the > " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l > r ) ); + end ">"; + + ------------------------------------------------------------------- + function ">=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_GEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the >= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l >= r ) ); + end ">="; + + ------------------------------------------------------------------- + function "<" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LT + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the < " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l < r ) ); + end "<"; + + ------------------------------------------------------------------- + function "<=" ( l,r : std_ulogic_vector) return std_ulogic is + -- pragma built_in SYN_LEQ + begin + -- Synopsys translate_off + if l'length /= r'length then + assert false + report "The bit lengths of the two inputs to the <= " & + "operator are unequal. " + severity error; + return '0' ; + end if ; + -- Synopsys translate_on + return ( tconv( l <= r ) ); + end "<="; + +--============================================================== + -- Shift and Rotate Functions +--============================================================== +----------Local Subprograms - shift/rotate ops------------------- + -- Synopsys translate_off + constant NAU: std_ulogic_vector(0 downto 1) := (others => '0'); + -- Synopsys translate_on + + function xsll (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SLLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l downto count) := xarg(arg_l-count downto 0); + end if; + return result; + end xsll; + + function xsrl (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + -- pragma built_in SYN_SRLU + begin + result := (others => '0'); + if count <= arg_l then + result(arg_l-count downto 0) := xarg(arg_l downto count); + end if; + return result; + end xsrl; + + function xsra (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0); + variable xcount: natural ; + -- pragma built_in SYN_SHR + begin + xcount := count; + if ((arg'length <= 1) or (xcount = 0)) then return arg; + else + if (xcount > arg_l) then xcount := arg_l; + end if; + result(arg_l-xcount downto 0) := xarg(arg_l downto xcount); + result(arg_l downto (arg_l - xcount + 1)) := (others => xarg(arg_l)); + end if; + return result; + end xsra; + + function xrol (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_ROLU + begin + result := xarg; + countm := count mod (arg_l + 1); + if countm /= 0 then + result(arg_l downto countm) := xarg(arg_l-countm downto 0); + result(countm-1 downto 0) := xarg(arg_l downto arg_l-countm+1); + end if; + return result; + end xrol; + + function xror (arg: std_ulogic_vector; count: natural) return std_ulogic_vector + is + constant arg_l: integer := arg'length-1; + alias xarg: std_ulogic_vector(arg_l downto 0) is arg; + variable result: std_ulogic_vector(arg_l downto 0) ; + variable countm: integer; + -- pragma built_in SYN_RORU + begin + countm := count mod (arg_l + 1); + result := xarg; + if countm /= 0 then + result(arg_l-countm downto 0) := xarg(arg_l downto countm); + result(arg_l downto arg_l-countm+1) := xarg(countm-1 downto 0); + end if; + return result; + end xror; + +--=================================================================== + + -- Id: S.1 + function shift_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SLLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsll( std_ulogic_vector(arg), count ) ); + end shift_left; + + -- Id: S.2 + function shift_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_SRLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xsrl( std_ulogic_vector(arg), count ) ); + end shift_right; + + + -- Id: S.5 + function rotate_left (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_ROLU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xrol( std_ulogic_vector(arg), count ) ); + end rotate_left; + + -- Id: S.6 + function rotate_right (arg: std_ulogic_vector; count: natural) return std_ulogic_vector is + -- pragma built_in SYN_RORU + begin + -- Synopsys translate_off + if (arg'length < 1) then return NAU; + end if; + -- Synopsys translate_on + return std_ulogic_vector( xror( std_ulogic_vector(arg), count ) ); + end rotate_right; + + -- Id: S.9 + function "sll" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SLL + begin + if (count >= 0) then + return shift_left(arg, count); + else + return shift_right(arg, -count); + end if; + end "sll"; + + -- Id: S.11 + function "srl" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_SRL + begin + if (count >= 0) then + return shift_right(arg, count); + else + return shift_left(arg, -count); + end if; + end "srl"; + + -- Id: S.13 + function "rol" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROL + begin + if (count >= 0) then + return rotate_left(arg, count); + else + return rotate_right(arg, -count); + end if; + end "rol"; + + -- Id: S.15 + function "ror" (arg: std_ulogic_vector; count: integer) return std_ulogic_vector is + -- pragma built_in SYN_ROR + begin + if (count >= 0) then + return rotate_right(arg, count); + else + return rotate_left(arg, -count); + end if; + end "ror"; + +--============================================================== + --End Shift and Rotate Functions +--============================================================== + +end std_ulogic_support ; + diff --git a/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl b/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl index 4059cfc..f37ff1b 100644 --- a/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_unsigned.vhdl @@ -1,346 +1,346 @@ ---*************************************************************************** --- Copyright 2020 International Business Machines --- --- Licensed under the Apache License, Version 2.0 (the “License”); --- you may not use this file except in compliance with the License. --- You may obtain a copy of the License at --- http://www.apache.org/licenses/LICENSE-2.0 --- --- The patent license granted to you in Section 3 of the License, as applied --- to the “Work,” hereby includes implementations of the Work in physical form. --- --- Unless required by applicable law or agreed to in writing, the reference design --- distributed under the License is distributed on an “AS IS” BASIS, --- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --- See the License for the specific language governing permissions and --- limitations under the License. --- ---*************************************************************************** -library IEEE, IBM; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use IBM.std_ulogic_support.all; - -package std_ulogic_unsigned is - - function "+"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; - function "+"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; - function "+"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; - function "+"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; - function "+"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; - - function "-"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; - function "-"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; - function "-"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; - function "-"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; - function "-"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; - - function "+"(l: std_ulogic_vector) return std_ulogic_vector; - - function "*"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; - - function "=" ( l : natural; r : std_ulogic_vector) return boolean; - function "/="( l : natural; r : std_ulogic_vector) return boolean; - function "<" ( l : natural; r : std_ulogic_vector) return boolean; - function "<="( l : natural; r : std_ulogic_vector) return boolean; - function ">" ( l : natural; r : std_ulogic_vector) return boolean; - function ">="( l : natural; r : std_ulogic_vector) return boolean; - - function "=" ( l : std_ulogic_vector; r : natural) return boolean; - function "/="( l : std_ulogic_vector; r : natural) return boolean; - function "<" ( l : std_ulogic_vector; r : natural) return boolean; - function "<="( l : std_ulogic_vector; r : natural) return boolean; - function ">" ( l : std_ulogic_vector; r : natural) return boolean; - function ">="( l : std_ulogic_vector; r : natural) return boolean; - - function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic; - function "/="( l : natural; r : std_ulogic_vector) return std_ulogic; - function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic; - function "<="( l : natural; r : std_ulogic_vector) return std_ulogic; - function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic; - function ">="( l : natural; r : std_ulogic_vector) return std_ulogic; - - function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic; - function "/="( l : std_ulogic_vector; r : natural) return std_ulogic; - function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic; - function "<="( l : std_ulogic_vector; r : natural) return std_ulogic; - function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic; - function ">="( l : std_ulogic_vector; r : natural) return std_ulogic; - - function to_integer( d : std_ulogic_vector ) return natural; - -- synopsys translate_off - attribute type_convert of to_integer : function is true; - attribute btr_name of to_integer : function is "PASS"; - attribute pin_bit_information of to_integer : function is - (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), - 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); - -- synopsys translate_on - - -- synopsys translate_off - function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector; - attribute type_convert of to_std_ulogic_vector : function is true; - attribute btr_name of to_std_ulogic_vector : function is "PASS"; - attribute pin_bit_information of to_std_ulogic_vector : function is - (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), - 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); - -- synopsys translate_on - -end std_ulogic_unsigned; - -package body std_ulogic_unsigned is - - function maximum(L, R: INTEGER) return INTEGER is - begin - if L > R then - return L; - else - return R; - end if; - end; - - function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - constant length : INTEGER := maximum(L'length, R'length); - variable result : UNSIGNED(length-1 downto 0); - -- pragma label_applies_to plus - begin - result := UNSIGNED(L) + UNSIGNED(R); -- pragma label plus - return std_ulogic_vector(result); - end; - - function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (L'range); - -- pragma label_applies_to plus - begin - result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus - return result ; - end; - - function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (R'range); - -- pragma label_applies_to plus - begin - result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus - return result; - end; - - function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (L'range); - -- pragma label_applies_to plus - begin - if R = '1' then - result := std_ulogic_vector( UNSIGNED(L) + 1 ); - else - result := L; - end if; - return result ; - end; - - function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (R'range); - -- pragma label_applies_to plus - begin - if L = '1' then - result := std_ulogic_vector( UNSIGNED(R) + 1 ); - else - result := R; - end if; - return result ; - end; - - function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (L'range); - -- pragma label_applies_to plus - begin - result := L; - return result ; - end; - - function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - constant length: INTEGER := maximum(L'length, R'length); - variable result : STD_ULOGIC_VECTOR (length-1 downto 0); - -- pragma label_applies_to minus - begin - result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus - return result ; - end; - - function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (L'range); - -- pragma label_applies_to minus - begin - result := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus - return result ; - end; - - function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (R'range); - -- pragma label_applies_to minus - begin - result := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus - return result ; - end; - - function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (L'range); - -- pragma label_applies_to minus - begin - if R = '1' then - result := std_ulogic_vector( UNSIGNED(L) - 1 ); - else - result := L; - end if; - return result ; - end; - - function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - variable result : STD_ULOGIC_VECTOR (R'range); - -- pragma label_applies_to minus - begin - if L = '1' then - result := std_ulogic_vector( 1 - UNSIGNED(R) ); - else - result := std_ulogic_vector( 0 - UNSIGNED(R) ); - end if; - return result ; - end; - - function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is - constant length: INTEGER := maximum(L'length, R'length); - variable result : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0); - -- pragma label_applies_to mult - begin - result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult - return result ; - end; - - function "=" ( l : natural; r : std_ulogic_vector) return boolean is - begin - return l = unsigned(r); - end "="; - - function "/="( l : natural; r : std_ulogic_vector) return boolean is - begin - return l /= unsigned(r); - end "/="; - - function "<" ( l : natural; r : std_ulogic_vector) return boolean is - begin - return l < unsigned(r); - end "<"; - - function "<="( l : natural; r : std_ulogic_vector) return boolean is - begin - return l <= unsigned(r); - end "<="; - - function ">" ( l : natural; r : std_ulogic_vector) return boolean is - begin - return l > unsigned(r); - end ">"; - - function ">="( l : natural; r : std_ulogic_vector) return boolean is - begin - return l >= unsigned(r); - end ">="; - - function "=" ( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) = r; - end "="; - - function "/="( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) /= r; - end "/="; - - function "<" ( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) < r; - end "<"; - - function "<="( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) <= r; - end "<="; - - function ">" ( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) > r; - end ">"; - - function ">="( l : std_ulogic_vector; r : natural) return boolean is - begin - return unsigned(l) >= r; - end ">="; - - function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l = unsigned(r) ); - end "="; - - function "/="( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l /= unsigned(r) ); - end "/="; - - function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l < unsigned(r) ); - end "<"; - - function "<="( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l <= unsigned(r) ); - end "<="; - - function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l > unsigned(r) ); - end ">"; - - function ">="( l : natural; r : std_ulogic_vector) return std_ulogic is - begin - return tconv( l >= unsigned(r) ); - end ">="; - - function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) = r ); - end "="; - - function "/="( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) /= r ); - end "/="; - - function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) < r ); - end "<"; - - function "<="( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) <= r ); - end "<="; - - function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) > r ); - end ">"; - - function ">="( l : std_ulogic_vector; r : natural) return std_ulogic is - begin - return tconv( unsigned(l) >= r ); - end ">="; - - function to_integer( d : std_ulogic_vector ) return natural is - begin - return tconv( d ); - end to_integer; - - function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is - begin - return tconv( d, w ); - end to_std_ulogic_vector; - -end std_ulogic_unsigned; +--*************************************************************************** +-- Copyright 2020 International Business Machines +-- +-- Licensed under the Apache License, Version 2.0 (the “License”); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- The patent license granted to you in Section 3 of the License, as applied +-- to the “Work,” hereby includes implementations of the Work in physical form. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an “AS IS” BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- +--*************************************************************************** +library IEEE, IBM; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use IBM.std_ulogic_support.all; + +package std_ulogic_unsigned is + + function "+"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "+"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "+"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "+"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "-"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: integer) return std_ulogic_vector; + function "-"(l: integer; r: std_ulogic_vector) return std_ulogic_vector; + function "-"(l: std_ulogic_vector; r: std_ulogic) return std_ulogic_vector; + function "-"(l: std_ulogic; r: std_ulogic_vector) return std_ulogic_vector; + + function "+"(l: std_ulogic_vector) return std_ulogic_vector; + + function "*"(l: std_ulogic_vector; r: std_ulogic_vector) return std_ulogic_vector; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean; + function "/="( l : natural; r : std_ulogic_vector) return boolean; + function "<" ( l : natural; r : std_ulogic_vector) return boolean; + function "<="( l : natural; r : std_ulogic_vector) return boolean; + function ">" ( l : natural; r : std_ulogic_vector) return boolean; + function ">="( l : natural; r : std_ulogic_vector) return boolean; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean; + function "/="( l : std_ulogic_vector; r : natural) return boolean; + function "<" ( l : std_ulogic_vector; r : natural) return boolean; + function "<="( l : std_ulogic_vector; r : natural) return boolean; + function ">" ( l : std_ulogic_vector; r : natural) return boolean; + function ">="( l : std_ulogic_vector; r : natural) return boolean; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic; + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic; + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic; + + function to_integer( d : std_ulogic_vector ) return natural; + -- synopsys translate_off + attribute type_convert of to_integer : function is true; + attribute btr_name of to_integer : function is "PASS"; + attribute pin_bit_information of to_integer : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + + -- synopsys translate_off + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector; + attribute type_convert of to_std_ulogic_vector : function is true; + attribute btr_name of to_std_ulogic_vector : function is "PASS"; + attribute pin_bit_information of to_std_ulogic_vector : function is + (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), + 2 => (" ","10 ","INCR","PIN_BIT_SCALAR")); + -- synopsys translate_on + +end std_ulogic_unsigned; + +package body std_ulogic_unsigned is + + function maximum(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length : INTEGER := maximum(L'length, R'length); + variable result : UNSIGNED(length-1 downto 0); + -- pragma label_applies_to plus + begin + result := UNSIGNED(L) + UNSIGNED(R); -- pragma label plus + return std_ulogic_vector(result); + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( UNSIGNED(L) + R ); -- pragma label plus + return result ; + end; + + function "+"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + result := std_ulogic_vector( L + UNSIGNED(R) ); -- pragma label plus + return result; + end; + + function "+"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) + 1 ); + else + result := L; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to plus + begin + if L = '1' then + result := std_ulogic_vector( UNSIGNED(R) + 1 ); + else + result := R; + end if; + return result ; + end; + + function "+"(L: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to plus + begin + result := L; + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR (length-1 downto 0); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: INTEGER) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( UNSIGNED(L) - R ); -- pragma label minus + return result ; + end; + + function "-"(L: INTEGER; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + result := std_ulogic_vector( L - UNSIGNED(R) ); -- pragma label minus + return result ; + end; + + function "-"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (L'range); + -- pragma label_applies_to minus + begin + if R = '1' then + result := std_ulogic_vector( UNSIGNED(L) - 1 ); + else + result := L; + end if; + return result ; + end; + + function "-"(L: STD_ULOGIC; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + variable result : STD_ULOGIC_VECTOR (R'range); + -- pragma label_applies_to minus + begin + if L = '1' then + result := std_ulogic_vector( 1 - UNSIGNED(R) ); + else + result := std_ulogic_vector( 0 - UNSIGNED(R) ); + end if; + return result ; + end; + + function "*"(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is + constant length: INTEGER := maximum(L'length, R'length); + variable result : STD_ULOGIC_VECTOR ((L'length+R'length-1) downto 0); + -- pragma label_applies_to mult + begin + result := std_ulogic_vector( UNSIGNED(L) * UNSIGNED(R) ); -- pragma label mult + return result ; + end; + + function "=" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l = unsigned(r); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l /= unsigned(r); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l < unsigned(r); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l <= unsigned(r); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return boolean is + begin + return l > unsigned(r); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return boolean is + begin + return l >= unsigned(r); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) = r; + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) /= r; + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) < r; + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) <= r; + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) > r; + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return boolean is + begin + return unsigned(l) >= r; + end ">="; + + function "=" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l = unsigned(r) ); + end "="; + + function "/="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l /= unsigned(r) ); + end "/="; + + function "<" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l < unsigned(r) ); + end "<"; + + function "<="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l <= unsigned(r) ); + end "<="; + + function ">" ( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l > unsigned(r) ); + end ">"; + + function ">="( l : natural; r : std_ulogic_vector) return std_ulogic is + begin + return tconv( l >= unsigned(r) ); + end ">="; + + function "=" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) = r ); + end "="; + + function "/="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) /= r ); + end "/="; + + function "<" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) < r ); + end "<"; + + function "<="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) <= r ); + end "<="; + + function ">" ( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) > r ); + end ">"; + + function ">="( l : std_ulogic_vector; r : natural) return std_ulogic is + begin + return tconv( unsigned(l) >= r ); + end ">="; + + function to_integer( d : std_ulogic_vector ) return natural is + begin + return tconv( d ); + end to_integer; + + function to_std_ulogic_vector( d : natural; w : positive ) return std_ulogic_vector is + begin + return tconv( d, w ); + end to_std_ulogic_vector; + +end std_ulogic_unsigned; diff --git a/rel/src/vhdl/work/acq_soft.vhdl b/rel/src/vhdl/work/acq_soft.vhdl index 5474573..4f7f2bf 100644 --- a/rel/src/vhdl/work/acq_soft.vhdl +++ b/rel/src/vhdl/work/acq_soft.vhdl @@ -7,864 +7,864 @@ -- This README will be updated with additional information when OpenPOWER's -- license is available. -library ieee; use ieee.std_logic_1164.all; -library ibm; -library work; use work.all; - use ibm.std_ulogic_support.all; - use ibm.std_ulogic_function_support.all; -library support; - use support.power_logic_pkg.all; - use work.iuq_pkg.all; -library tri; - use tri.tri_latches_pkg.all; -use work.xuq_pkg.all; - -ENTITY acq_soft IS - GENERIC(xu_eff_ifar : integer := 62; - expand_type : integer := 2; - regmode : integer := 6; - hvmode : integer := 1; - a2mode : integer := 1; - bcfg_epn_0to15 : integer := 0; - bcfg_epn_16to31 : integer := 0; - bcfg_epn_32to47 : integer := (2**16)-1; - bcfg_epn_48to51 : integer := (2**4)-1; - bcfg_rpn_22to31 : integer := (2**10)-1; - bcfg_rpn_32to47 : integer := (2**16)-1; - bcfg_rpn_48to51 : integer := (2**4)-1; - fpr_addr_width : integer := 5; - lmq_entries : integer := 8; - threads : integer := 4; - ucode_mode : integer := 1; - uc_ifar : integer := 21; - data_out_width : integer := 64; - debug_event_width : integer := 16; - debug_trace_width : integer := 88; - epn_width : integer := 52; - eptr_width : integer := 4; - erat_ary_data_width : integer := 73; - erat_cam_data_width : integer := 75; - erat_rel_data_width : integer := 132; - error_width : integer := 3; - expand_tlb_type : integer := 2; - extclass_width : integer := 2; - inv_seq_width : integer := 6; - lpid_width : integer := 8; +library ieee; use ieee.std_logic_1164.all; +library ibm; +library work; use work.all; + use ibm.std_ulogic_support.all; + use ibm.std_ulogic_function_support.all; +library support; + use support.power_logic_pkg.all; + use work.iuq_pkg.all; +library tri; + use tri.tri_latches_pkg.all; +use work.xuq_pkg.all; + +ENTITY acq_soft IS + GENERIC(xu_eff_ifar : integer := 62; + expand_type : integer := 2; + regmode : integer := 6; + hvmode : integer := 1; + a2mode : integer := 1; + bcfg_epn_0to15 : integer := 0; + bcfg_epn_16to31 : integer := 0; + bcfg_epn_32to47 : integer := (2**16)-1; + bcfg_epn_48to51 : integer := (2**4)-1; + bcfg_rpn_22to31 : integer := (2**10)-1; + bcfg_rpn_32to47 : integer := (2**16)-1; + bcfg_rpn_48to51 : integer := (2**4)-1; + fpr_addr_width : integer := 5; + lmq_entries : integer := 8; + threads : integer := 4; + ucode_mode : integer := 1; + uc_ifar : integer := 21; + data_out_width : integer := 64; + debug_event_width : integer := 16; + debug_trace_width : integer := 88; + epn_width : integer := 52; + eptr_width : integer := 4; + erat_ary_data_width : integer := 73; + erat_cam_data_width : integer := 75; + erat_rel_data_width : integer := 132; + error_width : integer := 3; + expand_tlb_type : integer := 2; + extclass_width : integer := 2; + inv_seq_width : integer := 6; + lpid_width : integer := 8; lru_width : integer := 16; - mmucr0_width : integer := 20; - mmucr1_width : integer := 32; - mmucr2_width : integer := 32; - mmucr3_width : integer := 15; - pid_width : integer := 14; - pid_width_erat : integer := 8; - por_seq_width : integer := 3; - ra_entry_width : integer := 12; - real_addr_width : integer := 42; - req_epn_width : integer := 52; - rpn_width : integer := 30; - rs_data_width : integer := 64; - rs_is_width : integer := 9; - spr_addr_width : integer := 10; - spr_ctl_width : integer := 3; - spr_data_width : integer := 64; - spr_etid_width : integer := 2; - spr_xucr0_init_mod : integer := 0; - state_width : integer := 4; - thdid_width : integer := 4; - tlb_addr_width : natural := 7; - tlb_num_entry : natural := 512; - tlb_num_entry_log2 : natural := 9; - tlb_seq_width : integer := 6; - tlb_tag_width : natural := 110; - tlb_way_width : natural := 168; - tlb_ways : natural := 4; - tlb_word_width : natural := 84; - tlbsel_width : integer := 2; - ttype_width : integer := 4; - vpn_width : integer := 61; - watermark_width : integer := 4; - ws_width : integer := 2; + mmucr0_width : integer := 20; + mmucr1_width : integer := 32; + mmucr2_width : integer := 32; + mmucr3_width : integer := 15; + pid_width : integer := 14; + pid_width_erat : integer := 8; + por_seq_width : integer := 3; + ra_entry_width : integer := 12; + real_addr_width : integer := 42; + req_epn_width : integer := 52; + rpn_width : integer := 30; + rs_data_width : integer := 64; + rs_is_width : integer := 9; + spr_addr_width : integer := 10; + spr_ctl_width : integer := 3; + spr_data_width : integer := 64; + spr_etid_width : integer := 2; + spr_xucr0_init_mod : integer := 0; + state_width : integer := 4; + thdid_width : integer := 4; + tlb_addr_width : natural := 7; + tlb_num_entry : natural := 512; + tlb_num_entry_log2 : natural := 9; + tlb_seq_width : integer := 6; + tlb_tag_width : natural := 110; + tlb_way_width : natural := 168; + tlb_ways : natural := 4; + tlb_word_width : natural := 84; + tlbsel_width : integer := 2; + ttype_width : integer := 4; + vpn_width : integer := 61; + watermark_width : integer := 4; + ws_width : integer := 2; dc_size : natural := 14; - include_boxes : integer := 1; - l_endian_m : integer := 1; - load_credits : integer := 4; - xu_real_data_add : integer := 42; - st_data_32b_mode : integer := 1; - ac_st_data_32b_mode : integer := 0; - store_credits : integer := 20 - ); - PORT ( - an_ac_back_inv : in std_ulogic; - an_ac_back_inv_addr : in std_ulogic_vector(64-xu_real_data_add to 63); - an_ac_back_inv_lbit : in std_ulogic; - an_ac_back_inv_gs : in std_ulogic; - an_ac_back_inv_ind : in std_ulogic; - an_ac_back_inv_local : in std_ulogic; - an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); - an_ac_back_inv_target : in std_ulogic_vector(0 to 4); - an_ac_dcr_act : in std_ulogic; - an_ac_dcr_val : in std_ulogic; - an_ac_dcr_read : in std_ulogic; - an_ac_dcr_etid : in std_ulogic_vector(0 to 1); - an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); - an_ac_dcr_done : in std_ulogic; - an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); - an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); + include_boxes : integer := 1; + l_endian_m : integer := 1; + load_credits : integer := 4; + xu_real_data_add : integer := 42; + st_data_32b_mode : integer := 1; + ac_st_data_32b_mode : integer := 0; + store_credits : integer := 20 + ); + PORT ( + an_ac_back_inv : in std_ulogic; + an_ac_back_inv_addr : in std_ulogic_vector(64-xu_real_data_add to 63); + an_ac_back_inv_lbit : in std_ulogic; + an_ac_back_inv_gs : in std_ulogic; + an_ac_back_inv_ind : in std_ulogic; + an_ac_back_inv_local : in std_ulogic; + an_ac_back_inv_lpar_id : in std_ulogic_vector(0 to lpid_width-1); + an_ac_back_inv_target : in std_ulogic_vector(0 to 4); + an_ac_dcr_act : in std_ulogic; + an_ac_dcr_val : in std_ulogic; + an_ac_dcr_read : in std_ulogic; + an_ac_dcr_etid : in std_ulogic_vector(0 to 1); + an_ac_dcr_data : in std_ulogic_vector(64-(2**regmode) to 63); + an_ac_dcr_done : in std_ulogic; + an_ac_crit_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_ext_interrupt : in std_ulogic_vector(0 to threads-1); an_ac_camfence_en_dc : in std_ulogic; an_ac_flh2l2_gate : in std_ulogic; - an_ac_icbi_ack : in std_ulogic; - an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); - an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); - an_ac_reld_data : in std_ulogic_vector(0 to 127); - an_ac_reld_data_vld : in std_ulogic; - an_ac_reld_ecc_err : in std_ulogic; - an_ac_reld_ecc_err_ue : in std_ulogic; - an_ac_reld_qw : in std_ulogic_vector(57 to 59); - an_ac_reld_data_coming : in std_ulogic; - an_ac_reld_ditc : in std_ulogic; - an_ac_reld_crit_qw : in std_ulogic; - an_ac_reld_l1_dump : in std_ulogic; - an_ac_req_ld_pop : in std_ulogic; - an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); - an_ac_req_st_gather : in std_ulogic; - an_ac_req_st_pop : in std_ulogic; - an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); - an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); - an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); - an_ac_stcx_complete : in std_ulogic_vector(0 to 3); - an_ac_stcx_pass : in std_ulogic_vector(0 to 3); - an_ac_sync_ack : in std_ulogic_vector(0 to 3); - a2_nclk : in clk_logic; - an_ac_abist_mode_dc : in std_ulogic; - an_ac_abist_start_test : in std_ulogic; - an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); - an_ac_ary_nsl_thold_7 : in std_ulogic; - an_ac_atpg_en_dc : in std_ulogic; - an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); - an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; - an_ac_ccenable_dc : in std_ulogic; - an_ac_ccflush_dc : in std_ulogic; - an_ac_coreid : in std_ulogic_vector(0 to 7); - an_ac_reset_1_complete : in std_ulogic; - an_ac_reset_2_complete : in std_ulogic; - an_ac_reset_3_complete : in std_ulogic; - an_ac_reset_wd_complete : in std_ulogic; - an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); - an_ac_debug_stop : in std_ulogic; - an_ac_external_mchk : in std_ulogic_vector(0 to 3); - an_ac_fce_7 : in std_ulogic; - an_ac_func_nsl_thold_7 : in std_ulogic; - an_ac_func_scan_in : in std_ulogic_vector(0 to 63); - an_ac_func_sl_thold_7 : in std_ulogic; - an_ac_gsd_test_enable_dc : in std_ulogic; - an_ac_gsd_test_acmode_dc : in std_ulogic; - an_ac_gptr_scan_in : in std_ulogic; - an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); - an_ac_lbist_en_dc : in std_ulogic; - an_ac_lbist_ac_mode_dc : in std_ulogic; - an_ac_lbist_ip_dc : in std_ulogic; - an_ac_malf_alert : in std_ulogic; - an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); - an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); - an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); - an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); - an_ac_repr_scan_in : in std_ulogic; - an_ac_rtim_sl_thold_7 : in std_ulogic; - an_ac_scan_diag_dc : in std_ulogic; - an_ac_scan_dis_dc_b : in std_ulogic; - an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); - an_ac_scom_cch : in std_ulogic; - an_ac_scom_dch : in std_ulogic; - an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); - an_ac_sg_7 : in std_ulogic; - an_ac_checkstop : in std_ulogic; - an_ac_tb_update_enable : in std_ulogic; - an_ac_tb_update_pulse : in std_ulogic; - an_ac_time_scan_in : in std_ulogic; - ac_an_back_inv_reject : out std_ulogic; - ac_an_box_empty : out std_ulogic_vector(0 to 3); + an_ac_icbi_ack : in std_ulogic; + an_ac_icbi_ack_thread : in std_ulogic_vector(0 to 1); + an_ac_reld_core_tag : in std_ulogic_vector(0 to 4); + an_ac_reld_data : in std_ulogic_vector(0 to 127); + an_ac_reld_data_vld : in std_ulogic; + an_ac_reld_ecc_err : in std_ulogic; + an_ac_reld_ecc_err_ue : in std_ulogic; + an_ac_reld_qw : in std_ulogic_vector(57 to 59); + an_ac_reld_data_coming : in std_ulogic; + an_ac_reld_ditc : in std_ulogic; + an_ac_reld_crit_qw : in std_ulogic; + an_ac_reld_l1_dump : in std_ulogic; + an_ac_req_ld_pop : in std_ulogic; + an_ac_req_spare_ctrl_a1 : in std_ulogic_vector(0 to 3); + an_ac_req_st_gather : in std_ulogic; + an_ac_req_st_pop : in std_ulogic; + an_ac_req_st_pop_thrd : in std_ulogic_vector(0 to 2); + an_ac_reservation_vld : in std_ulogic_vector(0 to threads-1); + an_ac_sleep_en : in std_ulogic_vector(0 to threads-1); + an_ac_stcx_complete : in std_ulogic_vector(0 to 3); + an_ac_stcx_pass : in std_ulogic_vector(0 to 3); + an_ac_sync_ack : in std_ulogic_vector(0 to 3); + a2_nclk : in clk_logic; + an_ac_abist_mode_dc : in std_ulogic; + an_ac_abist_start_test : in std_ulogic; + an_ac_abst_scan_in : in std_ulogic_vector(0 to 9); + an_ac_ary_nsl_thold_7 : in std_ulogic; + an_ac_atpg_en_dc : in std_ulogic; + an_ac_bcfg_scan_in : in std_ulogic_vector(0 to 4); + an_ac_lbist_ary_wrt_thru_dc : in std_ulogic; + an_ac_ccenable_dc : in std_ulogic; + an_ac_ccflush_dc : in std_ulogic; + an_ac_coreid : in std_ulogic_vector(0 to 7); + an_ac_reset_1_complete : in std_ulogic; + an_ac_reset_2_complete : in std_ulogic; + an_ac_reset_3_complete : in std_ulogic; + an_ac_reset_wd_complete : in std_ulogic; + an_ac_dcfg_scan_in : in std_ulogic_vector(0 to 2); + an_ac_debug_stop : in std_ulogic; + an_ac_external_mchk : in std_ulogic_vector(0 to 3); + an_ac_fce_7 : in std_ulogic; + an_ac_func_nsl_thold_7 : in std_ulogic; + an_ac_func_scan_in : in std_ulogic_vector(0 to 63); + an_ac_func_sl_thold_7 : in std_ulogic; + an_ac_gsd_test_enable_dc : in std_ulogic; + an_ac_gsd_test_acmode_dc : in std_ulogic; + an_ac_gptr_scan_in : in std_ulogic; + an_ac_hang_pulse : in std_ulogic_vector(0 to threads-1); + an_ac_lbist_en_dc : in std_ulogic; + an_ac_lbist_ac_mode_dc : in std_ulogic; + an_ac_lbist_ip_dc : in std_ulogic; + an_ac_malf_alert : in std_ulogic; + an_ac_perf_interrupt : in std_ulogic_vector(0 to threads-1); + an_ac_pm_thread_stop : in std_ulogic_vector(0 to 3); + an_ac_psro_enable_dc : in std_ulogic_vector(0 to 2); + an_ac_regf_scan_in : in std_ulogic_vector(0 to 11); + an_ac_repr_scan_in : in std_ulogic; + an_ac_rtim_sl_thold_7 : in std_ulogic; + an_ac_scan_diag_dc : in std_ulogic; + an_ac_scan_dis_dc_b : in std_ulogic; + an_ac_scan_type_dc : in std_ulogic_vector(0 to 8); + an_ac_scom_cch : in std_ulogic; + an_ac_scom_dch : in std_ulogic; + an_ac_scom_sat_id : in std_ulogic_vector(0 to 3); + an_ac_sg_7 : in std_ulogic; + an_ac_checkstop : in std_ulogic; + an_ac_tb_update_enable : in std_ulogic; + an_ac_tb_update_pulse : in std_ulogic; + an_ac_time_scan_in : in std_ulogic; + ac_an_back_inv_reject : out std_ulogic; + ac_an_box_empty : out std_ulogic_vector(0 to 3); ac_an_reld_ditc_pop : out std_ulogic_vector(0 to 3); - ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); - ac_an_machine_check : out std_ulogic_vector(0 to threads-1); - ac_an_power_managed : out std_ulogic; - ac_an_req : out std_ulogic; - ac_an_req_endian : out std_ulogic; - ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); - ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); - ac_an_req_pwr_token : out std_ulogic; - ac_an_req_ra : out std_ulogic_vector(64-xu_real_data_add to 63); - ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); - ac_an_req_thread : out std_ulogic_vector(0 to 2); - ac_an_req_ttype : out std_ulogic_vector(0 to 5); - ac_an_req_user_defined : out std_ulogic_vector(0 to 3); - ac_an_req_wimg_g : out std_ulogic; - ac_an_req_wimg_i : out std_ulogic; - ac_an_req_wimg_m : out std_ulogic; - ac_an_req_wimg_w : out std_ulogic; - ac_an_rvwinkle_mode : out std_ulogic; - ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); - ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); - ac_an_st_data_pwr_token : out std_ulogic; - ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); - ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); - ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); - ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); - ac_an_debug_bus : out std_ulogic_vector(0 to 87); - ac_an_event_bus : out std_ulogic_vector(0 to 7); - ac_an_trace_triggers : out std_ulogic_vector(0 to 11); - ac_an_abist_done_dc : out std_ulogic; - ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); - ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); - ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); - ac_an_debug_trigger : out std_ulogic_vector(0 to threads-1); - ac_an_func_scan_out : out std_ulogic_vector(0 to 63); - ac_an_gptr_scan_out : out std_ulogic; - ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); - ac_an_psro_ringsig : out std_ulogic; - ac_an_recov_err : out std_ulogic_vector(0 to 2); - ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); - ac_an_repr_scan_out : out std_ulogic; - ac_an_reset_1_request : out std_ulogic; - ac_an_reset_2_request : out std_ulogic; - ac_an_reset_3_request : out std_ulogic; - ac_an_reset_wd_request : out std_ulogic; - ac_an_scom_cch : out std_ulogic; - ac_an_scom_dch : out std_ulogic; - ac_an_time_scan_out : out std_ulogic; - ac_an_special_attn : out std_ulogic_vector(0 to 3); - ac_an_checkstop : out std_ulogic_vector(0 to 2); - ac_an_local_checkstop : out std_ulogic_vector(0 to 2); - ac_an_trace_error : out std_ulogic; - ac_an_dcr_act : out std_ulogic; - ac_an_dcr_val : out std_ulogic; - ac_an_dcr_read : out std_ulogic; - ac_an_dcr_user : out std_ulogic; - ac_an_dcr_etid : out std_ulogic_vector(0 to 1); - ac_an_dcr_addr : out std_ulogic_vector(11 to 20); - ac_an_dcr_data : out std_ulogic_vector(64-(2**regmode) to 63); - gnd : inout power_logic; - vcs : inout power_logic; - vdd : inout power_logic - ); - -- synopsys translate_off - -- synopsys translate_on -END acq_soft; - -ARCHITECTURE acq_soft OF acq_soft IS - - -signal a2_nclk_copy : clk_logic; -signal bx_pc_err_inbox_ue : std_ulogic; -signal bx_pc_err_outbox_ue : std_ulogic; -signal fu_iu_uc_special : std_ulogic_vector(0 to 3); -signal fu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); -signal fu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); -signal fu_pc_event_data : std_ulogic_vector(0 to 7); -signal fu_pc_ram_data : std_ulogic_vector(0 to 63); -signal fu_pc_ram_done : std_ulogic; -signal fu_xu_ex2_async_block : std_ulogic_vector(0 to 3); -signal fu_xu_ex1_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); -signal fu_xu_ex2_ifar_val : std_ulogic_vector(0 to 3); + ac_an_lpar_id : out std_ulogic_vector(0 to lpid_width-1); + ac_an_machine_check : out std_ulogic_vector(0 to threads-1); + ac_an_power_managed : out std_ulogic; + ac_an_req : out std_ulogic; + ac_an_req_endian : out std_ulogic; + ac_an_req_ld_core_tag : out std_ulogic_vector(0 to 4); + ac_an_req_ld_xfr_len : out std_ulogic_vector(0 to 2); + ac_an_req_pwr_token : out std_ulogic; + ac_an_req_ra : out std_ulogic_vector(64-xu_real_data_add to 63); + ac_an_req_spare_ctrl_a0 : out std_ulogic_vector(0 to 3); + ac_an_req_thread : out std_ulogic_vector(0 to 2); + ac_an_req_ttype : out std_ulogic_vector(0 to 5); + ac_an_req_user_defined : out std_ulogic_vector(0 to 3); + ac_an_req_wimg_g : out std_ulogic; + ac_an_req_wimg_i : out std_ulogic; + ac_an_req_wimg_m : out std_ulogic; + ac_an_req_wimg_w : out std_ulogic; + ac_an_rvwinkle_mode : out std_ulogic; + ac_an_st_byte_enbl : out std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); + ac_an_st_data : out std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); + ac_an_st_data_pwr_token : out std_ulogic; + ac_an_fu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_iu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_mm_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_lsu_bypass_events : out std_ulogic_vector(0 to 7); + ac_an_debug_bus : out std_ulogic_vector(0 to 87); + ac_an_event_bus : out std_ulogic_vector(0 to 7); + ac_an_trace_triggers : out std_ulogic_vector(0 to 11); + ac_an_abist_done_dc : out std_ulogic; + ac_an_abst_scan_out : out std_ulogic_vector(0 to 9); + ac_an_bcfg_scan_out : out std_ulogic_vector(0 to 4); + ac_an_dcfg_scan_out : out std_ulogic_vector(0 to 2); + ac_an_debug_trigger : out std_ulogic_vector(0 to threads-1); + ac_an_func_scan_out : out std_ulogic_vector(0 to 63); + ac_an_gptr_scan_out : out std_ulogic; + ac_an_pm_thread_running : out std_ulogic_vector(0 to 3); + ac_an_psro_ringsig : out std_ulogic; + ac_an_recov_err : out std_ulogic_vector(0 to 2); + ac_an_regf_scan_out : out std_ulogic_vector(0 to 11); + ac_an_repr_scan_out : out std_ulogic; + ac_an_reset_1_request : out std_ulogic; + ac_an_reset_2_request : out std_ulogic; + ac_an_reset_3_request : out std_ulogic; + ac_an_reset_wd_request : out std_ulogic; + ac_an_scom_cch : out std_ulogic; + ac_an_scom_dch : out std_ulogic; + ac_an_time_scan_out : out std_ulogic; + ac_an_special_attn : out std_ulogic_vector(0 to 3); + ac_an_checkstop : out std_ulogic_vector(0 to 2); + ac_an_local_checkstop : out std_ulogic_vector(0 to 2); + ac_an_trace_error : out std_ulogic; + ac_an_dcr_act : out std_ulogic; + ac_an_dcr_val : out std_ulogic; + ac_an_dcr_read : out std_ulogic; + ac_an_dcr_user : out std_ulogic; + ac_an_dcr_etid : out std_ulogic_vector(0 to 1); + ac_an_dcr_addr : out std_ulogic_vector(11 to 20); + ac_an_dcr_data : out std_ulogic_vector(64-(2**regmode) to 63); + gnd : inout power_logic; + vcs : inout power_logic; + vdd : inout power_logic + ); + -- synopsys translate_off + -- synopsys translate_on +END acq_soft; + +ARCHITECTURE acq_soft OF acq_soft IS + + +signal a2_nclk_copy : clk_logic; +signal bx_pc_err_inbox_ue : std_ulogic; +signal bx_pc_err_outbox_ue : std_ulogic; +signal fu_iu_uc_special : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal fu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal fu_pc_event_data : std_ulogic_vector(0 to 7); +signal fu_pc_ram_data : std_ulogic_vector(0 to 63); +signal fu_pc_ram_done : std_ulogic; +signal fu_xu_ex2_async_block : std_ulogic_vector(0 to 3); +signal fu_xu_ex1_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal fu_xu_ex2_ifar_val : std_ulogic_vector(0 to 3); signal fu_xu_ex2_ifar_issued : std_ulogic_vector(0 to 3); -signal fu_xu_ex2_store_data : std_ulogic_vector(0 to 63); -signal fu_xu_ex2_store_data_val : std_ulogic; -signal fu_xu_ex3_ap_int_req : std_ulogic_vector(0 to 3); -signal fu_xu_ex3_flush2ucode : std_ulogic_vector(0 to 3); -signal fu_xu_ex2_instr_match : std_ulogic_vector(0 to 3); -signal fu_xu_ex2_instr_type : std_ulogic_vector(0 to 11); -signal fu_xu_ex2_is_ucode : std_ulogic_vector(0 to 3); -signal fu_xu_ex3_n_flush : std_ulogic_vector(0 to 3); -signal fu_xu_ex3_np1_flush : std_ulogic_vector(0 to 3); -signal fu_xu_ex3_regfile_err_det : std_ulogic_vector(0 to 3); -signal fu_xu_ex3_trap : std_ulogic_vector(0 to 3); -signal fu_xu_ex4_cr : std_ulogic_vector(0 to 3); -signal fu_xu_ex4_cr_bf : std_ulogic_vector(0 to 2); -signal fu_xu_ex4_cr_noflush : std_ulogic_vector(0 to 3); -signal fu_xu_ex4_cr_val : std_ulogic_vector(0 to 3); -signal fu_xu_regfile_seq_end : std_ulogic; -signal fu_xu_rf1_act : std_ulogic_vector(0 to 3); -signal fu_bx_slowspr_addr : std_ulogic_vector(0 to 9); -signal fu_bx_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); -signal fu_bx_slowspr_done : std_ulogic; -signal fu_bx_slowspr_etid : std_ulogic_vector(0 to 1); -signal fu_bx_slowspr_rw : std_ulogic; -signal fu_bx_slowspr_val : std_ulogic; -signal bx_xu_slowspr_addr : std_ulogic_vector(0 to 9); -signal bx_xu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); -signal bx_xu_slowspr_done : std_ulogic; -signal bx_xu_slowspr_etid : std_ulogic_vector(0 to 1); -signal bx_xu_slowspr_rw : std_ulogic; -signal bx_xu_slowspr_val : std_ulogic; -signal bx_xu_quiesce : std_ulogic_vector(0 to 3); -signal iu_fu_ex2_n_flush : std_ulogic_vector(0 to 3); -signal iu_fu_is2_tid_decode : std_ulogic_vector(0 to 3); -signal iu_fu_rf0_bypsel : std_ulogic_vector(0 to 5); -signal iu_fu_rf0_fra : std_ulogic_vector(0 to 6); -signal iu_fu_rf0_fra_v : std_ulogic; -signal iu_fu_rf0_frb : std_ulogic_vector(0 to 6); -signal iu_fu_rf0_frb_v : std_ulogic; -signal iu_fu_rf0_frc : std_ulogic_vector(0 to 6); -signal iu_fu_rf0_frc_v : std_ulogic; -signal iu_fu_rf0_frt : std_ulogic_vector(0 to 6); -signal iu_fu_rf0_ifar : eff_ifar; -signal iu_fu_rf0_instr : std_ulogic_vector(0 to 31); -signal iu_fu_rf0_instr_match : std_ulogic; -signal iu_fu_rf0_instr_v : std_ulogic; -signal iu_fu_rf0_is_ucode : std_ulogic; -signal iu_fu_rf0_ucfmul : std_ulogic; -signal iu_fu_rf0_ldst_val : std_ulogic; -signal iu_fu_rf0_ldst_tid : std_ulogic_vector(0 to 1); -signal iu_fu_rf0_ldst_tag : std_ulogic_vector(0 to 8); -signal iu_fu_rf0_str_val : std_ulogic; -signal iu_fu_rf0_tid : std_ulogic_vector(0 to 1); -signal iu_mm_ierat_epn : std_ulogic_vector(0 to 51); -signal iu_mm_ierat_flush : std_ulogic_vector(0 to 3); -signal iu_mm_ierat_mmucr0 : std_ulogic_vector(0 to 17); -signal iu_mm_ierat_mmucr0_we : std_ulogic_vector(0 to 3); -signal iu_mm_ierat_mmucr1 : std_ulogic_vector(0 to 3); -signal iu_mm_ierat_mmucr1_we : std_ulogic; -signal iu_mm_ierat_req : std_ulogic; -signal iu_mm_ierat_snoop_ack : std_ulogic; -signal iu_mm_ierat_thdid : std_ulogic_vector(0 to 3); -signal iu_mm_ierat_tid : std_ulogic_vector(0 to 13); -signal iu_mm_ierat_state : std_ulogic_vector(0 to 3); -signal iu_mm_lmq_empty : std_ulogic; -signal iu_pc_err_icache_parity : std_ulogic; -signal iu_pc_err_icachedir_multihit : std_ulogic; -signal iu_pc_err_icachedir_parity : std_ulogic; -signal iu_pc_err_ucode_illegal : std_ulogic_vector(0 to 3); -signal iu_pc_event_data : std_ulogic_vector(0 to 7); -signal iu_pc_slowspr_addr : std_ulogic_vector(0 to 9); -signal iu_pc_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); -signal iu_pc_slowspr_done : std_ulogic; -signal iu_pc_slowspr_etid : std_ulogic_vector(0 to 1); -signal iu_pc_slowspr_rw : std_ulogic; -signal iu_pc_slowspr_val : std_ulogic; -signal iu_xu_ex4_tlb_data : std_ulogic_vector(64-(2**regmode) to 63); -signal iu_xu_ierat_ex2_flush_req : std_ulogic_vector(0 to threads-1); -signal iu_xu_ierat_ex3_par_err : std_ulogic_vector(0 to threads-1); -signal iu_xu_ierat_ex4_par_err : std_ulogic_vector(0 to threads-1); -signal iu_xu_is2_axu_instr_type : std_ulogic_vector(0 to 2); -signal iu_xu_is2_axu_ld_or_st : std_ulogic; -signal iu_xu_is2_axu_ldst_extpid : std_ulogic; -signal iu_xu_is2_axu_ldst_forcealign : std_ulogic; -signal iu_xu_is2_axu_ldst_forceexcept : std_ulogic; -signal iu_xu_is2_axu_ldst_indexed : std_ulogic; -signal iu_xu_is2_axu_ldst_size : std_ulogic_vector(0 to 5); -signal iu_xu_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); -signal iu_xu_is2_axu_ldst_update : std_ulogic; -signal iu_xu_is2_axu_mffgpr : std_ulogic; -signal iu_xu_is2_axu_mftgpr : std_ulogic; -signal iu_xu_is2_axu_movedp : std_ulogic; -signal iu_xu_is2_axu_store : std_ulogic; -signal iu_xu_is2_error : std_ulogic_vector(0 to 2); -signal iu_xu_is2_gshare : std_ulogic_vector(0 to 3); -signal iu_xu_is2_ifar : eff_ifar; -signal iu_xu_is2_instr : std_ulogic_vector(0 to 31); -signal iu_xu_is2_is_ucode : std_ulogic; -signal iu_xu_is2_match : std_ulogic; -signal iu_xu_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); -signal iu_xu_is2_pred_update : std_ulogic; -signal iu_xu_is2_s1 : std_ulogic_vector(0 to 5); -signal iu_xu_is2_s1_vld : std_ulogic; -signal iu_xu_is2_s2 : std_ulogic_vector(0 to 5); -signal iu_xu_is2_s2_vld : std_ulogic; -signal iu_xu_is2_s3 : std_ulogic_vector(0 to 5); -signal iu_xu_is2_s3_vld : std_ulogic; -signal iu_xu_is2_ta : std_ulogic_vector(0 to 5); -signal iu_xu_is2_ta_vld : std_ulogic; -signal iu_xu_is2_tid : std_ulogic_vector(0 to 3); -signal iu_xu_is2_ucode_vld : std_ulogic; -signal iu_xu_is2_vld : std_ulogic; -signal iu_xu_quiesce : std_ulogic_vector(0 to threads-1); -signal iu_xu_ra : std_ulogic_vector(real_ifar'left to 59); -signal iu_xu_request : std_ulogic; -signal iu_xu_thread : std_ulogic_vector(0 to 3); -signal iu_xu_userdef : std_ulogic_vector(0 to 3); -signal iu_xu_wimge : std_ulogic_vector(0 to 4); -signal mm_iu_ierat_mmucr0_0 : std_ulogic_vector(0 to 19); -signal mm_iu_ierat_mmucr0_1 : std_ulogic_vector(0 to 19); -signal mm_iu_ierat_mmucr0_2 : std_ulogic_vector(0 to 19); -signal mm_iu_ierat_mmucr0_3 : std_ulogic_vector(0 to 19); -signal mm_iu_ierat_mmucr1 : std_ulogic_vector(0 to 8); -signal mm_iu_ierat_pid0 : std_ulogic_vector(0 to 13); -signal mm_iu_ierat_pid1 : std_ulogic_vector(0 to 13); -signal mm_iu_ierat_pid2 : std_ulogic_vector(0 to 13); -signal mm_iu_ierat_pid3 : std_ulogic_vector(0 to 13); -signal mm_iu_ierat_rel_data : std_ulogic_vector(0 to 131); -signal mm_iu_ierat_rel_val : std_ulogic_vector(0 to 4); -signal mm_iu_ierat_snoop_attr : std_ulogic_vector(0 to 25); -signal mm_iu_ierat_snoop_coming : std_ulogic; -signal mm_iu_ierat_snoop_val : std_ulogic; -signal mm_iu_ierat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); -signal mm_iu_slowspr_addr : std_ulogic_vector(0 to 9); -signal mm_iu_slowspr_data : std_ulogic_vector(64-spr_data_width to 63); -signal mm_iu_slowspr_done : std_ulogic; -signal mm_iu_slowspr_etid : std_ulogic_vector(0 to 1); -signal mm_iu_slowspr_rw : std_ulogic; -signal mm_iu_slowspr_val : std_ulogic; -signal xu_pc_err_mcsr_summary : std_ulogic_vector(0 to threads-1); -signal xu_pc_err_ierat_parity : std_ulogic; -signal xu_pc_err_derat_parity : std_ulogic; -signal xu_pc_err_tlb_parity : std_ulogic; -signal xu_pc_err_tlb_lru_parity : std_ulogic; -signal xu_pc_err_ierat_multihit : std_ulogic; -signal xu_pc_err_derat_multihit : std_ulogic; -signal xu_pc_err_tlb_multihit : std_ulogic; -signal xu_pc_err_ext_mchk : std_ulogic; -signal xu_pc_err_local_snoop_reject : std_ulogic; -signal mm_xu_derat_mmucr0_0 : std_ulogic_vector(0 to 19); -signal mm_xu_derat_mmucr0_1 : std_ulogic_vector(0 to 19); -signal mm_xu_derat_mmucr0_2 : std_ulogic_vector(0 to 19); -signal mm_xu_derat_mmucr0_3 : std_ulogic_vector(0 to 19); -signal mm_xu_derat_mmucr1 : std_ulogic_vector(0 to 9); -signal mm_xu_derat_pid0 : std_ulogic_vector(0 to 13); -signal mm_xu_derat_pid1 : std_ulogic_vector(0 to 13); -signal mm_xu_derat_pid2 : std_ulogic_vector(0 to 13); -signal mm_xu_derat_pid3 : std_ulogic_vector(0 to 13); -signal mm_xu_derat_rel_data : std_ulogic_vector(0 to 131); -signal mm_xu_derat_rel_val : std_ulogic_vector(0 to 4); -signal mm_xu_derat_snoop_attr : std_ulogic_vector(0 to 25); -signal mm_xu_derat_snoop_coming : std_ulogic; -signal mm_xu_derat_snoop_val : std_ulogic; -signal mm_xu_derat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); -signal mm_iu_barrier_done : std_ulogic_vector(0 to 3); -signal mm_xu_eratmiss_done : std_ulogic_vector(0 to 3); -signal mm_xu_esr_pt : std_ulogic_vector(0 to 3); -signal mm_xu_esr_data : std_ulogic_vector(0 to 3); -signal mm_xu_esr_epid : std_ulogic_vector(0 to 3); -signal mm_xu_esr_st : std_ulogic_vector(0 to 3); -signal mm_xu_ex3_flush_req : std_ulogic_vector(0 to 3); -signal xu_mm_rf1_is_tlbsxr : std_ulogic; -signal mm_xu_hold_done : std_ulogic_vector(0 to 3); -signal mm_xu_hold_req : std_ulogic_vector(0 to 3); -signal mm_xu_hv_priv : std_ulogic_vector(0 to threads-1); -signal mm_xu_illeg_instr : std_ulogic_vector(0 to threads-1); -signal mm_xu_lru_par_err : std_ulogic_vector(0 to 3); -signal mm_xu_lrat_miss : std_ulogic_vector(0 to 3); -signal mm_xu_local_snoop_reject : std_ulogic_vector(0 to thdid_width-1); -signal mm_xu_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); -signal mm_xu_lsu_lpid : std_ulogic_vector(0 to 7); -signal mm_xu_lsu_lpidr : std_ulogic_vector(0 to 7); -signal mm_xu_lsu_gs : std_ulogic; -signal mm_xu_lsu_ind : std_ulogic; -signal mm_xu_lsu_lbit : std_ulogic; -signal mm_xu_lsu_req : std_ulogic_vector(0 to 3); -signal mm_xu_lsu_ttype : std_ulogic_vector(0 to 1); -signal mm_xu_lsu_u : std_ulogic_vector(0 to 3); -signal mm_xu_lsu_wimge : std_ulogic_vector(0 to 4); -signal mm_xu_pt_fault : std_ulogic_vector(0 to 3); -signal mm_xu_quiesce : std_ulogic_vector(0 to threads-1); -signal mm_xu_tlb_inelig : std_ulogic_vector(0 to 3); -signal mm_xu_tlb_miss : std_ulogic_vector(0 to 3); -signal mm_xu_tlb_multihit_err : std_ulogic_vector(0 to 3); -signal mm_xu_tlb_par_err : std_ulogic_vector(0 to 3); -signal mm_xu_cr0_eq : std_ulogic_vector(0 to 3); -signal mm_xu_cr0_eq_valid : std_ulogic_vector(0 to 3); -signal pc_bx_inj_inbox_ecc : std_ulogic; -signal pc_bx_inj_outbox_ecc : std_ulogic; -signal pc_fu_abst_sl_thold_3 : std_ulogic; -signal pc_fu_abst_slp_sl_thold_3 : std_ulogic; -signal pc_fu_ary_nsl_thold_3 : std_ulogic; -signal pc_fu_ary_slp_nsl_thold_3 : std_ulogic; -signal pc_fu_cfg_sl_thold_3 : std_ulogic; -signal pc_fu_cfg_slp_sl_thold_3 : std_ulogic; -signal pc_bx_debug_mux1_ctrls : std_ulogic_vector(0 to 15); -signal pc_fu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); -signal pc_fu_fce_3 : std_ulogic; -signal pc_fu_func_nsl_thold_3 : std_ulogic; -signal pc_fu_func_sl_thold_3 : std_ulogic_vector(0 to 1); -signal pc_fu_func_slp_nsl_thold_3 : std_ulogic; -signal pc_fu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); -signal pc_fu_gptr_sl_thold_3 : std_ulogic; -signal pc_fu_ram_mode : std_ulogic; -signal pc_fu_ram_thread : std_ulogic_vector(0 to 1); -signal pc_fu_repr_sl_thold_3 : std_ulogic; -signal pc_fu_sg_3 : std_ulogic_vector(0 to 1); -signal pc_fu_slowspr_addr : std_ulogic_vector(0 to 9); -signal pc_fu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); -signal pc_fu_slowspr_done : std_ulogic; -signal pc_fu_slowspr_etid : std_ulogic_vector(0 to 1); -signal pc_fu_slowspr_rw : std_ulogic; -signal pc_fu_slowspr_val : std_ulogic; -signal pc_bx_trace_bus_enable : std_ulogic; -signal pc_fu_time_sl_thold_3 : std_ulogic; -signal pc_fu_trace_bus_enable : std_ulogic; -signal pc_iu_gptr_sl_thold_4 : std_ulogic; -signal pc_iu_time_sl_thold_4 : std_ulogic; -signal pc_iu_repr_sl_thold_4 : std_ulogic; -signal pc_iu_abst_sl_thold_4 : std_ulogic; -signal pc_iu_abst_slp_sl_thold_4 : std_ulogic; -signal pc_iu_bolt_sl_thold_4 : std_ulogic; -signal pc_iu_regf_slp_sl_thold_4 : std_ulogic; -signal pc_iu_func_sl_thold_4 : std_ulogic; -signal pc_iu_func_slp_sl_thold_4 : std_ulogic; -signal pc_iu_cfg_sl_thold_4 : std_ulogic; -signal pc_iu_cfg_slp_sl_thold_4 : std_ulogic; -signal pc_iu_func_nsl_thold_4 : std_ulogic; -signal pc_iu_func_slp_nsl_thold_4 : std_ulogic; -signal pc_iu_ary_nsl_thold_4 : std_ulogic; -signal pc_iu_ary_slp_nsl_thold_4 : std_ulogic; -signal pc_iu_sg_4 : std_ulogic; -signal pc_iu_fce_4 : std_ulogic; -signal pc_iu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); -signal pc_iu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); -signal pc_iu_init_reset : std_ulogic; -signal pc_iu_inj_icache_parity : std_ulogic; -signal pc_iu_inj_icachedir_parity : std_ulogic; -signal pc_iu_inj_icachedir_multihit : std_ulogic; -signal pc_iu_ram_force_cmplt : std_ulogic; -signal pc_iu_ram_instr : std_ulogic_vector(0 to 31); -signal pc_iu_ram_instr_ext : std_ulogic_vector(0 to 3); -signal pc_iu_ram_mode : std_ulogic; -signal pc_iu_ram_thread : std_ulogic_vector(0 to 1); -signal pc_iu_trace_bus_enable : std_ulogic; -signal pc_xu_abst_sl_thold_3 : std_ulogic; -signal pc_xu_abst_slp_sl_thold_3 : std_ulogic; -signal pc_xu_regf_sl_thold_3 : std_ulogic; -signal pc_xu_regf_slp_sl_thold_3 : std_ulogic; -signal pc_xu_ary_nsl_thold_3 : std_ulogic; -signal pc_xu_ary_slp_nsl_thold_3 : std_ulogic; -signal pc_xu_cache_par_err_event : std_ulogic; -signal pc_xu_cfg_sl_thold_3 : std_ulogic; -signal pc_xu_cfg_slp_sl_thold_3 : std_ulogic; -signal pc_xu_dbg_action : std_ulogic_vector(0 to 11); -signal pc_xu_decrem_dis_on_stop : std_ulogic; -signal spr_pvr_version_dc : std_ulogic_vector(8 to 15); -signal spr_pvr_revision_dc : std_ulogic_vector(12 to 15); -signal xu_pc_spr_ccr0_we : std_ulogic_vector(0 to 3); -signal xu_pc_spr_ccr0_pme : std_ulogic_vector(0 to 1); -signal pc_xu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux3_ctrls : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux4_ctrls : std_ulogic_vector(0 to 15); -signal pc_xu_extirpts_dis_on_stop : std_ulogic; -signal pc_xu_fce_3 : std_ulogic_vector(0 to 1); -signal pc_xu_force_ude : std_ulogic_vector(0 to 3); -signal pc_xu_func_nsl_thold_3 : std_ulogic; -signal pc_xu_func_sl_thold_3 : std_ulogic_vector(0 to 4); -signal pc_xu_func_slp_nsl_thold_3 : std_ulogic; -signal pc_xu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 4); -signal pc_xu_gptr_sl_thold_3 : std_ulogic; -signal pc_xu_init_reset : std_ulogic; -signal pc_xu_inj_dcache_parity : std_ulogic; -signal pc_xu_inj_dcachedir_parity : std_ulogic; -signal pc_xu_inj_llbust_attempt : std_ulogic_vector(0 to 3); -signal pc_xu_inj_llbust_failed : std_ulogic_vector(0 to 3); -signal pc_xu_inj_sprg_ecc : std_ulogic_vector(0 to 3); -signal pc_xu_inj_regfile_parity : std_ulogic_vector(0 to 3); -signal pc_xu_inj_wdt_reset : std_ulogic_vector(0 to 3); -signal pc_xu_inj_dcachedir_multihit : std_ulogic; -signal pc_xu_msrovride_enab : std_ulogic; -signal pc_xu_msrovride_pr : std_ulogic; -signal pc_xu_msrovride_gs : std_ulogic; -signal pc_xu_ram_mode : std_ulogic; -signal pc_xu_ram_thread : std_ulogic_vector(0 to 1); -signal pc_xu_ram_execute : std_ulogic; -signal pc_xu_repr_sl_thold_3 : std_ulogic; -signal pc_xu_reset_1_complete : std_ulogic; -signal pc_xu_reset_2_complete : std_ulogic; -signal pc_xu_reset_3_complete : std_ulogic; -signal pc_xu_reset_wd_complete : std_ulogic; -signal pc_xu_sg_3 : std_ulogic_vector(0 to 4); -signal pc_xu_step : std_ulogic_vector(0 to 3); -signal pc_xu_stop : std_ulogic_vector(0 to 3); -signal pc_xu_timebase_dis_on_stop : std_ulogic; -signal pc_xu_time_sl_thold_3 : std_ulogic; -signal pc_xu_trace_bus_enable : std_ulogic; -signal xu_n_is2_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_rf0_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_rf1_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_ex1_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_ex2_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_ex3_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_ex4_flush : std_ulogic_vector(0 to threads-1); -signal xu_n_ex5_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_rf1_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_ex1_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_ex2_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_ex3_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_ex4_flush : std_ulogic_vector(0 to threads-1); -signal xu_s_ex5_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_rf1_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_ex1_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_ex2_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_ex3_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_ex4_flush : std_ulogic_vector(0 to threads-1); -signal xu_wu_ex5_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_rf1_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_ex1_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_ex2_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_ex3_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_ex4_flush : std_ulogic_vector(0 to threads-1); -signal xu_wl_ex5_flush : std_ulogic_vector(0 to threads-1); -signal xu_fu_ccr2_ap : std_ulogic_vector(0 to threads-1); -signal xu_fu_ex3_eff_addr : std_ulogic_vector(59 to 63); -signal xu_fu_ex6_load_data : std_ulogic_vector(0 to 255); -signal xu_fu_ex5_load_le : std_ulogic; -signal xu_fu_ex5_load_tag : std_ulogic_vector(0 to 8); -signal xu_fu_ex5_load_val : std_ulogic_vector(0 to threads-1); -signal xu_fu_ex5_reload_val : std_ulogic; -signal xu_fu_msr_fp : std_ulogic_vector(0 to 3); -signal xu_fu_msr_pr : std_ulogic_vector(0 to 3); -signal xu_fu_msr_gs : std_ulogic_vector(0 to 3); -signal xu_fu_msr_spv : std_ulogic_vector(0 to threads-1); -signal xu_fu_regfile_seq_beg : std_ulogic; -signal xu_iu_complete_qentry : std_ulogic_vector(0 to lmq_entries-1); -signal xu_iu_complete_target_type : std_ulogic_vector(0 to 1); -signal xu_iu_complete_tid : std_ulogic_vector(0 to 3); -signal xu_iu_ex1_ra_entry : std_ulogic_vector(8 to 11); -signal xu_iu_ex1_rb : std_ulogic_vector(64-(2**regmode) to 51); -signal xu_iu_ex1_rs_is : std_ulogic_vector(0 to 8); -signal xu_iu_ex5_bclr : std_ulogic; -signal xu_iu_ex5_bh : std_ulogic_vector(0 to 1); -signal xu_iu_ex5_br_hist : std_ulogic_vector(0 to 1); -signal xu_iu_ex5_br_taken : std_ulogic; -signal xu_iu_ex5_br_update : std_ulogic; -signal xu_iu_ex5_getNIA : std_ulogic; -signal xu_iu_ex5_gshare : std_ulogic_vector(0 to 3); -signal xu_iu_ex5_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); -signal xu_iu_ex5_lk : std_ulogic; -signal xu_iu_ex5_ppc_cpl : std_ulogic_vector(0 to 3); -signal xu_iu_ex4_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); -signal xu_iu_ex4_loadmiss_target : std_ulogic_vector(0 to 8); -signal xu_iu_ex4_loadmiss_target_type: std_ulogic_vector(0 to 1); -signal xu_iu_ex4_loadmiss_tid : std_ulogic_vector(0 to 3); -signal xu_iu_ex4_rs_data : std_ulogic_vector(64-(2**regmode) to 63); -signal xu_iu_ex5_tid : std_ulogic_vector(0 to threads-1); -signal xu_iu_ex5_val : std_ulogic; -signal xu_iu_ex5_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); -signal xu_iu_ex5_loadmiss_target : std_ulogic_vector(0 to 8); -signal xu_iu_ex5_loadmiss_target_type: std_ulogic_vector(0 to 1); -signal xu_iu_ex5_loadmiss_tid : std_ulogic_vector(0 to 3); -signal xu_iu_ex6_icbi_val : std_ulogic_vector(0 to threads-1); -signal xu_iu_ex6_icbi_addr : std_ulogic_vector(64-xu_real_data_add to 57); -signal xu_iu_ex6_pri : std_ulogic_vector(0 to 2); -signal xu_iu_ex6_pri_val : std_ulogic_vector(0 to 3); -signal xu_iu_flush_2ucode : std_ulogic_vector(0 to 3); -signal xu_iu_flush_2ucode_type : std_ulogic_vector(0 to 3); -signal xu_iu_hid_mmu_mode : std_ulogic; -signal xu_iu_xucr0_rel : std_ulogic; -signal xu_iu_ici : std_ulogic; -signal xu_iu_iu0_flush_ifar0 : std_ulogic_vector(62-xu_eff_ifar to 61); -signal xu_iu_iu0_flush_ifar1 : std_ulogic_vector(62-xu_eff_ifar to 61); -signal xu_iu_iu0_flush_ifar2 : std_ulogic_vector(62-xu_eff_ifar to 61); -signal xu_iu_iu0_flush_ifar3 : std_ulogic_vector(62-xu_eff_ifar to 61); -signal xu_iu_larx_done_tid : std_ulogic_vector(0 to 3); -signal xu_iu_membar_tid : std_ulogic_vector(0 to 3); -signal xu_iu_msr_cm : std_ulogic_vector(0 to threads-1); -signal xu_iu_msr_gs : std_ulogic_vector(0 to 3); -signal xu_iu_msr_hv : std_ulogic_vector(0 to threads-1); -signal xu_iu_msr_is : std_ulogic_vector(0 to threads-1); -signal xu_iu_msr_pr : std_ulogic_vector(0 to threads-1); -signal xu_iu_multdiv_done : std_ulogic_vector(0 to threads-1); -signal xu_iu_need_hole : std_ulogic; -signal xu_iu_raise_iss_pri : std_ulogic_vector(0 to 3); -signal xu_iu_ram_issue : std_ulogic_vector(0 to threads-1); -signal xu_iu_ex1_is_csync : std_ulogic; -signal xu_iu_ex1_is_isync : std_ulogic; -signal xu_iu_rf1_is_eratilx : std_ulogic; -signal xu_iu_rf1_is_eratre : std_ulogic; -signal xu_iu_rf1_is_eratsx : std_ulogic; -signal xu_iu_rf1_is_eratwe : std_ulogic; -signal xu_iu_rf1_val : std_ulogic_vector(0 to 3); -signal xu_iu_rf1_ws : std_ulogic_vector(0 to 1); -signal xu_iu_rf1_t : std_ulogic_vector(0 to 2); -signal xu_iu_run_thread : std_ulogic_vector(0 to 3); -signal xu_iu_set_barr_tid : std_ulogic_vector(0 to 3); -signal xu_iu_single_instr_mode : std_ulogic_vector(0 to threads-1); -signal xu_iu_slowspr_done : std_ulogic_vector(0 to 3); -signal xu_iu_spr_ccr2_en_dcr : std_ulogic; -signal xu_iu_spr_ccr2_ifratsc : std_ulogic_vector(0 to 8); -signal xu_iu_spr_ccr2_ifrat : std_ulogic; -signal xu_bx_ccr2_en_ditc : std_ulogic; -signal xu_iu_spr_xer0 : std_ulogic_vector(57 to 63); -signal xu_iu_spr_xer1 : std_ulogic_vector(57 to 63); -signal xu_iu_spr_xer2 : std_ulogic_vector(57 to 63); -signal xu_iu_spr_xer3 : std_ulogic_vector(57 to 63); -signal xu_iu_uc_flush_ifar0 : std_ulogic_vector(62-uc_ifar to 61); -signal xu_iu_uc_flush_ifar1 : std_ulogic_vector(62-uc_ifar to 61); -signal xu_iu_uc_flush_ifar2 : std_ulogic_vector(62-uc_ifar to 61); -signal xu_iu_uc_flush_ifar3 : std_ulogic_vector(62-uc_ifar to 61); -signal xu_iu_ucode_restart : std_ulogic_vector(0 to 3); -signal xu_mm_derat_epn : std_ulogic_vector(64-rs_data_width to 51); -signal xu_mm_derat_lpid : std_ulogic_vector(0 to lpid_width-1); -signal xu_mm_derat_mmucr0 : std_ulogic_vector(0 to 17); -signal xu_mm_derat_mmucr0_we : std_ulogic_vector(0 to 3); -signal xu_mm_derat_mmucr1 : std_ulogic_vector(0 to 4); -signal xu_mm_derat_mmucr1_we : std_ulogic; -signal xu_mm_derat_req : std_ulogic; -signal xu_mm_derat_snoop_ack : std_ulogic; -signal xu_mm_derat_thdid : std_ulogic_vector(0 to 3); -signal xu_mm_derat_tid : std_ulogic_vector(0 to pid_width-1); -signal xu_mm_derat_ttype : std_ulogic_vector(0 to 1); -signal xu_mm_derat_state : std_ulogic_vector(0 to 3); -signal xu_mm_ex2_eff_addr : std_ulogic_vector(64-rs_data_width to 63); -signal xu_mm_ex1_rs_is : std_ulogic_vector(0 to 8); -signal xu_mm_ex4_flush : std_ulogic_vector(0 to thdid_width-1); -signal xu_mm_ex5_flush : std_ulogic_vector(0 to thdid_width-1); -signal xu_mm_ex5_perf_dtlb : std_ulogic_vector(0 to thdid_width-1); -signal xu_mm_ex5_perf_itlb : std_ulogic_vector(0 to thdid_width-1); -signal xu_mm_hid_mmu_mode : std_ulogic; -signal xu_mm_hold_ack : std_ulogic_vector(0 to thdid_width-1); -signal xu_mm_ierat_flush : std_ulogic_vector(0 to threads-1); -signal xu_mm_ierat_miss : std_ulogic_vector(0 to threads-1); -signal xu_mm_lmq_stq_empty : std_ulogic; -signal xu_mm_lsu_token : std_ulogic; -signal xu_mm_msr_cm : std_ulogic_vector(0 to threads-1); -signal xu_mm_msr_ds : std_ulogic_vector(0 to threads-1); -signal xu_mm_msr_gs : std_ulogic_vector(0 to threads-1); -signal xu_mm_msr_is : std_ulogic_vector(0 to threads-1); -signal xu_mm_msr_pr : std_ulogic_vector(0 to threads-1); -signal xu_mm_ex1_is_csync : std_ulogic; -signal xu_mm_ex1_is_isync : std_ulogic; -signal xu_mm_rf1_is_eratilx : std_ulogic; -signal xu_mm_rf1_is_erativax : std_ulogic; -signal xu_mm_rf1_is_tlbilx : std_ulogic; -signal xu_mm_rf1_is_tlbivax : std_ulogic; -signal xu_mm_rf1_is_tlbre : std_ulogic; -signal xu_mm_rf1_is_tlbsx : std_ulogic; -signal xu_mm_rf1_is_tlbsrx : std_ulogic; -signal xu_mm_rf1_is_tlbwe : std_ulogic; -signal xu_mm_rf1_val : std_ulogic_vector(0 to 3); -signal xu_mm_rf1_t : std_ulogic_vector(0 to 2); -signal xu_mm_slowspr_addr : std_ulogic_vector(0 to 9); -signal xu_mm_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); -signal xu_mm_slowspr_done : std_ulogic; -signal xu_mm_slowspr_etid : std_ulogic_vector(0 to 1); -signal xu_mm_slowspr_rw : std_ulogic; -signal xu_mm_slowspr_val : std_ulogic; -signal xu_mm_spr_epcr_dgtmi : std_ulogic_vector(0 to threads-1); -signal xu_mm_spr_epcr_dmiuh : std_ulogic_vector(0 to thdid_width-1); -signal xu_pc_err_attention_instr : std_ulogic_vector(0 to 3); -signal xu_pc_err_dcache_parity : std_ulogic; -signal xu_pc_err_dcachedir_parity : std_ulogic; -signal xu_pc_err_dcachedir_multihit : std_ulogic; -signal xu_pc_err_debug_event : std_ulogic_vector(0 to 3); -signal xu_pc_err_ditc_overrun : std_ulogic; -signal bx_pc_err_inbox_ecc : std_ulogic; -signal xu_pc_err_invld_reld : std_ulogic; -signal bx_pc_err_outbox_ecc : std_ulogic; -signal xu_pc_err_l2intrf_ecc : std_ulogic; -signal xu_pc_err_l2intrf_ue : std_ulogic; -signal xu_pc_err_l2credit_overrun : std_ulogic; -signal xu_pc_err_llbust_attempt : std_ulogic_vector(0 to 3); -signal xu_pc_err_llbust_failed : std_ulogic_vector(0 to 3); -signal xu_pc_err_nia_miscmpr : std_ulogic_vector(0 to 3); -signal xu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); -signal xu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); -signal xu_pc_err_sprg_ecc : std_ulogic_vector(0 to 3); -signal xu_pc_err_sprg_ue : std_ulogic_vector(0 to 3); -signal xu_pc_err_wdt_reset : std_ulogic_vector(0 to 3); -signal xu_pc_event_data : std_ulogic_vector(0 to 7); -signal xu_pc_lsu_event_data : std_ulogic_vector(0 to 7); -signal xu_pc_ram_data : std_ulogic_vector(64-(2**regmode) to 63); -signal xu_pc_ram_done : std_ulogic; -signal xu_pc_ram_interrupt : std_ulogic; -signal xu_pc_running : std_ulogic_vector(0 to 3); -signal xu_pc_step_done : std_ulogic_vector(0 to threads-1); -signal xu_pc_stop_dbg_event : std_ulogic_vector(0 to 3); -signal pc_fu_ccflush_dc : std_ulogic; -signal pc_iu_ccflush_dc : std_ulogic; -signal pc_xu_ccflush_dc : std_ulogic; -signal pc_bx_ccflush_dc : std_ulogic; -signal pc_fu_event_count_mode : std_ulogic_vector(0 to 2); -signal pc_iu_event_count_mode : std_ulogic_vector(0 to 2); -signal pc_xu_event_count_mode : std_ulogic_vector(0 to 2); -signal pc_fu_inj_regfile_parity : std_ulogic_vector(0 to 3); -signal pc_fu_instr_trace_mode : std_ulogic; -signal pc_fu_instr_trace_tid : std_ulogic_vector(0 to 1); -signal pc_xu_instr_trace_mode : std_ulogic; -signal pc_xu_instr_trace_tid : std_ulogic_vector(0 to 1); -signal pc_xu_ram_flush_thread : std_ulogic; -signal pc_bx_abist_di_0 : std_ulogic_vector(0 to 3); -signal pc_bx_abist_ena_dc : std_ulogic; -signal pc_bx_abist_g8t1p_renb_0 : std_ulogic; -signal pc_bx_abist_g8t_bw_0 : std_ulogic; -signal pc_bx_abist_g8t_bw_1 : std_ulogic; -signal pc_bx_abist_g8t_dcomp : std_ulogic_vector(0 to 3); -signal pc_bx_abist_g8t_wenb : std_ulogic; -signal pc_bx_abist_raddr_0 : std_ulogic_vector(0 to 9); -signal pc_bx_abist_raw_dc_b : std_ulogic; -signal pc_bx_abist_waddr_0 : std_ulogic_vector(0 to 9); -signal pc_bx_abist_wl64_comp_ena : std_ulogic; -signal pc_fu_abist_di_0 : std_ulogic_vector(0 to 3); -signal pc_fu_abist_di_1 : std_ulogic_vector(0 to 3); -signal pc_fu_abist_ena_dc : std_ulogic; -signal pc_fu_abist_grf_renb_0 : std_ulogic; -signal pc_fu_abist_grf_renb_1 : std_ulogic; -signal pc_fu_abist_grf_wenb_0 : std_ulogic; -signal pc_fu_abist_grf_wenb_1 : std_ulogic; -signal pc_fu_abist_raddr_0 : std_ulogic_vector(0 to 9); -signal pc_fu_abist_raddr_1 : std_ulogic_vector(0 to 9); -signal pc_fu_abist_raw_dc_b : std_ulogic; -signal pc_fu_abist_waddr_0 : std_ulogic_vector(0 to 9); -signal pc_fu_abist_waddr_1 : std_ulogic_vector(0 to 9); -signal pc_fu_abist_wl144_comp_ena : std_ulogic; -signal pc_iu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); -signal pc_iu_abist_di_0 : std_ulogic_vector(0 to 3); -signal pc_iu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); -signal pc_iu_abist_ena_dc : std_ulogic; -signal pc_iu_abist_g6t_bw : std_ulogic_vector(0 to 1); -signal pc_iu_abist_g6t_r_wb : std_ulogic; -signal pc_iu_abist_g8t1p_renb_0 : std_ulogic; -signal pc_iu_abist_g8t_bw_0 : std_ulogic; -signal pc_iu_abist_g8t_bw_1 : std_ulogic; -signal pc_iu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); -signal pc_iu_abist_g8t_wenb : std_ulogic; -signal pc_iu_abist_raddr_0 : std_ulogic_vector(0 to 9); -signal pc_iu_abist_raw_dc_b : std_ulogic; -signal pc_iu_abist_waddr_0 : std_ulogic_vector(0 to 9); -signal pc_iu_abist_wl128_comp_ena : std_ulogic; -signal pc_iu_abist_wl256_comp_ena : std_ulogic; -signal pc_iu_abist_wl64_comp_ena : std_ulogic; -signal pc_xu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_0 : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_1 : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); -signal pc_xu_abist_ena_dc : std_ulogic; -signal pc_xu_abist_g6t_bw : std_ulogic_vector(0 to 1); -signal pc_xu_abist_g6t_r_wb : std_ulogic; -signal pc_xu_abist_g8t1p_renb_0 : std_ulogic; -signal pc_xu_abist_g8t_bw_0 : std_ulogic; -signal pc_xu_abist_g8t_bw_1 : std_ulogic; -signal pc_xu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); -signal pc_xu_abist_g8t_wenb : std_ulogic; -signal pc_xu_abist_grf_renb_0 : std_ulogic; -signal pc_xu_abist_grf_renb_1 : std_ulogic; -signal pc_xu_abist_grf_wenb_0 : std_ulogic; -signal pc_xu_abist_grf_wenb_1 : std_ulogic; -signal pc_xu_abist_raddr_0 : std_ulogic_vector(0 to 9); -signal pc_xu_abist_raddr_1 : std_ulogic_vector(0 to 9); -signal pc_xu_abist_raw_dc_b : std_ulogic; -signal pc_xu_abist_waddr_0 : std_ulogic_vector(0 to 9); -signal pc_xu_abist_waddr_1 : std_ulogic_vector(0 to 9); -signal pc_xu_abist_wl144_comp_ena : std_ulogic; -signal pc_xu_abist_wl32_comp_ena : std_ulogic; -signal pc_xu_abist_wl512_comp_ena : std_ulogic; +signal fu_xu_ex2_store_data : std_ulogic_vector(0 to 63); +signal fu_xu_ex2_store_data_val : std_ulogic; +signal fu_xu_ex3_ap_int_req : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_flush2ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_match : std_ulogic_vector(0 to 3); +signal fu_xu_ex2_instr_type : std_ulogic_vector(0 to 11); +signal fu_xu_ex2_is_ucode : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_n_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_np1_flush : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_regfile_err_det : std_ulogic_vector(0 to 3); +signal fu_xu_ex3_trap : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_bf : std_ulogic_vector(0 to 2); +signal fu_xu_ex4_cr_noflush : std_ulogic_vector(0 to 3); +signal fu_xu_ex4_cr_val : std_ulogic_vector(0 to 3); +signal fu_xu_regfile_seq_end : std_ulogic; +signal fu_xu_rf1_act : std_ulogic_vector(0 to 3); +signal fu_bx_slowspr_addr : std_ulogic_vector(0 to 9); +signal fu_bx_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal fu_bx_slowspr_done : std_ulogic; +signal fu_bx_slowspr_etid : std_ulogic_vector(0 to 1); +signal fu_bx_slowspr_rw : std_ulogic; +signal fu_bx_slowspr_val : std_ulogic; +signal bx_xu_slowspr_addr : std_ulogic_vector(0 to 9); +signal bx_xu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal bx_xu_slowspr_done : std_ulogic; +signal bx_xu_slowspr_etid : std_ulogic_vector(0 to 1); +signal bx_xu_slowspr_rw : std_ulogic; +signal bx_xu_slowspr_val : std_ulogic; +signal bx_xu_quiesce : std_ulogic_vector(0 to 3); +signal iu_fu_ex2_n_flush : std_ulogic_vector(0 to 3); +signal iu_fu_is2_tid_decode : std_ulogic_vector(0 to 3); +signal iu_fu_rf0_bypsel : std_ulogic_vector(0 to 5); +signal iu_fu_rf0_fra : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_fra_v : std_ulogic; +signal iu_fu_rf0_frb : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frb_v : std_ulogic; +signal iu_fu_rf0_frc : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_frc_v : std_ulogic; +signal iu_fu_rf0_frt : std_ulogic_vector(0 to 6); +signal iu_fu_rf0_ifar : eff_ifar; +signal iu_fu_rf0_instr : std_ulogic_vector(0 to 31); +signal iu_fu_rf0_instr_match : std_ulogic; +signal iu_fu_rf0_instr_v : std_ulogic; +signal iu_fu_rf0_is_ucode : std_ulogic; +signal iu_fu_rf0_ucfmul : std_ulogic; +signal iu_fu_rf0_ldst_val : std_ulogic; +signal iu_fu_rf0_ldst_tid : std_ulogic_vector(0 to 1); +signal iu_fu_rf0_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_fu_rf0_str_val : std_ulogic; +signal iu_fu_rf0_tid : std_ulogic_vector(0 to 1); +signal iu_mm_ierat_epn : std_ulogic_vector(0 to 51); +signal iu_mm_ierat_flush : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr0 : std_ulogic_vector(0 to 17); +signal iu_mm_ierat_mmucr0_we : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1 : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_mmucr1_we : std_ulogic; +signal iu_mm_ierat_req : std_ulogic; +signal iu_mm_ierat_snoop_ack : std_ulogic; +signal iu_mm_ierat_thdid : std_ulogic_vector(0 to 3); +signal iu_mm_ierat_tid : std_ulogic_vector(0 to 13); +signal iu_mm_ierat_state : std_ulogic_vector(0 to 3); +signal iu_mm_lmq_empty : std_ulogic; +signal iu_pc_err_icache_parity : std_ulogic; +signal iu_pc_err_icachedir_multihit : std_ulogic; +signal iu_pc_err_icachedir_parity : std_ulogic; +signal iu_pc_err_ucode_illegal : std_ulogic_vector(0 to 3); +signal iu_pc_event_data : std_ulogic_vector(0 to 7); +signal iu_pc_slowspr_addr : std_ulogic_vector(0 to 9); +signal iu_pc_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_pc_slowspr_done : std_ulogic; +signal iu_pc_slowspr_etid : std_ulogic_vector(0 to 1); +signal iu_pc_slowspr_rw : std_ulogic; +signal iu_pc_slowspr_val : std_ulogic; +signal iu_xu_ex4_tlb_data : std_ulogic_vector(64-(2**regmode) to 63); +signal iu_xu_ierat_ex2_flush_req : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex3_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_ierat_ex4_par_err : std_ulogic_vector(0 to threads-1); +signal iu_xu_is2_axu_instr_type : std_ulogic_vector(0 to 2); +signal iu_xu_is2_axu_ld_or_st : std_ulogic; +signal iu_xu_is2_axu_ldst_extpid : std_ulogic; +signal iu_xu_is2_axu_ldst_forcealign : std_ulogic; +signal iu_xu_is2_axu_ldst_forceexcept : std_ulogic; +signal iu_xu_is2_axu_ldst_indexed : std_ulogic; +signal iu_xu_is2_axu_ldst_size : std_ulogic_vector(0 to 5); +signal iu_xu_is2_axu_ldst_tag : std_ulogic_vector(0 to 8); +signal iu_xu_is2_axu_ldst_update : std_ulogic; +signal iu_xu_is2_axu_mffgpr : std_ulogic; +signal iu_xu_is2_axu_mftgpr : std_ulogic; +signal iu_xu_is2_axu_movedp : std_ulogic; +signal iu_xu_is2_axu_store : std_ulogic; +signal iu_xu_is2_error : std_ulogic_vector(0 to 2); +signal iu_xu_is2_gshare : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ifar : eff_ifar; +signal iu_xu_is2_instr : std_ulogic_vector(0 to 31); +signal iu_xu_is2_is_ucode : std_ulogic; +signal iu_xu_is2_match : std_ulogic; +signal iu_xu_is2_pred_taken_cnt : std_ulogic_vector(0 to 1); +signal iu_xu_is2_pred_update : std_ulogic; +signal iu_xu_is2_s1 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s1_vld : std_ulogic; +signal iu_xu_is2_s2 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s2_vld : std_ulogic; +signal iu_xu_is2_s3 : std_ulogic_vector(0 to 5); +signal iu_xu_is2_s3_vld : std_ulogic; +signal iu_xu_is2_ta : std_ulogic_vector(0 to 5); +signal iu_xu_is2_ta_vld : std_ulogic; +signal iu_xu_is2_tid : std_ulogic_vector(0 to 3); +signal iu_xu_is2_ucode_vld : std_ulogic; +signal iu_xu_is2_vld : std_ulogic; +signal iu_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal iu_xu_ra : std_ulogic_vector(real_ifar'left to 59); +signal iu_xu_request : std_ulogic; +signal iu_xu_thread : std_ulogic_vector(0 to 3); +signal iu_xu_userdef : std_ulogic_vector(0 to 3); +signal iu_xu_wimge : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_iu_ierat_mmucr1 : std_ulogic_vector(0 to 8); +signal mm_iu_ierat_pid0 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid1 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid2 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_pid3 : std_ulogic_vector(0 to 13); +signal mm_iu_ierat_rel_data : std_ulogic_vector(0 to 131); +signal mm_iu_ierat_rel_val : std_ulogic_vector(0 to 4); +signal mm_iu_ierat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_iu_ierat_snoop_coming : std_ulogic; +signal mm_iu_ierat_snoop_val : std_ulogic; +signal mm_iu_ierat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_slowspr_addr : std_ulogic_vector(0 to 9); +signal mm_iu_slowspr_data : std_ulogic_vector(64-spr_data_width to 63); +signal mm_iu_slowspr_done : std_ulogic; +signal mm_iu_slowspr_etid : std_ulogic_vector(0 to 1); +signal mm_iu_slowspr_rw : std_ulogic; +signal mm_iu_slowspr_val : std_ulogic; +signal xu_pc_err_mcsr_summary : std_ulogic_vector(0 to threads-1); +signal xu_pc_err_ierat_parity : std_ulogic; +signal xu_pc_err_derat_parity : std_ulogic; +signal xu_pc_err_tlb_parity : std_ulogic; +signal xu_pc_err_tlb_lru_parity : std_ulogic; +signal xu_pc_err_ierat_multihit : std_ulogic; +signal xu_pc_err_derat_multihit : std_ulogic; +signal xu_pc_err_tlb_multihit : std_ulogic; +signal xu_pc_err_ext_mchk : std_ulogic; +signal xu_pc_err_local_snoop_reject : std_ulogic; +signal mm_xu_derat_mmucr0_0 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_1 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_2 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr0_3 : std_ulogic_vector(0 to 19); +signal mm_xu_derat_mmucr1 : std_ulogic_vector(0 to 9); +signal mm_xu_derat_pid0 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid1 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid2 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_pid3 : std_ulogic_vector(0 to 13); +signal mm_xu_derat_rel_data : std_ulogic_vector(0 to 131); +signal mm_xu_derat_rel_val : std_ulogic_vector(0 to 4); +signal mm_xu_derat_snoop_attr : std_ulogic_vector(0 to 25); +signal mm_xu_derat_snoop_coming : std_ulogic; +signal mm_xu_derat_snoop_val : std_ulogic; +signal mm_xu_derat_snoop_vpn : std_ulogic_vector(52-epn_width to 51); +signal mm_iu_barrier_done : std_ulogic_vector(0 to 3); +signal mm_xu_eratmiss_done : std_ulogic_vector(0 to 3); +signal mm_xu_esr_pt : std_ulogic_vector(0 to 3); +signal mm_xu_esr_data : std_ulogic_vector(0 to 3); +signal mm_xu_esr_epid : std_ulogic_vector(0 to 3); +signal mm_xu_esr_st : std_ulogic_vector(0 to 3); +signal mm_xu_ex3_flush_req : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_is_tlbsxr : std_ulogic; +signal mm_xu_hold_done : std_ulogic_vector(0 to 3); +signal mm_xu_hold_req : std_ulogic_vector(0 to 3); +signal mm_xu_hv_priv : std_ulogic_vector(0 to threads-1); +signal mm_xu_illeg_instr : std_ulogic_vector(0 to threads-1); +signal mm_xu_lru_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_lrat_miss : std_ulogic_vector(0 to 3); +signal mm_xu_local_snoop_reject : std_ulogic_vector(0 to thdid_width-1); +signal mm_xu_lsu_addr : std_ulogic_vector(64-real_addr_width to 63); +signal mm_xu_lsu_lpid : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_lpidr : std_ulogic_vector(0 to 7); +signal mm_xu_lsu_gs : std_ulogic; +signal mm_xu_lsu_ind : std_ulogic; +signal mm_xu_lsu_lbit : std_ulogic; +signal mm_xu_lsu_req : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_ttype : std_ulogic_vector(0 to 1); +signal mm_xu_lsu_u : std_ulogic_vector(0 to 3); +signal mm_xu_lsu_wimge : std_ulogic_vector(0 to 4); +signal mm_xu_pt_fault : std_ulogic_vector(0 to 3); +signal mm_xu_quiesce : std_ulogic_vector(0 to threads-1); +signal mm_xu_tlb_inelig : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_miss : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_multihit_err : std_ulogic_vector(0 to 3); +signal mm_xu_tlb_par_err : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq : std_ulogic_vector(0 to 3); +signal mm_xu_cr0_eq_valid : std_ulogic_vector(0 to 3); +signal pc_bx_inj_inbox_ecc : std_ulogic; +signal pc_bx_inj_outbox_ecc : std_ulogic; +signal pc_fu_abst_sl_thold_3 : std_ulogic; +signal pc_fu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_fu_ary_nsl_thold_3 : std_ulogic; +signal pc_fu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_cfg_sl_thold_3 : std_ulogic; +signal pc_fu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_bx_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_fu_fce_3 : std_ulogic; +signal pc_fu_func_nsl_thold_3 : std_ulogic; +signal pc_fu_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_fu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 1); +signal pc_fu_gptr_sl_thold_3 : std_ulogic; +signal pc_fu_ram_mode : std_ulogic; +signal pc_fu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_fu_repr_sl_thold_3 : std_ulogic; +signal pc_fu_sg_3 : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_addr : std_ulogic_vector(0 to 9); +signal pc_fu_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal pc_fu_slowspr_done : std_ulogic; +signal pc_fu_slowspr_etid : std_ulogic_vector(0 to 1); +signal pc_fu_slowspr_rw : std_ulogic; +signal pc_fu_slowspr_val : std_ulogic; +signal pc_bx_trace_bus_enable : std_ulogic; +signal pc_fu_time_sl_thold_3 : std_ulogic; +signal pc_fu_trace_bus_enable : std_ulogic; +signal pc_iu_gptr_sl_thold_4 : std_ulogic; +signal pc_iu_time_sl_thold_4 : std_ulogic; +signal pc_iu_repr_sl_thold_4 : std_ulogic; +signal pc_iu_abst_sl_thold_4 : std_ulogic; +signal pc_iu_abst_slp_sl_thold_4 : std_ulogic; +signal pc_iu_bolt_sl_thold_4 : std_ulogic; +signal pc_iu_regf_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_sl_thold_4 : std_ulogic; +signal pc_iu_func_slp_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_sl_thold_4 : std_ulogic; +signal pc_iu_cfg_slp_sl_thold_4 : std_ulogic; +signal pc_iu_func_nsl_thold_4 : std_ulogic; +signal pc_iu_func_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_nsl_thold_4 : std_ulogic; +signal pc_iu_ary_slp_nsl_thold_4 : std_ulogic; +signal pc_iu_sg_4 : std_ulogic; +signal pc_iu_fce_4 : std_ulogic; +signal pc_iu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_iu_init_reset : std_ulogic; +signal pc_iu_inj_icache_parity : std_ulogic; +signal pc_iu_inj_icachedir_parity : std_ulogic; +signal pc_iu_inj_icachedir_multihit : std_ulogic; +signal pc_iu_ram_force_cmplt : std_ulogic; +signal pc_iu_ram_instr : std_ulogic_vector(0 to 31); +signal pc_iu_ram_instr_ext : std_ulogic_vector(0 to 3); +signal pc_iu_ram_mode : std_ulogic; +signal pc_iu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_iu_trace_bus_enable : std_ulogic; +signal pc_xu_abst_sl_thold_3 : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3 : std_ulogic; +signal pc_xu_regf_sl_thold_3 : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3 : std_ulogic; +signal pc_xu_ary_nsl_thold_3 : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_cache_par_err_event : std_ulogic; +signal pc_xu_cfg_sl_thold_3 : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3 : std_ulogic; +signal pc_xu_dbg_action : std_ulogic_vector(0 to 11); +signal pc_xu_decrem_dis_on_stop : std_ulogic; +signal spr_pvr_version_dc : std_ulogic_vector(8 to 15); +signal spr_pvr_revision_dc : std_ulogic_vector(12 to 15); +signal xu_pc_spr_ccr0_we : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme : std_ulogic_vector(0 to 1); +signal pc_xu_debug_mux1_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls : std_ulogic_vector(0 to 15); +signal pc_xu_extirpts_dis_on_stop : std_ulogic; +signal pc_xu_fce_3 : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3 : std_ulogic; +signal pc_xu_func_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3 : std_ulogic; +signal pc_xu_func_slp_sl_thold_3 : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3 : std_ulogic; +signal pc_xu_init_reset : std_ulogic; +signal pc_xu_inj_dcache_parity : std_ulogic; +signal pc_xu_inj_dcachedir_parity : std_ulogic; +signal pc_xu_inj_llbust_attempt : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit : std_ulogic; +signal pc_xu_msrovride_enab : std_ulogic; +signal pc_xu_msrovride_pr : std_ulogic; +signal pc_xu_msrovride_gs : std_ulogic; +signal pc_xu_ram_mode : std_ulogic; +signal pc_xu_ram_thread : std_ulogic_vector(0 to 1); +signal pc_xu_ram_execute : std_ulogic; +signal pc_xu_repr_sl_thold_3 : std_ulogic; +signal pc_xu_reset_1_complete : std_ulogic; +signal pc_xu_reset_2_complete : std_ulogic; +signal pc_xu_reset_3_complete : std_ulogic; +signal pc_xu_reset_wd_complete : std_ulogic; +signal pc_xu_sg_3 : std_ulogic_vector(0 to 4); +signal pc_xu_step : std_ulogic_vector(0 to 3); +signal pc_xu_stop : std_ulogic_vector(0 to 3); +signal pc_xu_timebase_dis_on_stop : std_ulogic; +signal pc_xu_time_sl_thold_3 : std_ulogic; +signal pc_xu_trace_bus_enable : std_ulogic; +signal xu_n_is2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf0_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_n_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_s_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wu_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_rf1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex1_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex2_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex3_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex4_flush : std_ulogic_vector(0 to threads-1); +signal xu_wl_ex5_flush : std_ulogic_vector(0 to threads-1); +signal xu_fu_ccr2_ap : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex3_eff_addr : std_ulogic_vector(59 to 63); +signal xu_fu_ex6_load_data : std_ulogic_vector(0 to 255); +signal xu_fu_ex5_load_le : std_ulogic; +signal xu_fu_ex5_load_tag : std_ulogic_vector(0 to 8); +signal xu_fu_ex5_load_val : std_ulogic_vector(0 to threads-1); +signal xu_fu_ex5_reload_val : std_ulogic; +signal xu_fu_msr_fp : std_ulogic_vector(0 to 3); +signal xu_fu_msr_pr : std_ulogic_vector(0 to 3); +signal xu_fu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_fu_msr_spv : std_ulogic_vector(0 to threads-1); +signal xu_fu_regfile_seq_beg : std_ulogic; +signal xu_iu_complete_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_complete_target_type : std_ulogic_vector(0 to 1); +signal xu_iu_complete_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex1_ra_entry : std_ulogic_vector(8 to 11); +signal xu_iu_ex1_rb : std_ulogic_vector(64-(2**regmode) to 51); +signal xu_iu_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_bclr : std_ulogic; +signal xu_iu_ex5_bh : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_hist : std_ulogic_vector(0 to 1); +signal xu_iu_ex5_br_taken : std_ulogic; +signal xu_iu_ex5_br_update : std_ulogic; +signal xu_iu_ex5_getNIA : std_ulogic; +signal xu_iu_ex5_gshare : std_ulogic_vector(0 to 3); +signal xu_iu_ex5_ifar : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_ex5_lk : std_ulogic; +signal xu_iu_ex5_ppc_cpl : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex4_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex4_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex4_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex4_rs_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_iu_ex5_tid : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex5_val : std_ulogic; +signal xu_iu_ex5_loadmiss_qentry : std_ulogic_vector(0 to lmq_entries-1); +signal xu_iu_ex5_loadmiss_target : std_ulogic_vector(0 to 8); +signal xu_iu_ex5_loadmiss_target_type: std_ulogic_vector(0 to 1); +signal xu_iu_ex5_loadmiss_tid : std_ulogic_vector(0 to 3); +signal xu_iu_ex6_icbi_val : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex6_icbi_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal xu_iu_ex6_pri : std_ulogic_vector(0 to 2); +signal xu_iu_ex6_pri_val : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode : std_ulogic_vector(0 to 3); +signal xu_iu_flush_2ucode_type : std_ulogic_vector(0 to 3); +signal xu_iu_hid_mmu_mode : std_ulogic; +signal xu_iu_xucr0_rel : std_ulogic; +signal xu_iu_ici : std_ulogic; +signal xu_iu_iu0_flush_ifar0 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar1 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar2 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_iu0_flush_ifar3 : std_ulogic_vector(62-xu_eff_ifar to 61); +signal xu_iu_larx_done_tid : std_ulogic_vector(0 to 3); +signal xu_iu_membar_tid : std_ulogic_vector(0 to 3); +signal xu_iu_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_gs : std_ulogic_vector(0 to 3); +signal xu_iu_msr_hv : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_iu_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_iu_multdiv_done : std_ulogic_vector(0 to threads-1); +signal xu_iu_need_hole : std_ulogic; +signal xu_iu_raise_iss_pri : std_ulogic_vector(0 to 3); +signal xu_iu_ram_issue : std_ulogic_vector(0 to threads-1); +signal xu_iu_ex1_is_csync : std_ulogic; +signal xu_iu_ex1_is_isync : std_ulogic; +signal xu_iu_rf1_is_eratilx : std_ulogic; +signal xu_iu_rf1_is_eratre : std_ulogic; +signal xu_iu_rf1_is_eratsx : std_ulogic; +signal xu_iu_rf1_is_eratwe : std_ulogic; +signal xu_iu_rf1_val : std_ulogic_vector(0 to 3); +signal xu_iu_rf1_ws : std_ulogic_vector(0 to 1); +signal xu_iu_rf1_t : std_ulogic_vector(0 to 2); +signal xu_iu_run_thread : std_ulogic_vector(0 to 3); +signal xu_iu_set_barr_tid : std_ulogic_vector(0 to 3); +signal xu_iu_single_instr_mode : std_ulogic_vector(0 to threads-1); +signal xu_iu_slowspr_done : std_ulogic_vector(0 to 3); +signal xu_iu_spr_ccr2_en_dcr : std_ulogic; +signal xu_iu_spr_ccr2_ifratsc : std_ulogic_vector(0 to 8); +signal xu_iu_spr_ccr2_ifrat : std_ulogic; +signal xu_bx_ccr2_en_ditc : std_ulogic; +signal xu_iu_spr_xer0 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer1 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer2 : std_ulogic_vector(57 to 63); +signal xu_iu_spr_xer3 : std_ulogic_vector(57 to 63); +signal xu_iu_uc_flush_ifar0 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar1 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar2 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_uc_flush_ifar3 : std_ulogic_vector(62-uc_ifar to 61); +signal xu_iu_ucode_restart : std_ulogic_vector(0 to 3); +signal xu_mm_derat_epn : std_ulogic_vector(64-rs_data_width to 51); +signal xu_mm_derat_lpid : std_ulogic_vector(0 to lpid_width-1); +signal xu_mm_derat_mmucr0 : std_ulogic_vector(0 to 17); +signal xu_mm_derat_mmucr0_we : std_ulogic_vector(0 to 3); +signal xu_mm_derat_mmucr1 : std_ulogic_vector(0 to 4); +signal xu_mm_derat_mmucr1_we : std_ulogic; +signal xu_mm_derat_req : std_ulogic; +signal xu_mm_derat_snoop_ack : std_ulogic; +signal xu_mm_derat_thdid : std_ulogic_vector(0 to 3); +signal xu_mm_derat_tid : std_ulogic_vector(0 to pid_width-1); +signal xu_mm_derat_ttype : std_ulogic_vector(0 to 1); +signal xu_mm_derat_state : std_ulogic_vector(0 to 3); +signal xu_mm_ex2_eff_addr : std_ulogic_vector(64-rs_data_width to 63); +signal xu_mm_ex1_rs_is : std_ulogic_vector(0 to 8); +signal xu_mm_ex4_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_flush : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_dtlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ex5_perf_itlb : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_hid_mmu_mode : std_ulogic; +signal xu_mm_hold_ack : std_ulogic_vector(0 to thdid_width-1); +signal xu_mm_ierat_flush : std_ulogic_vector(0 to threads-1); +signal xu_mm_ierat_miss : std_ulogic_vector(0 to threads-1); +signal xu_mm_lmq_stq_empty : std_ulogic; +signal xu_mm_lsu_token : std_ulogic; +signal xu_mm_msr_cm : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_ds : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_gs : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_is : std_ulogic_vector(0 to threads-1); +signal xu_mm_msr_pr : std_ulogic_vector(0 to threads-1); +signal xu_mm_ex1_is_csync : std_ulogic; +signal xu_mm_ex1_is_isync : std_ulogic; +signal xu_mm_rf1_is_eratilx : std_ulogic; +signal xu_mm_rf1_is_erativax : std_ulogic; +signal xu_mm_rf1_is_tlbilx : std_ulogic; +signal xu_mm_rf1_is_tlbivax : std_ulogic; +signal xu_mm_rf1_is_tlbre : std_ulogic; +signal xu_mm_rf1_is_tlbsx : std_ulogic; +signal xu_mm_rf1_is_tlbsrx : std_ulogic; +signal xu_mm_rf1_is_tlbwe : std_ulogic; +signal xu_mm_rf1_val : std_ulogic_vector(0 to 3); +signal xu_mm_rf1_t : std_ulogic_vector(0 to 2); +signal xu_mm_slowspr_addr : std_ulogic_vector(0 to 9); +signal xu_mm_slowspr_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_mm_slowspr_done : std_ulogic; +signal xu_mm_slowspr_etid : std_ulogic_vector(0 to 1); +signal xu_mm_slowspr_rw : std_ulogic; +signal xu_mm_slowspr_val : std_ulogic; +signal xu_mm_spr_epcr_dgtmi : std_ulogic_vector(0 to threads-1); +signal xu_mm_spr_epcr_dmiuh : std_ulogic_vector(0 to thdid_width-1); +signal xu_pc_err_attention_instr : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity : std_ulogic; +signal xu_pc_err_dcachedir_parity : std_ulogic; +signal xu_pc_err_dcachedir_multihit : std_ulogic; +signal xu_pc_err_debug_event : std_ulogic_vector(0 to 3); +signal xu_pc_err_ditc_overrun : std_ulogic; +signal bx_pc_err_inbox_ecc : std_ulogic; +signal xu_pc_err_invld_reld : std_ulogic; +signal bx_pc_err_outbox_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ecc : std_ulogic; +signal xu_pc_err_l2intrf_ue : std_ulogic; +signal xu_pc_err_l2credit_overrun : std_ulogic; +signal xu_pc_err_llbust_attempt : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset : std_ulogic_vector(0 to 3); +signal xu_pc_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_lsu_event_data : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done : std_ulogic; +signal xu_pc_ram_interrupt : std_ulogic; +signal xu_pc_running : std_ulogic_vector(0 to 3); +signal xu_pc_step_done : std_ulogic_vector(0 to threads-1); +signal xu_pc_stop_dbg_event : std_ulogic_vector(0 to 3); +signal pc_fu_ccflush_dc : std_ulogic; +signal pc_iu_ccflush_dc : std_ulogic; +signal pc_xu_ccflush_dc : std_ulogic; +signal pc_bx_ccflush_dc : std_ulogic; +signal pc_fu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_iu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_xu_event_count_mode : std_ulogic_vector(0 to 2); +signal pc_fu_inj_regfile_parity : std_ulogic_vector(0 to 3); +signal pc_fu_instr_trace_mode : std_ulogic; +signal pc_fu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_instr_trace_mode : std_ulogic; +signal pc_xu_instr_trace_tid : std_ulogic_vector(0 to 1); +signal pc_xu_ram_flush_thread : std_ulogic; +signal pc_bx_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_0 : std_ulogic; +signal pc_bx_abist_g8t_bw_1 : std_ulogic; +signal pc_bx_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb : std_ulogic; +signal pc_bx_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_raw_dc_b : std_ulogic; +signal pc_bx_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_bx_abist_wl64_comp_ena : std_ulogic; +signal pc_fu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_fu_abist_ena_dc : std_ulogic; +signal pc_fu_abist_grf_renb_0 : std_ulogic; +signal pc_fu_abist_grf_renb_1 : std_ulogic; +signal pc_fu_abist_grf_wenb_0 : std_ulogic; +signal pc_fu_abist_grf_wenb_1 : std_ulogic; +signal pc_fu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_raw_dc_b : std_ulogic; +signal pc_fu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_fu_abist_wl144_comp_ena : std_ulogic; +signal pc_iu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_iu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_iu_abist_ena_dc : std_ulogic; +signal pc_iu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_iu_abist_g6t_r_wb : std_ulogic; +signal pc_iu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_0 : std_ulogic; +signal pc_iu_abist_g8t_bw_1 : std_ulogic; +signal pc_iu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_iu_abist_g8t_wenb : std_ulogic; +signal pc_iu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_raw_dc_b : std_ulogic; +signal pc_iu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_iu_abist_wl128_comp_ena : std_ulogic; +signal pc_iu_abist_wl256_comp_ena : std_ulogic; +signal pc_iu_abist_wl64_comp_ena : std_ulogic; +signal pc_xu_abist_dcomp_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1 : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc : std_ulogic; +signal pc_xu_abist_g6t_bw : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_0 : std_ulogic; +signal pc_xu_abist_g8t_bw_1 : std_ulogic; +signal pc_xu_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb : std_ulogic; +signal pc_xu_abist_grf_renb_0 : std_ulogic; +signal pc_xu_abist_grf_renb_1 : std_ulogic; +signal pc_xu_abist_grf_wenb_0 : std_ulogic; +signal pc_xu_abist_grf_wenb_1 : std_ulogic; +signal pc_xu_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b : std_ulogic; +signal pc_xu_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1 : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena : std_ulogic; +signal pc_xu_abist_wl32_comp_ena : std_ulogic; +signal pc_xu_abist_wl512_comp_ena : std_ulogic; signal xu_bx_ex1_mtdp_val : std_ulogic; signal xu_bx_ex1_mfdp_val : std_ulogic; signal xu_bx_ex1_ipc_thrd : std_ulogic_vector(0 to 1); signal xu_bx_ex2_ipc_ba : std_ulogic_vector(0 to 4); signal xu_bx_ex2_ipc_sz : std_ulogic_vector(0 to 1); -signal xu_bx_ex4_256st_data : std_ulogic_vector(128 to 255); +signal xu_bx_ex4_256st_data : std_ulogic_vector(128 to 255); signal bx_xu_ex4_mtdp_cr_status : std_ulogic; signal bx_xu_ex4_mfdp_cr_status : std_ulogic; -signal bx_xu_ex5_dp_data : std_ulogic_vector(0 to 127); -signal bx_lsu_ob_pwr_tok : std_ulogic; -signal bx_lsu_ob_req_val : std_ulogic; -signal bx_lsu_ob_ditc_val : std_ulogic; -signal bx_lsu_ob_thrd : std_ulogic_vector(0 to 1); -signal bx_lsu_ob_qw : std_ulogic_vector(58 to 59); -signal bx_lsu_ob_dest : std_ulogic_vector(0 to 14); -signal bx_lsu_ob_data : std_ulogic_vector(0 to 127); -signal bx_lsu_ob_addr : std_ulogic_vector(64-xu_real_data_add to 57); -signal lsu_bx_cmd_avail : std_ulogic; -signal lsu_bx_cmd_sent : std_ulogic; -signal lsu_bx_cmd_stall : std_ulogic; +signal bx_xu_ex5_dp_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_pwr_tok : std_ulogic; +signal bx_lsu_ob_req_val : std_ulogic; +signal bx_lsu_ob_ditc_val : std_ulogic; +signal bx_lsu_ob_thrd : std_ulogic_vector(0 to 1); +signal bx_lsu_ob_qw : std_ulogic_vector(58 to 59); +signal bx_lsu_ob_dest : std_ulogic_vector(0 to 14); +signal bx_lsu_ob_data : std_ulogic_vector(0 to 127); +signal bx_lsu_ob_addr : std_ulogic_vector(64-xu_real_data_add to 57); +signal lsu_bx_cmd_avail : std_ulogic; +signal lsu_bx_cmd_sent : std_ulogic; +signal lsu_bx_cmd_stall : std_ulogic; signal lsu_reld_data_vld : std_ulogic; -signal bx_ib_empty_int : std_ulogic_vector(0 to 3); -signal ac_an_reld_ditc_pop_int : std_ulogic_vector(0 to 3); +signal bx_ib_empty_int : std_ulogic_vector(0 to 3); +signal ac_an_reld_ditc_pop_int : std_ulogic_vector(0 to 3); signal lsu_reld_core_tag : std_ulogic_vector(3 to 4); signal lsu_reld_ditc : std_ulogic; signal lsu_reld_ecc_err : std_ulogic; @@ -872,1838 +872,1838 @@ signal lsu_reld_qw : std_ulogic_vector(58 to 59); signal lsu_reld_data : std_ulogic_vector(0 to 127); signal lsu_req_st_pop : std_ulogic; signal lsu_req_st_pop_thrd : std_ulogic_vector(0 to 2); -signal pc_bx_func_sl_thold_3 : std_ulogic; -signal pc_bx_func_slp_sl_thold_3 : std_ulogic; -signal pc_bx_gptr_sl_thold_3 : std_ulogic; -signal pc_bx_time_sl_thold_3 : std_ulogic; -signal pc_bx_repr_sl_thold_3 : std_ulogic; -signal pc_bx_abst_sl_thold_3 : std_ulogic; -signal pc_bx_ary_nsl_thold_3 : std_ulogic; -signal pc_bx_ary_slp_nsl_thold_3 : std_ulogic; -signal pc_bx_sg_3 : std_ulogic; -signal rp_pc_rtim_sl_thold_6 : std_ulogic; -signal rp_pc_func_sl_thold_6 : std_ulogic; -signal rp_pc_func_nsl_thold_6 : std_ulogic; -signal rp_pc_ary_nsl_thold_6 : std_ulogic; -signal rp_pc_sg_6 : std_ulogic; -signal rp_pc_fce_6 : std_ulogic; -signal debug_start_tiedowns : std_ulogic_vector(0 to 87); -signal trigger_start_tiedowns : std_ulogic_vector(0 to 11); -signal bx_fu_debug_data : std_ulogic_vector(0 to 87); -signal bx_fu_trigger_data : std_ulogic_vector(0 to 11); -signal fu_pc_debug_data : std_ulogic_vector(0 to 87); -signal fu_pc_trigger_data : std_ulogic_vector(0 to 11); -signal pc_iu_debug_data : std_ulogic_vector(0 to 87); -signal pc_iu_trigger_data : std_ulogic_vector(0 to 11); -signal iu_xu_debug_data : std_ulogic_vector(0 to 87); -signal iu_xu_trigger_data : std_ulogic_vector(0 to 11); -signal xu_mm_debug_data : std_ulogic_vector(0 to 87); -signal xu_mm_trigger_data : std_ulogic_vector(0 to 11); -signal iu_pc_gptr_scan_out : std_ulogic; -signal pc_fu_gptr_scan_out : std_ulogic; -signal fu_bx_gptr_scan_out : std_ulogic; -signal bx_xu_gptr_scan_out : std_ulogic; -signal xu_mm_gptr_scan_out : std_ulogic; -signal iu_fu_time_scan_out : std_ulogic; -signal fu_bx_time_scan_out : std_ulogic; -signal bx_xu_time_scan_out : std_ulogic; -signal xu_mm_time_scan_out : std_ulogic; -signal iu_fu_repr_scan_out : std_ulogic; -signal fu_bx_repr_scan_out : std_ulogic; -signal bx_xu_repr_scan_out : std_ulogic; -signal xu_mm_repr_scan_out : std_ulogic; -signal mm_iu_ccfg_scan_out : std_ulogic; -signal iu_pc_ccfg_scan_out : std_ulogic; -signal xu_fu_ccfg_scan_out : std_ulogic; -signal iu_fu_bcfg_scan_out : std_ulogic; -signal mm_rp_bcfg_scan_out : std_ulogic; -signal rp_pc_bcfg_scan_out_q : std_ulogic; -signal mm_rp_dcfg_scan_out : std_ulogic; -signal rp_pc_dcfg_scan_out_q : std_ulogic; -signal iu_fu_dcfg_scan_out : std_ulogic; -signal pc_rp_abst_scan_out : std_ulogic; -signal rp_pc_func_scan_in_q : std_ulogic_vector(0 to 1); -signal pc_rp_func_scan_out : std_ulogic_vector(0 to 1); -signal rp_fu_abst_scan_in_q : std_ulogic; -signal fu_rp_abst_scan_out : std_ulogic; -signal fu_rp_ccfg_scan_out : std_ulogic; -signal fu_rp_bcfg_scan_out : std_ulogic; -signal fu_rp_dcfg_scan_out : std_ulogic; -signal rp_fu_func_scan_in_q : std_ulogic_vector(0 to 3); -signal fu_rp_func_scan_out : std_ulogic_vector(0 to 3); -signal rp_bx_abst_scan_in_q : std_ulogic; -signal bx_rp_abst_scan_out : std_ulogic; -signal rp_bx_func_scan_in_q : std_ulogic_vector(0 to 1); -signal rp_fu_bx_abst_scan_in : std_ulogic; -signal bx_fu_rp_abst_scan_out : std_ulogic; -signal rp_fu_bx_func_scan_in : std_ulogic_vector(0 to 1); -signal bx_fu_rp_func_scan_out : std_ulogic_vector(0 to 1); -signal bx_rp_func_scan_out : std_ulogic_vector(0 to 1); -signal pc_rp_bcfg_scan_out : std_ulogic; -signal pc_rp_ccfg_scan_out : std_ulogic; -signal pc_rp_dcfg_scan_out : std_ulogic; -signal iu_pc_abst_scan_out : std_ulogic; -signal rp_pc_scom_dch_q : std_ulogic; -signal rp_pc_scom_cch_q : std_ulogic; -signal rp_pc_checkstop_q : std_ulogic; -signal rp_pc_debug_stop_q : std_ulogic; -signal rp_pc_pm_thread_stop_q : std_ulogic_vector(0 to 3); -signal rp_pc_reset_1_complete_q : std_ulogic; -signal rp_pc_reset_2_complete_q : std_ulogic; -signal rp_pc_reset_3_complete_q : std_ulogic; -signal rp_pc_reset_wd_complete_q : std_ulogic; -signal rp_pc_abist_start_test_q : std_ulogic; -signal pc_rp_scom_dch : std_ulogic; -signal pc_rp_scom_cch : std_ulogic; -signal pc_rp_special_attn : std_ulogic_vector(0 to 3); -signal pc_rp_checkstop : std_ulogic_vector(0 to 2); -signal pc_rp_trace_error : std_ulogic; -signal pc_rp_local_checkstop : std_ulogic_vector(0 to 2); -signal pc_rp_recov_err : std_ulogic_vector(0 to 2); -signal pc_rp_event_bus : std_ulogic_vector(0 to 7); -signal pc_rp_fu_bypass_events : std_ulogic_vector(0 to 7); -signal pc_rp_iu_bypass_events : std_ulogic_vector(0 to 7); -signal pc_rp_mm_bypass_events : std_ulogic_vector(0 to 7); -signal pc_rp_lsu_bypass_events : std_ulogic_vector(0 to 7); -signal pc_rp_pm_thread_running : std_ulogic_vector(0 to 3); -signal pc_rp_power_managed : std_ulogic; -signal pc_rp_rvwinkle_mode : std_ulogic; -signal pc_fu_event_mux_ctrls : std_ulogic_vector(0 to 31); -signal pc_iu_event_mux_ctrls : std_ulogic_vector(0 to 47); -signal pc_xu_event_mux_ctrls : std_ulogic_vector(0 to 47); -signal pc_xu_lsu_event_mux_ctrls : std_ulogic_vector(0 to 47); -signal pc_fu_event_bus_enable : std_ulogic; -signal pc_iu_event_bus_enable : std_ulogic; -signal pc_xu_event_bus_enable : std_ulogic; -signal pc_rp_event_bus_enable : std_ulogic; -signal rp_mm_event_bus_enable_q : std_ulogic; -signal ac_an_debug_bus_int : std_ulogic_vector(0 to 87); -signal ac_rp_trace_to_perfcntr : std_ulogic_vector(0 to 7); -signal rp_pc_trace_to_perfcntr_q : std_ulogic_vector(0 to 7); +signal pc_bx_func_sl_thold_3 : std_ulogic; +signal pc_bx_func_slp_sl_thold_3 : std_ulogic; +signal pc_bx_gptr_sl_thold_3 : std_ulogic; +signal pc_bx_time_sl_thold_3 : std_ulogic; +signal pc_bx_repr_sl_thold_3 : std_ulogic; +signal pc_bx_abst_sl_thold_3 : std_ulogic; +signal pc_bx_ary_nsl_thold_3 : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3 : std_ulogic; +signal pc_bx_sg_3 : std_ulogic; +signal rp_pc_rtim_sl_thold_6 : std_ulogic; +signal rp_pc_func_sl_thold_6 : std_ulogic; +signal rp_pc_func_nsl_thold_6 : std_ulogic; +signal rp_pc_ary_nsl_thold_6 : std_ulogic; +signal rp_pc_sg_6 : std_ulogic; +signal rp_pc_fce_6 : std_ulogic; +signal debug_start_tiedowns : std_ulogic_vector(0 to 87); +signal trigger_start_tiedowns : std_ulogic_vector(0 to 11); +signal bx_fu_debug_data : std_ulogic_vector(0 to 87); +signal bx_fu_trigger_data : std_ulogic_vector(0 to 11); +signal fu_pc_debug_data : std_ulogic_vector(0 to 87); +signal fu_pc_trigger_data : std_ulogic_vector(0 to 11); +signal pc_iu_debug_data : std_ulogic_vector(0 to 87); +signal pc_iu_trigger_data : std_ulogic_vector(0 to 11); +signal iu_xu_debug_data : std_ulogic_vector(0 to 87); +signal iu_xu_trigger_data : std_ulogic_vector(0 to 11); +signal xu_mm_debug_data : std_ulogic_vector(0 to 87); +signal xu_mm_trigger_data : std_ulogic_vector(0 to 11); +signal iu_pc_gptr_scan_out : std_ulogic; +signal pc_fu_gptr_scan_out : std_ulogic; +signal fu_bx_gptr_scan_out : std_ulogic; +signal bx_xu_gptr_scan_out : std_ulogic; +signal xu_mm_gptr_scan_out : std_ulogic; +signal iu_fu_time_scan_out : std_ulogic; +signal fu_bx_time_scan_out : std_ulogic; +signal bx_xu_time_scan_out : std_ulogic; +signal xu_mm_time_scan_out : std_ulogic; +signal iu_fu_repr_scan_out : std_ulogic; +signal fu_bx_repr_scan_out : std_ulogic; +signal bx_xu_repr_scan_out : std_ulogic; +signal xu_mm_repr_scan_out : std_ulogic; +signal mm_iu_ccfg_scan_out : std_ulogic; +signal iu_pc_ccfg_scan_out : std_ulogic; +signal xu_fu_ccfg_scan_out : std_ulogic; +signal iu_fu_bcfg_scan_out : std_ulogic; +signal mm_rp_bcfg_scan_out : std_ulogic; +signal rp_pc_bcfg_scan_out_q : std_ulogic; +signal mm_rp_dcfg_scan_out : std_ulogic; +signal rp_pc_dcfg_scan_out_q : std_ulogic; +signal iu_fu_dcfg_scan_out : std_ulogic; +signal pc_rp_abst_scan_out : std_ulogic; +signal rp_pc_func_scan_in_q : std_ulogic_vector(0 to 1); +signal pc_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal rp_fu_abst_scan_in_q : std_ulogic; +signal fu_rp_abst_scan_out : std_ulogic; +signal fu_rp_ccfg_scan_out : std_ulogic; +signal fu_rp_bcfg_scan_out : std_ulogic; +signal fu_rp_dcfg_scan_out : std_ulogic; +signal rp_fu_func_scan_in_q : std_ulogic_vector(0 to 3); +signal fu_rp_func_scan_out : std_ulogic_vector(0 to 3); +signal rp_bx_abst_scan_in_q : std_ulogic; +signal bx_rp_abst_scan_out : std_ulogic; +signal rp_bx_func_scan_in_q : std_ulogic_vector(0 to 1); +signal rp_fu_bx_abst_scan_in : std_ulogic; +signal bx_fu_rp_abst_scan_out : std_ulogic; +signal rp_fu_bx_func_scan_in : std_ulogic_vector(0 to 1); +signal bx_fu_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal bx_rp_func_scan_out : std_ulogic_vector(0 to 1); +signal pc_rp_bcfg_scan_out : std_ulogic; +signal pc_rp_ccfg_scan_out : std_ulogic; +signal pc_rp_dcfg_scan_out : std_ulogic; +signal iu_pc_abst_scan_out : std_ulogic; +signal rp_pc_scom_dch_q : std_ulogic; +signal rp_pc_scom_cch_q : std_ulogic; +signal rp_pc_checkstop_q : std_ulogic; +signal rp_pc_debug_stop_q : std_ulogic; +signal rp_pc_pm_thread_stop_q : std_ulogic_vector(0 to 3); +signal rp_pc_reset_1_complete_q : std_ulogic; +signal rp_pc_reset_2_complete_q : std_ulogic; +signal rp_pc_reset_3_complete_q : std_ulogic; +signal rp_pc_reset_wd_complete_q : std_ulogic; +signal rp_pc_abist_start_test_q : std_ulogic; +signal pc_rp_scom_dch : std_ulogic; +signal pc_rp_scom_cch : std_ulogic; +signal pc_rp_special_attn : std_ulogic_vector(0 to 3); +signal pc_rp_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_trace_error : std_ulogic; +signal pc_rp_local_checkstop : std_ulogic_vector(0 to 2); +signal pc_rp_recov_err : std_ulogic_vector(0 to 2); +signal pc_rp_event_bus : std_ulogic_vector(0 to 7); +signal pc_rp_fu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_iu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_mm_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_lsu_bypass_events : std_ulogic_vector(0 to 7); +signal pc_rp_pm_thread_running : std_ulogic_vector(0 to 3); +signal pc_rp_power_managed : std_ulogic; +signal pc_rp_rvwinkle_mode : std_ulogic; +signal pc_fu_event_mux_ctrls : std_ulogic_vector(0 to 31); +signal pc_iu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls : std_ulogic_vector(0 to 47); +signal pc_fu_event_bus_enable : std_ulogic; +signal pc_iu_event_bus_enable : std_ulogic; +signal pc_xu_event_bus_enable : std_ulogic; +signal pc_rp_event_bus_enable : std_ulogic; +signal rp_mm_event_bus_enable_q : std_ulogic; +signal ac_an_debug_bus_int : std_ulogic_vector(0 to 87); +signal ac_rp_trace_to_perfcntr : std_ulogic_vector(0 to 7); +signal rp_pc_trace_to_perfcntr_q : std_ulogic_vector(0 to 7); signal ac_an_power_managed_int : std_ulogic; -signal xu_iu_reld_core_tag : std_ulogic_vector(0 to 4); -signal xu_iu_reld_core_tag_clone : std_ulogic_vector(1 to 4); -signal xu_iu_reld_data : std_ulogic_vector(0 to 127); -signal xu_iu_reld_data_coming_clone : std_ulogic; -signal xu_iu_reld_data_vld : std_ulogic; -signal xu_iu_reld_data_vld_clone : std_ulogic; -signal xu_iu_reld_ecc_err : std_ulogic; -signal xu_iu_reld_ditc_clone : std_ulogic; -signal xu_iu_reld_ecc_err_ue : std_ulogic; -signal xu_iu_reld_qw : std_ulogic_vector(57 to 59); -signal xu_iu_stcx_complete : std_ulogic_vector(0 to 3); -signal xu_st_byte_enbl : std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); -signal xu_st_data : std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); -signal an_ac_bo_enable : std_ulogic; -signal an_ac_bo_go : std_ulogic; -signal an_ac_bo_cntlclk : std_ulogic; -signal an_ac_bo_ccflush : std_ulogic; -signal an_ac_bo_reset : std_ulogic; -signal an_ac_bo_data : std_ulogic; -signal an_ac_bo_shcntl : std_ulogic; -signal an_ac_bo_shdata : std_ulogic; -signal an_ac_bo_exe : std_ulogic; -signal an_ac_bo_sysrepair : std_ulogic; -signal an_ac_bo_donein : std_ulogic; -signal an_ac_bo_sdin : std_ulogic; -signal an_ac_bo_waitin : std_ulogic; -signal an_ac_bo_failin : std_ulogic; -signal an_ac_bo_fcshdata : std_ulogic; -signal an_ac_bo_fcreset : std_ulogic; -signal ac_an_bo_doneout : std_ulogic; -signal ac_an_bo_sdout : std_ulogic; -signal ac_an_bo_diagloopout : std_ulogic; -signal ac_an_bo_waitout : std_ulogic; -signal ac_an_bo_failout : std_ulogic; -signal pc_bx_bolt_sl_thold_3 : std_ulogic; -signal pc_fu_bolt_sl_thold_3 : std_ulogic; -signal pc_xu_bolt_sl_thold_3 : std_ulogic; -signal pc_bx_bo_enable_3 : std_ulogic; -signal pc_bx_bo_unload : std_ulogic; -signal pc_bx_bo_repair : std_ulogic; -signal pc_bx_bo_reset : std_ulogic; -signal pc_bx_bo_shdata : std_ulogic; -signal pc_bx_bo_select : std_ulogic_vector(0 to 3); -signal bx_pc_bo_fail : std_ulogic_vector(0 to 3); -signal bx_pc_bo_diagout : std_ulogic_vector(0 to 3); -signal pc_fu_bo_enable_3 : std_ulogic; -signal pc_fu_bo_unload : std_ulogic; -signal pc_fu_bo_load : std_ulogic; -signal pc_fu_bo_reset : std_ulogic; -signal pc_fu_bo_shdata : std_ulogic; -signal pc_fu_bo_select : std_ulogic_vector(0 to 1); -signal fu_pc_bo_fail : std_ulogic_vector(0 to 1); -signal fu_pc_bo_diagout : std_ulogic_vector(0 to 1); -signal pc_iu_bo_enable_4 : std_ulogic; -signal pc_iu_bo_unload : std_ulogic; -signal pc_iu_bo_repair : std_ulogic; -signal pc_iu_bo_reset : std_ulogic; -signal pc_iu_bo_shdata : std_ulogic; -signal pc_iu_bo_select : std_ulogic_vector(0 to 4); -signal iu_pc_bo_fail : std_ulogic_vector(0 to 4); -signal iu_pc_bo_diagout : std_ulogic_vector(0 to 4); -signal pc_xu_bo_enable_3 : std_ulogic; -signal pc_xu_bo_unload : std_ulogic; -signal pc_xu_bo_load : std_ulogic; -signal pc_xu_bo_repair : std_ulogic; -signal pc_xu_bo_reset : std_ulogic; -signal pc_xu_bo_shdata : std_ulogic; -signal pc_xu_bo_select : std_ulogic_vector(0 to 8); -signal xu_pc_bo_fail : std_ulogic_vector(0 to 8); -signal xu_pc_bo_diagout : std_ulogic_vector(0 to 8); - -signal an_ac_abist_mode_dc_oiu : std_ulogic; -signal an_ac_ccflush_dc_oiu : std_ulogic; -signal an_ac_gsd_test_enable_dc_oiu : std_ulogic; -signal an_ac_gsd_test_acmode_dc_oiu : std_ulogic; -signal an_ac_lbist_ip_dc_oiu : std_ulogic; -signal an_ac_lbist_ac_mode_dc_oiu : std_ulogic; -signal an_ac_malf_alert_oiu : std_ulogic; -signal an_ac_psro_enable_dc_oiu : std_ulogic_vector(0 to 2); -signal an_ac_scan_type_dc_oiu : std_ulogic_vector(0 to 8); -signal an_ac_scom_sat_id_oiu : std_ulogic_vector(0 to 3); -signal an_ac_back_inv_oiu : std_ulogic; -signal an_ac_back_inv_addr_oiu : std_ulogic_vector(64-xu_real_data_add to 63); -signal an_ac_back_inv_target_bit1_oiu : std_ulogic; -signal an_ac_back_inv_target_bit3_oiu : std_ulogic; -signal an_ac_back_inv_target_bit4_oiu : std_ulogic; -signal an_ac_atpg_en_dc_oiu : std_ulogic; -signal an_ac_lbist_ary_wrt_thru_dc_oiu : std_ulogic; -signal an_ac_lbist_en_dc_oiu : std_ulogic; -signal an_ac_scan_diag_dc_oiu : std_ulogic; -signal an_ac_scan_dis_dc_b_oiu : std_ulogic; -signal an_ac_back_inv_omm : std_ulogic; -signal an_ac_back_inv_addr_omm : std_ulogic_vector(64-real_addr_width to 63); -signal an_ac_back_inv_target_omm_iua : std_ulogic_vector(0 to 1); -signal an_ac_back_inv_target_omm_iub : std_ulogic_vector(3 to 4); -signal an_ac_reld_core_tag_omm : std_ulogic_vector(0 to 4); -signal an_ac_reld_data_omm : std_ulogic_vector(0 to 127); -signal an_ac_reld_data_vld_omm : std_ulogic; -signal an_ac_reld_ecc_err_omm : std_ulogic; -signal an_ac_reld_ecc_err_ue_omm : std_ulogic; -signal an_ac_reld_qw_omm : std_ulogic_vector(57 to 59); -signal an_ac_reld_ditc_omm : std_ulogic; -signal an_ac_reld_crit_qw_omm : std_ulogic; -signal an_ac_reld_data_coming_omm : std_ulogic; -signal an_ac_reld_l1_dump_omm : std_ulogic; -signal an_ac_camfence_en_dc_omm : std_ulogic; -signal an_ac_stcx_complete_omm : std_ulogic_vector(0 to 3); -signal an_ac_abist_mode_dc_omm : std_ulogic; -signal an_ac_abist_start_test_omm : std_ulogic; -signal an_ac_abst_scan_in_omm_iu : std_ulogic_vector(0 to 4); -signal an_ac_abst_scan_in_omm_xu : std_ulogic_vector(7 to 9); -signal an_ac_atpg_en_dc_omm : std_ulogic; -signal an_ac_bcfg_scan_in_omm_bit1 : std_ulogic; -signal an_ac_bcfg_scan_in_omm_bit3 : std_ulogic; -signal an_ac_bcfg_scan_in_omm_bit4 : std_ulogic; -signal an_ac_lbist_ary_wrt_thru_dc_omm : std_ulogic; -signal an_ac_ccflush_dc_omm : std_ulogic; -signal an_ac_reset_1_complete_omm : std_ulogic; -signal an_ac_reset_2_complete_omm : std_ulogic; -signal an_ac_reset_3_complete_omm : std_ulogic; -signal an_ac_reset_wd_complete_omm : std_ulogic; -signal an_ac_dcfg_scan_in_omm : std_ulogic_vector(1 to 2); -signal an_ac_debug_stop_omm : std_ulogic; -signal an_ac_func_scan_in_omm_iua : std_ulogic_vector(0 to 21); -signal an_ac_func_scan_in_omm_iub : std_ulogic_vector(60 to 63); -signal an_ac_func_scan_in_omm_xu : std_ulogic_vector(31 to 58); -signal an_ac_lbist_en_dc_omm : std_ulogic; -signal an_ac_pm_thread_stop_omm : std_ulogic_vector(0 to 3); -signal an_ac_regf_scan_in_omm : std_ulogic_vector(0 to 11); -signal an_ac_scan_diag_dc_omm : std_ulogic; -signal an_ac_scan_dis_dc_b_omm : std_ulogic; -signal an_ac_scom_cch_omm : std_ulogic; -signal an_ac_scom_dch_omm : std_ulogic; -signal an_ac_checkstop_omm : std_ulogic; -signal ac_an_abst_scan_out_imm_iu : std_ulogic_vector(0 to 4); -signal ac_an_abst_scan_out_imm_xu : std_ulogic_vector(7 to 9); -signal ac_an_bcfg_scan_out_imm : std_ulogic_vector(0 to 4); -signal ac_an_dcfg_scan_out_imm : std_ulogic_vector(0 to 2); -signal ac_an_func_scan_out_imm_iua : std_ulogic_vector(0 to 21); -signal ac_an_func_scan_out_imm_iub : std_ulogic_vector(60 to 63); -signal ac_an_func_scan_out_imm_xu : std_ulogic_vector(31 to 58); -signal ac_an_reld_ditc_pop_imm : std_ulogic_vector(0 to 3); -signal ac_an_power_managed_imm : std_ulogic; -signal ac_an_rvwinkle_mode_imm : std_ulogic; -signal ac_an_fu_bypass_events_imm : std_ulogic_vector(0 to 7); -signal ac_an_iu_bypass_events_imm : std_ulogic_vector(0 to 7); -signal ac_an_mm_bypass_events_imm : std_ulogic_vector(0 to 7); -signal ac_an_lsu_bypass_events_imm : std_ulogic_vector(0 to 7); -signal ac_an_event_bus_imm : std_ulogic_vector(0 to 7); -signal ac_an_pm_thread_running_imm : std_ulogic_vector(0 to 3); -signal ac_an_recov_err_imm : std_ulogic_vector(0 to 2); -signal ac_an_regf_scan_out_imm : std_ulogic_vector(0 to 11); -signal ac_an_scom_cch_imm : std_ulogic; -signal ac_an_scom_dch_imm : std_ulogic; -signal ac_an_special_attn_imm : std_ulogic_vector(0 to 3); -signal ac_an_checkstop_imm : std_ulogic_vector(0 to 2); -signal ac_an_local_checkstop_imm : std_ulogic_vector(0 to 2); -signal ac_an_trace_error_imm : std_ulogic; - -signal bx_pc_err_inbox_ue_ofu : std_ulogic; -signal bx_pc_err_outbox_ue_ofu : std_ulogic; -signal bx_pc_err_inbox_ecc_ofu : std_ulogic; -signal bx_pc_err_outbox_ecc_ofu : std_ulogic; -signal pc_bx_bolt_sl_thold_3_ofu : std_ulogic; -signal pc_bx_bo_enable_3_ofu : std_ulogic; -signal pc_bx_bo_unload_ofu : std_ulogic; -signal pc_bx_bo_repair_ofu : std_ulogic; -signal pc_bx_bo_reset_ofu : std_ulogic; -signal pc_bx_bo_shdata_ofu : std_ulogic; -signal pc_bx_bo_select_ofu : std_ulogic_vector(0 to 3); -signal bx_pc_bo_fail_ofu : std_ulogic_vector(0 to 3); -signal bx_pc_bo_diagout_ofu : std_ulogic_vector(0 to 3); -signal pc_bx_abist_di_0_ofu : std_ulogic_vector(0 to 3); -signal pc_bx_abist_ena_dc_ofu : std_ulogic; -signal pc_bx_abist_g8t1p_renb_0_ofu : std_ulogic; -signal pc_bx_abist_g8t_bw_0_ofu : std_ulogic; -signal pc_bx_abist_g8t_bw_1_ofu : std_ulogic; -signal pc_bx_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); -signal pc_bx_abist_g8t_wenb_ofu : std_ulogic; -signal pc_bx_abist_raddr_0_ofu : std_ulogic_vector(4 to 9); -signal pc_bx_abist_raw_dc_b_ofu : std_ulogic; -signal pc_bx_abist_waddr_0_ofu : std_ulogic_vector(4 to 9); -signal pc_bx_abist_wl64_comp_ena_ofu : std_ulogic; -signal pc_bx_trace_bus_enable_ofu : std_ulogic; -signal pc_bx_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); -signal pc_bx_inj_inbox_ecc_ofu : std_ulogic; -signal pc_bx_inj_outbox_ecc_ofu : std_ulogic; -signal pc_bx_ccflush_dc_ofu : std_ulogic; -signal pc_bx_sg_3_ofu : std_ulogic; -signal pc_bx_func_sl_thold_3_ofu : std_ulogic; -signal pc_bx_func_slp_sl_thold_3_ofu : std_ulogic; -signal pc_bx_gptr_sl_thold_3_ofu : std_ulogic; -signal pc_bx_time_sl_thold_3_ofu : std_ulogic; -signal pc_bx_repr_sl_thold_3_ofu : std_ulogic; -signal pc_bx_abst_sl_thold_3_ofu : std_ulogic; -signal pc_bx_ary_nsl_thold_3_ofu : std_ulogic; -signal pc_bx_ary_slp_nsl_thold_3_ofu : std_ulogic; - -signal xu_pc_err_mcsr_summary_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_ierat_parity_ofu : std_ulogic; -signal xu_pc_err_derat_parity_ofu : std_ulogic; -signal xu_pc_err_tlb_parity_ofu : std_ulogic; -signal xu_pc_err_tlb_lru_parity_ofu : std_ulogic; -signal xu_pc_err_ierat_multihit_ofu : std_ulogic; -signal xu_pc_err_derat_multihit_ofu : std_ulogic; -signal xu_pc_err_tlb_multihit_ofu : std_ulogic; -signal xu_pc_err_ext_mchk_ofu : std_ulogic; -signal xu_pc_err_ditc_overrun_ofu : std_ulogic; -signal xu_pc_err_local_snoop_reject_ofu : std_ulogic; -signal xu_pc_err_attention_instr_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_dcache_parity_ofu : std_ulogic; -signal xu_pc_err_dcachedir_parity_ofu : std_ulogic; -signal xu_pc_err_dcachedir_multihit_ofu : std_ulogic; -signal xu_pc_err_debug_event_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_invld_reld_ofu : std_ulogic; -signal xu_pc_err_l2intrf_ecc_ofu : std_ulogic; -signal xu_pc_err_l2intrf_ue_ofu : std_ulogic; -signal xu_pc_err_l2credit_overrun_ofu : std_ulogic; -signal xu_pc_err_llbust_attempt_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_llbust_failed_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_nia_miscmpr_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_regfile_parity_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_regfile_ue_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_sprg_ecc_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_sprg_ue_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_err_wdt_reset_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_event_data_ofu : std_ulogic_vector(0 to 7); -signal xu_pc_ram_data_ofu : std_ulogic_vector(64-(2**regmode) to 63); -signal xu_pc_ram_done_ofu : std_ulogic; -signal xu_pc_ram_interrupt_ofu : std_ulogic; -signal xu_pc_running_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_spr_ccr0_pme_ofu : std_ulogic_vector(0 to 1); -signal xu_pc_spr_ccr0_we_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_step_done_ofu : std_ulogic_vector(0 to 3); -signal xu_pc_stop_dbg_event_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_bolt_sl_thold_3_ofu : std_ulogic; -signal pc_xu_bo_enable_3_ofu : std_ulogic; -signal pc_xu_bo_unload_ofu : std_ulogic; -signal pc_xu_bo_load_ofu : std_ulogic; -signal pc_xu_bo_repair_ofu : std_ulogic; -signal pc_xu_bo_reset_ofu : std_ulogic; -signal pc_xu_bo_shdata_ofu : std_ulogic; -signal pc_xu_bo_select_ofu : std_ulogic_vector(0 to 8); -signal xu_pc_bo_fail_ofu : std_ulogic_vector(0 to 8); -signal xu_pc_bo_diagout_ofu : std_ulogic_vector(0 to 8); -signal pc_xu_abist_dcomp_g6t_2r_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_0_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_1_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_abist_di_g6t_2r_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_abist_ena_dc_ofu : std_ulogic; -signal pc_xu_abist_g6t_bw_ofu : std_ulogic_vector(0 to 1); -signal pc_xu_abist_g6t_r_wb_ofu : std_ulogic; -signal pc_xu_abist_g8t1p_renb_0_ofu : std_ulogic; -signal pc_xu_abist_g8t_bw_0_ofu : std_ulogic; -signal pc_xu_abist_g8t_bw_1_ofu : std_ulogic; -signal pc_xu_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_abist_g8t_wenb_ofu : std_ulogic; -signal pc_xu_abist_grf_renb_0_ofu : std_ulogic; -signal pc_xu_abist_grf_renb_1_ofu : std_ulogic; -signal pc_xu_abist_grf_wenb_0_ofu : std_ulogic; -signal pc_xu_abist_grf_wenb_1_ofu : std_ulogic; -signal pc_xu_abist_raddr_0_ofu : std_ulogic_vector(0 to 9); -signal pc_xu_abist_raddr_1_ofu : std_ulogic_vector(0 to 9); -signal pc_xu_abist_raw_dc_b_ofu : std_ulogic; -signal pc_xu_abist_waddr_0_ofu : std_ulogic_vector(0 to 9); -signal pc_xu_abist_waddr_1_ofu : std_ulogic_vector(0 to 9); -signal pc_xu_abist_wl144_comp_ena_ofu : std_ulogic; -signal pc_xu_abist_wl32_comp_ena_ofu : std_ulogic; -signal pc_xu_abist_wl512_comp_ena_ofu : std_ulogic; -signal pc_xu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); -signal pc_xu_lsu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); -signal pc_xu_event_bus_enable_ofu : std_ulogic; -signal pc_xu_abst_sl_thold_3_ofu : std_ulogic; -signal pc_xu_abst_slp_sl_thold_3_ofu : std_ulogic; -signal pc_xu_regf_sl_thold_3_ofu : std_ulogic; -signal pc_xu_regf_slp_sl_thold_3_ofu : std_ulogic; -signal pc_xu_ary_nsl_thold_3_ofu : std_ulogic; -signal pc_xu_ary_slp_nsl_thold_3_ofu : std_ulogic; -signal pc_xu_cache_par_err_event_ofu : std_ulogic; -signal pc_xu_ccflush_dc_ofu : std_ulogic; -signal pc_xu_cfg_sl_thold_3_ofu : std_ulogic; -signal pc_xu_cfg_slp_sl_thold_3_ofu : std_ulogic; -signal pc_xu_dbg_action_ofu : std_ulogic_vector(0 to 11); -signal pc_xu_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux2_ctrls_ofu : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux3_ctrls_ofu : std_ulogic_vector(0 to 15); -signal pc_xu_debug_mux4_ctrls_ofu : std_ulogic_vector(0 to 15); -signal pc_xu_decrem_dis_on_stop_ofu : std_ulogic; -signal pc_xu_event_count_mode_ofu : std_ulogic_vector(0 to 2); -signal pc_xu_extirpts_dis_on_stop_ofu : std_ulogic; -signal pc_xu_fce_3_ofu : std_ulogic_vector(0 to 1); -signal pc_xu_force_ude_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_func_nsl_thold_3_ofu : std_ulogic; -signal pc_xu_func_sl_thold_3_ofu : std_ulogic_vector(0 to 4); -signal pc_xu_func_slp_nsl_thold_3_ofu : std_ulogic; -signal pc_xu_func_slp_sl_thold_3_ofu : std_ulogic_vector(0 to 4); -signal pc_xu_gptr_sl_thold_3_ofu : std_ulogic; -signal pc_xu_init_reset_ofu : std_ulogic; -signal pc_xu_inj_dcache_parity_ofu : std_ulogic; -signal pc_xu_inj_dcachedir_parity_ofu : std_ulogic; -signal pc_xu_inj_llbust_attempt_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_inj_llbust_failed_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_inj_sprg_ecc_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_inj_regfile_parity_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_inj_wdt_reset_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_inj_dcachedir_multihit_ofu : std_ulogic; -signal pc_xu_instr_trace_mode_ofu : std_ulogic; -signal pc_xu_instr_trace_tid_ofu : std_ulogic_vector(0 to 1); -signal pc_xu_msrovride_enab_ofu : std_ulogic; -signal pc_xu_msrovride_gs_ofu : std_ulogic; -signal pc_xu_msrovride_pr_ofu : std_ulogic; -signal pc_xu_ram_execute_ofu : std_ulogic; -signal pc_xu_ram_flush_thread_ofu : std_ulogic; -signal pc_xu_ram_mode_ofu : std_ulogic; -signal pc_xu_ram_thread_ofu : std_ulogic_vector(0 to 1); -signal pc_xu_repr_sl_thold_3_ofu : std_ulogic; -signal pc_xu_reset_1_cmplt_ofu : std_ulogic; -signal pc_xu_reset_2_cmplt_ofu : std_ulogic; -signal pc_xu_reset_3_cmplt_ofu : std_ulogic; -signal pc_xu_reset_wd_cmplt_ofu : std_ulogic; -signal pc_xu_sg_3_ofu : std_ulogic_vector(0 to 4); -signal pc_xu_step_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_stop_ofu : std_ulogic_vector(0 to 3); -signal pc_xu_time_sl_thold_3_ofu : std_ulogic; -signal pc_xu_timebase_dis_on_stop_ofu : std_ulogic; -signal pc_xu_trace_bus_enable_ofu : std_ulogic; - -signal an_ac_crit_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_ext_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_flh2l2_gate_omm : std_ulogic; -signal an_ac_icbi_ack_omm : std_ulogic; -signal an_ac_icbi_ack_thread_omm : std_ulogic_vector(0 to 1); -signal an_ac_req_ld_pop_omm : std_ulogic; -signal an_ac_req_spare_ctrl_a1_omm : std_ulogic_vector(0 to 3); -signal an_ac_req_st_gather_omm : std_ulogic; -signal an_ac_req_st_pop_omm : std_ulogic; -signal an_ac_req_st_pop_thrd_omm : std_ulogic_vector(0 to 2); -signal an_ac_reservation_vld_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_sleep_en_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_stcx_pass_omm : std_ulogic_vector(0 to 3); -signal an_ac_sync_ack_omm : std_ulogic_vector(0 to 3); -signal an_ac_ary_nsl_thold_7_omm : std_ulogic; -signal an_ac_coreid_omm : std_ulogic_vector(0 to 7); -signal an_ac_external_mchk_omm : std_ulogic_vector(0 to 3); -signal an_ac_fce_7_omm : std_ulogic; -signal an_ac_func_nsl_thold_7_omm : std_ulogic; -signal an_ac_func_sl_thold_7_omm : std_ulogic; -signal an_ac_gsd_test_enable_dc_omm : std_ulogic; -signal an_ac_gsd_test_acmode_dc_omm : std_ulogic; -signal an_ac_gptr_scan_in_omm : std_ulogic; -signal an_ac_hang_pulse_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_lbist_ac_mode_dc_omm : std_ulogic; -signal an_ac_lbist_ip_dc_omm : std_ulogic; -signal an_ac_malf_alert_omm : std_ulogic; -signal an_ac_perf_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); -signal an_ac_psro_enable_dc_omm : std_ulogic_vector(0 to 2); -signal an_ac_repr_scan_in_omm : std_ulogic; -signal an_ac_rtim_sl_thold_7_omm : std_ulogic; -signal an_ac_scan_type_dc_omm : std_ulogic_vector(0 to 8); -signal an_ac_scom_sat_id_omm : std_ulogic_vector(0 to 3); -signal an_ac_sg_7_omm : std_ulogic; -signal an_ac_tb_update_enable_omm : std_ulogic; -signal an_ac_tb_update_pulse_omm : std_ulogic; -signal an_ac_time_scan_in_omm : std_ulogic; - -signal ac_an_box_empty_imm : std_ulogic_vector(0 to 3); -signal ac_an_machine_check_imm : std_ulogic_vector(0 to thdid_width-1); -signal ac_an_req_imm : std_ulogic; -signal ac_an_req_endian_imm : std_ulogic; -signal ac_an_req_ld_core_tag_imm : std_ulogic_vector(0 to 4); -signal ac_an_req_ld_xfr_len_imm : std_ulogic_vector(0 to 2); -signal ac_an_req_pwr_token_imm : std_ulogic; -signal ac_an_req_ra_imm : std_ulogic_vector(64-real_addr_width to 63); -signal ac_an_req_spare_ctrl_a0_imm : std_ulogic_vector(0 to 3); -signal ac_an_req_thread_imm : std_ulogic_vector(0 to 2); -signal ac_an_req_ttype_imm : std_ulogic_vector(0 to 5); -signal ac_an_req_user_defined_imm : std_ulogic_vector(0 to 3); -signal ac_an_req_wimg_g_imm : std_ulogic; -signal ac_an_req_wimg_i_imm : std_ulogic; -signal ac_an_req_wimg_m_imm : std_ulogic; -signal ac_an_req_wimg_w_imm : std_ulogic; -signal ac_an_st_byte_enbl_imm : std_ulogic_vector(0 to 31); -signal ac_an_st_byte_enbl_omm : std_ulogic_vector(16 to 31); -signal ac_an_st_data_imm : std_ulogic_vector(0 to 255); -signal ac_an_st_data_omm : std_ulogic_vector(128 to 255); -signal ac_an_st_data_pwr_token_imm : std_ulogic; -signal ac_an_debug_trigger_imm : std_ulogic_vector(0 to thdid_width-1); -signal ac_an_reset_1_request_imm : std_ulogic; -signal ac_an_reset_2_request_imm : std_ulogic; -signal ac_an_reset_3_request_imm : std_ulogic; -signal ac_an_reset_wd_request_imm : std_ulogic; -signal an_ac_scan_diag_dc_opc : std_ulogic; -signal an_ac_scan_dis_dc_b_opc : std_ulogic; -signal an_ac_scan_dis_dc_b_ofu : std_ulogic; -signal an_ac_scan_diag_dc_ofu : std_ulogic; - -signal ac_an_abist_done_dc_iiu : std_ulogic; -signal ac_an_psro_ringsig_iiu : std_ulogic; -signal an_ac_ccenable_dc_iiu : std_ulogic; -signal mm_pc_bo_fail_iiu : std_ulogic_vector(0 to 4); -signal mm_pc_bo_diagout_iiu : std_ulogic_vector(0 to 4); -signal mm_pc_event_data_iiu : std_ulogic_vector(0 to 7); - -signal ac_an_abist_done_dc_oiu : std_ulogic; -signal ac_an_psro_ringsig_oiu : std_ulogic; -signal an_ac_ccenable_dc_oiu : std_ulogic; -signal mm_pc_bo_fail_oiu : std_ulogic_vector(0 to 4); -signal mm_pc_bo_diagout_oiu : std_ulogic_vector(0 to 4); -signal mm_pc_event_data_oiu : std_ulogic_vector(0 to 7); - -signal pc_mm_abist_dcomp_g6t_2r_iiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_di_g6t_2r_iiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_di_0_iiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_ena_dc_iiu : std_ulogic; -signal pc_mm_abist_g6t_r_wb_iiu : std_ulogic; -signal pc_mm_abist_g8t_bw_0_iiu : std_ulogic; -signal pc_mm_abist_g8t_bw_1_iiu : std_ulogic; -signal pc_mm_abist_g8t_dcomp_iiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_g8t_wenb_iiu : std_ulogic; -signal pc_mm_abist_g8t1p_renb_0_iiu : std_ulogic; -signal pc_mm_abist_raddr_0_iiu : std_ulogic_vector(0 to 9); -signal pc_mm_abist_raw_dc_b_iiu : std_ulogic; -signal pc_mm_abist_waddr_0_iiu : std_ulogic_vector(0 to 9); -signal pc_mm_abist_wl128_comp_ena_iiu : std_ulogic; -signal pc_mm_bo_enable_4_iiu : std_ulogic; -signal pc_mm_bo_repair_iiu : std_ulogic; -signal pc_mm_bo_reset_iiu : std_ulogic; -signal pc_mm_bo_select_iiu : std_ulogic_vector(0 to 4); -signal pc_mm_bo_shdata_iiu : std_ulogic; -signal pc_mm_bo_unload_iiu : std_ulogic; -signal pc_mm_ccflush_dc_iiu : std_ulogic; -signal pc_mm_debug_mux1_ctrls_iiu : std_ulogic_vector(0 to 15); -signal pc_mm_event_count_mode_iiu : std_ulogic_vector(0 to 2); -signal pc_mm_event_mux_ctrls_iiu : std_ulogic_vector(0 to 39); -signal pc_mm_trace_bus_enable_iiu : std_ulogic; -signal pc_mm_abist_dcomp_g6t_2r_oiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_di_g6t_2r_oiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_di_0_oiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_ena_dc_oiu : std_ulogic; -signal pc_mm_abist_g6t_r_wb_oiu : std_ulogic; -signal pc_mm_abist_g8t_bw_0_oiu : std_ulogic; -signal pc_mm_abist_g8t_bw_1_oiu : std_ulogic; -signal pc_mm_abist_g8t_dcomp_oiu : std_ulogic_vector(0 to 3); -signal pc_mm_abist_g8t_wenb_oiu : std_ulogic; -signal pc_mm_abist_g8t1p_renb_0_oiu : std_ulogic; -signal pc_mm_abist_raddr_0_oiu : std_ulogic_vector(0 to 9); -signal pc_mm_abist_raw_dc_b_oiu : std_ulogic; -signal pc_mm_abist_waddr_0_oiu : std_ulogic_vector(0 to 9); -signal pc_mm_abist_wl128_comp_ena_oiu : std_ulogic; -signal pc_mm_abst_sl_thold_3_oiu : std_ulogic; -signal pc_mm_abst_slp_sl_thold_3_oiu : std_ulogic; -signal pc_mm_ary_nsl_thold_3_oiu : std_ulogic; -signal pc_mm_ary_slp_nsl_thold_3_oiu : std_ulogic; -signal pc_mm_bo_enable_3_oiu : std_ulogic; -signal pc_mm_bo_repair_oiu : std_ulogic; -signal pc_mm_bo_reset_oiu : std_ulogic; -signal pc_mm_bo_select_oiu : std_ulogic_vector(0 to 4); -signal pc_mm_bo_shdata_oiu : std_ulogic; -signal pc_mm_bo_unload_oiu : std_ulogic; -signal pc_mm_bolt_sl_thold_3_oiu : std_ulogic; -signal pc_mm_ccflush_dc_oiu : std_ulogic; -signal pc_mm_cfg_sl_thold_3_oiu : std_ulogic; -signal pc_mm_cfg_slp_sl_thold_3_oiu : std_ulogic; -signal pc_mm_debug_mux1_ctrls_oiu : std_ulogic_vector(0 to 15); -signal pc_mm_event_count_mode_oiu : std_ulogic_vector(0 to 2); -signal pc_mm_event_mux_ctrls_oiu : std_ulogic_vector(0 to 39); -signal pc_mm_fce_3_oiu : std_ulogic; -signal pc_mm_func_nsl_thold_3_oiu : std_ulogic; -signal pc_mm_func_sl_thold_3_oiu : std_ulogic_vector(0 to 1); -signal pc_mm_func_slp_nsl_thold_3_oiu : std_ulogic; -signal pc_mm_func_slp_sl_thold_3_oiu : std_ulogic_vector(0 to 1); -signal pc_mm_gptr_sl_thold_3_oiu : std_ulogic; -signal pc_mm_repr_sl_thold_3_oiu : std_ulogic; -signal pc_mm_sg_3_oiu : std_ulogic_vector(0 to 1); -signal pc_mm_time_sl_thold_3_oiu : std_ulogic; -signal pc_mm_trace_bus_enable_oiu : std_ulogic; -signal xu_ex2_flush_ofu : std_ulogic_vector(0 to 3); -signal xu_ex3_flush_ofu : std_ulogic_vector(0 to 3); -signal xu_ex4_flush_ofu : std_ulogic_vector(0 to 3); -signal xu_ex5_flush_ofu : std_ulogic_vector(0 to 3); -signal an_ac_lbist_ary_wrt_thru_dc_ofu : std_ulogic; -signal xu_pc_lsu_event_data_ofu : std_ulogic_vector(0 to 7); -signal xu_pc_err_mchk_disabled : std_ulogic; -signal xu_pc_err_mchk_disabled_ofu : std_ulogic; -signal xu_iu_l_flush : std_ulogic_vector(0 to 3); -signal xu_iu_u_flush : std_ulogic_vector(0 to 3); -signal debug_bus_out_int : std_ulogic_vector(0 to 7); -signal an_ac_grffence_en_dc_oiu : std_ulogic; -signal xu_fu_lbist_ary_wrt_thru_dc : std_ulogic; -signal pc_xu_msrovride_de : std_ulogic; - -signal bg_an_ac_func_scan_sn : std_ulogic_vector(60 to 69); -signal bg_an_ac_abst_scan_sn : std_ulogic_vector(10 to 11); -signal bg_an_ac_func_scan_sn_q : std_ulogic_vector(60 to 69); -signal bg_an_ac_abst_scan_sn_q : std_ulogic_vector(10 to 11); - -signal bg_ac_an_func_scan_ns : std_ulogic_vector(60 to 69); -signal bg_ac_an_abst_scan_ns : std_ulogic_vector(10 to 11); -signal bg_ac_an_func_scan_ns_q : std_ulogic_vector(60 to 69); -signal bg_ac_an_abst_scan_ns_q : std_ulogic_vector(10 to 11); - -signal bg_pc_l1p_abist_di_0 : std_ulogic_vector(0 to 3); -signal bg_pc_l1p_abist_g8t1p_renb_0 : std_ulogic; -signal bg_pc_l1p_abist_g8t_bw_0 : std_ulogic; -signal bg_pc_l1p_abist_g8t_bw_1 : std_ulogic; -signal bg_pc_l1p_abist_g8t_dcomp : std_ulogic_vector(0 to 3); -signal bg_pc_l1p_abist_g8t_wenb : std_ulogic; -signal bg_pc_l1p_abist_raddr_0 : std_ulogic_vector(0 to 9); -signal bg_pc_l1p_abist_waddr_0 : std_ulogic_vector(0 to 9); -signal bg_pc_l1p_abist_wl128_comp_ena : std_ulogic; -signal bg_pc_l1p_abist_wl32_comp_ena : std_ulogic; -signal bg_pc_l1p_abist_di_0_q : std_ulogic_vector(0 to 3); -signal bg_pc_l1p_abist_g8t1p_renb_0_q : std_ulogic; -signal bg_pc_l1p_abist_g8t_bw_0_q : std_ulogic; -signal bg_pc_l1p_abist_g8t_bw_1_q : std_ulogic; -signal bg_pc_l1p_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); -signal bg_pc_l1p_abist_g8t_wenb_q : std_ulogic; -signal bg_pc_l1p_abist_raddr_0_q : std_ulogic_vector(0 to 9); -signal bg_pc_l1p_abist_waddr_0_q : std_ulogic_vector(0 to 9); -signal bg_pc_l1p_abist_wl128_comp_ena_q : std_ulogic; -signal bg_pc_l1p_abist_wl32_comp_ena_q : std_ulogic; - -signal bg_pc_l1p_gptr_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_time_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_repr_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_abst_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_func_sl_thold_3 : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_func_slp_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_bolt_sl_thold_3 : std_ulogic; -signal bg_pc_l1p_ary_nsl_thold_3 : std_ulogic; -signal bg_pc_l1p_sg_3 : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_fce_3 : std_ulogic; -signal bg_pc_l1p_bo_enable_3 : std_ulogic; -signal bg_pc_l1p_gptr_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_time_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_repr_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_abst_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_func_sl_thold_2 : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_func_slp_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_bolt_sl_thold_2 : std_ulogic; -signal bg_pc_l1p_ary_nsl_thold_2 : std_ulogic; -signal bg_pc_l1p_sg_2 : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_fce_2 : std_ulogic; -signal bg_pc_l1p_bo_enable_2 : std_ulogic; - -signal bg_pc_bo_unload_iiu : std_ulogic; -signal bg_pc_bo_load_iiu : std_ulogic; -signal bg_pc_bo_repair_iiu : std_ulogic; -signal bg_pc_bo_reset_iiu : std_ulogic; -signal bg_pc_bo_shdata_iiu : std_ulogic; -signal bg_pc_bo_select_iiu : std_ulogic_vector(0 to 10); -signal bg_pc_l1p_ccflush_dc_iiu : std_ulogic; -signal bg_pc_l1p_abist_ena_dc_iiu : std_ulogic; -signal bg_pc_l1p_abist_raw_dc_b_iiu : std_ulogic; - -signal bg_pc_bo_unload_oiu : std_ulogic; -signal bg_pc_bo_load_oiu : std_ulogic; -signal bg_pc_bo_repair_oiu : std_ulogic; -signal bg_pc_bo_reset_oiu : std_ulogic; -signal bg_pc_bo_shdata_oiu : std_ulogic; -signal bg_pc_bo_select_oiu : std_ulogic_vector(0 to 10); -signal bg_pc_l1p_ccflush_dc_oiu : std_ulogic; -signal bg_pc_l1p_abist_ena_dc_oiu : std_ulogic; -signal bg_pc_l1p_abist_raw_dc_b_oiu : std_ulogic; - -signal bg_pc_bo_fail_oiu : std_ulogic_vector(0 to 10); -signal bg_pc_bo_diagout_oiu : std_ulogic_vector(0 to 10); - -signal bg_pc_l1p_gptr_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_time_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_repr_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_abst_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_func_sl_thold_2_imm : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_func_slp_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_bolt_sl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_ary_nsl_thold_2_imm : std_ulogic; -signal bg_pc_l1p_sg_2_imm : std_ulogic_vector(0 to 1); -signal bg_pc_l1p_fce_2_imm : std_ulogic; -signal bg_pc_l1p_bo_enable_2_imm : std_ulogic; -signal bg_pc_bo_unload : std_ulogic; -signal bg_pc_bo_load : std_ulogic; -signal bg_pc_bo_repair : std_ulogic; -signal bg_pc_bo_reset : std_ulogic; -signal bg_pc_bo_shdata : std_ulogic; -signal bg_pc_bo_select : std_ulogic_vector(0 to 10); -signal bg_pc_l1p_ccflush_dc : std_ulogic; -signal bg_pc_l1p_abist_ena_dc : std_ulogic; -signal bg_pc_l1p_abist_raw_dc_b : std_ulogic; -signal bg_an_ac_func_scan_sn_omm : std_ulogic_vector(60 to 69); -signal bg_an_ac_abst_scan_sn_omm : std_ulogic_vector(10 to 11); -signal bg_pc_bo_fail : std_ulogic_vector(0 to 10); -signal bg_pc_bo_diagout : std_ulogic_vector(0 to 10); -signal bg_pc_bo_fail_omm : std_ulogic_vector(0 to 10); -signal bg_pc_bo_diagout_omm : std_ulogic_vector(0 to 10); - -signal xu_fu_lbist_en_dc : std_ulogic; -signal xu_iu_xucr4_mmu_mchk : std_ulogic; -signal xu_mm_xucr4_mmu_mchk : std_ulogic; - --- synopsys translate_off - - - - - - - - - --- synopsys translate_on - - -BEGIN - - -debug_start_tiedowns <= (0 to 87 => '0'); -trigger_start_tiedowns <= (0 to 11 => '0'); - +signal xu_iu_reld_core_tag : std_ulogic_vector(0 to 4); +signal xu_iu_reld_core_tag_clone : std_ulogic_vector(1 to 4); +signal xu_iu_reld_data : std_ulogic_vector(0 to 127); +signal xu_iu_reld_data_coming_clone : std_ulogic; +signal xu_iu_reld_data_vld : std_ulogic; +signal xu_iu_reld_data_vld_clone : std_ulogic; +signal xu_iu_reld_ecc_err : std_ulogic; +signal xu_iu_reld_ditc_clone : std_ulogic; +signal xu_iu_reld_ecc_err_ue : std_ulogic; +signal xu_iu_reld_qw : std_ulogic_vector(57 to 59); +signal xu_iu_stcx_complete : std_ulogic_vector(0 to 3); +signal xu_st_byte_enbl : std_ulogic_vector(0 to 15+(st_data_32b_mode*16)); +signal xu_st_data : std_ulogic_vector(0 to 127+(st_data_32b_mode*128)); +signal an_ac_bo_enable : std_ulogic; +signal an_ac_bo_go : std_ulogic; +signal an_ac_bo_cntlclk : std_ulogic; +signal an_ac_bo_ccflush : std_ulogic; +signal an_ac_bo_reset : std_ulogic; +signal an_ac_bo_data : std_ulogic; +signal an_ac_bo_shcntl : std_ulogic; +signal an_ac_bo_shdata : std_ulogic; +signal an_ac_bo_exe : std_ulogic; +signal an_ac_bo_sysrepair : std_ulogic; +signal an_ac_bo_donein : std_ulogic; +signal an_ac_bo_sdin : std_ulogic; +signal an_ac_bo_waitin : std_ulogic; +signal an_ac_bo_failin : std_ulogic; +signal an_ac_bo_fcshdata : std_ulogic; +signal an_ac_bo_fcreset : std_ulogic; +signal ac_an_bo_doneout : std_ulogic; +signal ac_an_bo_sdout : std_ulogic; +signal ac_an_bo_diagloopout : std_ulogic; +signal ac_an_bo_waitout : std_ulogic; +signal ac_an_bo_failout : std_ulogic; +signal pc_bx_bolt_sl_thold_3 : std_ulogic; +signal pc_fu_bolt_sl_thold_3 : std_ulogic; +signal pc_xu_bolt_sl_thold_3 : std_ulogic; +signal pc_bx_bo_enable_3 : std_ulogic; +signal pc_bx_bo_unload : std_ulogic; +signal pc_bx_bo_repair : std_ulogic; +signal pc_bx_bo_reset : std_ulogic; +signal pc_bx_bo_shdata : std_ulogic; +signal pc_bx_bo_select : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout : std_ulogic_vector(0 to 3); +signal pc_fu_bo_enable_3 : std_ulogic; +signal pc_fu_bo_unload : std_ulogic; +signal pc_fu_bo_load : std_ulogic; +signal pc_fu_bo_reset : std_ulogic; +signal pc_fu_bo_shdata : std_ulogic; +signal pc_fu_bo_select : std_ulogic_vector(0 to 1); +signal fu_pc_bo_fail : std_ulogic_vector(0 to 1); +signal fu_pc_bo_diagout : std_ulogic_vector(0 to 1); +signal pc_iu_bo_enable_4 : std_ulogic; +signal pc_iu_bo_unload : std_ulogic; +signal pc_iu_bo_repair : std_ulogic; +signal pc_iu_bo_reset : std_ulogic; +signal pc_iu_bo_shdata : std_ulogic; +signal pc_iu_bo_select : std_ulogic_vector(0 to 4); +signal iu_pc_bo_fail : std_ulogic_vector(0 to 4); +signal iu_pc_bo_diagout : std_ulogic_vector(0 to 4); +signal pc_xu_bo_enable_3 : std_ulogic; +signal pc_xu_bo_unload : std_ulogic; +signal pc_xu_bo_load : std_ulogic; +signal pc_xu_bo_repair : std_ulogic; +signal pc_xu_bo_reset : std_ulogic; +signal pc_xu_bo_shdata : std_ulogic; +signal pc_xu_bo_select : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout : std_ulogic_vector(0 to 8); + +signal an_ac_abist_mode_dc_oiu : std_ulogic; +signal an_ac_ccflush_dc_oiu : std_ulogic; +signal an_ac_gsd_test_enable_dc_oiu : std_ulogic; +signal an_ac_gsd_test_acmode_dc_oiu : std_ulogic; +signal an_ac_lbist_ip_dc_oiu : std_ulogic; +signal an_ac_lbist_ac_mode_dc_oiu : std_ulogic; +signal an_ac_malf_alert_oiu : std_ulogic; +signal an_ac_psro_enable_dc_oiu : std_ulogic_vector(0 to 2); +signal an_ac_scan_type_dc_oiu : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_oiu : std_ulogic_vector(0 to 3); +signal an_ac_back_inv_oiu : std_ulogic; +signal an_ac_back_inv_addr_oiu : std_ulogic_vector(64-xu_real_data_add to 63); +signal an_ac_back_inv_target_bit1_oiu : std_ulogic; +signal an_ac_back_inv_target_bit3_oiu : std_ulogic; +signal an_ac_back_inv_target_bit4_oiu : std_ulogic; +signal an_ac_atpg_en_dc_oiu : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_oiu : std_ulogic; +signal an_ac_lbist_en_dc_oiu : std_ulogic; +signal an_ac_scan_diag_dc_oiu : std_ulogic; +signal an_ac_scan_dis_dc_b_oiu : std_ulogic; +signal an_ac_back_inv_omm : std_ulogic; +signal an_ac_back_inv_addr_omm : std_ulogic_vector(64-real_addr_width to 63); +signal an_ac_back_inv_target_omm_iua : std_ulogic_vector(0 to 1); +signal an_ac_back_inv_target_omm_iub : std_ulogic_vector(3 to 4); +signal an_ac_reld_core_tag_omm : std_ulogic_vector(0 to 4); +signal an_ac_reld_data_omm : std_ulogic_vector(0 to 127); +signal an_ac_reld_data_vld_omm : std_ulogic; +signal an_ac_reld_ecc_err_omm : std_ulogic; +signal an_ac_reld_ecc_err_ue_omm : std_ulogic; +signal an_ac_reld_qw_omm : std_ulogic_vector(57 to 59); +signal an_ac_reld_ditc_omm : std_ulogic; +signal an_ac_reld_crit_qw_omm : std_ulogic; +signal an_ac_reld_data_coming_omm : std_ulogic; +signal an_ac_reld_l1_dump_omm : std_ulogic; +signal an_ac_camfence_en_dc_omm : std_ulogic; +signal an_ac_stcx_complete_omm : std_ulogic_vector(0 to 3); +signal an_ac_abist_mode_dc_omm : std_ulogic; +signal an_ac_abist_start_test_omm : std_ulogic; +signal an_ac_abst_scan_in_omm_iu : std_ulogic_vector(0 to 4); +signal an_ac_abst_scan_in_omm_xu : std_ulogic_vector(7 to 9); +signal an_ac_atpg_en_dc_omm : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit1 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit3 : std_ulogic; +signal an_ac_bcfg_scan_in_omm_bit4 : std_ulogic; +signal an_ac_lbist_ary_wrt_thru_dc_omm : std_ulogic; +signal an_ac_ccflush_dc_omm : std_ulogic; +signal an_ac_reset_1_complete_omm : std_ulogic; +signal an_ac_reset_2_complete_omm : std_ulogic; +signal an_ac_reset_3_complete_omm : std_ulogic; +signal an_ac_reset_wd_complete_omm : std_ulogic; +signal an_ac_dcfg_scan_in_omm : std_ulogic_vector(1 to 2); +signal an_ac_debug_stop_omm : std_ulogic; +signal an_ac_func_scan_in_omm_iua : std_ulogic_vector(0 to 21); +signal an_ac_func_scan_in_omm_iub : std_ulogic_vector(60 to 63); +signal an_ac_func_scan_in_omm_xu : std_ulogic_vector(31 to 58); +signal an_ac_lbist_en_dc_omm : std_ulogic; +signal an_ac_pm_thread_stop_omm : std_ulogic_vector(0 to 3); +signal an_ac_regf_scan_in_omm : std_ulogic_vector(0 to 11); +signal an_ac_scan_diag_dc_omm : std_ulogic; +signal an_ac_scan_dis_dc_b_omm : std_ulogic; +signal an_ac_scom_cch_omm : std_ulogic; +signal an_ac_scom_dch_omm : std_ulogic; +signal an_ac_checkstop_omm : std_ulogic; +signal ac_an_abst_scan_out_imm_iu : std_ulogic_vector(0 to 4); +signal ac_an_abst_scan_out_imm_xu : std_ulogic_vector(7 to 9); +signal ac_an_bcfg_scan_out_imm : std_ulogic_vector(0 to 4); +signal ac_an_dcfg_scan_out_imm : std_ulogic_vector(0 to 2); +signal ac_an_func_scan_out_imm_iua : std_ulogic_vector(0 to 21); +signal ac_an_func_scan_out_imm_iub : std_ulogic_vector(60 to 63); +signal ac_an_func_scan_out_imm_xu : std_ulogic_vector(31 to 58); +signal ac_an_reld_ditc_pop_imm : std_ulogic_vector(0 to 3); +signal ac_an_power_managed_imm : std_ulogic; +signal ac_an_rvwinkle_mode_imm : std_ulogic; +signal ac_an_fu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_iu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_mm_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_lsu_bypass_events_imm : std_ulogic_vector(0 to 7); +signal ac_an_event_bus_imm : std_ulogic_vector(0 to 7); +signal ac_an_pm_thread_running_imm : std_ulogic_vector(0 to 3); +signal ac_an_recov_err_imm : std_ulogic_vector(0 to 2); +signal ac_an_regf_scan_out_imm : std_ulogic_vector(0 to 11); +signal ac_an_scom_cch_imm : std_ulogic; +signal ac_an_scom_dch_imm : std_ulogic; +signal ac_an_special_attn_imm : std_ulogic_vector(0 to 3); +signal ac_an_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_local_checkstop_imm : std_ulogic_vector(0 to 2); +signal ac_an_trace_error_imm : std_ulogic; + +signal bx_pc_err_inbox_ue_ofu : std_ulogic; +signal bx_pc_err_outbox_ue_ofu : std_ulogic; +signal bx_pc_err_inbox_ecc_ofu : std_ulogic; +signal bx_pc_err_outbox_ecc_ofu : std_ulogic; +signal pc_bx_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_bx_bo_enable_3_ofu : std_ulogic; +signal pc_bx_bo_unload_ofu : std_ulogic; +signal pc_bx_bo_repair_ofu : std_ulogic; +signal pc_bx_bo_reset_ofu : std_ulogic; +signal pc_bx_bo_shdata_ofu : std_ulogic; +signal pc_bx_bo_select_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_fail_ofu : std_ulogic_vector(0 to 3); +signal bx_pc_bo_diagout_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_ena_dc_ofu : std_ulogic; +signal pc_bx_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_bx_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_bx_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_bx_abist_g8t_wenb_ofu : std_ulogic; +signal pc_bx_abist_raddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_raw_dc_b_ofu : std_ulogic; +signal pc_bx_abist_waddr_0_ofu : std_ulogic_vector(4 to 9); +signal pc_bx_abist_wl64_comp_ena_ofu : std_ulogic; +signal pc_bx_trace_bus_enable_ofu : std_ulogic; +signal pc_bx_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_bx_inj_inbox_ecc_ofu : std_ulogic; +signal pc_bx_inj_outbox_ecc_ofu : std_ulogic; +signal pc_bx_ccflush_dc_ofu : std_ulogic; +signal pc_bx_sg_3_ofu : std_ulogic; +signal pc_bx_func_sl_thold_3_ofu : std_ulogic; +signal pc_bx_func_slp_sl_thold_3_ofu : std_ulogic; +signal pc_bx_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_time_sl_thold_3_ofu : std_ulogic; +signal pc_bx_repr_sl_thold_3_ofu : std_ulogic; +signal pc_bx_abst_sl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_bx_ary_slp_nsl_thold_3_ofu : std_ulogic; + +signal xu_pc_err_mcsr_summary_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_ierat_parity_ofu : std_ulogic; +signal xu_pc_err_derat_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_parity_ofu : std_ulogic; +signal xu_pc_err_tlb_lru_parity_ofu : std_ulogic; +signal xu_pc_err_ierat_multihit_ofu : std_ulogic; +signal xu_pc_err_derat_multihit_ofu : std_ulogic; +signal xu_pc_err_tlb_multihit_ofu : std_ulogic; +signal xu_pc_err_ext_mchk_ofu : std_ulogic; +signal xu_pc_err_ditc_overrun_ofu : std_ulogic; +signal xu_pc_err_local_snoop_reject_ofu : std_ulogic; +signal xu_pc_err_attention_instr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_dcache_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_parity_ofu : std_ulogic; +signal xu_pc_err_dcachedir_multihit_ofu : std_ulogic; +signal xu_pc_err_debug_event_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_invld_reld_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ecc_ofu : std_ulogic; +signal xu_pc_err_l2intrf_ue_ofu : std_ulogic; +signal xu_pc_err_l2credit_overrun_ofu : std_ulogic; +signal xu_pc_err_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_nia_miscmpr_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_regfile_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_sprg_ue_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_err_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_ram_data_ofu : std_ulogic_vector(64-(2**regmode) to 63); +signal xu_pc_ram_done_ofu : std_ulogic; +signal xu_pc_ram_interrupt_ofu : std_ulogic; +signal xu_pc_running_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_spr_ccr0_pme_ofu : std_ulogic_vector(0 to 1); +signal xu_pc_spr_ccr0_we_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_step_done_ofu : std_ulogic_vector(0 to 3); +signal xu_pc_stop_dbg_event_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_bolt_sl_thold_3_ofu : std_ulogic; +signal pc_xu_bo_enable_3_ofu : std_ulogic; +signal pc_xu_bo_unload_ofu : std_ulogic; +signal pc_xu_bo_load_ofu : std_ulogic; +signal pc_xu_bo_repair_ofu : std_ulogic; +signal pc_xu_bo_reset_ofu : std_ulogic; +signal pc_xu_bo_shdata_ofu : std_ulogic; +signal pc_xu_bo_select_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_fail_ofu : std_ulogic_vector(0 to 8); +signal xu_pc_bo_diagout_ofu : std_ulogic_vector(0 to 8); +signal pc_xu_abist_dcomp_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_0_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_1_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_di_g6t_2r_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_ena_dc_ofu : std_ulogic; +signal pc_xu_abist_g6t_bw_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_abist_g6t_r_wb_ofu : std_ulogic; +signal pc_xu_abist_g8t1p_renb_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_0_ofu : std_ulogic; +signal pc_xu_abist_g8t_bw_1_ofu : std_ulogic; +signal pc_xu_abist_g8t_dcomp_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_abist_g8t_wenb_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_renb_1_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_0_ofu : std_ulogic; +signal pc_xu_abist_grf_wenb_1_ofu : std_ulogic; +signal pc_xu_abist_raddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_raw_dc_b_ofu : std_ulogic; +signal pc_xu_abist_waddr_0_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_waddr_1_ofu : std_ulogic_vector(0 to 9); +signal pc_xu_abist_wl144_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl32_comp_ena_ofu : std_ulogic; +signal pc_xu_abist_wl512_comp_ena_ofu : std_ulogic; +signal pc_xu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_lsu_event_mux_ctrls_ofu : std_ulogic_vector(0 to 47); +signal pc_xu_event_bus_enable_ofu : std_ulogic; +signal pc_xu_abst_sl_thold_3_ofu : std_ulogic; +signal pc_xu_abst_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_sl_thold_3_ofu : std_ulogic; +signal pc_xu_regf_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_ary_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_cache_par_err_event_ofu : std_ulogic; +signal pc_xu_ccflush_dc_ofu : std_ulogic; +signal pc_xu_cfg_sl_thold_3_ofu : std_ulogic; +signal pc_xu_cfg_slp_sl_thold_3_ofu : std_ulogic; +signal pc_xu_dbg_action_ofu : std_ulogic_vector(0 to 11); +signal pc_xu_debug_mux1_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux2_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux3_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_debug_mux4_ctrls_ofu : std_ulogic_vector(0 to 15); +signal pc_xu_decrem_dis_on_stop_ofu : std_ulogic; +signal pc_xu_event_count_mode_ofu : std_ulogic_vector(0 to 2); +signal pc_xu_extirpts_dis_on_stop_ofu : std_ulogic; +signal pc_xu_fce_3_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_force_ude_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_func_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_func_slp_nsl_thold_3_ofu : std_ulogic; +signal pc_xu_func_slp_sl_thold_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_gptr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_init_reset_ofu : std_ulogic; +signal pc_xu_inj_dcache_parity_ofu : std_ulogic; +signal pc_xu_inj_dcachedir_parity_ofu : std_ulogic; +signal pc_xu_inj_llbust_attempt_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_llbust_failed_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_sprg_ecc_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_regfile_parity_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_wdt_reset_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_inj_dcachedir_multihit_ofu : std_ulogic; +signal pc_xu_instr_trace_mode_ofu : std_ulogic; +signal pc_xu_instr_trace_tid_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_msrovride_enab_ofu : std_ulogic; +signal pc_xu_msrovride_gs_ofu : std_ulogic; +signal pc_xu_msrovride_pr_ofu : std_ulogic; +signal pc_xu_ram_execute_ofu : std_ulogic; +signal pc_xu_ram_flush_thread_ofu : std_ulogic; +signal pc_xu_ram_mode_ofu : std_ulogic; +signal pc_xu_ram_thread_ofu : std_ulogic_vector(0 to 1); +signal pc_xu_repr_sl_thold_3_ofu : std_ulogic; +signal pc_xu_reset_1_cmplt_ofu : std_ulogic; +signal pc_xu_reset_2_cmplt_ofu : std_ulogic; +signal pc_xu_reset_3_cmplt_ofu : std_ulogic; +signal pc_xu_reset_wd_cmplt_ofu : std_ulogic; +signal pc_xu_sg_3_ofu : std_ulogic_vector(0 to 4); +signal pc_xu_step_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_stop_ofu : std_ulogic_vector(0 to 3); +signal pc_xu_time_sl_thold_3_ofu : std_ulogic; +signal pc_xu_timebase_dis_on_stop_ofu : std_ulogic; +signal pc_xu_trace_bus_enable_ofu : std_ulogic; + +signal an_ac_crit_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_ext_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_flh2l2_gate_omm : std_ulogic; +signal an_ac_icbi_ack_omm : std_ulogic; +signal an_ac_icbi_ack_thread_omm : std_ulogic_vector(0 to 1); +signal an_ac_req_ld_pop_omm : std_ulogic; +signal an_ac_req_spare_ctrl_a1_omm : std_ulogic_vector(0 to 3); +signal an_ac_req_st_gather_omm : std_ulogic; +signal an_ac_req_st_pop_omm : std_ulogic; +signal an_ac_req_st_pop_thrd_omm : std_ulogic_vector(0 to 2); +signal an_ac_reservation_vld_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_sleep_en_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_stcx_pass_omm : std_ulogic_vector(0 to 3); +signal an_ac_sync_ack_omm : std_ulogic_vector(0 to 3); +signal an_ac_ary_nsl_thold_7_omm : std_ulogic; +signal an_ac_coreid_omm : std_ulogic_vector(0 to 7); +signal an_ac_external_mchk_omm : std_ulogic_vector(0 to 3); +signal an_ac_fce_7_omm : std_ulogic; +signal an_ac_func_nsl_thold_7_omm : std_ulogic; +signal an_ac_func_sl_thold_7_omm : std_ulogic; +signal an_ac_gsd_test_enable_dc_omm : std_ulogic; +signal an_ac_gsd_test_acmode_dc_omm : std_ulogic; +signal an_ac_gptr_scan_in_omm : std_ulogic; +signal an_ac_hang_pulse_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_lbist_ac_mode_dc_omm : std_ulogic; +signal an_ac_lbist_ip_dc_omm : std_ulogic; +signal an_ac_malf_alert_omm : std_ulogic; +signal an_ac_perf_interrupt_omm : std_ulogic_vector(0 to thdid_width-1); +signal an_ac_psro_enable_dc_omm : std_ulogic_vector(0 to 2); +signal an_ac_repr_scan_in_omm : std_ulogic; +signal an_ac_rtim_sl_thold_7_omm : std_ulogic; +signal an_ac_scan_type_dc_omm : std_ulogic_vector(0 to 8); +signal an_ac_scom_sat_id_omm : std_ulogic_vector(0 to 3); +signal an_ac_sg_7_omm : std_ulogic; +signal an_ac_tb_update_enable_omm : std_ulogic; +signal an_ac_tb_update_pulse_omm : std_ulogic; +signal an_ac_time_scan_in_omm : std_ulogic; + +signal ac_an_box_empty_imm : std_ulogic_vector(0 to 3); +signal ac_an_machine_check_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_req_imm : std_ulogic; +signal ac_an_req_endian_imm : std_ulogic; +signal ac_an_req_ld_core_tag_imm : std_ulogic_vector(0 to 4); +signal ac_an_req_ld_xfr_len_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_pwr_token_imm : std_ulogic; +signal ac_an_req_ra_imm : std_ulogic_vector(64-real_addr_width to 63); +signal ac_an_req_spare_ctrl_a0_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_thread_imm : std_ulogic_vector(0 to 2); +signal ac_an_req_ttype_imm : std_ulogic_vector(0 to 5); +signal ac_an_req_user_defined_imm : std_ulogic_vector(0 to 3); +signal ac_an_req_wimg_g_imm : std_ulogic; +signal ac_an_req_wimg_i_imm : std_ulogic; +signal ac_an_req_wimg_m_imm : std_ulogic; +signal ac_an_req_wimg_w_imm : std_ulogic; +signal ac_an_st_byte_enbl_imm : std_ulogic_vector(0 to 31); +signal ac_an_st_byte_enbl_omm : std_ulogic_vector(16 to 31); +signal ac_an_st_data_imm : std_ulogic_vector(0 to 255); +signal ac_an_st_data_omm : std_ulogic_vector(128 to 255); +signal ac_an_st_data_pwr_token_imm : std_ulogic; +signal ac_an_debug_trigger_imm : std_ulogic_vector(0 to thdid_width-1); +signal ac_an_reset_1_request_imm : std_ulogic; +signal ac_an_reset_2_request_imm : std_ulogic; +signal ac_an_reset_3_request_imm : std_ulogic; +signal ac_an_reset_wd_request_imm : std_ulogic; +signal an_ac_scan_diag_dc_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_opc : std_ulogic; +signal an_ac_scan_dis_dc_b_ofu : std_ulogic; +signal an_ac_scan_diag_dc_ofu : std_ulogic; + +signal ac_an_abist_done_dc_iiu : std_ulogic; +signal ac_an_psro_ringsig_iiu : std_ulogic; +signal an_ac_ccenable_dc_iiu : std_ulogic; +signal mm_pc_bo_fail_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_iiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_iiu : std_ulogic_vector(0 to 7); + +signal ac_an_abist_done_dc_oiu : std_ulogic; +signal ac_an_psro_ringsig_oiu : std_ulogic; +signal an_ac_ccenable_dc_oiu : std_ulogic; +signal mm_pc_bo_fail_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_bo_diagout_oiu : std_ulogic_vector(0 to 4); +signal mm_pc_event_data_oiu : std_ulogic_vector(0 to 7); + +signal pc_mm_abist_dcomp_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_iiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_iiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_iiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_iiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_iiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_iiu : std_ulogic; +signal pc_mm_abist_raddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_iiu : std_ulogic; +signal pc_mm_abist_waddr_0_iiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_iiu : std_ulogic; +signal pc_mm_bo_enable_4_iiu : std_ulogic; +signal pc_mm_bo_repair_iiu : std_ulogic; +signal pc_mm_bo_reset_iiu : std_ulogic; +signal pc_mm_bo_select_iiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_iiu : std_ulogic; +signal pc_mm_bo_unload_iiu : std_ulogic; +signal pc_mm_ccflush_dc_iiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_iiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_iiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_iiu : std_ulogic_vector(0 to 39); +signal pc_mm_trace_bus_enable_iiu : std_ulogic; +signal pc_mm_abist_dcomp_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_g6t_2r_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_di_0_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_ena_dc_oiu : std_ulogic; +signal pc_mm_abist_g6t_r_wb_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_0_oiu : std_ulogic; +signal pc_mm_abist_g8t_bw_1_oiu : std_ulogic; +signal pc_mm_abist_g8t_dcomp_oiu : std_ulogic_vector(0 to 3); +signal pc_mm_abist_g8t_wenb_oiu : std_ulogic; +signal pc_mm_abist_g8t1p_renb_0_oiu : std_ulogic; +signal pc_mm_abist_raddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_raw_dc_b_oiu : std_ulogic; +signal pc_mm_abist_waddr_0_oiu : std_ulogic_vector(0 to 9); +signal pc_mm_abist_wl128_comp_ena_oiu : std_ulogic; +signal pc_mm_abst_sl_thold_3_oiu : std_ulogic; +signal pc_mm_abst_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_ary_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_bo_enable_3_oiu : std_ulogic; +signal pc_mm_bo_repair_oiu : std_ulogic; +signal pc_mm_bo_reset_oiu : std_ulogic; +signal pc_mm_bo_select_oiu : std_ulogic_vector(0 to 4); +signal pc_mm_bo_shdata_oiu : std_ulogic; +signal pc_mm_bo_unload_oiu : std_ulogic; +signal pc_mm_bolt_sl_thold_3_oiu : std_ulogic; +signal pc_mm_ccflush_dc_oiu : std_ulogic; +signal pc_mm_cfg_sl_thold_3_oiu : std_ulogic; +signal pc_mm_cfg_slp_sl_thold_3_oiu : std_ulogic; +signal pc_mm_debug_mux1_ctrls_oiu : std_ulogic_vector(0 to 15); +signal pc_mm_event_count_mode_oiu : std_ulogic_vector(0 to 2); +signal pc_mm_event_mux_ctrls_oiu : std_ulogic_vector(0 to 39); +signal pc_mm_fce_3_oiu : std_ulogic; +signal pc_mm_func_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_func_slp_nsl_thold_3_oiu : std_ulogic; +signal pc_mm_func_slp_sl_thold_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_gptr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_repr_sl_thold_3_oiu : std_ulogic; +signal pc_mm_sg_3_oiu : std_ulogic_vector(0 to 1); +signal pc_mm_time_sl_thold_3_oiu : std_ulogic; +signal pc_mm_trace_bus_enable_oiu : std_ulogic; +signal xu_ex2_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex3_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex4_flush_ofu : std_ulogic_vector(0 to 3); +signal xu_ex5_flush_ofu : std_ulogic_vector(0 to 3); +signal an_ac_lbist_ary_wrt_thru_dc_ofu : std_ulogic; +signal xu_pc_lsu_event_data_ofu : std_ulogic_vector(0 to 7); +signal xu_pc_err_mchk_disabled : std_ulogic; +signal xu_pc_err_mchk_disabled_ofu : std_ulogic; +signal xu_iu_l_flush : std_ulogic_vector(0 to 3); +signal xu_iu_u_flush : std_ulogic_vector(0 to 3); +signal debug_bus_out_int : std_ulogic_vector(0 to 7); +signal an_ac_grffence_en_dc_oiu : std_ulogic; +signal xu_fu_lbist_ary_wrt_thru_dc : std_ulogic; +signal pc_xu_msrovride_de : std_ulogic; + +signal bg_an_ac_func_scan_sn : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn : std_ulogic_vector(10 to 11); +signal bg_an_ac_func_scan_sn_q : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_q : std_ulogic_vector(10 to 11); + +signal bg_ac_an_func_scan_ns : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns : std_ulogic_vector(10 to 11); +signal bg_ac_an_func_scan_ns_q : std_ulogic_vector(60 to 69); +signal bg_ac_an_abst_scan_ns_q : std_ulogic_vector(10 to 11); + +signal bg_pc_l1p_abist_di_0 : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0 : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1 : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb : std_ulogic; +signal bg_pc_l1p_abist_raddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0 : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena : std_ulogic; +signal bg_pc_l1p_abist_di_0_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t1p_renb_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_0_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_bw_1_q : std_ulogic; +signal bg_pc_l1p_abist_g8t_dcomp_q : std_ulogic_vector(0 to 3); +signal bg_pc_l1p_abist_g8t_wenb_q : std_ulogic; +signal bg_pc_l1p_abist_raddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_waddr_0_q : std_ulogic_vector(0 to 9); +signal bg_pc_l1p_abist_wl128_comp_ena_q : std_ulogic; +signal bg_pc_l1p_abist_wl32_comp_ena_q : std_ulogic; + +signal bg_pc_l1p_gptr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_3 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_3 : std_ulogic; +signal bg_pc_l1p_sg_3 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_3 : std_ulogic; +signal bg_pc_l1p_bo_enable_3 : std_ulogic; +signal bg_pc_l1p_gptr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2 : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2 : std_ulogic; +signal bg_pc_l1p_sg_2 : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2 : std_ulogic; +signal bg_pc_l1p_bo_enable_2 : std_ulogic; + +signal bg_pc_bo_unload_iiu : std_ulogic; +signal bg_pc_bo_load_iiu : std_ulogic; +signal bg_pc_bo_repair_iiu : std_ulogic; +signal bg_pc_bo_reset_iiu : std_ulogic; +signal bg_pc_bo_shdata_iiu : std_ulogic; +signal bg_pc_bo_select_iiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_iiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_iiu : std_ulogic; + +signal bg_pc_bo_unload_oiu : std_ulogic; +signal bg_pc_bo_load_oiu : std_ulogic; +signal bg_pc_bo_repair_oiu : std_ulogic; +signal bg_pc_bo_reset_oiu : std_ulogic; +signal bg_pc_bo_shdata_oiu : std_ulogic; +signal bg_pc_bo_select_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_ena_dc_oiu : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b_oiu : std_ulogic; + +signal bg_pc_bo_fail_oiu : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_oiu : std_ulogic_vector(0 to 10); + +signal bg_pc_l1p_gptr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_time_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_repr_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_abst_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_func_sl_thold_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_func_slp_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_bolt_sl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_ary_nsl_thold_2_imm : std_ulogic; +signal bg_pc_l1p_sg_2_imm : std_ulogic_vector(0 to 1); +signal bg_pc_l1p_fce_2_imm : std_ulogic; +signal bg_pc_l1p_bo_enable_2_imm : std_ulogic; +signal bg_pc_bo_unload : std_ulogic; +signal bg_pc_bo_load : std_ulogic; +signal bg_pc_bo_repair : std_ulogic; +signal bg_pc_bo_reset : std_ulogic; +signal bg_pc_bo_shdata : std_ulogic; +signal bg_pc_bo_select : std_ulogic_vector(0 to 10); +signal bg_pc_l1p_ccflush_dc : std_ulogic; +signal bg_pc_l1p_abist_ena_dc : std_ulogic; +signal bg_pc_l1p_abist_raw_dc_b : std_ulogic; +signal bg_an_ac_func_scan_sn_omm : std_ulogic_vector(60 to 69); +signal bg_an_ac_abst_scan_sn_omm : std_ulogic_vector(10 to 11); +signal bg_pc_bo_fail : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout : std_ulogic_vector(0 to 10); +signal bg_pc_bo_fail_omm : std_ulogic_vector(0 to 10); +signal bg_pc_bo_diagout_omm : std_ulogic_vector(0 to 10); + +signal xu_fu_lbist_en_dc : std_ulogic; +signal xu_iu_xucr4_mmu_mchk : std_ulogic; +signal xu_mm_xucr4_mmu_mchk : std_ulogic; + +-- synopsys translate_off + + + + + + + + + +-- synopsys translate_on + + +BEGIN + + +debug_start_tiedowns <= (0 to 87 => '0'); +trigger_start_tiedowns <= (0 to 11 => '0'); + ac_rp_trace_to_perfcntr <= debug_bus_out_int; -ac_an_debug_bus <= ac_an_debug_bus_int; - +ac_an_debug_bus <= ac_an_debug_bus_int; + ac_an_power_managed_imm <= ac_an_power_managed_int; - -a2_nclk_copy <= a2_nclk; - - -an_ac_bo_enable <= '0'; -an_ac_bo_go <= '0'; -an_ac_bo_cntlclk <= '0'; -an_ac_bo_ccflush <= '1'; -an_ac_bo_reset <= '0'; -an_ac_bo_data <= '0'; -an_ac_bo_shcntl <= '0'; -an_ac_bo_shdata <= '0'; -an_ac_bo_exe <= '0'; -an_ac_bo_sysrepair <= '0'; -an_ac_bo_donein <= '0'; -an_ac_bo_sdin <= '0'; -an_ac_bo_waitin <= '0'; -an_ac_bo_failin <= '0'; -an_ac_bo_fcshdata <= '0'; -an_ac_bo_fcreset <= '0'; - + +a2_nclk_copy <= a2_nclk; + + +an_ac_bo_enable <= '0'; +an_ac_bo_go <= '0'; +an_ac_bo_cntlclk <= '0'; +an_ac_bo_ccflush <= '1'; +an_ac_bo_reset <= '0'; +an_ac_bo_data <= '0'; +an_ac_bo_shcntl <= '0'; +an_ac_bo_shdata <= '0'; +an_ac_bo_exe <= '0'; +an_ac_bo_sysrepair <= '0'; +an_ac_bo_donein <= '0'; +an_ac_bo_sdin <= '0'; +an_ac_bo_waitin <= '0'; +an_ac_bo_failin <= '0'; +an_ac_bo_fcshdata <= '0'; +an_ac_bo_fcreset <= '0'; + bg_an_ac_func_scan_sn <= "0000000000"; bg_an_ac_abst_scan_sn <= "00"; - bg_pc_l1p_gptr_sl_thold_3 <= '0'; - bg_pc_l1p_time_sl_thold_3 <= '0'; - bg_pc_l1p_repr_sl_thold_3 <= '0'; - bg_pc_l1p_abst_sl_thold_3 <= '0'; + bg_pc_l1p_gptr_sl_thold_3 <= '0'; + bg_pc_l1p_time_sl_thold_3 <= '0'; + bg_pc_l1p_repr_sl_thold_3 <= '0'; + bg_pc_l1p_abst_sl_thold_3 <= '0'; bg_pc_l1p_func_sl_thold_3 <= "00"; - bg_pc_l1p_func_slp_sl_thold_3 <= '0'; - bg_pc_l1p_bolt_sl_thold_3 <= '0'; - bg_pc_l1p_ary_nsl_thold_3 <= '0'; + bg_pc_l1p_func_slp_sl_thold_3 <= '0'; + bg_pc_l1p_bolt_sl_thold_3 <= '0'; + bg_pc_l1p_ary_nsl_thold_3 <= '0'; bg_pc_l1p_sg_3 <= "00"; - bg_pc_l1p_fce_3 <= '0'; - bg_pc_l1p_bo_enable_3 <= '0'; - bg_pc_bo_unload_iiu <= '0'; - bg_pc_bo_load_iiu <= '0'; - bg_pc_bo_repair_iiu <= '0'; - bg_pc_bo_reset_iiu <= '0'; - bg_pc_bo_shdata_iiu <= '0'; + bg_pc_l1p_fce_3 <= '0'; + bg_pc_l1p_bo_enable_3 <= '0'; + bg_pc_bo_unload_iiu <= '0'; + bg_pc_bo_load_iiu <= '0'; + bg_pc_bo_repair_iiu <= '0'; + bg_pc_bo_reset_iiu <= '0'; + bg_pc_bo_shdata_iiu <= '0'; bg_pc_bo_select_iiu <= "00000000000"; - bg_pc_l1p_ccflush_dc_iiu <= '0'; - bg_pc_l1p_abist_ena_dc_iiu <= '0'; - bg_pc_l1p_abist_raw_dc_b_iiu <= '0'; + bg_pc_l1p_ccflush_dc_iiu <= '0'; + bg_pc_l1p_abist_ena_dc_iiu <= '0'; + bg_pc_l1p_abist_raw_dc_b_iiu <= '0'; bg_pc_bo_fail <= "00000000000"; bg_pc_bo_diagout <= "00000000000"; - - -spr_pvr_version_dc <= "01001000"; -spr_pvr_revision_dc <= "0010"; - - -a_fuq: entity work.fuq - generic map(expand_type => expand_type, eff_ifar => xu_eff_ifar, regmode => regmode) - port map ( - an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, - an_ac_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + + +spr_pvr_version_dc <= "01001000"; +spr_pvr_revision_dc <= "0010"; + + +a_fuq: entity work.fuq + generic map(expand_type => expand_type, eff_ifar => xu_eff_ifar, regmode => regmode) + port map ( + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, an_ac_lbist_en_dc => xu_fu_lbist_en_dc, - pc_fu_ccflush_dc => pc_fu_ccflush_dc, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_opc, - an_ac_scan_diag_dc => an_ac_scan_diag_dc_opc, - abst_scan_in => rp_fu_abst_scan_in_q, - bcfg_scan_in => iu_fu_bcfg_scan_out, - ccfg_scan_in => xu_fu_ccfg_scan_out, - dcfg_scan_in => iu_fu_dcfg_scan_out, - func_scan_in => rp_fu_func_scan_in_q(0 to 3), - gptr_scan_in => pc_fu_gptr_scan_out, - repr_scan_in => iu_fu_repr_scan_out, - time_scan_in => iu_fu_time_scan_out, - bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out, - bx_rp_abst_scan_out => bx_rp_abst_scan_out, - rp_bx_abst_scan_in => rp_bx_abst_scan_in_q, - rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in, - rp_bx_func_scan_in => rp_bx_func_scan_in_q, - rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in, - bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out, - bx_rp_func_scan_out => bx_rp_func_scan_out, - debug_data_in => bx_fu_debug_data, - trace_triggers_in => bx_fu_trigger_data, - iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, - iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, - iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, - iu_fu_rf0_fra => iu_fu_rf0_fra, - iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, - iu_fu_rf0_frb => iu_fu_rf0_frb, - iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, - iu_fu_rf0_frc => iu_fu_rf0_frc, - iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, - iu_fu_rf0_frt => iu_fu_rf0_frt, - iu_fu_rf0_ifar => iu_fu_rf0_ifar, - iu_fu_rf0_instr => iu_fu_rf0_instr, - iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, - iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, - iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, - iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, - iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, - iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, - iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, - iu_fu_rf0_str_val => iu_fu_rf0_str_val, - iu_fu_rf0_tid => iu_fu_rf0_tid, - nclk => a2_nclk, - pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), - pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), - pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, - pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, - pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, - pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, - pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, - pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), - pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), - pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, - pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), - pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), - pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, - pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, - pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, - pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, - pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, - pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, - pc_fu_bo_enable_3 => pc_fu_bo_enable_3, - pc_fu_bo_unload => pc_fu_bo_unload, - pc_fu_bo_load => pc_fu_bo_load, - pc_fu_bo_reset => pc_fu_bo_reset, - pc_fu_bo_shdata => pc_fu_bo_shdata, - pc_fu_bo_select => pc_fu_bo_select, - pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, - pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, - pc_fu_debug_mux_ctrls => pc_fu_debug_mux1_ctrls, - pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, - pc_fu_event_count_mode => pc_fu_event_count_mode, - pc_fu_fce_3 => pc_fu_fce_3, - pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, - pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, - pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, - pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, - pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, - pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, - pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, - pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, - pc_fu_ram_mode => pc_fu_ram_mode, - pc_fu_ram_thread => pc_fu_ram_thread, - pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, - pc_fu_sg_3 => pc_fu_sg_3, - slowspr_addr_in => pc_fu_slowspr_addr, - slowspr_data_in => pc_fu_slowspr_data, - slowspr_done_in => pc_fu_slowspr_done, - slowspr_etid_in => pc_fu_slowspr_etid, - slowspr_rw_in => pc_fu_slowspr_rw, - slowspr_val_in => pc_fu_slowspr_val, - pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, - pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_opc, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_opc, + abst_scan_in => rp_fu_abst_scan_in_q, + bcfg_scan_in => iu_fu_bcfg_scan_out, + ccfg_scan_in => xu_fu_ccfg_scan_out, + dcfg_scan_in => iu_fu_dcfg_scan_out, + func_scan_in => rp_fu_func_scan_in_q(0 to 3), + gptr_scan_in => pc_fu_gptr_scan_out, + repr_scan_in => iu_fu_repr_scan_out, + time_scan_in => iu_fu_time_scan_out, + bx_fu_rp_abst_scan_out => bx_fu_rp_abst_scan_out, + bx_rp_abst_scan_out => bx_rp_abst_scan_out, + rp_bx_abst_scan_in => rp_bx_abst_scan_in_q, + rp_fu_bx_abst_scan_in => rp_fu_bx_abst_scan_in, + rp_bx_func_scan_in => rp_bx_func_scan_in_q, + rp_fu_bx_func_scan_in => rp_fu_bx_func_scan_in, + bx_fu_rp_func_scan_out => bx_fu_rp_func_scan_out, + bx_rp_func_scan_out => bx_rp_func_scan_out, + debug_data_in => bx_fu_debug_data, + trace_triggers_in => bx_fu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + nclk => a2_nclk, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_in => pc_fu_slowspr_addr, + slowspr_data_in => pc_fu_slowspr_data, + slowspr_done_in => pc_fu_slowspr_done, + slowspr_etid_in => pc_fu_slowspr_etid, + slowspr_rw_in => pc_fu_slowspr_rw, + slowspr_val_in => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, pc_fu_event_bus_enable => pc_fu_event_bus_enable, - xu_ex1_flush => xu_n_ex1_flush, - xu_ex2_flush => xu_n_ex2_flush, - xu_ex3_flush => xu_n_ex3_flush, - xu_ex4_flush => xu_n_ex4_flush, - xu_ex5_flush => xu_n_ex5_flush, - xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, - xu_fu_ex6_load_data => xu_fu_ex6_load_data(192 to 255), - xu_fu_ex5_load_le => xu_fu_ex5_load_le, - xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, - xu_fu_ex5_load_val => xu_fu_ex5_load_val, - xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, - xu_fu_msr_fp => xu_fu_msr_fp, - xu_fu_msr_pr => xu_fu_msr_pr, - xu_fu_msr_gs => xu_fu_msr_gs, - xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, - xu_is2_flush => xu_n_is2_flush, - xu_rf0_flush => xu_n_rf0_flush, - xu_rf1_flush => xu_n_rf1_flush, - abst_scan_out => fu_rp_abst_scan_out, - bcfg_scan_out => fu_rp_bcfg_scan_out, - ccfg_scan_out => fu_rp_ccfg_scan_out, - dcfg_scan_out => fu_rp_dcfg_scan_out, - func_scan_out => fu_rp_func_scan_out(0 to 3), - gptr_scan_out => fu_bx_gptr_scan_out, - repr_scan_out => fu_bx_repr_scan_out, - time_scan_out => fu_bx_time_scan_out, - debug_data_out => fu_pc_debug_data, - trace_triggers_out => fu_pc_trigger_data, - fu_iu_uc_special => fu_iu_uc_special, - fu_pc_bo_fail => fu_pc_bo_fail, - fu_pc_bo_diagout => fu_pc_bo_diagout, - fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, - fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, - fu_pc_event_data => fu_pc_event_data, - fu_pc_ram_data => fu_pc_ram_data, - fu_pc_ram_done => fu_pc_ram_done, - fu_xu_ex1_ifar => fu_xu_ex1_ifar, - fu_xu_ex2_async_block => fu_xu_ex2_async_block, - fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, - fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, - fu_xu_ex2_store_data => fu_xu_ex2_store_data, - fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, - fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, - fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, - fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, - fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, - fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, - fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, - fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, - fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, - fu_xu_ex3_trap => fu_xu_ex3_trap, - fu_xu_ex4_cr => fu_xu_ex4_cr, - fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf, - fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, - fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, - fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, - fu_xu_rf1_act => fu_xu_rf1_act, - slowspr_addr_out => fu_bx_slowspr_addr, - slowspr_data_out => fu_bx_slowspr_data, - slowspr_done_out => fu_bx_slowspr_done, - slowspr_etid_out => fu_bx_slowspr_etid, - slowspr_rw_out => fu_bx_slowspr_rw, - slowspr_val_out => fu_bx_slowspr_val, - - bx_pc_err_inbox_ue_ifu => bx_pc_err_inbox_ue, - bx_pc_err_outbox_ue_ifu => bx_pc_err_outbox_ue, - bx_pc_err_inbox_ecc_ifu => bx_pc_err_inbox_ecc, - bx_pc_err_outbox_ecc_ifu => bx_pc_err_outbox_ecc, - pc_bx_bolt_sl_thold_3_ifu => pc_bx_bolt_sl_thold_3, - pc_bx_bo_enable_3_ifu => pc_bx_bo_enable_3, - pc_bx_bo_unload_ifu => pc_bx_bo_unload, - pc_bx_bo_repair_ifu => pc_bx_bo_repair, - pc_bx_bo_reset_ifu => pc_bx_bo_reset, - pc_bx_bo_shdata_ifu => pc_bx_bo_shdata, - pc_bx_bo_select_ifu => pc_bx_bo_select, - bx_pc_bo_fail_ifu => bx_pc_bo_fail, - bx_pc_bo_diagout_ifu => bx_pc_bo_diagout, - pc_bx_abist_di_0_ifu => pc_bx_abist_di_0, - pc_bx_abist_ena_dc_ifu => pc_bx_abist_ena_dc, - pc_bx_abist_g8t1p_renb_0_ifu => pc_bx_abist_g8t1p_renb_0, - pc_bx_abist_g8t_bw_0_ifu => pc_bx_abist_g8t_bw_0, - pc_bx_abist_g8t_bw_1_ifu => pc_bx_abist_g8t_bw_1, - pc_bx_abist_g8t_dcomp_ifu => pc_bx_abist_g8t_dcomp, - pc_bx_abist_g8t_wenb_ifu => pc_bx_abist_g8t_wenb, - pc_bx_abist_raddr_0_ifu => pc_bx_abist_raddr_0(4 to 9), - pc_bx_abist_raw_dc_b_ifu => pc_bx_abist_raw_dc_b, - pc_bx_abist_waddr_0_ifu => pc_bx_abist_waddr_0(4 to 9), - pc_bx_abist_wl64_comp_ena_ifu => pc_bx_abist_wl64_comp_ena, - pc_bx_trace_bus_enable_ifu => pc_bx_trace_bus_enable, - pc_bx_debug_mux1_ctrls_ifu => pc_bx_debug_mux1_ctrls, - pc_bx_inj_inbox_ecc_ifu => pc_bx_inj_inbox_ecc, - pc_bx_inj_outbox_ecc_ifu => pc_bx_inj_outbox_ecc, - pc_bx_ccflush_dc_ifu => pc_bx_ccflush_dc, - pc_bx_sg_3_ifu => pc_bx_sg_3, - pc_bx_func_sl_thold_3_ifu => pc_bx_func_sl_thold_3, - pc_bx_func_slp_sl_thold_3_ifu => pc_bx_func_slp_sl_thold_3, - pc_bx_gptr_sl_thold_3_ifu => pc_bx_gptr_sl_thold_3, - pc_bx_time_sl_thold_3_ifu => pc_bx_time_sl_thold_3, - pc_bx_repr_sl_thold_3_ifu => pc_bx_repr_sl_thold_3, - pc_bx_abst_sl_thold_3_ifu => pc_bx_abst_sl_thold_3, - pc_bx_ary_nsl_thold_3_ifu => pc_bx_ary_nsl_thold_3, - pc_bx_ary_slp_nsl_thold_3_ifu => pc_bx_ary_slp_nsl_thold_3, - - xu_pc_err_mcsr_summary_ifu => xu_pc_err_mcsr_summary, - xu_pc_err_ierat_parity_ifu => xu_pc_err_ierat_parity, - xu_pc_err_derat_parity_ifu => xu_pc_err_derat_parity, - xu_pc_err_tlb_parity_ifu => xu_pc_err_tlb_parity, - xu_pc_err_tlb_lru_parity_ifu => xu_pc_err_tlb_lru_parity, - xu_pc_err_ierat_multihit_ifu => xu_pc_err_ierat_multihit, - xu_pc_err_derat_multihit_ifu => xu_pc_err_derat_multihit, - xu_pc_err_tlb_multihit_ifu => xu_pc_err_tlb_multihit, - xu_pc_err_ext_mchk_ifu => xu_pc_err_ext_mchk, - xu_pc_err_ditc_overrun_ifu => xu_pc_err_ditc_overrun, - xu_pc_err_local_snoop_reject_ifu => xu_pc_err_local_snoop_reject, - xu_pc_err_attention_instr_ifu => xu_pc_err_attention_instr, - xu_pc_err_dcache_parity_ifu => xu_pc_err_dcache_parity, - xu_pc_err_dcachedir_parity_ifu => xu_pc_err_dcachedir_parity, - xu_pc_err_dcachedir_multihit_ifu => xu_pc_err_dcachedir_multihit, - xu_pc_err_debug_event_ifu => xu_pc_err_debug_event, - xu_pc_err_invld_reld_ifu => xu_pc_err_invld_reld, - xu_pc_err_l2intrf_ecc_ifu => xu_pc_err_l2intrf_ecc, - xu_pc_err_l2intrf_ue_ifu => xu_pc_err_l2intrf_ue, - xu_pc_err_l2credit_overrun_ifu => xu_pc_err_l2credit_overrun, - xu_pc_err_llbust_attempt_ifu => xu_pc_err_llbust_attempt, - xu_pc_err_llbust_failed_ifu => xu_pc_err_llbust_failed, - xu_pc_err_nia_miscmpr_ifu => xu_pc_err_nia_miscmpr, - xu_pc_err_regfile_parity_ifu => xu_pc_err_regfile_parity, - xu_pc_err_regfile_ue_ifu => xu_pc_err_regfile_ue, - xu_pc_err_sprg_ecc_ifu => xu_pc_err_sprg_ecc, - xu_pc_err_sprg_ue_ifu => xu_pc_err_sprg_ue, - xu_pc_err_wdt_reset_ifu => xu_pc_err_wdt_reset, - xu_pc_event_data_ifu => xu_pc_event_data, - xu_pc_ram_data_ifu => xu_pc_ram_data, - xu_pc_ram_done_ifu => xu_pc_ram_done, - xu_pc_ram_interrupt_ifu => xu_pc_ram_interrupt, - xu_pc_running_ifu => xu_pc_running, - xu_pc_spr_ccr0_pme_ifu => xu_pc_spr_ccr0_pme, - xu_pc_spr_ccr0_we_ifu => xu_pc_spr_ccr0_we, - xu_pc_step_done_ifu => xu_pc_step_done, - xu_pc_stop_dbg_event_ifu => xu_pc_stop_dbg_event, - pc_xu_bolt_sl_thold_3_ifu => pc_xu_bolt_sl_thold_3, - pc_xu_bo_enable_3_ifu => pc_xu_bo_enable_3, - pc_xu_bo_unload_ifu => pc_xu_bo_unload, - pc_xu_bo_load_ifu => pc_xu_bo_load, - pc_xu_bo_repair_ifu => pc_xu_bo_repair, - pc_xu_bo_reset_ifu => pc_xu_bo_reset, - pc_xu_bo_shdata_ifu => pc_xu_bo_shdata, - pc_xu_bo_select_ifu => pc_xu_bo_select, - xu_pc_bo_fail_ifu => xu_pc_bo_fail, - xu_pc_bo_diagout_ifu => xu_pc_bo_diagout, - pc_xu_abist_dcomp_g6t_2r_ifu => pc_xu_abist_dcomp_g6t_2r, - pc_xu_abist_di_0_ifu => pc_xu_abist_di_0, - pc_xu_abist_di_1_ifu => pc_xu_abist_di_1, - pc_xu_abist_di_g6t_2r_ifu => pc_xu_abist_di_g6t_2r, - pc_xu_abist_ena_dc_ifu => pc_xu_abist_ena_dc, - pc_xu_abist_g6t_bw_ifu => pc_xu_abist_g6t_bw, - pc_xu_abist_g6t_r_wb_ifu => pc_xu_abist_g6t_r_wb, - pc_xu_abist_g8t1p_renb_0_ifu => pc_xu_abist_g8t1p_renb_0, - pc_xu_abist_g8t_bw_0_ifu => pc_xu_abist_g8t_bw_0, - pc_xu_abist_g8t_bw_1_ifu => pc_xu_abist_g8t_bw_1, - pc_xu_abist_g8t_dcomp_ifu => pc_xu_abist_g8t_dcomp, - pc_xu_abist_g8t_wenb_ifu => pc_xu_abist_g8t_wenb, - pc_xu_abist_grf_renb_0_ifu => pc_xu_abist_grf_renb_0, - pc_xu_abist_grf_renb_1_ifu => pc_xu_abist_grf_renb_1, - pc_xu_abist_grf_wenb_0_ifu => pc_xu_abist_grf_wenb_0, - pc_xu_abist_grf_wenb_1_ifu => pc_xu_abist_grf_wenb_1, - pc_xu_abist_raddr_0_ifu => pc_xu_abist_raddr_0, - pc_xu_abist_raddr_1_ifu => pc_xu_abist_raddr_1, - pc_xu_abist_raw_dc_b_ifu => pc_xu_abist_raw_dc_b, - pc_xu_abist_waddr_0_ifu => pc_xu_abist_waddr_0, - pc_xu_abist_waddr_1_ifu => pc_xu_abist_waddr_1, - pc_xu_abist_wl144_comp_ena_ifu => pc_xu_abist_wl144_comp_ena, - pc_xu_abist_wl32_comp_ena_ifu => pc_xu_abist_wl32_comp_ena, - pc_xu_abist_wl512_comp_ena_ifu => pc_xu_abist_wl512_comp_ena, - pc_xu_event_mux_ctrls_ifu => pc_xu_event_mux_ctrls, - pc_xu_lsu_event_mux_ctrls_ifu => pc_xu_lsu_event_mux_ctrls, - pc_xu_event_bus_enable_ifu => pc_xu_event_bus_enable, - pc_xu_abst_sl_thold_3_ifu => pc_xu_abst_sl_thold_3, - pc_xu_abst_slp_sl_thold_3_ifu => pc_xu_abst_slp_sl_thold_3, - pc_xu_regf_sl_thold_3_ifu => pc_xu_regf_sl_thold_3, - pc_xu_regf_slp_sl_thold_3_ifu => pc_xu_regf_slp_sl_thold_3, - pc_xu_ary_nsl_thold_3_ifu => pc_xu_ary_nsl_thold_3, - pc_xu_ary_slp_nsl_thold_3_ifu => pc_xu_ary_slp_nsl_thold_3, - pc_xu_cache_par_err_event_ifu => pc_xu_cache_par_err_event, - pc_xu_ccflush_dc_ifu => pc_xu_ccflush_dc, - pc_xu_cfg_sl_thold_3_ifu => pc_xu_cfg_sl_thold_3, - pc_xu_cfg_slp_sl_thold_3_ifu => pc_xu_cfg_slp_sl_thold_3, - pc_xu_dbg_action_ifu => pc_xu_dbg_action, - pc_xu_debug_mux1_ctrls_ifu => pc_xu_debug_mux1_ctrls, - pc_xu_debug_mux2_ctrls_ifu => pc_xu_debug_mux2_ctrls, - pc_xu_debug_mux3_ctrls_ifu => pc_xu_debug_mux3_ctrls, - pc_xu_debug_mux4_ctrls_ifu => pc_xu_debug_mux4_ctrls, - pc_xu_decrem_dis_on_stop_ifu => pc_xu_decrem_dis_on_stop, - pc_xu_event_count_mode_ifu => pc_xu_event_count_mode, - pc_xu_extirpts_dis_on_stop_ifu => pc_xu_extirpts_dis_on_stop, - pc_xu_fce_3_ifu => pc_xu_fce_3, - pc_xu_force_ude_ifu => pc_xu_force_ude, - pc_xu_func_nsl_thold_3_ifu => pc_xu_func_nsl_thold_3, - pc_xu_func_sl_thold_3_ifu => pc_xu_func_sl_thold_3, - pc_xu_func_slp_nsl_thold_3_ifu => pc_xu_func_slp_nsl_thold_3, - pc_xu_func_slp_sl_thold_3_ifu => pc_xu_func_slp_sl_thold_3, - pc_xu_gptr_sl_thold_3_ifu => pc_xu_gptr_sl_thold_3, - pc_xu_init_reset_ifu => pc_xu_init_reset, - pc_xu_inj_dcache_parity_ifu => pc_xu_inj_dcache_parity, - pc_xu_inj_dcachedir_parity_ifu => pc_xu_inj_dcachedir_parity, - pc_xu_inj_llbust_attempt_ifu => pc_xu_inj_llbust_attempt, - pc_xu_inj_llbust_failed_ifu => pc_xu_inj_llbust_failed, - pc_xu_inj_sprg_ecc_ifu => pc_xu_inj_sprg_ecc, - pc_xu_inj_regfile_parity_ifu => pc_xu_inj_regfile_parity, - pc_xu_inj_wdt_reset_ifu => pc_xu_inj_wdt_reset, - pc_xu_inj_dcachedir_multihit_ifu => pc_xu_inj_dcachedir_multihit, - pc_xu_instr_trace_mode_ifu => pc_xu_instr_trace_mode, - pc_xu_instr_trace_tid_ifu => pc_xu_instr_trace_tid, - pc_xu_msrovride_enab_ifu => pc_xu_msrovride_enab, - pc_xu_msrovride_gs_ifu => pc_xu_msrovride_gs, - pc_xu_msrovride_pr_ifu => pc_xu_msrovride_pr, - pc_xu_ram_execute_ifu => pc_xu_ram_execute, - pc_xu_ram_flush_thread_ifu => pc_xu_ram_flush_thread, - pc_xu_ram_mode_ifu => pc_xu_ram_mode, - pc_xu_ram_thread_ifu => pc_xu_ram_thread, - pc_xu_repr_sl_thold_3_ifu => pc_xu_repr_sl_thold_3, - pc_xu_reset_1_cmplt_ifu => pc_xu_reset_1_complete, - pc_xu_reset_2_cmplt_ifu => pc_xu_reset_2_complete, - pc_xu_reset_3_cmplt_ifu => pc_xu_reset_3_complete, - pc_xu_reset_wd_cmplt_ifu => pc_xu_reset_wd_complete, - pc_xu_sg_3_ifu => pc_xu_sg_3, - pc_xu_step_ifu => pc_xu_step, - pc_xu_stop_ifu => pc_xu_stop, - pc_xu_time_sl_thold_3_ifu => pc_xu_time_sl_thold_3, - pc_xu_timebase_dis_on_stop_ifu => pc_xu_timebase_dis_on_stop, - pc_xu_trace_bus_enable_ifu => pc_xu_trace_bus_enable, - - bx_pc_err_inbox_ue_ofu => bx_pc_err_inbox_ue_ofu , - bx_pc_err_outbox_ue_ofu => bx_pc_err_outbox_ue_ofu, - bx_pc_err_inbox_ecc_ofu => bx_pc_err_inbox_ecc_ofu, - bx_pc_err_outbox_ecc_ofu => bx_pc_err_outbox_ecc_ofu, - pc_bx_bolt_sl_thold_3_ofu => pc_bx_bolt_sl_thold_3_ofu, - pc_bx_bo_enable_3_ofu => pc_bx_bo_enable_3_ofu , - pc_bx_bo_unload_ofu => pc_bx_bo_unload_ofu , - pc_bx_bo_repair_ofu => pc_bx_bo_repair_ofu , - pc_bx_bo_reset_ofu => pc_bx_bo_reset_ofu , - pc_bx_bo_shdata_ofu => pc_bx_bo_shdata_ofu , - pc_bx_bo_select_ofu => pc_bx_bo_select_ofu , - bx_pc_bo_fail_ofu => bx_pc_bo_fail_ofu , - bx_pc_bo_diagout_ofu => bx_pc_bo_diagout_ofu , - pc_bx_abist_di_0_ofu => pc_bx_abist_di_0_ofu , - pc_bx_abist_ena_dc_ofu => pc_bx_abist_ena_dc_ofu , - pc_bx_abist_g8t1p_renb_0_ofu => pc_bx_abist_g8t1p_renb_0_ofu, - pc_bx_abist_g8t_bw_0_ofu => pc_bx_abist_g8t_bw_0_ofu, - pc_bx_abist_g8t_bw_1_ofu => pc_bx_abist_g8t_bw_1_ofu, - pc_bx_abist_g8t_dcomp_ofu => pc_bx_abist_g8t_dcomp_ofu, - pc_bx_abist_g8t_wenb_ofu => pc_bx_abist_g8t_wenb_ofu, - pc_bx_abist_raddr_0_ofu => pc_bx_abist_raddr_0_ofu, - pc_bx_abist_raw_dc_b_ofu => pc_bx_abist_raw_dc_b_ofu, - pc_bx_abist_waddr_0_ofu => pc_bx_abist_waddr_0_ofu, - pc_bx_abist_wl64_comp_ena_ofu => pc_bx_abist_wl64_comp_ena_ofu, - pc_bx_trace_bus_enable_ofu => pc_bx_trace_bus_enable_ofu, - pc_bx_debug_mux1_ctrls_ofu => pc_bx_debug_mux1_ctrls_ofu, - pc_bx_inj_inbox_ecc_ofu => pc_bx_inj_inbox_ecc_ofu, - pc_bx_inj_outbox_ecc_ofu => pc_bx_inj_outbox_ecc_ofu, - pc_bx_ccflush_dc_ofu => pc_bx_ccflush_dc_ofu , - pc_bx_sg_3_ofu => pc_bx_sg_3_ofu , - pc_bx_func_sl_thold_3_ofu => pc_bx_func_sl_thold_3_ofu, - pc_bx_func_slp_sl_thold_3_ofu => pc_bx_func_slp_sl_thold_3_ofu, - pc_bx_gptr_sl_thold_3_ofu => pc_bx_gptr_sl_thold_3_ofu, - pc_bx_time_sl_thold_3_ofu => pc_bx_time_sl_thold_3_ofu, - pc_bx_repr_sl_thold_3_ofu => pc_bx_repr_sl_thold_3_ofu, - pc_bx_abst_sl_thold_3_ofu => pc_bx_abst_sl_thold_3_ofu, - pc_bx_ary_nsl_thold_3_ofu => pc_bx_ary_nsl_thold_3_ofu, - pc_bx_ary_slp_nsl_thold_3_ofu => pc_bx_ary_slp_nsl_thold_3_ofu, - - xu_pc_err_mcsr_summary_ofu => xu_pc_err_mcsr_summary_ofu , - xu_pc_err_ierat_parity_ofu => xu_pc_err_ierat_parity_ofu , - xu_pc_err_derat_parity_ofu => xu_pc_err_derat_parity_ofu , - xu_pc_err_tlb_parity_ofu => xu_pc_err_tlb_parity_ofu , - xu_pc_err_tlb_lru_parity_ofu => xu_pc_err_tlb_lru_parity_ofu , - xu_pc_err_ierat_multihit_ofu => xu_pc_err_ierat_multihit_ofu , - xu_pc_err_derat_multihit_ofu => xu_pc_err_derat_multihit_ofu , - xu_pc_err_tlb_multihit_ofu => xu_pc_err_tlb_multihit_ofu , - xu_pc_err_ext_mchk_ofu => xu_pc_err_ext_mchk_ofu , - xu_pc_err_ditc_overrun_ofu => xu_pc_err_ditc_overrun_ofu , - xu_pc_err_local_snoop_reject_ofu => xu_pc_err_local_snoop_reject_ofu , - xu_pc_err_attention_instr_ofu => xu_pc_err_attention_instr_ofu , - xu_pc_err_dcache_parity_ofu => xu_pc_err_dcache_parity_ofu , - xu_pc_err_dcachedir_parity_ofu => xu_pc_err_dcachedir_parity_ofu , - xu_pc_err_dcachedir_multihit_ofu => xu_pc_err_dcachedir_multihit_ofu , - xu_pc_err_debug_event_ofu => xu_pc_err_debug_event_ofu , - xu_pc_err_invld_reld_ofu => xu_pc_err_invld_reld_ofu , - xu_pc_err_l2intrf_ecc_ofu => xu_pc_err_l2intrf_ecc_ofu , - xu_pc_err_l2intrf_ue_ofu => xu_pc_err_l2intrf_ue_ofu , - xu_pc_err_l2credit_overrun_ofu => xu_pc_err_l2credit_overrun_ofu , - xu_pc_err_llbust_attempt_ofu => xu_pc_err_llbust_attempt_ofu , - xu_pc_err_llbust_failed_ofu => xu_pc_err_llbust_failed_ofu , - xu_pc_err_nia_miscmpr_ofu => xu_pc_err_nia_miscmpr_ofu , - xu_pc_err_regfile_parity_ofu => xu_pc_err_regfile_parity_ofu , - xu_pc_err_regfile_ue_ofu => xu_pc_err_regfile_ue_ofu , - xu_pc_err_sprg_ecc_ofu => xu_pc_err_sprg_ecc_ofu , - xu_pc_err_sprg_ue_ofu => xu_pc_err_sprg_ue_ofu , - xu_pc_err_wdt_reset_ofu => xu_pc_err_wdt_reset_ofu , - xu_pc_event_data_ofu => xu_pc_event_data_ofu , - xu_pc_ram_data_ofu => xu_pc_ram_data_ofu , - xu_pc_ram_done_ofu => xu_pc_ram_done_ofu , - xu_pc_ram_interrupt_ofu => xu_pc_ram_interrupt_ofu , - xu_pc_running_ofu => xu_pc_running_ofu , - xu_pc_spr_ccr0_pme_ofu => xu_pc_spr_ccr0_pme_ofu , - xu_pc_spr_ccr0_we_ofu => xu_pc_spr_ccr0_we_ofu , - xu_pc_step_done_ofu => xu_pc_step_done_ofu , - xu_pc_stop_dbg_event_ofu => xu_pc_stop_dbg_event_ofu , - pc_xu_bolt_sl_thold_3_ofu => pc_xu_bolt_sl_thold_3_ofu , - pc_xu_bo_enable_3_ofu => pc_xu_bo_enable_3_ofu , - pc_xu_bo_unload_ofu => pc_xu_bo_unload_ofu , - pc_xu_bo_load_ofu => pc_xu_bo_load_ofu , - pc_xu_bo_repair_ofu => pc_xu_bo_repair_ofu , - pc_xu_bo_reset_ofu => pc_xu_bo_reset_ofu , - pc_xu_bo_shdata_ofu => pc_xu_bo_shdata_ofu , - pc_xu_bo_select_ofu => pc_xu_bo_select_ofu , - xu_pc_bo_fail_ofu => xu_pc_bo_fail_ofu , - xu_pc_bo_diagout_ofu => xu_pc_bo_diagout_ofu , - pc_xu_abist_dcomp_g6t_2r_ofu => pc_xu_abist_dcomp_g6t_2r_ofu , - pc_xu_abist_di_0_ofu => pc_xu_abist_di_0_ofu , - pc_xu_abist_di_1_ofu => pc_xu_abist_di_1_ofu , - pc_xu_abist_di_g6t_2r_ofu => pc_xu_abist_di_g6t_2r_ofu , - pc_xu_abist_ena_dc_ofu => pc_xu_abist_ena_dc_ofu , - pc_xu_abist_g6t_bw_ofu => pc_xu_abist_g6t_bw_ofu , - pc_xu_abist_g6t_r_wb_ofu => pc_xu_abist_g6t_r_wb_ofu , - pc_xu_abist_g8t1p_renb_0_ofu => pc_xu_abist_g8t1p_renb_0_ofu , - pc_xu_abist_g8t_bw_0_ofu => pc_xu_abist_g8t_bw_0_ofu , - pc_xu_abist_g8t_bw_1_ofu => pc_xu_abist_g8t_bw_1_ofu , - pc_xu_abist_g8t_dcomp_ofu => pc_xu_abist_g8t_dcomp_ofu , - pc_xu_abist_g8t_wenb_ofu => pc_xu_abist_g8t_wenb_ofu , - pc_xu_abist_grf_renb_0_ofu => pc_xu_abist_grf_renb_0_ofu , - pc_xu_abist_grf_renb_1_ofu => pc_xu_abist_grf_renb_1_ofu , - pc_xu_abist_grf_wenb_0_ofu => pc_xu_abist_grf_wenb_0_ofu , - pc_xu_abist_grf_wenb_1_ofu => pc_xu_abist_grf_wenb_1_ofu , - pc_xu_abist_raddr_0_ofu => pc_xu_abist_raddr_0_ofu , - pc_xu_abist_raddr_1_ofu => pc_xu_abist_raddr_1_ofu , - pc_xu_abist_raw_dc_b_ofu => pc_xu_abist_raw_dc_b_ofu , - pc_xu_abist_waddr_0_ofu => pc_xu_abist_waddr_0_ofu , - pc_xu_abist_waddr_1_ofu => pc_xu_abist_waddr_1_ofu , - pc_xu_abist_wl144_comp_ena_ofu => pc_xu_abist_wl144_comp_ena_ofu , - pc_xu_abist_wl32_comp_ena_ofu => pc_xu_abist_wl32_comp_ena_ofu , - pc_xu_abist_wl512_comp_ena_ofu => pc_xu_abist_wl512_comp_ena_ofu , - pc_xu_event_mux_ctrls_ofu => pc_xu_event_mux_ctrls_ofu , - pc_xu_lsu_event_mux_ctrls_ofu => pc_xu_lsu_event_mux_ctrls_ofu , - pc_xu_event_bus_enable_ofu => pc_xu_event_bus_enable_ofu , - pc_xu_abst_sl_thold_3_ofu => pc_xu_abst_sl_thold_3_ofu , - pc_xu_abst_slp_sl_thold_3_ofu => pc_xu_abst_slp_sl_thold_3_ofu , - pc_xu_regf_sl_thold_3_ofu => pc_xu_regf_sl_thold_3_ofu , - pc_xu_regf_slp_sl_thold_3_ofu => pc_xu_regf_slp_sl_thold_3_ofu , - pc_xu_ary_nsl_thold_3_ofu => pc_xu_ary_nsl_thold_3_ofu , - pc_xu_ary_slp_nsl_thold_3_ofu => pc_xu_ary_slp_nsl_thold_3_ofu , - pc_xu_cache_par_err_event_ofu => pc_xu_cache_par_err_event_ofu , - pc_xu_ccflush_dc_ofu => pc_xu_ccflush_dc_ofu , - pc_xu_cfg_sl_thold_3_ofu => pc_xu_cfg_sl_thold_3_ofu , - pc_xu_cfg_slp_sl_thold_3_ofu => pc_xu_cfg_slp_sl_thold_3_ofu , - pc_xu_dbg_action_ofu => pc_xu_dbg_action_ofu , - pc_xu_debug_mux1_ctrls_ofu => pc_xu_debug_mux1_ctrls_ofu , - pc_xu_debug_mux2_ctrls_ofu => pc_xu_debug_mux2_ctrls_ofu , - pc_xu_debug_mux3_ctrls_ofu => pc_xu_debug_mux3_ctrls_ofu , - pc_xu_debug_mux4_ctrls_ofu => pc_xu_debug_mux4_ctrls_ofu , - pc_xu_decrem_dis_on_stop_ofu => pc_xu_decrem_dis_on_stop_ofu , - pc_xu_event_count_mode_ofu => pc_xu_event_count_mode_ofu , - pc_xu_extirpts_dis_on_stop_ofu => pc_xu_extirpts_dis_on_stop_ofu , - pc_xu_fce_3_ofu => pc_xu_fce_3_ofu , - pc_xu_force_ude_ofu => pc_xu_force_ude_ofu , - pc_xu_func_nsl_thold_3_ofu => pc_xu_func_nsl_thold_3_ofu , - pc_xu_func_sl_thold_3_ofu => pc_xu_func_sl_thold_3_ofu , - pc_xu_func_slp_nsl_thold_3_ofu => pc_xu_func_slp_nsl_thold_3_ofu , - pc_xu_func_slp_sl_thold_3_ofu => pc_xu_func_slp_sl_thold_3_ofu , - pc_xu_gptr_sl_thold_3_ofu => pc_xu_gptr_sl_thold_3_ofu , - pc_xu_init_reset_ofu => pc_xu_init_reset_ofu , - pc_xu_inj_dcache_parity_ofu => pc_xu_inj_dcache_parity_ofu , - pc_xu_inj_dcachedir_parity_ofu => pc_xu_inj_dcachedir_parity_ofu , - pc_xu_inj_llbust_attempt_ofu => pc_xu_inj_llbust_attempt_ofu , - pc_xu_inj_llbust_failed_ofu => pc_xu_inj_llbust_failed_ofu , - pc_xu_inj_sprg_ecc_ofu => pc_xu_inj_sprg_ecc_ofu , - pc_xu_inj_regfile_parity_ofu => pc_xu_inj_regfile_parity_ofu , - pc_xu_inj_wdt_reset_ofu => pc_xu_inj_wdt_reset_ofu , - pc_xu_inj_dcachedir_multihit_ofu => pc_xu_inj_dcachedir_multihit_ofu, - pc_xu_instr_trace_mode_ofu => pc_xu_instr_trace_mode_ofu , - pc_xu_instr_trace_tid_ofu => pc_xu_instr_trace_tid_ofu , - pc_xu_msrovride_enab_ofu => pc_xu_msrovride_enab_ofu , - pc_xu_msrovride_gs_ofu => pc_xu_msrovride_gs_ofu , - pc_xu_msrovride_pr_ofu => pc_xu_msrovride_pr_ofu , - pc_xu_ram_execute_ofu => pc_xu_ram_execute_ofu , - pc_xu_ram_flush_thread_ofu => pc_xu_ram_flush_thread_ofu , - pc_xu_ram_mode_ofu => pc_xu_ram_mode_ofu , - pc_xu_ram_thread_ofu => pc_xu_ram_thread_ofu , - pc_xu_repr_sl_thold_3_ofu => pc_xu_repr_sl_thold_3_ofu , - pc_xu_reset_1_cmplt_ofu => pc_xu_reset_1_cmplt_ofu , - pc_xu_reset_2_cmplt_ofu => pc_xu_reset_2_cmplt_ofu , - pc_xu_reset_3_cmplt_ofu => pc_xu_reset_3_cmplt_ofu , - pc_xu_reset_wd_cmplt_ofu => pc_xu_reset_wd_cmplt_ofu , - pc_xu_sg_3_ofu => pc_xu_sg_3_ofu , - pc_xu_step_ofu => pc_xu_step_ofu , - pc_xu_stop_ofu => pc_xu_stop_ofu , - pc_xu_time_sl_thold_3_ofu => pc_xu_time_sl_thold_3_ofu , - pc_xu_timebase_dis_on_stop_ofu => pc_xu_timebase_dis_on_stop_ofu , - pc_xu_trace_bus_enable_ofu => pc_xu_trace_bus_enable_ofu , - an_ac_scan_dis_dc_b_ofu => an_ac_scan_dis_dc_b_ofu, - an_ac_scan_diag_dc_ofu => an_ac_scan_diag_dc_ofu, - - xu_ex2_flush_ofu => xu_ex2_flush_ofu, - xu_ex3_flush_ofu => xu_ex3_flush_ofu, - xu_ex4_flush_ofu => xu_ex4_flush_ofu, - xu_ex5_flush_ofu => xu_ex5_flush_ofu, - an_ac_lbist_ary_wrt_thru_dc_ofu => an_ac_lbist_ary_wrt_thru_dc_ofu, - - xu_pc_err_mchk_disabled_ifu => xu_pc_err_mchk_disabled, - xu_pc_lsu_event_data_ifu => xu_pc_lsu_event_data, - xu_pc_err_mchk_disabled_ofu => xu_pc_err_mchk_disabled_ofu, - xu_pc_lsu_event_data_ofu => xu_pc_lsu_event_data_ofu, - - gnd => gnd, - vdd => vdd + xu_ex1_flush => xu_n_ex1_flush, + xu_ex2_flush => xu_n_ex2_flush, + xu_ex3_flush => xu_n_ex3_flush, + xu_ex4_flush => xu_n_ex4_flush, + xu_ex5_flush => xu_n_ex5_flush, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data(192 to 255), + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_is2_flush => xu_n_is2_flush, + xu_rf0_flush => xu_n_rf0_flush, + xu_rf1_flush => xu_n_rf1_flush, + abst_scan_out => fu_rp_abst_scan_out, + bcfg_scan_out => fu_rp_bcfg_scan_out, + ccfg_scan_out => fu_rp_ccfg_scan_out, + dcfg_scan_out => fu_rp_dcfg_scan_out, + func_scan_out => fu_rp_func_scan_out(0 to 3), + gptr_scan_out => fu_bx_gptr_scan_out, + repr_scan_out => fu_bx_repr_scan_out, + time_scan_out => fu_bx_time_scan_out, + debug_data_out => fu_pc_debug_data, + trace_triggers_out => fu_pc_trigger_data, + fu_iu_uc_special => fu_iu_uc_special, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + fu_xu_ex1_ifar => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr => fu_xu_ex4_cr, + fu_xu_ex4_cr_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + slowspr_addr_out => fu_bx_slowspr_addr, + slowspr_data_out => fu_bx_slowspr_data, + slowspr_done_out => fu_bx_slowspr_done, + slowspr_etid_out => fu_bx_slowspr_etid, + slowspr_rw_out => fu_bx_slowspr_rw, + slowspr_val_out => fu_bx_slowspr_val, + + bx_pc_err_inbox_ue_ifu => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue_ifu => bx_pc_err_outbox_ue, + bx_pc_err_inbox_ecc_ifu => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc_ifu => bx_pc_err_outbox_ecc, + pc_bx_bolt_sl_thold_3_ifu => pc_bx_bolt_sl_thold_3, + pc_bx_bo_enable_3_ifu => pc_bx_bo_enable_3, + pc_bx_bo_unload_ifu => pc_bx_bo_unload, + pc_bx_bo_repair_ifu => pc_bx_bo_repair, + pc_bx_bo_reset_ifu => pc_bx_bo_reset, + pc_bx_bo_shdata_ifu => pc_bx_bo_shdata, + pc_bx_bo_select_ifu => pc_bx_bo_select, + bx_pc_bo_fail_ifu => bx_pc_bo_fail, + bx_pc_bo_diagout_ifu => bx_pc_bo_diagout, + pc_bx_abist_di_0_ifu => pc_bx_abist_di_0, + pc_bx_abist_ena_dc_ifu => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0_ifu => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0_ifu => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1_ifu => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp_ifu => pc_bx_abist_g8t_dcomp, + pc_bx_abist_g8t_wenb_ifu => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0_ifu => pc_bx_abist_raddr_0(4 to 9), + pc_bx_abist_raw_dc_b_ifu => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0_ifu => pc_bx_abist_waddr_0(4 to 9), + pc_bx_abist_wl64_comp_ena_ifu => pc_bx_abist_wl64_comp_ena, + pc_bx_trace_bus_enable_ifu => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls_ifu => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc_ifu => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc_ifu => pc_bx_inj_outbox_ecc, + pc_bx_ccflush_dc_ifu => pc_bx_ccflush_dc, + pc_bx_sg_3_ifu => pc_bx_sg_3, + pc_bx_func_sl_thold_3_ifu => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3_ifu => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3_ifu => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3_ifu => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3_ifu => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3_ifu => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3_ifu => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3_ifu => pc_bx_ary_slp_nsl_thold_3, + + xu_pc_err_mcsr_summary_ifu => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity_ifu => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity_ifu => xu_pc_err_derat_parity, + xu_pc_err_tlb_parity_ifu => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity_ifu => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit_ifu => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit_ifu => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit_ifu => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk_ifu => xu_pc_err_ext_mchk, + xu_pc_err_ditc_overrun_ifu => xu_pc_err_ditc_overrun, + xu_pc_err_local_snoop_reject_ifu => xu_pc_err_local_snoop_reject, + xu_pc_err_attention_instr_ifu => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity_ifu => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_parity_ifu => xu_pc_err_dcachedir_parity, + xu_pc_err_dcachedir_multihit_ifu => xu_pc_err_dcachedir_multihit, + xu_pc_err_debug_event_ifu => xu_pc_err_debug_event, + xu_pc_err_invld_reld_ifu => xu_pc_err_invld_reld, + xu_pc_err_l2intrf_ecc_ifu => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue_ifu => xu_pc_err_l2intrf_ue, + xu_pc_err_l2credit_overrun_ifu => xu_pc_err_l2credit_overrun, + xu_pc_err_llbust_attempt_ifu => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed_ifu => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr_ifu => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity_ifu => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue_ifu => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc_ifu => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue_ifu => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset_ifu => xu_pc_err_wdt_reset, + xu_pc_event_data_ifu => xu_pc_event_data, + xu_pc_ram_data_ifu => xu_pc_ram_data, + xu_pc_ram_done_ifu => xu_pc_ram_done, + xu_pc_ram_interrupt_ifu => xu_pc_ram_interrupt, + xu_pc_running_ifu => xu_pc_running, + xu_pc_spr_ccr0_pme_ifu => xu_pc_spr_ccr0_pme, + xu_pc_spr_ccr0_we_ifu => xu_pc_spr_ccr0_we, + xu_pc_step_done_ifu => xu_pc_step_done, + xu_pc_stop_dbg_event_ifu => xu_pc_stop_dbg_event, + pc_xu_bolt_sl_thold_3_ifu => pc_xu_bolt_sl_thold_3, + pc_xu_bo_enable_3_ifu => pc_xu_bo_enable_3, + pc_xu_bo_unload_ifu => pc_xu_bo_unload, + pc_xu_bo_load_ifu => pc_xu_bo_load, + pc_xu_bo_repair_ifu => pc_xu_bo_repair, + pc_xu_bo_reset_ifu => pc_xu_bo_reset, + pc_xu_bo_shdata_ifu => pc_xu_bo_shdata, + pc_xu_bo_select_ifu => pc_xu_bo_select, + xu_pc_bo_fail_ifu => xu_pc_bo_fail, + xu_pc_bo_diagout_ifu => xu_pc_bo_diagout, + pc_xu_abist_dcomp_g6t_2r_ifu => pc_xu_abist_dcomp_g6t_2r, + pc_xu_abist_di_0_ifu => pc_xu_abist_di_0, + pc_xu_abist_di_1_ifu => pc_xu_abist_di_1, + pc_xu_abist_di_g6t_2r_ifu => pc_xu_abist_di_g6t_2r, + pc_xu_abist_ena_dc_ifu => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw_ifu => pc_xu_abist_g6t_bw, + pc_xu_abist_g6t_r_wb_ifu => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0_ifu => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0_ifu => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1_ifu => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp_ifu => pc_xu_abist_g8t_dcomp, + pc_xu_abist_g8t_wenb_ifu => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0_ifu => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1_ifu => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0_ifu => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1_ifu => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0_ifu => pc_xu_abist_raddr_0, + pc_xu_abist_raddr_1_ifu => pc_xu_abist_raddr_1, + pc_xu_abist_raw_dc_b_ifu => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0_ifu => pc_xu_abist_waddr_0, + pc_xu_abist_waddr_1_ifu => pc_xu_abist_waddr_1, + pc_xu_abist_wl144_comp_ena_ifu => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_comp_ena_ifu => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena_ifu => pc_xu_abist_wl512_comp_ena, + pc_xu_event_mux_ctrls_ifu => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls_ifu => pc_xu_lsu_event_mux_ctrls, + pc_xu_event_bus_enable_ifu => pc_xu_event_bus_enable, + pc_xu_abst_sl_thold_3_ifu => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3_ifu => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3_ifu => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3_ifu => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3_ifu => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3_ifu => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event_ifu => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc_ifu => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3_ifu => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3_ifu => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action_ifu => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls_ifu => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls_ifu => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls_ifu => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls_ifu => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop_ifu => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode_ifu => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop_ifu => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3_ifu => pc_xu_fce_3, + pc_xu_force_ude_ifu => pc_xu_force_ude, + pc_xu_func_nsl_thold_3_ifu => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3_ifu => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3_ifu => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3_ifu => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3_ifu => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset_ifu => pc_xu_init_reset, + pc_xu_inj_dcache_parity_ifu => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity_ifu => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt_ifu => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed_ifu => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc_ifu => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity_ifu => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset_ifu => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit_ifu => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode_ifu => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid_ifu => pc_xu_instr_trace_tid, + pc_xu_msrovride_enab_ifu => pc_xu_msrovride_enab, + pc_xu_msrovride_gs_ifu => pc_xu_msrovride_gs, + pc_xu_msrovride_pr_ifu => pc_xu_msrovride_pr, + pc_xu_ram_execute_ifu => pc_xu_ram_execute, + pc_xu_ram_flush_thread_ifu => pc_xu_ram_flush_thread, + pc_xu_ram_mode_ifu => pc_xu_ram_mode, + pc_xu_ram_thread_ifu => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3_ifu => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt_ifu => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt_ifu => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt_ifu => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt_ifu => pc_xu_reset_wd_complete, + pc_xu_sg_3_ifu => pc_xu_sg_3, + pc_xu_step_ifu => pc_xu_step, + pc_xu_stop_ifu => pc_xu_stop, + pc_xu_time_sl_thold_3_ifu => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop_ifu => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable_ifu => pc_xu_trace_bus_enable, + + bx_pc_err_inbox_ue_ofu => bx_pc_err_inbox_ue_ofu , + bx_pc_err_outbox_ue_ofu => bx_pc_err_outbox_ue_ofu, + bx_pc_err_inbox_ecc_ofu => bx_pc_err_inbox_ecc_ofu, + bx_pc_err_outbox_ecc_ofu => bx_pc_err_outbox_ecc_ofu, + pc_bx_bolt_sl_thold_3_ofu => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3_ofu => pc_bx_bo_enable_3_ofu , + pc_bx_bo_unload_ofu => pc_bx_bo_unload_ofu , + pc_bx_bo_repair_ofu => pc_bx_bo_repair_ofu , + pc_bx_bo_reset_ofu => pc_bx_bo_reset_ofu , + pc_bx_bo_shdata_ofu => pc_bx_bo_shdata_ofu , + pc_bx_bo_select_ofu => pc_bx_bo_select_ofu , + bx_pc_bo_fail_ofu => bx_pc_bo_fail_ofu , + bx_pc_bo_diagout_ofu => bx_pc_bo_diagout_ofu , + pc_bx_abist_di_0_ofu => pc_bx_abist_di_0_ofu , + pc_bx_abist_ena_dc_ofu => pc_bx_abist_ena_dc_ofu , + pc_bx_abist_g8t1p_renb_0_ofu => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0_ofu => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1_ofu => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp_ofu => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb_ofu => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0_ofu => pc_bx_abist_raddr_0_ofu, + pc_bx_abist_raw_dc_b_ofu => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0_ofu => pc_bx_abist_waddr_0_ofu, + pc_bx_abist_wl64_comp_ena_ofu => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_trace_bus_enable_ofu => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls_ofu => pc_bx_debug_mux1_ctrls_ofu, + pc_bx_inj_inbox_ecc_ofu => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc_ofu => pc_bx_inj_outbox_ecc_ofu, + pc_bx_ccflush_dc_ofu => pc_bx_ccflush_dc_ofu , + pc_bx_sg_3_ofu => pc_bx_sg_3_ofu , + pc_bx_func_sl_thold_3_ofu => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3_ofu => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3_ofu => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_time_sl_thold_3_ofu => pc_bx_time_sl_thold_3_ofu, + pc_bx_repr_sl_thold_3_ofu => pc_bx_repr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3_ofu => pc_bx_abst_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3_ofu => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3_ofu => pc_bx_ary_slp_nsl_thold_3_ofu, + + xu_pc_err_mcsr_summary_ofu => xu_pc_err_mcsr_summary_ofu , + xu_pc_err_ierat_parity_ofu => xu_pc_err_ierat_parity_ofu , + xu_pc_err_derat_parity_ofu => xu_pc_err_derat_parity_ofu , + xu_pc_err_tlb_parity_ofu => xu_pc_err_tlb_parity_ofu , + xu_pc_err_tlb_lru_parity_ofu => xu_pc_err_tlb_lru_parity_ofu , + xu_pc_err_ierat_multihit_ofu => xu_pc_err_ierat_multihit_ofu , + xu_pc_err_derat_multihit_ofu => xu_pc_err_derat_multihit_ofu , + xu_pc_err_tlb_multihit_ofu => xu_pc_err_tlb_multihit_ofu , + xu_pc_err_ext_mchk_ofu => xu_pc_err_ext_mchk_ofu , + xu_pc_err_ditc_overrun_ofu => xu_pc_err_ditc_overrun_ofu , + xu_pc_err_local_snoop_reject_ofu => xu_pc_err_local_snoop_reject_ofu , + xu_pc_err_attention_instr_ofu => xu_pc_err_attention_instr_ofu , + xu_pc_err_dcache_parity_ofu => xu_pc_err_dcache_parity_ofu , + xu_pc_err_dcachedir_parity_ofu => xu_pc_err_dcachedir_parity_ofu , + xu_pc_err_dcachedir_multihit_ofu => xu_pc_err_dcachedir_multihit_ofu , + xu_pc_err_debug_event_ofu => xu_pc_err_debug_event_ofu , + xu_pc_err_invld_reld_ofu => xu_pc_err_invld_reld_ofu , + xu_pc_err_l2intrf_ecc_ofu => xu_pc_err_l2intrf_ecc_ofu , + xu_pc_err_l2intrf_ue_ofu => xu_pc_err_l2intrf_ue_ofu , + xu_pc_err_l2credit_overrun_ofu => xu_pc_err_l2credit_overrun_ofu , + xu_pc_err_llbust_attempt_ofu => xu_pc_err_llbust_attempt_ofu , + xu_pc_err_llbust_failed_ofu => xu_pc_err_llbust_failed_ofu , + xu_pc_err_nia_miscmpr_ofu => xu_pc_err_nia_miscmpr_ofu , + xu_pc_err_regfile_parity_ofu => xu_pc_err_regfile_parity_ofu , + xu_pc_err_regfile_ue_ofu => xu_pc_err_regfile_ue_ofu , + xu_pc_err_sprg_ecc_ofu => xu_pc_err_sprg_ecc_ofu , + xu_pc_err_sprg_ue_ofu => xu_pc_err_sprg_ue_ofu , + xu_pc_err_wdt_reset_ofu => xu_pc_err_wdt_reset_ofu , + xu_pc_event_data_ofu => xu_pc_event_data_ofu , + xu_pc_ram_data_ofu => xu_pc_ram_data_ofu , + xu_pc_ram_done_ofu => xu_pc_ram_done_ofu , + xu_pc_ram_interrupt_ofu => xu_pc_ram_interrupt_ofu , + xu_pc_running_ofu => xu_pc_running_ofu , + xu_pc_spr_ccr0_pme_ofu => xu_pc_spr_ccr0_pme_ofu , + xu_pc_spr_ccr0_we_ofu => xu_pc_spr_ccr0_we_ofu , + xu_pc_step_done_ofu => xu_pc_step_done_ofu , + xu_pc_stop_dbg_event_ofu => xu_pc_stop_dbg_event_ofu , + pc_xu_bolt_sl_thold_3_ofu => pc_xu_bolt_sl_thold_3_ofu , + pc_xu_bo_enable_3_ofu => pc_xu_bo_enable_3_ofu , + pc_xu_bo_unload_ofu => pc_xu_bo_unload_ofu , + pc_xu_bo_load_ofu => pc_xu_bo_load_ofu , + pc_xu_bo_repair_ofu => pc_xu_bo_repair_ofu , + pc_xu_bo_reset_ofu => pc_xu_bo_reset_ofu , + pc_xu_bo_shdata_ofu => pc_xu_bo_shdata_ofu , + pc_xu_bo_select_ofu => pc_xu_bo_select_ofu , + xu_pc_bo_fail_ofu => xu_pc_bo_fail_ofu , + xu_pc_bo_diagout_ofu => xu_pc_bo_diagout_ofu , + pc_xu_abist_dcomp_g6t_2r_ofu => pc_xu_abist_dcomp_g6t_2r_ofu , + pc_xu_abist_di_0_ofu => pc_xu_abist_di_0_ofu , + pc_xu_abist_di_1_ofu => pc_xu_abist_di_1_ofu , + pc_xu_abist_di_g6t_2r_ofu => pc_xu_abist_di_g6t_2r_ofu , + pc_xu_abist_ena_dc_ofu => pc_xu_abist_ena_dc_ofu , + pc_xu_abist_g6t_bw_ofu => pc_xu_abist_g6t_bw_ofu , + pc_xu_abist_g6t_r_wb_ofu => pc_xu_abist_g6t_r_wb_ofu , + pc_xu_abist_g8t1p_renb_0_ofu => pc_xu_abist_g8t1p_renb_0_ofu , + pc_xu_abist_g8t_bw_0_ofu => pc_xu_abist_g8t_bw_0_ofu , + pc_xu_abist_g8t_bw_1_ofu => pc_xu_abist_g8t_bw_1_ofu , + pc_xu_abist_g8t_dcomp_ofu => pc_xu_abist_g8t_dcomp_ofu , + pc_xu_abist_g8t_wenb_ofu => pc_xu_abist_g8t_wenb_ofu , + pc_xu_abist_grf_renb_0_ofu => pc_xu_abist_grf_renb_0_ofu , + pc_xu_abist_grf_renb_1_ofu => pc_xu_abist_grf_renb_1_ofu , + pc_xu_abist_grf_wenb_0_ofu => pc_xu_abist_grf_wenb_0_ofu , + pc_xu_abist_grf_wenb_1_ofu => pc_xu_abist_grf_wenb_1_ofu , + pc_xu_abist_raddr_0_ofu => pc_xu_abist_raddr_0_ofu , + pc_xu_abist_raddr_1_ofu => pc_xu_abist_raddr_1_ofu , + pc_xu_abist_raw_dc_b_ofu => pc_xu_abist_raw_dc_b_ofu , + pc_xu_abist_waddr_0_ofu => pc_xu_abist_waddr_0_ofu , + pc_xu_abist_waddr_1_ofu => pc_xu_abist_waddr_1_ofu , + pc_xu_abist_wl144_comp_ena_ofu => pc_xu_abist_wl144_comp_ena_ofu , + pc_xu_abist_wl32_comp_ena_ofu => pc_xu_abist_wl32_comp_ena_ofu , + pc_xu_abist_wl512_comp_ena_ofu => pc_xu_abist_wl512_comp_ena_ofu , + pc_xu_event_mux_ctrls_ofu => pc_xu_event_mux_ctrls_ofu , + pc_xu_lsu_event_mux_ctrls_ofu => pc_xu_lsu_event_mux_ctrls_ofu , + pc_xu_event_bus_enable_ofu => pc_xu_event_bus_enable_ofu , + pc_xu_abst_sl_thold_3_ofu => pc_xu_abst_sl_thold_3_ofu , + pc_xu_abst_slp_sl_thold_3_ofu => pc_xu_abst_slp_sl_thold_3_ofu , + pc_xu_regf_sl_thold_3_ofu => pc_xu_regf_sl_thold_3_ofu , + pc_xu_regf_slp_sl_thold_3_ofu => pc_xu_regf_slp_sl_thold_3_ofu , + pc_xu_ary_nsl_thold_3_ofu => pc_xu_ary_nsl_thold_3_ofu , + pc_xu_ary_slp_nsl_thold_3_ofu => pc_xu_ary_slp_nsl_thold_3_ofu , + pc_xu_cache_par_err_event_ofu => pc_xu_cache_par_err_event_ofu , + pc_xu_ccflush_dc_ofu => pc_xu_ccflush_dc_ofu , + pc_xu_cfg_sl_thold_3_ofu => pc_xu_cfg_sl_thold_3_ofu , + pc_xu_cfg_slp_sl_thold_3_ofu => pc_xu_cfg_slp_sl_thold_3_ofu , + pc_xu_dbg_action_ofu => pc_xu_dbg_action_ofu , + pc_xu_debug_mux1_ctrls_ofu => pc_xu_debug_mux1_ctrls_ofu , + pc_xu_debug_mux2_ctrls_ofu => pc_xu_debug_mux2_ctrls_ofu , + pc_xu_debug_mux3_ctrls_ofu => pc_xu_debug_mux3_ctrls_ofu , + pc_xu_debug_mux4_ctrls_ofu => pc_xu_debug_mux4_ctrls_ofu , + pc_xu_decrem_dis_on_stop_ofu => pc_xu_decrem_dis_on_stop_ofu , + pc_xu_event_count_mode_ofu => pc_xu_event_count_mode_ofu , + pc_xu_extirpts_dis_on_stop_ofu => pc_xu_extirpts_dis_on_stop_ofu , + pc_xu_fce_3_ofu => pc_xu_fce_3_ofu , + pc_xu_force_ude_ofu => pc_xu_force_ude_ofu , + pc_xu_func_nsl_thold_3_ofu => pc_xu_func_nsl_thold_3_ofu , + pc_xu_func_sl_thold_3_ofu => pc_xu_func_sl_thold_3_ofu , + pc_xu_func_slp_nsl_thold_3_ofu => pc_xu_func_slp_nsl_thold_3_ofu , + pc_xu_func_slp_sl_thold_3_ofu => pc_xu_func_slp_sl_thold_3_ofu , + pc_xu_gptr_sl_thold_3_ofu => pc_xu_gptr_sl_thold_3_ofu , + pc_xu_init_reset_ofu => pc_xu_init_reset_ofu , + pc_xu_inj_dcache_parity_ofu => pc_xu_inj_dcache_parity_ofu , + pc_xu_inj_dcachedir_parity_ofu => pc_xu_inj_dcachedir_parity_ofu , + pc_xu_inj_llbust_attempt_ofu => pc_xu_inj_llbust_attempt_ofu , + pc_xu_inj_llbust_failed_ofu => pc_xu_inj_llbust_failed_ofu , + pc_xu_inj_sprg_ecc_ofu => pc_xu_inj_sprg_ecc_ofu , + pc_xu_inj_regfile_parity_ofu => pc_xu_inj_regfile_parity_ofu , + pc_xu_inj_wdt_reset_ofu => pc_xu_inj_wdt_reset_ofu , + pc_xu_inj_dcachedir_multihit_ofu => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode_ofu => pc_xu_instr_trace_mode_ofu , + pc_xu_instr_trace_tid_ofu => pc_xu_instr_trace_tid_ofu , + pc_xu_msrovride_enab_ofu => pc_xu_msrovride_enab_ofu , + pc_xu_msrovride_gs_ofu => pc_xu_msrovride_gs_ofu , + pc_xu_msrovride_pr_ofu => pc_xu_msrovride_pr_ofu , + pc_xu_ram_execute_ofu => pc_xu_ram_execute_ofu , + pc_xu_ram_flush_thread_ofu => pc_xu_ram_flush_thread_ofu , + pc_xu_ram_mode_ofu => pc_xu_ram_mode_ofu , + pc_xu_ram_thread_ofu => pc_xu_ram_thread_ofu , + pc_xu_repr_sl_thold_3_ofu => pc_xu_repr_sl_thold_3_ofu , + pc_xu_reset_1_cmplt_ofu => pc_xu_reset_1_cmplt_ofu , + pc_xu_reset_2_cmplt_ofu => pc_xu_reset_2_cmplt_ofu , + pc_xu_reset_3_cmplt_ofu => pc_xu_reset_3_cmplt_ofu , + pc_xu_reset_wd_cmplt_ofu => pc_xu_reset_wd_cmplt_ofu , + pc_xu_sg_3_ofu => pc_xu_sg_3_ofu , + pc_xu_step_ofu => pc_xu_step_ofu , + pc_xu_stop_ofu => pc_xu_stop_ofu , + pc_xu_time_sl_thold_3_ofu => pc_xu_time_sl_thold_3_ofu , + pc_xu_timebase_dis_on_stop_ofu => pc_xu_timebase_dis_on_stop_ofu , + pc_xu_trace_bus_enable_ofu => pc_xu_trace_bus_enable_ofu , + an_ac_scan_dis_dc_b_ofu => an_ac_scan_dis_dc_b_ofu, + an_ac_scan_diag_dc_ofu => an_ac_scan_diag_dc_ofu, + + xu_ex2_flush_ofu => xu_ex2_flush_ofu, + xu_ex3_flush_ofu => xu_ex3_flush_ofu, + xu_ex4_flush_ofu => xu_ex4_flush_ofu, + xu_ex5_flush_ofu => xu_ex5_flush_ofu, + an_ac_lbist_ary_wrt_thru_dc_ofu => an_ac_lbist_ary_wrt_thru_dc_ofu, + + xu_pc_err_mchk_disabled_ifu => xu_pc_err_mchk_disabled, + xu_pc_lsu_event_data_ifu => xu_pc_lsu_event_data, + xu_pc_err_mchk_disabled_ofu => xu_pc_err_mchk_disabled_ofu, + xu_pc_lsu_event_data_ofu => xu_pc_lsu_event_data_ofu, + + gnd => gnd, + vdd => vdd ); - -a_iuq: entity work.iuq - generic map(expand_type => expand_type, - bcfg_epn_0to15 => bcfg_epn_0to15, - bcfg_epn_16to31 => bcfg_epn_16to31, - bcfg_epn_32to47 => bcfg_epn_32to47, - bcfg_epn_48to51 => bcfg_epn_48to51, - bcfg_rpn_22to31 => bcfg_rpn_22to31, - bcfg_rpn_32to47 => bcfg_rpn_32to47, - bcfg_rpn_48to51 => bcfg_rpn_48to51, - fpr_addr_width => fpr_addr_width, - lmq_entries => lmq_entries, - regmode => regmode, - threads => threads, - ucode_mode => ucode_mode) - port map ( - abst_scan_in => an_ac_abst_scan_in_omm_iu(0 to 2), - bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit3, - ccfg_scan_in => mm_iu_ccfg_scan_out, - dcfg_scan_in => an_ac_dcfg_scan_in_omm(1), - func_scan_in => an_ac_func_scan_in_omm_iua(6 to 19), - gptr_scan_in => an_ac_gptr_scan_in_omm, - repr_scan_in => an_ac_repr_scan_in_omm, - time_scan_in => an_ac_time_scan_in_omm, - regf_scan_in => an_ac_regf_scan_in_omm(0 to 4), - debug_data_in => pc_iu_debug_data, - trace_triggers_in => pc_iu_trigger_data, - an_ac_back_inv => an_ac_back_inv_omm, - an_ac_back_inv_addr => an_ac_back_inv_addr_omm(real_ifar'left to 63), - an_ac_back_inv_target_iiu_a => an_ac_back_inv_target_omm_iua, - an_ac_back_inv_target_iiu_b => an_ac_back_inv_target_omm_iub, - an_ac_grffence_en_dc => an_ac_camfence_en_dc_omm, - an_ac_icbi_ack => an_ac_icbi_ack_omm, - an_ac_icbi_ack_thread => an_ac_icbi_ack_thread_omm, - an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_omm, - an_ac_reld_core_tag => xu_iu_reld_core_tag, - an_ac_reld_data => xu_iu_reld_data, - an_ac_reld_data_vld => xu_iu_reld_data_vld, - an_ac_reld_data_coming_clone => xu_iu_reld_data_coming_clone, - an_ac_reld_ditc_clone => xu_iu_reld_ditc_clone, - an_ac_reld_ecc_err => xu_iu_reld_ecc_err, - an_ac_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, - an_ac_reld_qw => xu_iu_reld_qw, - an_ac_reld_data_vld_clone => xu_iu_reld_data_vld_clone, - an_ac_reld_core_tag_clone => xu_iu_reld_core_tag_clone, - an_ac_scan_diag_dc => an_ac_scan_diag_dc_omm, - an_ac_stcx_complete => xu_iu_stcx_complete, - an_ac_sync_ack => an_ac_sync_ack_omm, - fu_iu_uc_special => fu_iu_uc_special, - mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, - mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, - mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, - mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, - mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, - mm_iu_ierat_pid0 => mm_iu_ierat_pid0, - mm_iu_ierat_pid1 => mm_iu_ierat_pid1, - mm_iu_ierat_pid2 => mm_iu_ierat_pid2, - mm_iu_ierat_pid3 => mm_iu_ierat_pid3, - mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, - mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, - mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, - mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, - mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, - mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, - slowspr_addr_in => mm_iu_slowspr_addr, - slowspr_data_in => mm_iu_slowspr_data, - slowspr_done_in => mm_iu_slowspr_done, - slowspr_etid_in => mm_iu_slowspr_etid, - slowspr_rw_in => mm_iu_slowspr_rw, - slowspr_val_in => mm_iu_slowspr_val, - nclk => a2_nclk, - pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), - pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), - pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), - pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, - pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), - pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, - pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, - pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, - pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, - pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), - pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, - pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), - pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, - pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), - pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, - pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, - pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, - pc_iu_bo_enable_4 => pc_iu_bo_enable_4, - pc_iu_bo_reset => pc_iu_bo_reset, - pc_iu_bo_unload => pc_iu_bo_unload, - pc_iu_bo_repair => pc_iu_bo_repair, - pc_iu_bo_shdata => pc_iu_bo_shdata, - pc_iu_bo_select => pc_iu_bo_select, - pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, - pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, - pc_iu_event_bus_enable => pc_iu_event_bus_enable, - pc_iu_event_count_mode => pc_iu_event_count_mode, - pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, - pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, - pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, - pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, - pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, - pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, - pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, - pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, - pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, - pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, - pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, - pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, - pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, - pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, - pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, - pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, - pc_iu_sg_4 => pc_iu_sg_4, - pc_iu_fce_4 => pc_iu_fce_4, - pc_iu_init_reset => pc_iu_init_reset, - pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, - pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, - pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, - pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, - pc_iu_ram_instr => pc_iu_ram_instr, - pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, - pc_iu_ram_mode => pc_iu_ram_mode, - pc_iu_ram_thread => pc_iu_ram_thread, - pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, - tc_ac_ccflush_dc => pc_iu_ccflush_dc, - an_ac_lbist_en_dc => an_ac_lbist_en_dc_omm, - an_ac_atpg_en_dc => an_ac_atpg_en_dc_omm, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_omm, - xu_iu_complete_qentry => xu_iu_complete_qentry, - xu_iu_complete_target_type => xu_iu_complete_target_type, - xu_iu_complete_tid => xu_iu_complete_tid, - xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, - xu_iu_ex1_rb => xu_iu_ex1_rb, - xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, - xu_iu_ex5_bclr => xu_iu_ex5_bclr, - xu_iu_ex5_bh => xu_iu_ex5_bh, - xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, - xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, - xu_iu_ex5_br_update => xu_iu_ex5_br_update, - xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, - xu_iu_ex5_gshare => xu_iu_ex5_gshare, - xu_iu_ex5_ifar => xu_iu_ex5_ifar, - xu_iu_ex5_lk => xu_iu_ex5_lk, - xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, - xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, - xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, - xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, - xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, - xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, - xu_iu_ex5_tid => xu_iu_ex5_tid, - xu_iu_ex5_val => xu_iu_ex5_val, - xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, - xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, - xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, - xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, - xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, - xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, - xu_iu_ex6_pri => xu_iu_ex6_pri, - xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, - xu_iu_flush_2ucode => xu_iu_flush_2ucode, - xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, - xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, - xu_iu_xucr0_rel => xu_iu_xucr0_rel, - xu_iu_ici => xu_iu_ici, - xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, - xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, - xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, - xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, - xu_iu_larx_done_tid => xu_iu_larx_done_tid, - xu_iu_membar_tid => xu_iu_membar_tid, - xu_iu_msr_cm => xu_iu_msr_cm, - xu_iu_msr_gs => xu_iu_msr_gs, - xu_iu_msr_hv => xu_iu_msr_hv, - xu_iu_msr_is => xu_iu_msr_is, - xu_iu_msr_pr => xu_iu_msr_pr, - xu_iu_multdiv_done => xu_iu_multdiv_done, - xu_iu_need_hole => xu_iu_need_hole, - xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, - xu_iu_ram_issue => xu_iu_ram_issue, - xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, - xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, - xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, - xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, - xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, - xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, - xu_iu_rf1_val => xu_iu_rf1_val, - xu_iu_rf1_ws => xu_iu_rf1_ws, - xu_iu_rf1_t => xu_iu_rf1_t, - xu_iu_run_thread => xu_iu_run_thread, - xu_iu_set_barr_tid => xu_iu_set_barr_tid, - xu_iu_single_instr_mode => xu_iu_single_instr_mode, - xu_iu_slowspr_done => xu_iu_slowspr_done, - xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, - xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, - xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, - xu_iu_spr_xer0 => xu_iu_spr_xer0, - xu_iu_spr_xer1 => xu_iu_spr_xer1, - xu_iu_spr_xer2 => xu_iu_spr_xer2, - xu_iu_spr_xer3 => xu_iu_spr_xer3, - xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, - xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, - xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, - xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, - xu_iu_ucode_restart => xu_iu_ucode_restart, - abst_scan_out(0 to 1) => ac_an_abst_scan_out_imm_iu(0 to 1), - abst_scan_out(2) => iu_pc_abst_scan_out, - bcfg_scan_out => iu_fu_bcfg_scan_out, - ccfg_scan_out => iu_pc_ccfg_scan_out, - dcfg_scan_out => iu_fu_dcfg_scan_out, - func_scan_out => ac_an_func_scan_out_imm_iua(6 to 19), - gptr_scan_out => iu_pc_gptr_scan_out, - repr_scan_out => iu_fu_repr_scan_out, - time_scan_out => iu_fu_time_scan_out, - regf_scan_out => ac_an_regf_scan_out_imm(0 to 4), - debug_data_out => iu_xu_debug_data, - trace_triggers_out => iu_xu_trigger_data, - iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, - iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, - iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, - iu_fu_rf0_fra => iu_fu_rf0_fra, - iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, - iu_fu_rf0_frb => iu_fu_rf0_frb, - iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, - iu_fu_rf0_frc => iu_fu_rf0_frc, - iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, - iu_fu_rf0_frt => iu_fu_rf0_frt, - iu_fu_rf0_ifar => iu_fu_rf0_ifar, - iu_fu_rf0_instr => iu_fu_rf0_instr, - iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, - iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, - iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, - iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, - iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, - iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, - iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, - iu_fu_rf0_str_val => iu_fu_rf0_str_val, - iu_fu_rf0_tid => iu_fu_rf0_tid, - iu_mm_ierat_epn => iu_mm_ierat_epn, - iu_mm_ierat_flush => iu_mm_ierat_flush, - iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, - iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, - iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, - iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, - iu_mm_ierat_req => iu_mm_ierat_req, - iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, - iu_mm_ierat_thdid => iu_mm_ierat_thdid, - iu_mm_ierat_tid => iu_mm_ierat_tid, - iu_mm_ierat_state => iu_mm_ierat_state, - iu_mm_lmq_empty => iu_mm_lmq_empty, - mm_iu_barrier_done => mm_iu_barrier_done, - iu_pc_bo_fail => iu_pc_bo_fail, - iu_pc_bo_diagout => iu_pc_bo_diagout, - iu_pc_err_icache_parity => iu_pc_err_icache_parity, - iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, - iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, - iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, - iu_pc_event_data => iu_pc_event_data, - slowspr_addr_out => iu_pc_slowspr_addr, - slowspr_data_out => iu_pc_slowspr_data, - slowspr_done_out => iu_pc_slowspr_done, - slowspr_etid_out => iu_pc_slowspr_etid, - slowspr_rw_out => iu_pc_slowspr_rw, - slowspr_val_out => iu_pc_slowspr_val, - iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, - iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, - iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, - iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, - iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, - iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, - iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, - iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, - iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, - iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, - iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, - iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, - iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, - iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, - iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, - iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, - iu_xu_is2_axu_store => iu_xu_is2_axu_store, - iu_xu_is2_error => iu_xu_is2_error, - iu_xu_is2_gshare => iu_xu_is2_gshare, - iu_xu_is2_ifar => iu_xu_is2_ifar, - iu_xu_is2_instr => iu_xu_is2_instr, - iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, - iu_xu_is2_match => iu_xu_is2_match, - iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, - iu_xu_is2_pred_update => iu_xu_is2_pred_update, - iu_xu_is2_s1 => iu_xu_is2_s1, - iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, - iu_xu_is2_s2 => iu_xu_is2_s2, - iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, - iu_xu_is2_s3 => iu_xu_is2_s3, - iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, - iu_xu_is2_ta => iu_xu_is2_ta, - iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, - iu_xu_is2_tid => iu_xu_is2_tid, - iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, - iu_xu_is2_vld => iu_xu_is2_vld, - iu_xu_quiesce => iu_xu_quiesce, - iu_xu_ra => iu_xu_ra, - iu_xu_request => iu_xu_request, - iu_xu_thread => iu_xu_thread, - iu_xu_userdef => iu_xu_userdef, - iu_xu_wimge => iu_xu_wimge, - - rtim_sl_thold_7 => an_ac_rtim_sl_thold_7_omm, - func_sl_thold_7 => an_ac_func_sl_thold_7_omm, - func_nsl_thold_7 => an_ac_func_nsl_thold_7_omm, - ary_nsl_thold_7 => an_ac_ary_nsl_thold_7_omm, - sg_7 => an_ac_sg_7_omm, - fce_7 => an_ac_fce_7_omm, - rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, - func_sl_thold_6 => rp_pc_func_sl_thold_6, - func_nsl_thold_6 => rp_pc_func_nsl_thold_6, - ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, - sg_6 => rp_pc_sg_6, - fce_6 => rp_pc_fce_6, - an_ac_scom_dch => an_ac_scom_dch_omm, - an_ac_scom_cch => an_ac_scom_cch_omm, - an_ac_checkstop => an_ac_checkstop_omm, - an_ac_debug_stop => an_ac_debug_stop_omm, - an_ac_pm_thread_stop => an_ac_pm_thread_stop_omm, - an_ac_reset_1_complete => an_ac_reset_1_complete_omm, - an_ac_reset_2_complete => an_ac_reset_2_complete_omm, - an_ac_reset_3_complete => an_ac_reset_3_complete_omm, - an_ac_reset_wd_complete => an_ac_reset_wd_complete_omm, - an_ac_abist_start_test => an_ac_abist_start_test_omm, - ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, - rp_pc_scom_dch_q => rp_pc_scom_dch_q, - rp_pc_scom_cch_q => rp_pc_scom_cch_q, - rp_pc_checkstop_q => rp_pc_checkstop_q, - rp_pc_debug_stop_q => rp_pc_debug_stop_q, - rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, - rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, - rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, - rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, - rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, - rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, - rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, - pc_rp_scom_dch => pc_rp_scom_dch, - pc_rp_scom_cch => pc_rp_scom_cch, - pc_rp_special_attn => pc_rp_special_attn, - pc_rp_checkstop => pc_rp_checkstop, - pc_rp_local_checkstop => pc_rp_local_checkstop, - pc_rp_recov_err => pc_rp_recov_err, - pc_rp_trace_error => pc_rp_trace_error, - pc_rp_event_bus_enable => pc_rp_event_bus_enable, - pc_rp_event_bus => pc_rp_event_bus, - pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, - pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, - pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, - pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, - pc_rp_pm_thread_running => pc_rp_pm_thread_running, - pc_rp_power_managed => pc_rp_power_managed, - pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, - ac_an_scom_dch_q => ac_an_scom_dch_imm, - ac_an_scom_cch_q => ac_an_scom_cch_imm, - ac_an_special_attn_q => ac_an_special_attn_imm, - ac_an_checkstop_q => ac_an_checkstop_imm, - ac_an_local_checkstop_q => ac_an_local_checkstop_imm, - ac_an_recov_err_q => ac_an_recov_err_imm, - ac_an_trace_error_q => ac_an_trace_error_imm, - rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, - ac_an_event_bus_q => ac_an_event_bus_imm, - ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_imm, - ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_imm, - ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_imm, - ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_imm, - ac_an_pm_thread_running_q => ac_an_pm_thread_running_imm, - ac_an_power_managed_q => ac_an_power_managed_int, - ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_imm, - - pc_func_scan_in => an_ac_func_scan_in_omm_iua(0 to 1), - pc_func_scan_in_q => rp_pc_func_scan_in_q(0 to 1), - pc_func_scan_out => pc_rp_func_scan_out(1), - pc_func_scan_out_q => ac_an_func_scan_out_imm_iua(1), - pc_bcfg_scan_in => mm_rp_bcfg_scan_out, - pc_bcfg_scan_in_q => rp_pc_bcfg_scan_out_q, - pc_dcfg_scan_in => mm_rp_dcfg_scan_out, - pc_dcfg_scan_in_q => rp_pc_dcfg_scan_out_q, - pc_bcfg_scan_out => pc_rp_bcfg_scan_out, - pc_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(2), - pc_ccfg_scan_out => pc_rp_ccfg_scan_out, - pc_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(0), - pc_dcfg_scan_out => pc_rp_dcfg_scan_out, - pc_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(0), - fu_abst_scan_in => an_ac_abst_scan_in_omm_iu(3), - fu_abst_scan_in_q => rp_fu_abst_scan_in_q, - fu_abst_scan_out => fu_rp_abst_scan_out, - fu_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(3), - fu_bcfg_scan_out => fu_rp_bcfg_scan_out, - fu_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(3), - fu_ccfg_scan_out => fu_rp_ccfg_scan_out, - fu_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(1), - fu_dcfg_scan_out => fu_rp_dcfg_scan_out, - fu_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(1), - fu_func_scan_in => an_ac_func_scan_in_omm_iua(2 to 5), - fu_func_scan_in_q => rp_fu_func_scan_in_q(0 to 3), - fu_func_scan_out => fu_rp_func_scan_out(0 to 3), - fu_func_scan_out_q => ac_an_func_scan_out_imm_iua(2 to 5), - bx_abst_scan_in => an_ac_abst_scan_in_omm_iu(4), - bx_abst_scan_in_q => rp_bx_abst_scan_in_q, - bx_abst_scan_out => bx_rp_abst_scan_out, - bx_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(4), - bx_func_scan_in => an_ac_func_scan_in_omm_iua(20 to 21), - bx_func_scan_in_q => rp_bx_func_scan_in_q(0 to 1), - bx_func_scan_out => bx_rp_func_scan_out(0 to 1), - bx_func_scan_out_q => ac_an_func_scan_out_imm_iua(20 to 21), - spare_func_scan_in => an_ac_func_scan_in_omm_iub(60 to 63), - spare_func_scan_out_q => ac_an_func_scan_out_imm_iub(60 to 63), + +a_iuq: entity work.iuq + generic map(expand_type => expand_type, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + fpr_addr_width => fpr_addr_width, + lmq_entries => lmq_entries, + regmode => regmode, + threads => threads, + ucode_mode => ucode_mode) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_iu(0 to 2), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit3, + ccfg_scan_in => mm_iu_ccfg_scan_out, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(1), + func_scan_in => an_ac_func_scan_in_omm_iua(6 to 19), + gptr_scan_in => an_ac_gptr_scan_in_omm, + repr_scan_in => an_ac_repr_scan_in_omm, + time_scan_in => an_ac_time_scan_in_omm, + regf_scan_in => an_ac_regf_scan_in_omm(0 to 4), + debug_data_in => pc_iu_debug_data, + trace_triggers_in => pc_iu_trigger_data, + an_ac_back_inv => an_ac_back_inv_omm, + an_ac_back_inv_addr => an_ac_back_inv_addr_omm(real_ifar'left to 63), + an_ac_back_inv_target_iiu_a => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_iiu_b => an_ac_back_inv_target_omm_iub, + an_ac_grffence_en_dc => an_ac_camfence_en_dc_omm, + an_ac_icbi_ack => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread_omm, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_reld_core_tag => xu_iu_reld_core_tag, + an_ac_reld_data => xu_iu_reld_data, + an_ac_reld_data_vld => xu_iu_reld_data_vld, + an_ac_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + an_ac_reld_ditc_clone => xu_iu_reld_ditc_clone, + an_ac_reld_ecc_err => xu_iu_reld_ecc_err, + an_ac_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + an_ac_reld_qw => xu_iu_reld_qw, + an_ac_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + an_ac_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_omm, + an_ac_stcx_complete => xu_iu_stcx_complete, + an_ac_sync_ack => an_ac_sync_ack_omm, + fu_iu_uc_special => fu_iu_uc_special, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_in => mm_iu_slowspr_addr, + slowspr_data_in => mm_iu_slowspr_data, + slowspr_done_in => mm_iu_slowspr_done, + slowspr_etid_in => mm_iu_slowspr_etid, + slowspr_rw_in => mm_iu_slowspr_rw, + slowspr_val_in => mm_iu_slowspr_val, + nclk => a2_nclk, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + tc_ac_ccflush_dc => pc_iu_ccflush_dc, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_omm, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_omm, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_omm, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + abst_scan_out(0 to 1) => ac_an_abst_scan_out_imm_iu(0 to 1), + abst_scan_out(2) => iu_pc_abst_scan_out, + bcfg_scan_out => iu_fu_bcfg_scan_out, + ccfg_scan_out => iu_pc_ccfg_scan_out, + dcfg_scan_out => iu_fu_dcfg_scan_out, + func_scan_out => ac_an_func_scan_out_imm_iua(6 to 19), + gptr_scan_out => iu_pc_gptr_scan_out, + repr_scan_out => iu_fu_repr_scan_out, + time_scan_out => iu_fu_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(0 to 4), + debug_data_out => iu_xu_debug_data, + trace_triggers_out => iu_xu_trigger_data, + iu_fu_ex2_n_flush => iu_fu_ex2_n_flush, + iu_fu_is2_tid_decode => iu_fu_is2_tid_decode, + iu_fu_rf0_bypsel => iu_fu_rf0_bypsel, + iu_fu_rf0_fra => iu_fu_rf0_fra, + iu_fu_rf0_fra_v => iu_fu_rf0_fra_v, + iu_fu_rf0_frb => iu_fu_rf0_frb, + iu_fu_rf0_frb_v => iu_fu_rf0_frb_v, + iu_fu_rf0_frc => iu_fu_rf0_frc, + iu_fu_rf0_frc_v => iu_fu_rf0_frc_v, + iu_fu_rf0_frt => iu_fu_rf0_frt, + iu_fu_rf0_ifar => iu_fu_rf0_ifar, + iu_fu_rf0_instr => iu_fu_rf0_instr, + iu_fu_rf0_instr_match => iu_fu_rf0_instr_match, + iu_fu_rf0_instr_v => iu_fu_rf0_instr_v, + iu_fu_rf0_is_ucode => iu_fu_rf0_is_ucode, + iu_fu_rf0_ucfmul => iu_fu_rf0_ucfmul, + iu_fu_rf0_ldst_val => iu_fu_rf0_ldst_val, + iu_fu_rf0_ldst_tid => iu_fu_rf0_ldst_tid, + iu_fu_rf0_ldst_tag => iu_fu_rf0_ldst_tag, + iu_fu_rf0_str_val => iu_fu_rf0_str_val, + iu_fu_rf0_tid => iu_fu_rf0_tid, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + mm_iu_barrier_done => mm_iu_barrier_done, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_out => iu_pc_slowspr_addr, + slowspr_data_out => iu_pc_slowspr_data, + slowspr_done_out => iu_pc_slowspr_done, + slowspr_etid_out => iu_pc_slowspr_etid, + slowspr_rw_out => iu_pc_slowspr_rw, + slowspr_val_out => iu_pc_slowspr_val, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + + rtim_sl_thold_7 => an_ac_rtim_sl_thold_7_omm, + func_sl_thold_7 => an_ac_func_sl_thold_7_omm, + func_nsl_thold_7 => an_ac_func_nsl_thold_7_omm, + ary_nsl_thold_7 => an_ac_ary_nsl_thold_7_omm, + sg_7 => an_ac_sg_7_omm, + fce_7 => an_ac_fce_7_omm, + rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + func_sl_thold_6 => rp_pc_func_sl_thold_6, + func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + sg_6 => rp_pc_sg_6, + fce_6 => rp_pc_fce_6, + an_ac_scom_dch => an_ac_scom_dch_omm, + an_ac_scom_cch => an_ac_scom_cch_omm, + an_ac_checkstop => an_ac_checkstop_omm, + an_ac_debug_stop => an_ac_debug_stop_omm, + an_ac_pm_thread_stop => an_ac_pm_thread_stop_omm, + an_ac_reset_1_complete => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete => an_ac_reset_wd_complete_omm, + an_ac_abist_start_test => an_ac_abist_start_test_omm, + ac_rp_trace_to_perfcntr => ac_rp_trace_to_perfcntr, + rp_pc_scom_dch_q => rp_pc_scom_dch_q, + rp_pc_scom_cch_q => rp_pc_scom_cch_q, + rp_pc_checkstop_q => rp_pc_checkstop_q, + rp_pc_debug_stop_q => rp_pc_debug_stop_q, + rp_pc_pm_thread_stop_q => rp_pc_pm_thread_stop_q, + rp_pc_reset_1_complete_q => rp_pc_reset_1_complete_q, + rp_pc_reset_2_complete_q => rp_pc_reset_2_complete_q, + rp_pc_reset_3_complete_q => rp_pc_reset_3_complete_q, + rp_pc_reset_wd_complete_q => rp_pc_reset_wd_complete_q, + rp_pc_abist_start_test_q => rp_pc_abist_start_test_q, + rp_pc_trace_to_perfcntr_q => rp_pc_trace_to_perfcntr_q, + pc_rp_scom_dch => pc_rp_scom_dch, + pc_rp_scom_cch => pc_rp_scom_cch, + pc_rp_special_attn => pc_rp_special_attn, + pc_rp_checkstop => pc_rp_checkstop, + pc_rp_local_checkstop => pc_rp_local_checkstop, + pc_rp_recov_err => pc_rp_recov_err, + pc_rp_trace_error => pc_rp_trace_error, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_rp_event_bus => pc_rp_event_bus, + pc_rp_fu_bypass_events => pc_rp_fu_bypass_events, + pc_rp_iu_bypass_events => pc_rp_iu_bypass_events, + pc_rp_mm_bypass_events => pc_rp_mm_bypass_events, + pc_rp_lsu_bypass_events => pc_rp_lsu_bypass_events, + pc_rp_pm_thread_running => pc_rp_pm_thread_running, + pc_rp_power_managed => pc_rp_power_managed, + pc_rp_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_scom_dch_q => ac_an_scom_dch_imm, + ac_an_scom_cch_q => ac_an_scom_cch_imm, + ac_an_special_attn_q => ac_an_special_attn_imm, + ac_an_checkstop_q => ac_an_checkstop_imm, + ac_an_local_checkstop_q => ac_an_local_checkstop_imm, + ac_an_recov_err_q => ac_an_recov_err_imm, + ac_an_trace_error_q => ac_an_trace_error_imm, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + ac_an_event_bus_q => ac_an_event_bus_imm, + ac_an_fu_bypass_events_q => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_q => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_q => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_q => ac_an_lsu_bypass_events_imm, + ac_an_pm_thread_running_q => ac_an_pm_thread_running_imm, + ac_an_power_managed_q => ac_an_power_managed_int, + ac_an_rvwinkle_mode_q => ac_an_rvwinkle_mode_imm, + + pc_func_scan_in => an_ac_func_scan_in_omm_iua(0 to 1), + pc_func_scan_in_q => rp_pc_func_scan_in_q(0 to 1), + pc_func_scan_out => pc_rp_func_scan_out(1), + pc_func_scan_out_q => ac_an_func_scan_out_imm_iua(1), + pc_bcfg_scan_in => mm_rp_bcfg_scan_out, + pc_bcfg_scan_in_q => rp_pc_bcfg_scan_out_q, + pc_dcfg_scan_in => mm_rp_dcfg_scan_out, + pc_dcfg_scan_in_q => rp_pc_dcfg_scan_out_q, + pc_bcfg_scan_out => pc_rp_bcfg_scan_out, + pc_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(2), + pc_ccfg_scan_out => pc_rp_ccfg_scan_out, + pc_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(0), + pc_dcfg_scan_out => pc_rp_dcfg_scan_out, + pc_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(0), + fu_abst_scan_in => an_ac_abst_scan_in_omm_iu(3), + fu_abst_scan_in_q => rp_fu_abst_scan_in_q, + fu_abst_scan_out => fu_rp_abst_scan_out, + fu_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(3), + fu_bcfg_scan_out => fu_rp_bcfg_scan_out, + fu_bcfg_scan_out_q => ac_an_bcfg_scan_out_imm(3), + fu_ccfg_scan_out => fu_rp_ccfg_scan_out, + fu_ccfg_scan_out_q => ac_an_bcfg_scan_out_imm(1), + fu_dcfg_scan_out => fu_rp_dcfg_scan_out, + fu_dcfg_scan_out_q => ac_an_dcfg_scan_out_imm(1), + fu_func_scan_in => an_ac_func_scan_in_omm_iua(2 to 5), + fu_func_scan_in_q => rp_fu_func_scan_in_q(0 to 3), + fu_func_scan_out => fu_rp_func_scan_out(0 to 3), + fu_func_scan_out_q => ac_an_func_scan_out_imm_iua(2 to 5), + bx_abst_scan_in => an_ac_abst_scan_in_omm_iu(4), + bx_abst_scan_in_q => rp_bx_abst_scan_in_q, + bx_abst_scan_out => bx_rp_abst_scan_out, + bx_abst_scan_out_q => ac_an_abst_scan_out_imm_iu(4), + bx_func_scan_in => an_ac_func_scan_in_omm_iua(20 to 21), + bx_func_scan_in_q => rp_bx_func_scan_in_q(0 to 1), + bx_func_scan_out => bx_rp_func_scan_out(0 to 1), + bx_func_scan_out_q => ac_an_func_scan_out_imm_iua(20 to 21), + spare_func_scan_in => an_ac_func_scan_in_omm_iub(60 to 63), + spare_func_scan_out_q => ac_an_func_scan_out_imm_iub(60 to 63), rp_abst_scan_in => pc_rp_abst_scan_out, rp_func_scan_in => pc_rp_func_scan_out(0), rp_abst_scan_out => ac_an_abst_scan_out_imm_iu(2), rp_func_scan_out => ac_an_func_scan_out_imm_iua(0), - - an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_omm, - an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_omm, - an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_omm, - an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_omm, - an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_omm, - an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_omm, - an_ac_malf_alert_iiu => an_ac_malf_alert_omm, - an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_omm, - an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_omm, - an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_omm, - - an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, - an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, - an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, - an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, - an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, - an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, - an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, - an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, - an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, - an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, - - an_ac_back_inv_oiu => an_ac_back_inv_oiu, - an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, - an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, - an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, - an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, - an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, - an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, - an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, - an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, - an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, - - - - ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, - ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, - an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, - mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, - mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, - mm_pc_event_data_iiu => mm_pc_event_data_iiu, - - ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, - ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, - an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, - mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, - mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, - mm_pc_event_data_oiu => mm_pc_event_data_oiu, - - pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, - pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, - pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, - pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, - pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, - pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, - pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, - pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, - pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, - pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, - pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, - pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, - pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, - pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, - pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, - pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, - pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, - pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, - pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, - pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, - pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, - pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, - pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, - pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, - pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, - pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, - pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, - pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, - pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, - pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, - pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, - pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, - pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, - pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, - pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, - pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, - pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, - pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, - pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, - pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, - pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, - pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, - pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, - pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, - pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, - pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, - pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, - pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, - pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, - pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, - pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, - pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, - pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, - pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, - pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, - pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, - pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, - pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, - pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, - pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, - pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, - pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, - pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, - pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, - pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, - pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, - + + an_ac_abist_mode_dc_iiu => an_ac_abist_mode_dc_omm, + an_ac_ccflush_dc_iiu => an_ac_ccflush_dc_omm, + an_ac_gsd_test_enable_dc_iiu => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_iiu => an_ac_gsd_test_acmode_dc_omm, + an_ac_lbist_ip_dc_iiu => an_ac_lbist_ip_dc_omm, + an_ac_lbist_ac_mode_dc_iiu => an_ac_lbist_ac_mode_dc_omm, + an_ac_malf_alert_iiu => an_ac_malf_alert_omm, + an_ac_psro_enable_dc_iiu => an_ac_psro_enable_dc_omm, + an_ac_scan_type_dc_iiu => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_iiu => an_ac_scom_sat_id_omm, + + an_ac_abist_mode_dc_oiu => an_ac_abist_mode_dc_oiu, + an_ac_ccflush_dc_oiu => an_ac_ccflush_dc_oiu, + an_ac_gsd_test_enable_dc_oiu => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc_oiu => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_ip_dc_oiu => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc_oiu => an_ac_lbist_ac_mode_dc_oiu, + an_ac_malf_alert_oiu => an_ac_malf_alert_oiu, + an_ac_psro_enable_dc_oiu => an_ac_psro_enable_dc_oiu, + an_ac_scan_type_dc_oiu => an_ac_scan_type_dc_oiu, + an_ac_scom_sat_id_oiu => an_ac_scom_sat_id_oiu, + + an_ac_back_inv_oiu => an_ac_back_inv_oiu, + an_ac_back_inv_addr_oiu => an_ac_back_inv_addr_oiu, + an_ac_back_inv_target_bit1_oiu => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3_oiu => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4_oiu => an_ac_back_inv_target_bit4_oiu, + an_ac_atpg_en_dc_oiu => an_ac_atpg_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc_oiu => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_lbist_en_dc_oiu => an_ac_lbist_en_dc_oiu, + an_ac_scan_diag_dc_oiu => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b_oiu => an_ac_scan_dis_dc_b_oiu, + + + + ac_an_abist_done_dc_iiu => ac_an_abist_done_dc_iiu, + ac_an_psro_ringsig_iiu => ac_an_psro_ringsig_iiu, + an_ac_ccenable_dc_iiu => an_ac_ccenable_dc_iiu, + mm_pc_bo_fail_iiu => mm_pc_bo_fail_iiu, + mm_pc_bo_diagout_iiu => mm_pc_bo_diagout_iiu, + mm_pc_event_data_iiu => mm_pc_event_data_iiu, + + ac_an_abist_done_dc_oiu => ac_an_abist_done_dc_oiu, + ac_an_psro_ringsig_oiu => ac_an_psro_ringsig_oiu, + an_ac_ccenable_dc_oiu => an_ac_ccenable_dc_oiu, + mm_pc_bo_fail_oiu => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout_oiu => mm_pc_bo_diagout_oiu, + mm_pc_event_data_oiu => mm_pc_event_data_oiu, + + pc_mm_abist_dcomp_g6t_2r_iiu => pc_mm_abist_dcomp_g6t_2r_iiu, + pc_mm_abist_di_g6t_2r_iiu => pc_mm_abist_di_g6t_2r_iiu, + pc_mm_abist_di_0_iiu => pc_mm_abist_di_0_iiu, + pc_mm_abist_ena_dc_iiu => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb_iiu => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t_bw_0_iiu => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1_iiu => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp_iiu => pc_mm_abist_g8t_dcomp_iiu, + pc_mm_abist_g8t_wenb_iiu => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_g8t1p_renb_0_iiu => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_raddr_0_iiu => pc_mm_abist_raddr_0_iiu, + pc_mm_abist_raw_dc_b_iiu => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0_iiu => pc_mm_abist_waddr_0_iiu, + pc_mm_abist_wl128_comp_ena_iiu => pc_mm_abist_wl128_comp_ena_iiu, + pc_mm_bo_enable_4_iiu => pc_mm_bo_enable_4_iiu, + pc_mm_bo_repair_iiu => pc_mm_bo_repair_iiu, + pc_mm_bo_reset_iiu => pc_mm_bo_reset_iiu, + pc_mm_bo_select_iiu => pc_mm_bo_select_iiu, + pc_mm_bo_shdata_iiu => pc_mm_bo_shdata_iiu, + pc_mm_bo_unload_iiu => pc_mm_bo_unload_iiu, + pc_mm_ccflush_dc_iiu => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls_iiu => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode_iiu => pc_mm_event_count_mode_iiu, + pc_mm_event_mux_ctrls_iiu => pc_mm_event_mux_ctrls_iiu, + pc_mm_trace_bus_enable_iiu => pc_mm_trace_bus_enable_iiu, + pc_mm_abist_dcomp_g6t_2r_oiu => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_g6t_2r_oiu => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_di_0_oiu => pc_mm_abist_di_0_oiu, + pc_mm_abist_ena_dc_oiu => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb_oiu => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t_bw_0_oiu => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1_oiu => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp_oiu => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb_oiu => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_g8t1p_renb_0_oiu => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_raddr_0_oiu => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b_oiu => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0_oiu => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena_oiu => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3_oiu => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3_oiu => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3_oiu => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3_oiu => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bo_enable_3_oiu => pc_mm_bo_enable_3_oiu, + pc_mm_bo_repair_oiu => pc_mm_bo_repair_oiu, + pc_mm_bo_reset_oiu => pc_mm_bo_reset_oiu, + pc_mm_bo_select_oiu => pc_mm_bo_select_oiu, + pc_mm_bo_shdata_oiu => pc_mm_bo_shdata_oiu, + pc_mm_bo_unload_oiu => pc_mm_bo_unload_oiu, + pc_mm_bolt_sl_thold_3_oiu => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_ccflush_dc_oiu => pc_mm_ccflush_dc_oiu, + pc_mm_cfg_sl_thold_3_oiu => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3_oiu => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls_oiu => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode_oiu => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls_oiu => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3_oiu => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3_oiu => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3_oiu => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3_oiu => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3_oiu => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3_oiu => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3_oiu => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3_oiu => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3_oiu => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable_oiu => pc_mm_trace_bus_enable_oiu, + xu_wu_rf1_flush => xu_wu_rf1_flush, xu_wu_ex1_flush => xu_wu_ex1_flush, xu_wu_ex2_flush => xu_wu_ex2_flush, @@ -2716,21 +2716,21 @@ a_iuq: entity work.iuq xu_wl_ex3_flush => xu_wl_ex3_flush, xu_wl_ex4_flush => xu_wl_ex4_flush, xu_wl_ex5_flush => xu_wl_ex5_flush, - xu_iu_l_flush => xu_iu_l_flush, - xu_iu_u_flush => xu_iu_u_flush, - - an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, - - bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn_omm, - bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn_omm, - bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, - bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, - + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + + an_ac_grffence_en_dc_oiu => an_ac_grffence_en_dc_oiu, + + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn_omm, + bg_an_ac_func_scan_sn_q => bg_an_ac_func_scan_sn_q, + bg_an_ac_abst_scan_sn_q => bg_an_ac_abst_scan_sn_q, + bg_ac_an_func_scan_ns => "0000000000", bg_ac_an_abst_scan_ns => "00", - bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, - bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, - + bg_ac_an_func_scan_ns_q => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_q => bg_ac_an_abst_scan_ns_q, + bg_pc_l1p_abist_di_0 => "0000", bg_pc_l1p_abist_g8t1p_renb_0 => '0', bg_pc_l1p_abist_g8t_bw_0 => '0', @@ -2741,423 +2741,423 @@ a_iuq: entity work.iuq bg_pc_l1p_abist_waddr_0 => "0000000000", bg_pc_l1p_abist_wl128_comp_ena => '0', bg_pc_l1p_abist_wl32_comp_ena => '0', - bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, - bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, - bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, - bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, - bg_pc_l1p_abist_g8t_dcomp_q => bg_pc_l1p_abist_g8t_dcomp_q, - bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, - bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, - bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, - bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, - bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, - - bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, - bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, - bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, - bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, - bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, - bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, - bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, - bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, - bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, - bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, - bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, - bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2_imm, - bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2_imm, - bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2_imm, - bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2_imm, - bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2_imm, - bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2_imm, - bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2_imm, - bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2_imm, - bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2_imm, - bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2_imm, - bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2_imm, - - bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, - bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, - bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, - bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, - bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, - bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, - bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, - bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, - bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, - - bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, - bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, - bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, - bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, - bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, - bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, - bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, - bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, - bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, - - bg_pc_bo_fail_iiu => bg_pc_bo_fail_omm, - bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_omm, - bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, - bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, - + bg_pc_l1p_abist_di_0_q => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_q => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_q => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_q => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_q => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_q => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_q => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_q => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_q => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_q => bg_pc_l1p_abist_wl32_comp_ena_q, + + bg_pc_l1p_gptr_sl_thold_3 => bg_pc_l1p_gptr_sl_thold_3, + bg_pc_l1p_time_sl_thold_3 => bg_pc_l1p_time_sl_thold_3, + bg_pc_l1p_repr_sl_thold_3 => bg_pc_l1p_repr_sl_thold_3, + bg_pc_l1p_abst_sl_thold_3 => bg_pc_l1p_abst_sl_thold_3, + bg_pc_l1p_func_sl_thold_3 => bg_pc_l1p_func_sl_thold_3, + bg_pc_l1p_func_slp_sl_thold_3 => bg_pc_l1p_func_slp_sl_thold_3, + bg_pc_l1p_bolt_sl_thold_3 => bg_pc_l1p_bolt_sl_thold_3, + bg_pc_l1p_ary_nsl_thold_3 => bg_pc_l1p_ary_nsl_thold_3, + bg_pc_l1p_sg_3 => bg_pc_l1p_sg_3, + bg_pc_l1p_fce_3 => bg_pc_l1p_fce_3, + bg_pc_l1p_bo_enable_3 => bg_pc_l1p_bo_enable_3, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2_imm, + + bg_pc_bo_unload_iiu => bg_pc_bo_unload_iiu, + bg_pc_bo_load_iiu => bg_pc_bo_load_iiu, + bg_pc_bo_repair_iiu => bg_pc_bo_repair_iiu, + bg_pc_bo_reset_iiu => bg_pc_bo_reset_iiu, + bg_pc_bo_shdata_iiu => bg_pc_bo_shdata_iiu, + bg_pc_bo_select_iiu => bg_pc_bo_select_iiu, + bg_pc_l1p_ccflush_dc_iiu => bg_pc_l1p_ccflush_dc_iiu, + bg_pc_l1p_abist_ena_dc_iiu => bg_pc_l1p_abist_ena_dc_iiu, + bg_pc_l1p_abist_raw_dc_b_iiu => bg_pc_l1p_abist_raw_dc_b_iiu, + + bg_pc_bo_unload_oiu => bg_pc_bo_unload_oiu, + bg_pc_bo_load_oiu => bg_pc_bo_load_oiu, + bg_pc_bo_repair_oiu => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_oiu => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_oiu => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_oiu => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_oiu => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_oiu => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_oiu => bg_pc_l1p_abist_raw_dc_b_oiu, + + bg_pc_bo_fail_iiu => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_iiu => bg_pc_bo_diagout_omm, + bg_pc_bo_fail_oiu => bg_pc_bo_fail_oiu, + bg_pc_bo_diagout_oiu => bg_pc_bo_diagout_oiu, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, - - gnd => gnd, - vcs => vcs, - vdd => vdd + + gnd => gnd, + vcs => vcs, + vdd => vdd ); - -a_xuq: entity work.xuq - generic map(a2mode => a2mode, - bcfg_epn_0to15 => bcfg_epn_0to15, - bcfg_epn_16to31 => bcfg_epn_16to31, - bcfg_epn_32to47 => bcfg_epn_32to47, - bcfg_epn_48to51 => bcfg_epn_48to51, - bcfg_rpn_22to31 => bcfg_rpn_22to31, - bcfg_rpn_32to47 => bcfg_rpn_32to47, - bcfg_rpn_48to51 => bcfg_rpn_48to51, - eff_ifar => xu_eff_ifar, - expand_type => expand_type, - l_endian_m => l_endian_m, - lmq_entries => lmq_entries, - real_data_add => xu_real_data_add, - regmode => regmode, - hvmode => hvmode, - st_data_32b_mode => st_data_32b_mode, - threads => threads, - load_credits => load_credits, - store_credits => store_credits, - spr_xucr0_init_mod => spr_xucr0_init_mod, - dc_size => dc_size ) - port map ( - abst_scan_in => an_ac_abst_scan_in_omm_xu(7 to 9), - bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit4, - ccfg_scan_in => an_ac_bcfg_scan_in_omm_bit1, - dcfg_scan_in => an_ac_dcfg_scan_in_omm(2), - func_scan_in => an_ac_func_scan_in_omm_xu(31 to 58), - gptr_scan_in => bx_xu_gptr_scan_out, - repr_scan_in => bx_xu_repr_scan_out, - time_scan_in => bx_xu_time_scan_out, - an_ac_atpg_en_dc => an_ac_atpg_en_dc_oiu, - an_ac_back_inv => an_ac_back_inv_oiu, - an_ac_back_inv_addr => an_ac_back_inv_addr_oiu(64-xu_real_data_add to 63), - an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1_oiu, - an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3_oiu, - an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4_oiu, - an_ac_crit_interrupt => an_ac_crit_interrupt_omm, - an_ac_ext_interrupt => an_ac_ext_interrupt_omm, - an_ac_flh2l2_gate => an_ac_flh2l2_gate_omm, - an_ac_grffence_en_dc => an_ac_grffence_en_dc_oiu, - an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, - an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_oiu, - an_ac_perf_interrupt => an_ac_perf_interrupt_omm, - an_ac_reld_core_tag => an_ac_reld_core_tag_omm(0 to 4), - an_ac_reld_data => an_ac_reld_data_omm, - an_ac_reld_data_vld => an_ac_reld_data_vld_omm, - an_ac_reld_ecc_err => an_ac_reld_ecc_err_omm, - an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue_omm, - an_ac_reld_qw => an_ac_reld_qw_omm, - an_ac_reld_data_coming => an_ac_reld_data_coming_omm, - an_ac_reld_ditc => an_ac_reld_ditc_omm, - an_ac_reld_crit_qw => an_ac_reld_crit_qw_omm, - an_ac_req_ld_pop => an_ac_req_ld_pop_omm, - an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1_omm, - an_ac_req_st_gather => an_ac_req_st_gather_omm, - an_ac_req_st_pop => an_ac_req_st_pop_omm, - an_ac_reservation_vld => an_ac_reservation_vld_omm, - an_ac_sleep_en => an_ac_sleep_en_omm, - an_ac_stcx_complete => an_ac_stcx_complete_omm, - an_ac_stcx_pass => an_ac_stcx_pass_omm, - xu_iu_stcx_complete => xu_iu_stcx_complete, - lsu_reld_data_vld => lsu_reld_data_vld, - lsu_reld_core_tag => lsu_reld_core_tag, - lsu_reld_qw => lsu_reld_qw , - lsu_reld_ditc => lsu_reld_ditc, - lsu_reld_ecc_err => lsu_reld_ecc_err, - lsu_reld_data => lsu_reld_data, - lsu_req_st_pop => lsu_req_st_pop, - lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, - fu_xu_ex1_ifar0 => fu_xu_ex1_ifar, - fu_xu_ex1_ifar1 => fu_xu_ex1_ifar, - fu_xu_ex1_ifar2 => fu_xu_ex1_ifar, - fu_xu_ex1_ifar3 => fu_xu_ex1_ifar, - fu_xu_ex2_async_block => fu_xu_ex2_async_block, - fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, - fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, - fu_xu_ex2_store_data(0 to 63) => fu_xu_ex2_store_data, - fu_xu_ex2_store_data(64 to 127) => fu_xu_ex2_store_data, - fu_xu_ex2_store_data(128 to 191) => fu_xu_ex2_store_data, - fu_xu_ex2_store_data(192 to 255) => fu_xu_ex2_store_data, - fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, - fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, - fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, - fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, - fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, - fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, - fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, - fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, - fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, - fu_xu_ex3_trap => fu_xu_ex3_trap, - fu_xu_ex4_cr0 => fu_xu_ex4_cr, - fu_xu_ex4_cr0_bf => fu_xu_ex4_cr_bf, - fu_xu_ex4_cr1 => fu_xu_ex4_cr, - fu_xu_ex4_cr1_bf => fu_xu_ex4_cr_bf, - fu_xu_ex4_cr2 => fu_xu_ex4_cr, - fu_xu_ex4_cr2_bf => fu_xu_ex4_cr_bf, - fu_xu_ex4_cr3 => fu_xu_ex4_cr, - fu_xu_ex4_cr3_bf => fu_xu_ex4_cr_bf, - fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, - fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, - fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, - fu_xu_rf1_act => fu_xu_rf1_act, - regf_scan_in => an_ac_regf_scan_in_omm(5 to 11), - slowspr_addr_in => bx_xu_slowspr_addr, - slowspr_data_in => bx_xu_slowspr_data, - slowspr_done_in => bx_xu_slowspr_done, - slowspr_etid_in => bx_xu_slowspr_etid, - slowspr_rw_in => bx_xu_slowspr_rw, - slowspr_val_in => bx_xu_slowspr_val, - spr_pvr_version_dc => spr_pvr_version_dc, - spr_pvr_revision_dc => spr_pvr_revision_dc, - debug_data_in => iu_xu_debug_data, - trigger_data_in => iu_xu_trigger_data, - iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, - iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, - iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, - iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, - iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, - iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, - iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, - iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, - iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, - iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, - iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, - iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, - iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, - iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, - iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, - iu_xu_is2_axu_store => iu_xu_is2_axu_store, - iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, - iu_xu_is2_error => iu_xu_is2_error, - iu_xu_is2_gshare => iu_xu_is2_gshare, - iu_xu_is2_ifar => iu_xu_is2_ifar, - iu_xu_is2_instr => iu_xu_is2_instr, - iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, - iu_xu_is2_match => iu_xu_is2_match, - iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, - iu_xu_is2_pred_update => iu_xu_is2_pred_update, - iu_xu_is2_s1 => iu_xu_is2_s1, - iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, - iu_xu_is2_s2 => iu_xu_is2_s2, - iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, - iu_xu_is2_s3 => iu_xu_is2_s3, - iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, - iu_xu_is2_ta => iu_xu_is2_ta, - iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, - iu_xu_is2_tid => iu_xu_is2_tid, - iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, - iu_xu_is2_vld => iu_xu_is2_vld, - iu_xu_quiesce => iu_xu_quiesce, - iu_xu_ra => iu_xu_ra, - iu_xu_request => iu_xu_request, - iu_xu_thread => iu_xu_thread, - iu_xu_userdef => iu_xu_userdef, - iu_xu_wimge => iu_xu_wimge, - mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, - mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, - mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, - mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, - mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, - mm_xu_derat_pid0 => mm_xu_derat_pid0, - mm_xu_derat_pid1 => mm_xu_derat_pid1, - mm_xu_derat_pid2 => mm_xu_derat_pid2, - mm_xu_derat_pid3 => mm_xu_derat_pid3, - mm_xu_derat_rel_data => mm_xu_derat_rel_data, - mm_xu_derat_rel_val => mm_xu_derat_rel_val, - mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, - mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, - mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, - mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, - mm_xu_eratmiss_done => mm_xu_eratmiss_done, - mm_xu_esr_pt => mm_xu_esr_pt, - mm_xu_esr_data => mm_xu_esr_data, - mm_xu_esr_epid => mm_xu_esr_epid, - mm_xu_esr_st => mm_xu_esr_st, - mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, - xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, - mm_xu_hold_done => mm_xu_hold_done, - mm_xu_hold_req => mm_xu_hold_req, - mm_xu_hv_priv => mm_xu_hv_priv, - mm_xu_illeg_instr => mm_xu_illeg_instr, - mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, - mm_xu_lrat_miss => mm_xu_lrat_miss, - mm_xu_lsu_addr => mm_xu_lsu_addr, - mm_xu_lsu_lpid => mm_xu_lsu_lpid, - mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, - mm_xu_lsu_gs => mm_xu_lsu_gs, - mm_xu_lsu_ind => mm_xu_lsu_ind, - mm_xu_lsu_lbit => mm_xu_lsu_lbit, - mm_xu_lsu_req => mm_xu_lsu_req, - mm_xu_lsu_ttype => mm_xu_lsu_ttype, - mm_xu_lsu_u => mm_xu_lsu_u, - mm_xu_lsu_wimge => mm_xu_lsu_wimge, - mm_xu_pt_fault => mm_xu_pt_fault, - mm_xu_quiesce => mm_xu_quiesce, - mm_xu_tlb_inelig => mm_xu_tlb_inelig, - mm_xu_tlb_miss => mm_xu_tlb_miss, - mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, - mm_xu_tlb_par_err => mm_xu_tlb_par_err, - mm_xu_lru_par_err => mm_xu_lru_par_err, - mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, - mm_xu_cr0_eq => mm_xu_cr0_eq, - nclk => a2_nclk, - pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3_ofu, - pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3_ofu, - pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3_ofu, - pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3_ofu, - pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3_ofu, - pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3_ofu, - pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3_ofu, - pc_xu_bo_enable_3 => pc_xu_bo_enable_3_ofu, - pc_xu_bo_load => pc_xu_bo_load_ofu, - pc_xu_bo_unload => pc_xu_bo_unload_ofu, - pc_xu_bo_repair => pc_xu_bo_repair_ofu, - pc_xu_bo_reset => pc_xu_bo_reset_ofu, - pc_xu_bo_shdata => pc_xu_bo_shdata_ofu, - pc_xu_bo_select => pc_xu_bo_select_ofu, - pc_xu_cache_par_err_event => pc_xu_cache_par_err_event_ofu, - pc_xu_ccflush_dc => pc_xu_ccflush_dc_ofu, - pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3_ofu, - pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3_ofu, - pc_xu_dbg_action => pc_xu_dbg_action_ofu, - pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls_ofu, - pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls_ofu, - pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls_ofu, - pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls_ofu, - pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop_ofu, - xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, - xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, - pc_xu_event_bus_enable => pc_xu_event_bus_enable_ofu, - pc_xu_event_count_mode => pc_xu_event_count_mode_ofu, - pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls_ofu, - pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop_ofu, - pc_xu_fce_3 => pc_xu_fce_3_ofu, - pc_xu_force_ude => pc_xu_force_ude_ofu, - pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3_ofu, - pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3_ofu, - pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3_ofu, - pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3_ofu, - pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3_ofu, - pc_xu_init_reset => pc_xu_init_reset_ofu, - pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit_ofu, - pc_xu_instr_trace_mode => pc_xu_instr_trace_mode_ofu, - pc_xu_instr_trace_tid => pc_xu_instr_trace_tid_ofu, - pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls_ofu, - pc_xu_msrovride_de => pc_xu_msrovride_de, - pc_xu_msrovride_enab => pc_xu_msrovride_enab_ofu, - pc_xu_msrovride_pr => pc_xu_msrovride_pr_ofu, - pc_xu_msrovride_gs => pc_xu_msrovride_gs_ofu, - pc_xu_ram_execute => pc_xu_ram_execute_ofu, - pc_xu_ram_flush_thread => pc_xu_ram_flush_thread_ofu, - pc_xu_ram_mode => pc_xu_ram_mode_ofu, - pc_xu_ram_thread => pc_xu_ram_thread_ofu, - pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3_ofu, - pc_xu_reset_1_complete => pc_xu_reset_1_cmplt_ofu, - pc_xu_reset_2_complete => pc_xu_reset_2_cmplt_ofu, - pc_xu_reset_3_complete => pc_xu_reset_3_cmplt_ofu, - pc_xu_reset_wd_complete => pc_xu_reset_wd_cmplt_ofu, - pc_xu_sg_3 => pc_xu_sg_3_ofu, - pc_xu_step => pc_xu_step_ofu, - pc_xu_stop => pc_xu_stop_ofu, - pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop_ofu, - pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3_ofu, - pc_xu_trace_bus_enable => pc_xu_trace_bus_enable_ofu, - pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity_ofu, - pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity_ofu, - pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt_ofu, - pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed_ofu, - pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc_ofu, - pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity_ofu, - pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset_ofu, - pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r_ofu(0 to 3), - pc_xu_abist_di_0 => pc_xu_abist_di_0_ofu(0 to 3), - pc_xu_abist_di_1 => pc_xu_abist_di_1_ofu(0 to 3), - pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r_ofu(0 to 3), - pc_xu_abist_ena_dc => pc_xu_abist_ena_dc_ofu, - pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw_ofu(0 to 1), - pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb_ofu, - pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0_ofu, - pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0_ofu, - pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1_ofu, - pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp_ofu(0 to 3), - pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb_ofu, - pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0_ofu, - pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1_ofu, - pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0_ofu, - pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1_ofu, - pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0_ofu(0 to 9), - pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1_ofu(0 to 9), - pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b_ofu, - pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0_ofu(0 to 9), - pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1_ofu(0 to 9), - pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena_ofu, - pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena_ofu, - pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena_ofu, - an_ac_coreid => an_ac_coreid_omm, - an_ac_external_mchk => an_ac_external_mchk_omm, - an_ac_hang_pulse => an_ac_hang_pulse_omm, - an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, - an_ac_tb_update_enable => an_ac_tb_update_enable_omm, - an_ac_tb_update_pulse => an_ac_tb_update_pulse_omm, - an_ac_reld_l1_dump => an_ac_reld_l1_dump_omm, - ac_tc_machine_check => ac_an_machine_check_imm, - ac_an_req => ac_an_req_imm, - ac_an_req_endian => ac_an_req_endian_imm, - ac_an_req_ld_core_tag => ac_an_req_ld_core_tag_imm, - ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len_imm, - ac_an_req_pwr_token => ac_an_req_pwr_token_imm, - ac_an_req_ra => ac_an_req_ra_imm, - ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0_imm, - ac_an_req_thread => ac_an_req_thread_imm, - ac_an_req_ttype => ac_an_req_ttype_imm, - ac_an_req_user_defined => ac_an_req_user_defined_imm, - ac_an_req_wimg_g => ac_an_req_wimg_g_imm, - ac_an_req_wimg_i => ac_an_req_wimg_i_imm, - ac_an_req_wimg_m => ac_an_req_wimg_m_imm, - ac_an_req_wimg_w => ac_an_req_wimg_w_imm, - ac_an_st_byte_enbl => xu_st_byte_enbl, - ac_an_st_data => xu_st_data, - ac_an_st_data_pwr_token => ac_an_st_data_pwr_token_imm, - an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd_omm, - ac_tc_debug_trigger => ac_an_debug_trigger_imm, - ac_tc_reset_1_request => ac_an_reset_1_request_imm, - ac_tc_reset_2_request => ac_an_reset_2_request_imm, - ac_tc_reset_3_request => ac_an_reset_3_request_imm, - ac_tc_reset_wd_request => ac_an_reset_wd_request_imm, - abst_scan_out => ac_an_abst_scan_out_imm_xu(7 to 9), - bcfg_scan_out => ac_an_bcfg_scan_out_imm(4), - ccfg_scan_out => xu_fu_ccfg_scan_out, - dcfg_scan_out => ac_an_dcfg_scan_out_imm(2), - func_scan_out => ac_an_func_scan_out_imm_xu(31 to 58), - gptr_scan_out => xu_mm_gptr_scan_out, - repr_scan_out => xu_mm_repr_scan_out, - time_scan_out => xu_mm_time_scan_out, - regf_scan_out => ac_an_regf_scan_out_imm(5 to 11), - xu_n_is2_flush => xu_n_is2_flush, - xu_n_rf0_flush => xu_n_rf0_flush, - xu_n_rf1_flush => xu_n_rf1_flush, - xu_n_ex1_flush => xu_n_ex1_flush, - xu_n_ex2_flush => xu_n_ex2_flush, - xu_n_ex3_flush => xu_n_ex3_flush, - xu_n_ex4_flush => xu_n_ex4_flush, - xu_n_ex5_flush => xu_n_ex5_flush, - xu_s_rf1_flush => xu_s_rf1_flush, - xu_s_ex1_flush => xu_s_ex1_flush, - xu_s_ex2_flush => xu_s_ex2_flush, - xu_s_ex3_flush => xu_s_ex3_flush, - xu_s_ex4_flush => xu_s_ex4_flush, - xu_s_ex5_flush => xu_s_ex5_flush, + +a_xuq: entity work.xuq + generic map(a2mode => a2mode, + bcfg_epn_0to15 => bcfg_epn_0to15, + bcfg_epn_16to31 => bcfg_epn_16to31, + bcfg_epn_32to47 => bcfg_epn_32to47, + bcfg_epn_48to51 => bcfg_epn_48to51, + bcfg_rpn_22to31 => bcfg_rpn_22to31, + bcfg_rpn_32to47 => bcfg_rpn_32to47, + bcfg_rpn_48to51 => bcfg_rpn_48to51, + eff_ifar => xu_eff_ifar, + expand_type => expand_type, + l_endian_m => l_endian_m, + lmq_entries => lmq_entries, + real_data_add => xu_real_data_add, + regmode => regmode, + hvmode => hvmode, + st_data_32b_mode => st_data_32b_mode, + threads => threads, + load_credits => load_credits, + store_credits => store_credits, + spr_xucr0_init_mod => spr_xucr0_init_mod, + dc_size => dc_size ) + port map ( + abst_scan_in => an_ac_abst_scan_in_omm_xu(7 to 9), + bcfg_scan_in => an_ac_bcfg_scan_in_omm_bit4, + ccfg_scan_in => an_ac_bcfg_scan_in_omm_bit1, + dcfg_scan_in => an_ac_dcfg_scan_in_omm(2), + func_scan_in => an_ac_func_scan_in_omm_xu(31 to 58), + gptr_scan_in => bx_xu_gptr_scan_out, + repr_scan_in => bx_xu_repr_scan_out, + time_scan_in => bx_xu_time_scan_out, + an_ac_atpg_en_dc => an_ac_atpg_en_dc_oiu, + an_ac_back_inv => an_ac_back_inv_oiu, + an_ac_back_inv_addr => an_ac_back_inv_addr_oiu(64-xu_real_data_add to 63), + an_ac_back_inv_target_bit1 => an_ac_back_inv_target_bit1_oiu, + an_ac_back_inv_target_bit3 => an_ac_back_inv_target_bit3_oiu, + an_ac_back_inv_target_bit4 => an_ac_back_inv_target_bit4_oiu, + an_ac_crit_interrupt => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate => an_ac_flh2l2_gate_omm, + an_ac_grffence_en_dc => an_ac_grffence_en_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_oiu, + an_ac_perf_interrupt => an_ac_perf_interrupt_omm, + an_ac_reld_core_tag => an_ac_reld_core_tag_omm(0 to 4), + an_ac_reld_data => an_ac_reld_data_omm, + an_ac_reld_data_vld => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw => an_ac_reld_qw_omm, + an_ac_reld_data_coming => an_ac_reld_data_coming_omm, + an_ac_reld_ditc => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw => an_ac_reld_crit_qw_omm, + an_ac_req_ld_pop => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather => an_ac_req_st_gather_omm, + an_ac_req_st_pop => an_ac_req_st_pop_omm, + an_ac_reservation_vld => an_ac_reservation_vld_omm, + an_ac_sleep_en => an_ac_sleep_en_omm, + an_ac_stcx_complete => an_ac_stcx_complete_omm, + an_ac_stcx_pass => an_ac_stcx_pass_omm, + xu_iu_stcx_complete => xu_iu_stcx_complete, + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag, + lsu_reld_qw => lsu_reld_qw , + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + lsu_req_st_pop => lsu_req_st_pop, + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd, + fu_xu_ex1_ifar0 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar1 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar2 => fu_xu_ex1_ifar, + fu_xu_ex1_ifar3 => fu_xu_ex1_ifar, + fu_xu_ex2_async_block => fu_xu_ex2_async_block, + fu_xu_ex2_ifar_val => fu_xu_ex2_ifar_val, + fu_xu_ex2_ifar_issued => fu_xu_ex2_ifar_issued, + fu_xu_ex2_store_data(0 to 63) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(64 to 127) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(128 to 191) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data(192 to 255) => fu_xu_ex2_store_data, + fu_xu_ex2_store_data_val => fu_xu_ex2_store_data_val, + fu_xu_ex3_flush2ucode => fu_xu_ex3_flush2ucode, + fu_xu_ex2_instr_match => fu_xu_ex2_instr_match, + fu_xu_ex2_instr_type => fu_xu_ex2_instr_type, + fu_xu_ex2_is_ucode => fu_xu_ex2_is_ucode, + fu_xu_ex3_ap_int_req => fu_xu_ex3_ap_int_req, + fu_xu_ex3_n_flush => fu_xu_ex3_n_flush, + fu_xu_ex3_np1_flush => fu_xu_ex3_np1_flush, + fu_xu_ex3_regfile_err_det => fu_xu_ex3_regfile_err_det, + fu_xu_ex3_trap => fu_xu_ex3_trap, + fu_xu_ex4_cr0 => fu_xu_ex4_cr, + fu_xu_ex4_cr0_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr1 => fu_xu_ex4_cr, + fu_xu_ex4_cr1_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr2 => fu_xu_ex4_cr, + fu_xu_ex4_cr2_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr3 => fu_xu_ex4_cr, + fu_xu_ex4_cr3_bf => fu_xu_ex4_cr_bf, + fu_xu_ex4_cr_noflush => fu_xu_ex4_cr_noflush, + fu_xu_ex4_cr_val => fu_xu_ex4_cr_val, + fu_xu_regfile_seq_end => fu_xu_regfile_seq_end, + fu_xu_rf1_act => fu_xu_rf1_act, + regf_scan_in => an_ac_regf_scan_in_omm(5 to 11), + slowspr_addr_in => bx_xu_slowspr_addr, + slowspr_data_in => bx_xu_slowspr_data, + slowspr_done_in => bx_xu_slowspr_done, + slowspr_etid_in => bx_xu_slowspr_etid, + slowspr_rw_in => bx_xu_slowspr_rw, + slowspr_val_in => bx_xu_slowspr_val, + spr_pvr_version_dc => spr_pvr_version_dc, + spr_pvr_revision_dc => spr_pvr_revision_dc, + debug_data_in => iu_xu_debug_data, + trigger_data_in => iu_xu_trigger_data, + iu_xu_ex4_tlb_data => iu_xu_ex4_tlb_data, + iu_xu_ierat_ex2_flush_req => iu_xu_ierat_ex2_flush_req, + iu_xu_ierat_ex3_par_err => iu_xu_ierat_ex3_par_err, + iu_xu_ierat_ex4_par_err => iu_xu_ierat_ex4_par_err, + iu_xu_is2_axu_instr_type => iu_xu_is2_axu_instr_type, + iu_xu_is2_axu_ld_or_st => iu_xu_is2_axu_ld_or_st, + iu_xu_is2_axu_ldst_extpid => iu_xu_is2_axu_ldst_extpid, + iu_xu_is2_axu_ldst_forcealign => iu_xu_is2_axu_ldst_forcealign, + iu_xu_is2_axu_ldst_forceexcept => iu_xu_is2_axu_ldst_forceexcept, + iu_xu_is2_axu_ldst_indexed => iu_xu_is2_axu_ldst_indexed, + iu_xu_is2_axu_ldst_size => iu_xu_is2_axu_ldst_size, + iu_xu_is2_axu_ldst_tag => iu_xu_is2_axu_ldst_tag, + iu_xu_is2_axu_ldst_update => iu_xu_is2_axu_ldst_update, + iu_xu_is2_axu_mffgpr => iu_xu_is2_axu_mffgpr, + iu_xu_is2_axu_mftgpr => iu_xu_is2_axu_mftgpr, + iu_xu_is2_axu_store => iu_xu_is2_axu_store, + iu_xu_is2_axu_movedp => iu_xu_is2_axu_movedp, + iu_xu_is2_error => iu_xu_is2_error, + iu_xu_is2_gshare => iu_xu_is2_gshare, + iu_xu_is2_ifar => iu_xu_is2_ifar, + iu_xu_is2_instr => iu_xu_is2_instr, + iu_xu_is2_is_ucode => iu_xu_is2_is_ucode, + iu_xu_is2_match => iu_xu_is2_match, + iu_xu_is2_pred_taken_cnt => iu_xu_is2_pred_taken_cnt, + iu_xu_is2_pred_update => iu_xu_is2_pred_update, + iu_xu_is2_s1 => iu_xu_is2_s1, + iu_xu_is2_s1_vld => iu_xu_is2_s1_vld, + iu_xu_is2_s2 => iu_xu_is2_s2, + iu_xu_is2_s2_vld => iu_xu_is2_s2_vld, + iu_xu_is2_s3 => iu_xu_is2_s3, + iu_xu_is2_s3_vld => iu_xu_is2_s3_vld, + iu_xu_is2_ta => iu_xu_is2_ta, + iu_xu_is2_ta_vld => iu_xu_is2_ta_vld, + iu_xu_is2_tid => iu_xu_is2_tid, + iu_xu_is2_ucode_vld => iu_xu_is2_ucode_vld, + iu_xu_is2_vld => iu_xu_is2_vld, + iu_xu_quiesce => iu_xu_quiesce, + iu_xu_ra => iu_xu_ra, + iu_xu_request => iu_xu_request, + iu_xu_thread => iu_xu_thread, + iu_xu_userdef => iu_xu_userdef, + iu_xu_wimge => iu_xu_wimge, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + mm_xu_cr0_eq => mm_xu_cr0_eq, + nclk => a2_nclk, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3_ofu, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3_ofu, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3_ofu, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3_ofu, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3_ofu, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3_ofu, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3_ofu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3_ofu, + pc_xu_bo_load => pc_xu_bo_load_ofu, + pc_xu_bo_unload => pc_xu_bo_unload_ofu, + pc_xu_bo_repair => pc_xu_bo_repair_ofu, + pc_xu_bo_reset => pc_xu_bo_reset_ofu, + pc_xu_bo_shdata => pc_xu_bo_shdata_ofu, + pc_xu_bo_select => pc_xu_bo_select_ofu, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event_ofu, + pc_xu_ccflush_dc => pc_xu_ccflush_dc_ofu, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3_ofu, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3_ofu, + pc_xu_dbg_action => pc_xu_dbg_action_ofu, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls_ofu, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls_ofu, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls_ofu, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls_ofu, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme, + pc_xu_event_bus_enable => pc_xu_event_bus_enable_ofu, + pc_xu_event_count_mode => pc_xu_event_count_mode_ofu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls_ofu, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop_ofu, + pc_xu_fce_3 => pc_xu_fce_3_ofu, + pc_xu_force_ude => pc_xu_force_ude_ofu, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3_ofu, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3_ofu, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3_ofu, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3_ofu, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3_ofu, + pc_xu_init_reset => pc_xu_init_reset_ofu, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit_ofu, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode_ofu, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid_ofu, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls_ofu, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab_ofu, + pc_xu_msrovride_pr => pc_xu_msrovride_pr_ofu, + pc_xu_msrovride_gs => pc_xu_msrovride_gs_ofu, + pc_xu_ram_execute => pc_xu_ram_execute_ofu, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread_ofu, + pc_xu_ram_mode => pc_xu_ram_mode_ofu, + pc_xu_ram_thread => pc_xu_ram_thread_ofu, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3_ofu, + pc_xu_reset_1_complete => pc_xu_reset_1_cmplt_ofu, + pc_xu_reset_2_complete => pc_xu_reset_2_cmplt_ofu, + pc_xu_reset_3_complete => pc_xu_reset_3_cmplt_ofu, + pc_xu_reset_wd_complete => pc_xu_reset_wd_cmplt_ofu, + pc_xu_sg_3 => pc_xu_sg_3_ofu, + pc_xu_step => pc_xu_step_ofu, + pc_xu_stop => pc_xu_stop_ofu, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop_ofu, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3_ofu, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable_ofu, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity_ofu, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity_ofu, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt_ofu, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed_ofu, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc_ofu, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity_ofu, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset_ofu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r_ofu(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0_ofu(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1_ofu(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r_ofu(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc_ofu, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw_ofu(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb_ofu, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0_ofu, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0_ofu, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1_ofu, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp_ofu(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb_ofu, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0_ofu, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1_ofu, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0_ofu, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1_ofu, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0_ofu(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1_ofu(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b_ofu, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0_ofu(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1_ofu(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena_ofu, + pc_xu_abist_wl32_comp_ena => pc_xu_abist_wl32_comp_ena_ofu, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena_ofu, + an_ac_coreid => an_ac_coreid_omm, + an_ac_external_mchk => an_ac_external_mchk_omm, + an_ac_hang_pulse => an_ac_hang_pulse_omm, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_tb_update_enable => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse => an_ac_tb_update_pulse_omm, + an_ac_reld_l1_dump => an_ac_reld_l1_dump_omm, + ac_tc_machine_check => ac_an_machine_check_imm, + ac_an_req => ac_an_req_imm, + ac_an_req_endian => ac_an_req_endian_imm, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token => ac_an_req_pwr_token_imm, + ac_an_req_ra => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread => ac_an_req_thread_imm, + ac_an_req_ttype => ac_an_req_ttype_imm, + ac_an_req_user_defined => ac_an_req_user_defined_imm, + ac_an_req_wimg_g => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl => xu_st_byte_enbl, + ac_an_st_data => xu_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token_imm, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd_omm, + ac_tc_debug_trigger => ac_an_debug_trigger_imm, + ac_tc_reset_1_request => ac_an_reset_1_request_imm, + ac_tc_reset_2_request => ac_an_reset_2_request_imm, + ac_tc_reset_3_request => ac_an_reset_3_request_imm, + ac_tc_reset_wd_request => ac_an_reset_wd_request_imm, + abst_scan_out => ac_an_abst_scan_out_imm_xu(7 to 9), + bcfg_scan_out => ac_an_bcfg_scan_out_imm(4), + ccfg_scan_out => xu_fu_ccfg_scan_out, + dcfg_scan_out => ac_an_dcfg_scan_out_imm(2), + func_scan_out => ac_an_func_scan_out_imm_xu(31 to 58), + gptr_scan_out => xu_mm_gptr_scan_out, + repr_scan_out => xu_mm_repr_scan_out, + time_scan_out => xu_mm_time_scan_out, + regf_scan_out => ac_an_regf_scan_out_imm(5 to 11), + xu_n_is2_flush => xu_n_is2_flush, + xu_n_rf0_flush => xu_n_rf0_flush, + xu_n_rf1_flush => xu_n_rf1_flush, + xu_n_ex1_flush => xu_n_ex1_flush, + xu_n_ex2_flush => xu_n_ex2_flush, + xu_n_ex3_flush => xu_n_ex3_flush, + xu_n_ex4_flush => xu_n_ex4_flush, + xu_n_ex5_flush => xu_n_ex5_flush, + xu_s_rf1_flush => xu_s_rf1_flush, + xu_s_ex1_flush => xu_s_ex1_flush, + xu_s_ex2_flush => xu_s_ex2_flush, + xu_s_ex3_flush => xu_s_ex3_flush, + xu_s_ex4_flush => xu_s_ex4_flush, + xu_s_ex5_flush => xu_s_ex5_flush, xu_wu_rf1_flush => xu_wu_rf1_flush, xu_wu_ex1_flush => xu_wu_ex1_flush, xu_wu_ex2_flush => xu_wu_ex2_flush, @@ -3170,1437 +3170,1437 @@ a_xuq: entity work.xuq xu_wl_ex3_flush => xu_wl_ex3_flush, xu_wl_ex4_flush => xu_wl_ex4_flush, xu_wl_ex5_flush => xu_wl_ex5_flush, - xu_fu_ccr2_ap => xu_fu_ccr2_ap, - xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, - xu_fu_ex6_load_data => xu_fu_ex6_load_data, - xu_fu_ex5_load_le => xu_fu_ex5_load_le, - xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, - xu_fu_ex5_load_val => xu_fu_ex5_load_val, - xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, - xu_fu_msr_fp => xu_fu_msr_fp, - xu_fu_msr_pr => xu_fu_msr_pr, - xu_fu_msr_gs => xu_fu_msr_gs, - xu_fu_msr_spv => xu_fu_msr_spv, - xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, - xu_iu_complete_qentry => xu_iu_complete_qentry, - xu_iu_complete_target_type => xu_iu_complete_target_type, - xu_iu_complete_tid => xu_iu_complete_tid, - xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, - xu_iu_ex1_rb => xu_iu_ex1_rb, - xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, - xu_iu_ex5_bclr => xu_iu_ex5_bclr, - xu_iu_ex5_bh => xu_iu_ex5_bh, - xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, - xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, - xu_iu_ex5_br_update => xu_iu_ex5_br_update, - xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, - xu_iu_ex5_gshare => xu_iu_ex5_gshare, - xu_iu_ex5_ifar => xu_iu_ex5_ifar, - xu_iu_ex5_lk => xu_iu_ex5_lk, - xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, - xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, - xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, - xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, - xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, - xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, - xu_iu_ex5_tid => xu_iu_ex5_tid, - xu_iu_ex5_val => xu_iu_ex5_val, - xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, - xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, - xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, - xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, - xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, - xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, - xu_iu_ex6_pri => xu_iu_ex6_pri, - xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, - xu_iu_flush_2ucode => xu_iu_flush_2ucode, - xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, - xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, - xu_iu_xucr0_rel => xu_iu_xucr0_rel, - xu_iu_ici => xu_iu_ici, - xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, - xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, - xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, - xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, - xu_iu_larx_done_tid => xu_iu_larx_done_tid, - xu_iu_set_barr_tid => xu_iu_set_barr_tid, - xu_iu_membar_tid => xu_iu_membar_tid, - xu_iu_msr_cm => xu_iu_msr_cm, - xu_iu_msr_hv => xu_iu_msr_hv, - xu_iu_msr_is => xu_iu_msr_is, - xu_iu_msr_pr => xu_iu_msr_pr, - xu_iu_multdiv_done => xu_iu_multdiv_done, - xu_iu_need_hole => xu_iu_need_hole, - xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, - xu_iu_ram_issue => xu_iu_ram_issue, - xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, - xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, - xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, - xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, - xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, - xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, - xu_iu_rf1_val => xu_iu_rf1_val, - xu_iu_rf1_ws => xu_iu_rf1_ws, - xu_iu_rf1_t => xu_iu_rf1_t, - xu_iu_run_thread => xu_iu_run_thread, - xu_iu_single_instr_mode => xu_iu_single_instr_mode, - xu_iu_slowspr_done => xu_iu_slowspr_done, - xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, - xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, - xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, - xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, - xu_iu_spr_xer0 => xu_iu_spr_xer0, - xu_iu_spr_xer1 => xu_iu_spr_xer1, - xu_iu_spr_xer2 => xu_iu_spr_xer2, - xu_iu_spr_xer3 => xu_iu_spr_xer3, - xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, - xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, - xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, - xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, - xu_iu_ucode_restart => xu_iu_ucode_restart, - xu_mm_derat_epn => xu_mm_derat_epn, - xu_mm_derat_lpid => xu_mm_derat_lpid, - xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, - xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, - xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, - xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, - xu_mm_derat_req => xu_mm_derat_req, - xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, - xu_mm_derat_state => xu_mm_derat_state, - xu_mm_derat_thdid => xu_mm_derat_thdid, - xu_mm_derat_tid => xu_mm_derat_tid, - xu_mm_derat_ttype => xu_mm_derat_ttype, - xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, - xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, - xu_mm_ex4_flush => xu_mm_ex4_flush, - xu_mm_ex5_flush => xu_mm_ex5_flush, - xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, - xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, - xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, - xu_mm_hold_ack => xu_mm_hold_ack, - xu_mm_ierat_flush => xu_mm_ierat_flush, - xu_mm_ierat_miss => xu_mm_ierat_miss, - xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, - xu_mm_lsu_token => xu_mm_lsu_token, - xu_mm_msr_cm => xu_mm_msr_cm, - xu_mm_msr_ds => xu_mm_msr_ds, - xu_mm_msr_gs => xu_mm_msr_gs, - xu_iu_msr_gs => xu_iu_msr_gs, - xu_mm_msr_is => xu_mm_msr_is, - xu_mm_msr_pr => xu_mm_msr_pr, - xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, - xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, - xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, - xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, - xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, - xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, - xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, - xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, - xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, - xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, - xu_mm_rf1_val => xu_mm_rf1_val, - xu_mm_rf1_t => xu_mm_rf1_t, - xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, - xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, - slowspr_addr_out => xu_mm_slowspr_addr, - slowspr_data_out => xu_mm_slowspr_data, - slowspr_done_out => xu_mm_slowspr_done, - slowspr_etid_out => xu_mm_slowspr_etid, - slowspr_rw_out => xu_mm_slowspr_rw, - slowspr_val_out => xu_mm_slowspr_val, - debug_data_out => xu_mm_debug_data, - trigger_data_out => xu_mm_trigger_data, - xu_pc_bo_fail => xu_pc_bo_fail, - xu_pc_bo_diagout => xu_pc_bo_diagout, - xu_pc_err_attention_instr => xu_pc_err_attention_instr, - xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, - xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, - xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, - xu_pc_err_debug_event => xu_pc_err_debug_event, - xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, - xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, - xu_pc_err_derat_parity => xu_pc_err_derat_parity, - xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, - xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, - xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, - xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, - xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, - xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, - xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, - xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, - xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, - xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, - xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, - xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, - xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, - xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, - xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, - xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, - xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, - xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, - xu_pc_err_invld_reld => xu_pc_err_invld_reld, - xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, - xu_pc_lsu_event_data => xu_pc_lsu_event_data, - xu_pc_event_data => xu_pc_event_data, - xu_pc_ram_data => xu_pc_ram_data, - xu_pc_ram_done => xu_pc_ram_done, - xu_pc_ram_interrupt => xu_pc_ram_interrupt, - xu_pc_running => xu_pc_running, - xu_pc_step_done => xu_pc_step_done, - xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, - xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val , - xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val , - xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd , - xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba , - xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz , - xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , - xu_iu_reld_core_tag => xu_iu_reld_core_tag, - xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, - xu_iu_reld_data => xu_iu_reld_data, - xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, - xu_iu_reld_data_vld => xu_iu_reld_data_vld, - xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, - xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, - xu_iu_reld_ecc_err => xu_iu_reld_ecc_err, - xu_iu_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, - xu_iu_reld_qw => xu_iu_reld_qw, - - bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , - bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , - bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , - bx_xu_quiesce => bx_xu_quiesce, - - bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , - bx_lsu_ob_req_val => bx_lsu_ob_req_val , - bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, - bx_lsu_ob_thrd => bx_lsu_ob_thrd , - bx_lsu_ob_qw => bx_lsu_ob_qw , - bx_lsu_ob_dest => bx_lsu_ob_dest , - bx_lsu_ob_data => bx_lsu_ob_data , - bx_lsu_ob_addr => bx_lsu_ob_addr , - lsu_bx_cmd_avail => lsu_bx_cmd_avail , - lsu_bx_cmd_sent => lsu_bx_cmd_sent , - lsu_bx_cmd_stall => lsu_bx_cmd_stall , - - - - ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, - ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_imm, - bx_ib_empty_int => bx_ib_empty_int, - bx_ib_empty_q => ac_an_box_empty_imm, - xu_iu_l_flush => xu_iu_l_flush, - xu_iu_u_flush => xu_iu_u_flush, - xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, - xu_fu_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, - xu_fu_lbist_en_dc => xu_fu_lbist_en_dc, - xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, - xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, - - gnd => gnd, - vcs => vcs, - vdd => vdd + xu_fu_ccr2_ap => xu_fu_ccr2_ap, + xu_fu_ex3_eff_addr => xu_fu_ex3_eff_addr, + xu_fu_ex6_load_data => xu_fu_ex6_load_data, + xu_fu_ex5_load_le => xu_fu_ex5_load_le, + xu_fu_ex5_load_tag => xu_fu_ex5_load_tag, + xu_fu_ex5_load_val => xu_fu_ex5_load_val, + xu_fu_ex5_reload_val => xu_fu_ex5_reload_val, + xu_fu_msr_fp => xu_fu_msr_fp, + xu_fu_msr_pr => xu_fu_msr_pr, + xu_fu_msr_gs => xu_fu_msr_gs, + xu_fu_msr_spv => xu_fu_msr_spv, + xu_fu_regfile_seq_beg => xu_fu_regfile_seq_beg, + xu_iu_complete_qentry => xu_iu_complete_qentry, + xu_iu_complete_target_type => xu_iu_complete_target_type, + xu_iu_complete_tid => xu_iu_complete_tid, + xu_iu_ex1_ra_entry => xu_iu_ex1_ra_entry, + xu_iu_ex1_rb => xu_iu_ex1_rb, + xu_iu_ex1_rs_is => xu_iu_ex1_rs_is, + xu_iu_ex5_bclr => xu_iu_ex5_bclr, + xu_iu_ex5_bh => xu_iu_ex5_bh, + xu_iu_ex5_br_hist => xu_iu_ex5_br_hist, + xu_iu_ex5_br_taken => xu_iu_ex5_br_taken, + xu_iu_ex5_br_update => xu_iu_ex5_br_update, + xu_iu_ex5_getNIA => xu_iu_ex5_getNIA, + xu_iu_ex5_gshare => xu_iu_ex5_gshare, + xu_iu_ex5_ifar => xu_iu_ex5_ifar, + xu_iu_ex5_lk => xu_iu_ex5_lk, + xu_iu_ex5_ppc_cpl => xu_iu_ex5_ppc_cpl, + xu_iu_ex4_loadmiss_qentry => xu_iu_ex4_loadmiss_qentry, + xu_iu_ex4_loadmiss_target => xu_iu_ex4_loadmiss_target, + xu_iu_ex4_loadmiss_target_type=> xu_iu_ex4_loadmiss_target_type, + xu_iu_ex4_loadmiss_tid => xu_iu_ex4_loadmiss_tid, + xu_iu_ex4_rs_data => xu_iu_ex4_rs_data, + xu_iu_ex5_tid => xu_iu_ex5_tid, + xu_iu_ex5_val => xu_iu_ex5_val, + xu_iu_ex5_loadmiss_qentry => xu_iu_ex5_loadmiss_qentry, + xu_iu_ex5_loadmiss_target => xu_iu_ex5_loadmiss_target, + xu_iu_ex5_loadmiss_target_type=> xu_iu_ex5_loadmiss_target_type, + xu_iu_ex5_loadmiss_tid => xu_iu_ex5_loadmiss_tid, + xu_iu_ex6_icbi_val => xu_iu_ex6_icbi_val, + xu_iu_ex6_icbi_addr => xu_iu_ex6_icbi_addr, + xu_iu_ex6_pri => xu_iu_ex6_pri, + xu_iu_ex6_pri_val => xu_iu_ex6_pri_val, + xu_iu_flush_2ucode => xu_iu_flush_2ucode, + xu_iu_flush_2ucode_type => xu_iu_flush_2ucode_type, + xu_iu_hid_mmu_mode => xu_iu_hid_mmu_mode, + xu_iu_xucr0_rel => xu_iu_xucr0_rel, + xu_iu_ici => xu_iu_ici, + xu_iu_iu0_flush_ifar0 => xu_iu_iu0_flush_ifar0, + xu_iu_iu0_flush_ifar1 => xu_iu_iu0_flush_ifar1, + xu_iu_iu0_flush_ifar2 => xu_iu_iu0_flush_ifar2, + xu_iu_iu0_flush_ifar3 => xu_iu_iu0_flush_ifar3, + xu_iu_larx_done_tid => xu_iu_larx_done_tid, + xu_iu_set_barr_tid => xu_iu_set_barr_tid, + xu_iu_membar_tid => xu_iu_membar_tid, + xu_iu_msr_cm => xu_iu_msr_cm, + xu_iu_msr_hv => xu_iu_msr_hv, + xu_iu_msr_is => xu_iu_msr_is, + xu_iu_msr_pr => xu_iu_msr_pr, + xu_iu_multdiv_done => xu_iu_multdiv_done, + xu_iu_need_hole => xu_iu_need_hole, + xu_iu_raise_iss_pri => xu_iu_raise_iss_pri, + xu_iu_ram_issue => xu_iu_ram_issue, + xu_iu_ex1_is_csync => xu_iu_ex1_is_csync, + xu_iu_ex1_is_isync => xu_iu_ex1_is_isync, + xu_iu_rf1_is_eratilx => xu_iu_rf1_is_eratilx, + xu_iu_rf1_is_eratre => xu_iu_rf1_is_eratre, + xu_iu_rf1_is_eratsx => xu_iu_rf1_is_eratsx, + xu_iu_rf1_is_eratwe => xu_iu_rf1_is_eratwe, + xu_iu_rf1_val => xu_iu_rf1_val, + xu_iu_rf1_ws => xu_iu_rf1_ws, + xu_iu_rf1_t => xu_iu_rf1_t, + xu_iu_run_thread => xu_iu_run_thread, + xu_iu_single_instr_mode => xu_iu_single_instr_mode, + xu_iu_slowspr_done => xu_iu_slowspr_done, + xu_iu_spr_ccr2_en_dcr => xu_iu_spr_ccr2_en_dcr, + xu_iu_spr_ccr2_ifratsc => xu_iu_spr_ccr2_ifratsc, + xu_iu_spr_ccr2_ifrat => xu_iu_spr_ccr2_ifrat, + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_iu_spr_xer0 => xu_iu_spr_xer0, + xu_iu_spr_xer1 => xu_iu_spr_xer1, + xu_iu_spr_xer2 => xu_iu_spr_xer2, + xu_iu_spr_xer3 => xu_iu_spr_xer3, + xu_iu_uc_flush_ifar0 => xu_iu_uc_flush_ifar0, + xu_iu_uc_flush_ifar1 => xu_iu_uc_flush_ifar1, + xu_iu_uc_flush_ifar2 => xu_iu_uc_flush_ifar2, + xu_iu_uc_flush_ifar3 => xu_iu_uc_flush_ifar3, + xu_iu_ucode_restart => xu_iu_ucode_restart, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_iu_msr_gs => xu_iu_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_out => xu_mm_slowspr_addr, + slowspr_data_out => xu_mm_slowspr_data, + slowspr_done_out => xu_mm_slowspr_done, + slowspr_etid_out => xu_mm_slowspr_etid, + slowspr_rw_out => xu_mm_slowspr_rw, + slowspr_val_out => xu_mm_slowspr_val, + debug_data_out => xu_mm_debug_data, + trigger_data_out => xu_mm_trigger_data, + xu_pc_bo_fail => xu_pc_bo_fail, + xu_pc_bo_diagout => xu_pc_bo_diagout, + xu_pc_err_attention_instr => xu_pc_err_attention_instr, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity, + xu_pc_err_debug_event => xu_pc_err_debug_event, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity, + xu_pc_err_derat_parity => xu_pc_err_derat_parity, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset, + xu_pc_err_invld_reld => xu_pc_err_invld_reld, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun, + xu_pc_lsu_event_data => xu_pc_lsu_event_data, + xu_pc_event_data => xu_pc_event_data, + xu_pc_ram_data => xu_pc_ram_data, + xu_pc_ram_done => xu_pc_ram_done, + xu_pc_ram_interrupt => xu_pc_ram_interrupt, + xu_pc_running => xu_pc_running, + xu_pc_step_done => xu_pc_step_done, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val , + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val , + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd , + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba , + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz , + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + xu_iu_reld_core_tag => xu_iu_reld_core_tag, + xu_iu_reld_core_tag_clone => xu_iu_reld_core_tag_clone, + xu_iu_reld_data => xu_iu_reld_data, + xu_iu_reld_data_coming_clone => xu_iu_reld_data_coming_clone, + xu_iu_reld_data_vld => xu_iu_reld_data_vld, + xu_iu_reld_data_vld_clone => xu_iu_reld_data_vld_clone, + xu_iu_reld_ditc_clone => xu_iu_reld_ditc_clone, + xu_iu_reld_ecc_err => xu_iu_reld_ecc_err, + xu_iu_reld_ecc_err_ue => xu_iu_reld_ecc_err_ue, + xu_iu_reld_qw => xu_iu_reld_qw, + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + bx_xu_quiesce => bx_xu_quiesce, + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok , + bx_lsu_ob_req_val => bx_lsu_ob_req_val , + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd , + bx_lsu_ob_qw => bx_lsu_ob_qw , + bx_lsu_ob_dest => bx_lsu_ob_dest , + bx_lsu_ob_data => bx_lsu_ob_data , + bx_lsu_ob_addr => bx_lsu_ob_addr , + lsu_bx_cmd_avail => lsu_bx_cmd_avail , + lsu_bx_cmd_sent => lsu_bx_cmd_sent , + lsu_bx_cmd_stall => lsu_bx_cmd_stall , + + + + ac_an_reld_ditc_pop_int => ac_an_reld_ditc_pop_int, + ac_an_reld_ditc_pop_q => ac_an_reld_ditc_pop_imm, + bx_ib_empty_int => bx_ib_empty_int, + bx_ib_empty_q => ac_an_box_empty_imm, + xu_iu_l_flush => xu_iu_l_flush, + xu_iu_u_flush => xu_iu_u_flush, + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled, + xu_fu_lbist_ary_wrt_thru_dc => xu_fu_lbist_ary_wrt_thru_dc, + xu_fu_lbist_en_dc => xu_fu_lbist_en_dc, + xu_iu_xucr4_mmu_mchk => xu_iu_xucr4_mmu_mchk, + xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, + + gnd => gnd, + vcs => vcs, + vdd => vdd ); - - ac_an_st_byte_enbl_imm <= xu_st_byte_enbl; - ac_an_st_data_imm <= xu_st_data; - - - - - - -a_mmq: entity work.mmq - generic map(data_out_width => data_out_width, - debug_event_width => debug_event_width, - debug_trace_width => debug_trace_width, - epn_width => epn_width, - eptr_width => eptr_width, - erat_ary_data_width => erat_ary_data_width, - erat_cam_data_width => erat_cam_data_width, - erat_rel_data_width => erat_rel_data_width, - error_width => error_width, - expand_tlb_type => expand_tlb_type, - expand_type => expand_type, - extclass_width => extclass_width, - inv_seq_width => inv_seq_width, - lpid_width => lpid_width, - lru_width => lru_width, - mmucr0_width => mmucr0_width, - mmucr1_width => mmucr1_width, - mmucr2_width => mmucr2_width, - mmucr3_width => mmucr3_width, - pid_width => pid_width, - por_seq_width => por_seq_width, - ra_entry_width => ra_entry_width, - real_addr_width => real_addr_width, - req_epn_width => req_epn_width, - rpn_width => rpn_width, - rs_data_width => rs_data_width, - rs_is_width => rs_is_width, - spr_addr_width => spr_addr_width, - spr_ctl_width => spr_ctl_width, - spr_data_width => spr_data_width, - spr_etid_width => spr_etid_width, - state_width => state_width, - thdid_width => thdid_width, - tlb_addr_width => tlb_addr_width, - tlb_num_entry => tlb_num_entry, - tlb_num_entry_log2 => tlb_num_entry_log2, - tlb_seq_width => tlb_seq_width, - tlb_tag_width => tlb_tag_width, - tlb_way_width => tlb_way_width, - tlb_ways => tlb_ways, - tlb_word_width => tlb_word_width, - tlbsel_width => tlbsel_width, - ttype_width => ttype_width, - vpn_width => vpn_width, - watermark_width => watermark_width, - ws_width => ws_width) - port map ( - an_ac_abst_scan_in => an_ac_abst_scan_in(0 to 9), - an_ac_bcfg_scan_in => an_ac_bcfg_scan_in(0 to 4), - an_ac_dcfg_scan_in => an_ac_dcfg_scan_in(0 to 2), - an_ac_func_scan_in => an_ac_func_scan_in(0 to 63), - gptr_scan_in => xu_mm_gptr_scan_out, - repr_scan_in => xu_mm_repr_scan_out, - time_scan_in => xu_mm_time_scan_out, - an_ac_back_inv => an_ac_back_inv, - an_ac_back_inv_addr => an_ac_back_inv_addr, - an_ac_back_inv_lbit => an_ac_back_inv_lbit, - an_ac_back_inv_gs => an_ac_back_inv_gs, - an_ac_back_inv_ind => an_ac_back_inv_ind, - an_ac_back_inv_local => an_ac_back_inv_local, - an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, - an_ac_back_inv_target => an_ac_back_inv_target, - an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, - an_ac_reld_core_tag => an_ac_reld_core_tag, - an_ac_reld_data => an_ac_reld_data, - an_ac_reld_data_vld => an_ac_reld_data_vld, - an_ac_reld_ecc_err => an_ac_reld_ecc_err, - an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, - an_ac_reld_qw => an_ac_reld_qw(57 to 59), - an_ac_reld_ditc => an_ac_reld_ditc, - an_ac_reld_crit_qw => an_ac_reld_crit_qw, - iu_mm_ierat_epn => iu_mm_ierat_epn, - iu_mm_ierat_flush => iu_mm_ierat_flush, - iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, - iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, - iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, - iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, - iu_mm_ierat_req => iu_mm_ierat_req, - iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, - iu_mm_ierat_thdid => iu_mm_ierat_thdid, - iu_mm_ierat_tid => iu_mm_ierat_tid, - iu_mm_ierat_state => iu_mm_ierat_state, - iu_mm_lmq_empty => iu_mm_lmq_empty, - nclk => a2_nclk, - pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_oiu, - pc_mm_abist_di_0 => pc_mm_abist_di_0_oiu, - pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_oiu, - pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_oiu, - pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_oiu, - pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_oiu, - pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_oiu, - pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_oiu, - pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_oiu, - pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_oiu, - pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_oiu, - pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_oiu, - pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_oiu, - pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena_oiu, - pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3_oiu, - pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3_oiu, - pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3_oiu, - pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3_oiu, - pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3_oiu, - pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, - pc_mm_bo_reset => pc_mm_bo_reset_oiu, - pc_mm_bo_unload => pc_mm_bo_unload_oiu, - pc_mm_bo_repair => pc_mm_bo_repair_oiu, - pc_mm_bo_shdata => pc_mm_bo_shdata_oiu, - pc_mm_bo_select => pc_mm_bo_select_oiu, - pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3_oiu, - pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3_oiu, - pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_oiu, - pc_mm_event_count_mode => pc_mm_event_count_mode_oiu, - pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_oiu, - pc_mm_fce_3 => pc_mm_fce_3_oiu, - pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3_oiu, - pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3_oiu, - pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3_oiu, - pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3_oiu, - pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3_oiu, - pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3_oiu, - pc_mm_sg_3 => pc_mm_sg_3_oiu, - pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3_oiu, - pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_oiu, - rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, - tc_ac_ccflush_dc => pc_mm_ccflush_dc_oiu, - tc_ac_lbist_en_dc => an_ac_lbist_en_dc, - tc_ac_scan_diag_dc => an_ac_scan_diag_dc, - tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, - debug_bus_in => xu_mm_debug_data, - trace_triggers_in => xu_mm_trigger_data, - xu_ex1_flush => xu_s_ex1_flush, - xu_ex2_flush => xu_s_ex2_flush, - xu_ex3_flush => xu_s_ex3_flush, - xu_ex4_flush => xu_s_ex4_flush, - xu_ex5_flush => xu_s_ex5_flush, - mm_xu_cr0_eq => mm_xu_cr0_eq, - mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, - xu_mm_derat_epn => xu_mm_derat_epn, - xu_mm_derat_lpid => xu_mm_derat_lpid, - xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, - xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, - xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, - xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, - xu_mm_derat_req => xu_mm_derat_req, - xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, - xu_mm_derat_state => xu_mm_derat_state, - xu_mm_derat_thdid => xu_mm_derat_thdid, - xu_mm_derat_tid => xu_mm_derat_tid, - xu_mm_derat_ttype => xu_mm_derat_ttype, - xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, - xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, - xu_mm_ex4_flush => xu_mm_ex4_flush, - xu_mm_ex5_flush => xu_mm_ex5_flush, - xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, - xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, - xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, - xu_mm_hold_ack => xu_mm_hold_ack, - xu_mm_ierat_flush => xu_mm_ierat_flush, - xu_mm_ierat_miss => xu_mm_ierat_miss, - xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, - xu_mm_lsu_token => xu_mm_lsu_token, - xu_mm_msr_cm => xu_mm_msr_cm, - xu_mm_msr_ds => xu_mm_msr_ds, - xu_mm_msr_gs => xu_mm_msr_gs, - xu_mm_msr_is => xu_mm_msr_is, - xu_mm_msr_pr => xu_mm_msr_pr, - xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, - xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, - xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, - xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, - xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, - xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, - xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, - xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, - xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, - xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, - xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, - xu_mm_rf1_val => xu_mm_rf1_val, - xu_mm_rf1_t => xu_mm_rf1_t, - xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, - xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, - slowspr_addr_in => xu_mm_slowspr_addr, - slowspr_data_in => xu_mm_slowspr_data, - slowspr_done_in => xu_mm_slowspr_done, - slowspr_etid_in => xu_mm_slowspr_etid, - slowspr_rw_in => xu_mm_slowspr_rw, - slowspr_val_in => xu_mm_slowspr_val, - xu_rf1_flush => xu_s_rf1_flush, - bcfg_scan_out => mm_rp_bcfg_scan_out, - ccfg_scan_out => mm_iu_ccfg_scan_out, - dcfg_scan_out => mm_rp_dcfg_scan_out, - ac_an_gptr_scan_out => ac_an_gptr_scan_out, - ac_an_repr_scan_out => ac_an_repr_scan_out, - ac_an_time_scan_out => ac_an_time_scan_out, - ac_an_back_inv_reject => ac_an_back_inv_reject, - ac_an_lpar_id => ac_an_lpar_id, - mm_iu_barrier_done => mm_iu_barrier_done, - mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, - mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, - mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, - mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, - mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, - mm_iu_ierat_pid0 => mm_iu_ierat_pid0, - mm_iu_ierat_pid1 => mm_iu_ierat_pid1, - mm_iu_ierat_pid2 => mm_iu_ierat_pid2, - mm_iu_ierat_pid3 => mm_iu_ierat_pid3, - mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, - mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, - mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, - mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, - mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, - mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, - slowspr_addr_out => mm_iu_slowspr_addr, - slowspr_data_out => mm_iu_slowspr_data, - slowspr_done_out => mm_iu_slowspr_done, - slowspr_etid_out => mm_iu_slowspr_etid, - slowspr_rw_out => mm_iu_slowspr_rw, - slowspr_val_out => mm_iu_slowspr_val, - debug_bus_out => ac_an_debug_bus_int, - trace_triggers_out => ac_an_trace_triggers, - mm_pc_bo_diagout => mm_pc_bo_diagout_iiu, - mm_pc_bo_fail => mm_pc_bo_fail_iiu, - mm_pc_event_data => mm_pc_event_data_iiu, - mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, - mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, - mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, - mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, - mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, - mm_xu_derat_pid0 => mm_xu_derat_pid0, - mm_xu_derat_pid1 => mm_xu_derat_pid1, - mm_xu_derat_pid2 => mm_xu_derat_pid2, - mm_xu_derat_pid3 => mm_xu_derat_pid3, - mm_xu_derat_rel_data => mm_xu_derat_rel_data, - mm_xu_derat_rel_val => mm_xu_derat_rel_val, - mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, - mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, - mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, - mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, - mm_xu_eratmiss_done => mm_xu_eratmiss_done, - mm_xu_esr_pt => mm_xu_esr_pt, - mm_xu_esr_data => mm_xu_esr_data, - mm_xu_esr_epid => mm_xu_esr_epid, - mm_xu_esr_st => mm_xu_esr_st, - mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, - mm_xu_hold_done => mm_xu_hold_done, - mm_xu_hold_req => mm_xu_hold_req, - mm_xu_hv_priv => mm_xu_hv_priv, - mm_xu_illeg_instr => mm_xu_illeg_instr, - mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, - mm_xu_lrat_miss => mm_xu_lrat_miss, - mm_xu_lsu_addr => mm_xu_lsu_addr, - mm_xu_lsu_lpid => mm_xu_lsu_lpid, - mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, - mm_xu_lsu_gs => mm_xu_lsu_gs, - mm_xu_lsu_ind => mm_xu_lsu_ind, - mm_xu_lsu_lbit => mm_xu_lsu_lbit, - mm_xu_lsu_req => mm_xu_lsu_req, - mm_xu_lsu_ttype => mm_xu_lsu_ttype, - mm_xu_lsu_u => mm_xu_lsu_u, - mm_xu_lsu_wimge => mm_xu_lsu_wimge, - mm_xu_pt_fault => mm_xu_pt_fault, - mm_xu_quiesce => mm_xu_quiesce, - mm_xu_tlb_inelig => mm_xu_tlb_inelig, - mm_xu_tlb_miss => mm_xu_tlb_miss, - mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, - mm_xu_tlb_par_err => mm_xu_tlb_par_err, - mm_xu_lru_par_err => mm_xu_lru_par_err, - - an_ac_reld_data_coming => an_ac_reld_data_coming, - an_ac_reld_l1_dump => an_ac_reld_l1_dump, - an_ac_grffence_en_dc => an_ac_camfence_en_dc, - an_ac_stcx_complete => an_ac_stcx_complete, - an_ac_abist_mode_dc => an_ac_abist_mode_dc, - an_ac_abist_start_test => an_ac_abist_start_test, - an_ac_atpg_en_dc => an_ac_atpg_en_dc, - an_ac_ccflush_dc => an_ac_ccflush_dc, - an_ac_reset_1_complete => an_ac_reset_1_complete, - an_ac_reset_2_complete => an_ac_reset_2_complete, - an_ac_reset_3_complete => an_ac_reset_3_complete, - an_ac_reset_wd_complete => an_ac_reset_wd_complete, - an_ac_debug_stop => an_ac_debug_stop, - an_ac_lbist_en_dc => an_ac_lbist_en_dc, - an_ac_pm_thread_stop => an_ac_pm_thread_stop, - an_ac_regf_scan_in => an_ac_regf_scan_in, - an_ac_scan_diag_dc => an_ac_scan_diag_dc, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, - an_ac_scom_cch => an_ac_scom_cch, - an_ac_scom_dch => an_ac_scom_dch, - an_ac_checkstop => an_ac_checkstop, - an_ac_back_inv_omm => an_ac_back_inv_omm, - an_ac_back_inv_addr_omm => an_ac_back_inv_addr_omm, - an_ac_back_inv_target_omm_iua => an_ac_back_inv_target_omm_iua, - an_ac_back_inv_target_omm_iub => an_ac_back_inv_target_omm_iub, - an_ac_reld_core_tag_omm => an_ac_reld_core_tag_omm, - an_ac_reld_data_omm => an_ac_reld_data_omm, - an_ac_reld_data_vld_omm => an_ac_reld_data_vld_omm, - an_ac_reld_ecc_err_omm => an_ac_reld_ecc_err_omm, - an_ac_reld_ecc_err_ue_omm => an_ac_reld_ecc_err_ue_omm, - an_ac_reld_qw_omm => an_ac_reld_qw_omm, - an_ac_reld_ditc_omm => an_ac_reld_ditc_omm, - an_ac_reld_crit_qw_omm => an_ac_reld_crit_qw_omm, - an_ac_reld_data_coming_omm => an_ac_reld_data_coming_omm, - an_ac_reld_l1_dump_omm => an_ac_reld_l1_dump_omm, - an_ac_grffence_en_dc_omm => an_ac_camfence_en_dc_omm, - an_ac_stcx_complete_omm => an_ac_stcx_complete_omm, - an_ac_abist_mode_dc_omm => an_ac_abist_mode_dc_omm, - an_ac_abist_start_test_omm => an_ac_abist_start_test_omm, - an_ac_abst_scan_in_omm_iu => an_ac_abst_scan_in_omm_iu, - an_ac_abst_scan_in_omm_xu => an_ac_abst_scan_in_omm_xu, - an_ac_atpg_en_dc_omm => an_ac_atpg_en_dc_omm, - an_ac_bcfg_scan_in_omm_bit1 => an_ac_bcfg_scan_in_omm_bit1, - an_ac_bcfg_scan_in_omm_bit3 => an_ac_bcfg_scan_in_omm_bit3, - an_ac_bcfg_scan_in_omm_bit4 => an_ac_bcfg_scan_in_omm_bit4, - an_ac_lbist_ary_wrt_thru_dc_omm => an_ac_lbist_ary_wrt_thru_dc_omm, - an_ac_ccflush_dc_omm => an_ac_ccflush_dc_omm, - an_ac_reset_1_complete_omm => an_ac_reset_1_complete_omm, - an_ac_reset_2_complete_omm => an_ac_reset_2_complete_omm, - an_ac_reset_3_complete_omm => an_ac_reset_3_complete_omm, - an_ac_reset_wd_complete_omm => an_ac_reset_wd_complete_omm, - an_ac_dcfg_scan_in_omm => an_ac_dcfg_scan_in_omm, - an_ac_debug_stop_omm => an_ac_debug_stop_omm, - an_ac_func_scan_in_omm_iua => an_ac_func_scan_in_omm_iua, - an_ac_func_scan_in_omm_iub => an_ac_func_scan_in_omm_iub, - an_ac_func_scan_in_omm_xu => an_ac_func_scan_in_omm_xu, - an_ac_lbist_en_dc_omm => an_ac_lbist_en_dc_omm, - an_ac_pm_thread_stop_omm => an_ac_pm_thread_stop_omm, - an_ac_regf_scan_in_omm => an_ac_regf_scan_in_omm, - an_ac_scan_diag_dc_omm => an_ac_scan_diag_dc_omm, - an_ac_scan_dis_dc_b_omm => an_ac_scan_dis_dc_b_omm, - an_ac_scom_cch_omm => an_ac_scom_cch_omm, - an_ac_scom_dch_omm => an_ac_scom_dch_omm, - an_ac_checkstop_omm => an_ac_checkstop_omm, - ac_an_abst_scan_out_imm_iu => ac_an_abst_scan_out_imm_iu, - ac_an_abst_scan_out_imm_xu => ac_an_abst_scan_out_imm_xu, - ac_an_bcfg_scan_out_imm => ac_an_bcfg_scan_out_imm, - ac_an_dcfg_scan_out_imm => ac_an_dcfg_scan_out_imm, - ac_an_func_scan_out_imm_iua => ac_an_func_scan_out_imm_iua, - ac_an_func_scan_out_imm_iub => ac_an_func_scan_out_imm_iub, - ac_an_func_scan_out_imm_xu => ac_an_func_scan_out_imm_xu, - ac_an_reld_ditc_pop_imm => ac_an_reld_ditc_pop_imm, - ac_an_power_managed_imm => ac_an_power_managed_imm, - ac_an_rvwinkle_mode_imm => ac_an_rvwinkle_mode_imm, - ac_an_fu_bypass_events_imm => ac_an_fu_bypass_events_imm, - ac_an_iu_bypass_events_imm => ac_an_iu_bypass_events_imm, - ac_an_mm_bypass_events_imm => ac_an_mm_bypass_events_imm, - ac_an_lsu_bypass_events_imm => ac_an_lsu_bypass_events_imm, - ac_an_event_bus_imm => ac_an_event_bus_imm, - ac_an_pm_thread_running_imm => ac_an_pm_thread_running_imm, - ac_an_recov_err_imm => ac_an_recov_err_imm, - ac_an_regf_scan_out_imm => ac_an_regf_scan_out_imm, - ac_an_scom_cch_imm => ac_an_scom_cch_imm, - ac_an_scom_dch_imm => ac_an_scom_dch_imm, - ac_an_special_attn_imm => ac_an_special_attn_imm, - ac_an_checkstop_imm => ac_an_checkstop_imm, - ac_an_local_checkstop_imm => ac_an_local_checkstop_imm, - ac_an_trace_error_imm => ac_an_trace_error_imm, - ac_an_abst_scan_out => ac_an_abst_scan_out, - ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, - ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, - ac_an_func_scan_out => ac_an_func_scan_out, - ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, - ac_an_power_managed => ac_an_power_managed, - ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, - ac_an_fu_bypass_events => ac_an_fu_bypass_events, - ac_an_iu_bypass_events => ac_an_iu_bypass_events, - ac_an_mm_bypass_events => ac_an_mm_bypass_events, - ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, - ac_an_event_bus => ac_an_event_bus, - ac_an_pm_thread_running => ac_an_pm_thread_running, - ac_an_recov_err => ac_an_recov_err, - ac_an_regf_scan_out => ac_an_regf_scan_out, - ac_an_scom_cch => ac_an_scom_cch, - ac_an_scom_dch => ac_an_scom_dch, - ac_an_special_attn => ac_an_special_attn, - ac_an_checkstop => ac_an_checkstop, - ac_an_local_checkstop => ac_an_local_checkstop, - ac_an_trace_error => ac_an_trace_error, - an_ac_dcr_act => an_ac_dcr_act, - an_ac_dcr_val => an_ac_dcr_val, - an_ac_dcr_read => an_ac_dcr_read, - an_ac_dcr_etid => an_ac_dcr_etid, - an_ac_dcr_data => an_ac_dcr_data, - an_ac_dcr_done => an_ac_dcr_done, - an_ac_crit_interrupt => an_ac_crit_interrupt, - an_ac_ext_interrupt => an_ac_ext_interrupt, - an_ac_flh2l2_gate => an_ac_flh2l2_gate, - an_ac_icbi_ack => an_ac_icbi_ack, - an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, - an_ac_req_ld_pop => an_ac_req_ld_pop, - an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, - an_ac_req_st_gather => an_ac_req_st_gather, - an_ac_req_st_pop => an_ac_req_st_pop, - an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, - an_ac_reservation_vld => an_ac_reservation_vld, - an_ac_sleep_en => an_ac_sleep_en, - an_ac_stcx_pass => an_ac_stcx_pass, - an_ac_sync_ack => an_ac_sync_ack, - an_ac_ary_nsl_thold_7 => an_ac_ary_nsl_thold_7, - an_ac_ccenable_dc => an_ac_ccenable_dc, - an_ac_coreid => an_ac_coreid, - an_ac_external_mchk => an_ac_external_mchk, - an_ac_fce_7 => an_ac_fce_7, - an_ac_func_nsl_thold_7 => an_ac_func_nsl_thold_7, - an_ac_func_sl_thold_7 => an_ac_func_sl_thold_7, - an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, - an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, - an_ac_gptr_scan_in => an_ac_gptr_scan_in, - an_ac_hang_pulse => an_ac_hang_pulse, - an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, - an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, - an_ac_malf_alert => an_ac_malf_alert, - an_ac_perf_interrupt => an_ac_perf_interrupt, - an_ac_psro_enable_dc => an_ac_psro_enable_dc, - an_ac_repr_scan_in => an_ac_repr_scan_in, - an_ac_rtim_sl_thold_7 => an_ac_rtim_sl_thold_7, - an_ac_scan_type_dc => an_ac_scan_type_dc, - an_ac_scom_sat_id => an_ac_scom_sat_id, - an_ac_sg_7 => an_ac_sg_7, - an_ac_tb_update_enable => an_ac_tb_update_enable, - an_ac_tb_update_pulse => an_ac_tb_update_pulse, - an_ac_time_scan_in => an_ac_time_scan_in, - an_ac_crit_interrupt_omm => an_ac_crit_interrupt_omm, - an_ac_ext_interrupt_omm => an_ac_ext_interrupt_omm, - an_ac_flh2l2_gate_omm => an_ac_flh2l2_gate_omm, - an_ac_icbi_ack_omm => an_ac_icbi_ack_omm, - an_ac_icbi_ack_thread_omm => an_ac_icbi_ack_thread_omm, - an_ac_req_ld_pop_omm => an_ac_req_ld_pop_omm, - an_ac_req_spare_ctrl_a1_omm => an_ac_req_spare_ctrl_a1_omm, - an_ac_req_st_gather_omm => an_ac_req_st_gather_omm, - an_ac_req_st_pop_omm => an_ac_req_st_pop_omm, - an_ac_req_st_pop_thrd_omm => an_ac_req_st_pop_thrd_omm, - an_ac_reservation_vld_omm => an_ac_reservation_vld_omm, - an_ac_sleep_en_omm => an_ac_sleep_en_omm, - an_ac_stcx_pass_omm => an_ac_stcx_pass_omm, - an_ac_sync_ack_omm => an_ac_sync_ack_omm, - an_ac_ary_nsl_thold_7_omm => an_ac_ary_nsl_thold_7_omm, - an_ac_ccenable_dc_omm => an_ac_ccenable_dc_iiu, - an_ac_coreid_omm => an_ac_coreid_omm, - an_ac_external_mchk_omm => an_ac_external_mchk_omm, - an_ac_fce_7_omm => an_ac_fce_7_omm, - an_ac_func_nsl_thold_7_omm => an_ac_func_nsl_thold_7_omm, - an_ac_func_sl_thold_7_omm => an_ac_func_sl_thold_7_omm, - an_ac_gsd_test_enable_dc_omm => an_ac_gsd_test_enable_dc_omm, - an_ac_gsd_test_acmode_dc_omm => an_ac_gsd_test_acmode_dc_omm, - an_ac_gptr_scan_in_omm => an_ac_gptr_scan_in_omm, - an_ac_hang_pulse_omm => an_ac_hang_pulse_omm, - an_ac_lbist_ac_mode_dc_omm => an_ac_lbist_ac_mode_dc_omm, - an_ac_lbist_ip_dc_omm => an_ac_lbist_ip_dc_omm, - an_ac_malf_alert_omm => an_ac_malf_alert_omm, - an_ac_perf_interrupt_omm => an_ac_perf_interrupt_omm, - an_ac_psro_enable_dc_omm => an_ac_psro_enable_dc_omm, - an_ac_repr_scan_in_omm => an_ac_repr_scan_in_omm, - an_ac_rtim_sl_thold_7_omm => an_ac_rtim_sl_thold_7_omm, - an_ac_scan_type_dc_omm => an_ac_scan_type_dc_omm, - an_ac_scom_sat_id_omm => an_ac_scom_sat_id_omm, - an_ac_sg_7_omm => an_ac_sg_7_omm, - an_ac_tb_update_enable_omm => an_ac_tb_update_enable_omm, - an_ac_tb_update_pulse_omm => an_ac_tb_update_pulse_omm, - an_ac_time_scan_in_omm => an_ac_time_scan_in_omm, - - ac_an_box_empty_imm => ac_an_box_empty_imm, - ac_an_machine_check_imm => ac_an_machine_check_imm, - ac_an_req_imm => ac_an_req_imm, - ac_an_req_endian_imm => ac_an_req_endian_imm, - ac_an_req_ld_core_tag_imm => ac_an_req_ld_core_tag_imm, - ac_an_req_ld_xfr_len_imm => ac_an_req_ld_xfr_len_imm, - ac_an_req_pwr_token_imm => ac_an_req_pwr_token_imm, - ac_an_req_ra_imm => ac_an_req_ra_imm, - ac_an_req_spare_ctrl_a0_imm => ac_an_req_spare_ctrl_a0_imm, - ac_an_req_thread_imm => ac_an_req_thread_imm, - ac_an_req_ttype_imm => ac_an_req_ttype_imm, - ac_an_req_user_defined_imm => ac_an_req_user_defined_imm, - ac_an_req_wimg_g_imm => ac_an_req_wimg_g_imm, - ac_an_req_wimg_i_imm => ac_an_req_wimg_i_imm, - ac_an_req_wimg_m_imm => ac_an_req_wimg_m_imm, - ac_an_req_wimg_w_imm => ac_an_req_wimg_w_imm, - ac_an_st_byte_enbl_imm => ac_an_st_byte_enbl_imm, - ac_an_st_data_imm => ac_an_st_data_imm, - ac_an_st_data_pwr_token_imm => ac_an_st_data_pwr_token_imm, - ac_an_abist_done_dc_imm => ac_an_abist_done_dc_oiu, - ac_an_debug_trigger_imm => ac_an_debug_trigger_imm, - ac_an_psro_ringsig_imm => ac_an_psro_ringsig_oiu, - ac_an_reset_1_request_imm => ac_an_reset_1_request_imm, - ac_an_reset_2_request_imm => ac_an_reset_2_request_imm, - ac_an_reset_3_request_imm => ac_an_reset_3_request_imm, - ac_an_reset_wd_request_imm => ac_an_reset_wd_request_imm, - - ac_an_box_empty => ac_an_box_empty, - ac_an_machine_check => ac_an_machine_check, - ac_an_req => ac_an_req, - ac_an_req_endian => ac_an_req_endian, - ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, - ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, - ac_an_req_pwr_token => ac_an_req_pwr_token, - ac_an_req_ra => ac_an_req_ra, - ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, - ac_an_req_thread => ac_an_req_thread, - ac_an_req_ttype => ac_an_req_ttype, - ac_an_req_user_defined => ac_an_req_user_defined, - ac_an_req_wimg_g => ac_an_req_wimg_g, - ac_an_req_wimg_i => ac_an_req_wimg_i, - ac_an_req_wimg_m => ac_an_req_wimg_m, - ac_an_req_wimg_w => ac_an_req_wimg_w, - ac_an_st_byte_enbl => ac_an_st_byte_enbl, - ac_an_st_data => ac_an_st_data, - ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, - ac_an_abist_done_dc => ac_an_abist_done_dc, - ac_an_debug_trigger => ac_an_debug_trigger, - ac_an_psro_ringsig => ac_an_psro_ringsig, - ac_an_reset_1_request => ac_an_reset_1_request, - ac_an_reset_2_request => ac_an_reset_2_request, - ac_an_reset_3_request => ac_an_reset_3_request, - ac_an_reset_wd_request => ac_an_reset_wd_request, - ac_an_dcr_act => ac_an_dcr_act, - ac_an_dcr_val => ac_an_dcr_val, - ac_an_dcr_read => ac_an_dcr_read, - ac_an_dcr_user => ac_an_dcr_user, - ac_an_dcr_etid => ac_an_dcr_etid, - ac_an_dcr_addr => ac_an_dcr_addr, - ac_an_dcr_data => ac_an_dcr_data, - - debug_bus_out_int => debug_bus_out_int, - - bg_ac_an_func_scan_ns_imm => bg_ac_an_func_scan_ns_q, - bg_ac_an_abst_scan_ns_imm => bg_ac_an_abst_scan_ns_q, - bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, - bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, - bg_pc_l1p_abist_di_0_imm => bg_pc_l1p_abist_di_0_q, - bg_pc_l1p_abist_g8t1p_renb_0_imm => bg_pc_l1p_abist_g8t1p_renb_0_q, - bg_pc_l1p_abist_g8t_bw_0_imm => bg_pc_l1p_abist_g8t_bw_0_q, - bg_pc_l1p_abist_g8t_bw_1_imm => bg_pc_l1p_abist_g8t_bw_1_q, - bg_pc_l1p_abist_g8t_dcomp_imm => bg_pc_l1p_abist_g8t_dcomp_q, - bg_pc_l1p_abist_g8t_wenb_imm => bg_pc_l1p_abist_g8t_wenb_q, - bg_pc_l1p_abist_raddr_0_imm => bg_pc_l1p_abist_raddr_0_q, - bg_pc_l1p_abist_waddr_0_imm => bg_pc_l1p_abist_waddr_0_q, - bg_pc_l1p_abist_wl128_comp_ena_imm => bg_pc_l1p_abist_wl128_comp_ena_q, - bg_pc_l1p_abist_wl32_comp_ena_imm => bg_pc_l1p_abist_wl32_comp_ena_q, - bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, - bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, - bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, - bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, - bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, - bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, - bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, - bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, - bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, - bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, - bg_pc_l1p_gptr_sl_thold_2_imm => bg_pc_l1p_gptr_sl_thold_2_imm, - bg_pc_l1p_time_sl_thold_2_imm => bg_pc_l1p_time_sl_thold_2_imm, - bg_pc_l1p_repr_sl_thold_2_imm => bg_pc_l1p_repr_sl_thold_2_imm, - bg_pc_l1p_abst_sl_thold_2_imm => bg_pc_l1p_abst_sl_thold_2_imm, - bg_pc_l1p_func_sl_thold_2_imm => bg_pc_l1p_func_sl_thold_2_imm, - bg_pc_l1p_func_slp_sl_thold_2_imm => bg_pc_l1p_func_slp_sl_thold_2_imm, - bg_pc_l1p_bolt_sl_thold_2_imm => bg_pc_l1p_bolt_sl_thold_2_imm, - bg_pc_l1p_ary_nsl_thold_2_imm => bg_pc_l1p_ary_nsl_thold_2_imm, - bg_pc_l1p_sg_2_imm => bg_pc_l1p_sg_2_imm, - bg_pc_l1p_fce_2_imm => bg_pc_l1p_fce_2_imm, - bg_pc_l1p_bo_enable_2_imm => bg_pc_l1p_bo_enable_2_imm, - bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, - bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, - bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, - bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, - bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, - bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, - bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, - bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, - bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, - bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, - bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, - bg_pc_bo_unload_imm => bg_pc_bo_unload_oiu, - bg_pc_bo_load_imm => bg_pc_bo_load_oiu, - bg_pc_bo_repair_imm => bg_pc_bo_repair_oiu, - bg_pc_bo_reset_imm => bg_pc_bo_reset_oiu, - bg_pc_bo_shdata_imm => bg_pc_bo_shdata_oiu, - bg_pc_bo_select_imm => bg_pc_bo_select_oiu, - bg_pc_l1p_ccflush_dc_imm => bg_pc_l1p_ccflush_dc_oiu, - bg_pc_l1p_abist_ena_dc_imm => bg_pc_l1p_abist_ena_dc_oiu, - bg_pc_l1p_abist_raw_dc_b_imm => bg_pc_l1p_abist_raw_dc_b_oiu, - bg_pc_bo_unload => bg_pc_bo_unload, - bg_pc_bo_load => bg_pc_bo_load, - bg_pc_bo_repair => bg_pc_bo_repair, - bg_pc_bo_reset => bg_pc_bo_reset, - bg_pc_bo_shdata => bg_pc_bo_shdata, - bg_pc_bo_select => bg_pc_bo_select, - bg_pc_l1p_ccflush_dc => bg_pc_l1p_ccflush_dc, - bg_pc_l1p_abist_ena_dc => bg_pc_l1p_abist_ena_dc, - bg_pc_l1p_abist_raw_dc_b => bg_pc_l1p_abist_raw_dc_b, - bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, - bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, - bg_an_ac_func_scan_sn_omm => bg_an_ac_func_scan_sn_omm, - bg_an_ac_abst_scan_sn_omm => bg_an_ac_abst_scan_sn_omm, - bg_pc_bo_fail => bg_pc_bo_fail, - bg_pc_bo_diagout => bg_pc_bo_diagout, - bg_pc_bo_fail_omm => bg_pc_bo_fail_omm, - bg_pc_bo_diagout_omm => bg_pc_bo_diagout_omm, + + ac_an_st_byte_enbl_imm <= xu_st_byte_enbl; + ac_an_st_data_imm <= xu_st_data; + + + + + + +a_mmq: entity work.mmq + generic map(data_out_width => data_out_width, + debug_event_width => debug_event_width, + debug_trace_width => debug_trace_width, + epn_width => epn_width, + eptr_width => eptr_width, + erat_ary_data_width => erat_ary_data_width, + erat_cam_data_width => erat_cam_data_width, + erat_rel_data_width => erat_rel_data_width, + error_width => error_width, + expand_tlb_type => expand_tlb_type, + expand_type => expand_type, + extclass_width => extclass_width, + inv_seq_width => inv_seq_width, + lpid_width => lpid_width, + lru_width => lru_width, + mmucr0_width => mmucr0_width, + mmucr1_width => mmucr1_width, + mmucr2_width => mmucr2_width, + mmucr3_width => mmucr3_width, + pid_width => pid_width, + por_seq_width => por_seq_width, + ra_entry_width => ra_entry_width, + real_addr_width => real_addr_width, + req_epn_width => req_epn_width, + rpn_width => rpn_width, + rs_data_width => rs_data_width, + rs_is_width => rs_is_width, + spr_addr_width => spr_addr_width, + spr_ctl_width => spr_ctl_width, + spr_data_width => spr_data_width, + spr_etid_width => spr_etid_width, + state_width => state_width, + thdid_width => thdid_width, + tlb_addr_width => tlb_addr_width, + tlb_num_entry => tlb_num_entry, + tlb_num_entry_log2 => tlb_num_entry_log2, + tlb_seq_width => tlb_seq_width, + tlb_tag_width => tlb_tag_width, + tlb_way_width => tlb_way_width, + tlb_ways => tlb_ways, + tlb_word_width => tlb_word_width, + tlbsel_width => tlbsel_width, + ttype_width => ttype_width, + vpn_width => vpn_width, + watermark_width => watermark_width, + ws_width => ws_width) + port map ( + an_ac_abst_scan_in => an_ac_abst_scan_in(0 to 9), + an_ac_bcfg_scan_in => an_ac_bcfg_scan_in(0 to 4), + an_ac_dcfg_scan_in => an_ac_dcfg_scan_in(0 to 2), + an_ac_func_scan_in => an_ac_func_scan_in(0 to 63), + gptr_scan_in => xu_mm_gptr_scan_out, + repr_scan_in => xu_mm_repr_scan_out, + time_scan_in => xu_mm_time_scan_out, + an_ac_back_inv => an_ac_back_inv, + an_ac_back_inv_addr => an_ac_back_inv_addr, + an_ac_back_inv_lbit => an_ac_back_inv_lbit, + an_ac_back_inv_gs => an_ac_back_inv_gs, + an_ac_back_inv_ind => an_ac_back_inv_ind, + an_ac_back_inv_local => an_ac_back_inv_local, + an_ac_back_inv_lpar_id => an_ac_back_inv_lpar_id, + an_ac_back_inv_target => an_ac_back_inv_target, + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc, + an_ac_reld_core_tag => an_ac_reld_core_tag, + an_ac_reld_data => an_ac_reld_data, + an_ac_reld_data_vld => an_ac_reld_data_vld, + an_ac_reld_ecc_err => an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue => an_ac_reld_ecc_err_ue, + an_ac_reld_qw => an_ac_reld_qw(57 to 59), + an_ac_reld_ditc => an_ac_reld_ditc, + an_ac_reld_crit_qw => an_ac_reld_crit_qw, + iu_mm_ierat_epn => iu_mm_ierat_epn, + iu_mm_ierat_flush => iu_mm_ierat_flush, + iu_mm_ierat_mmucr0 => iu_mm_ierat_mmucr0, + iu_mm_ierat_mmucr0_we => iu_mm_ierat_mmucr0_we, + iu_mm_ierat_mmucr1 => iu_mm_ierat_mmucr1, + iu_mm_ierat_mmucr1_we => iu_mm_ierat_mmucr1_we, + iu_mm_ierat_req => iu_mm_ierat_req, + iu_mm_ierat_snoop_ack => iu_mm_ierat_snoop_ack, + iu_mm_ierat_thdid => iu_mm_ierat_thdid, + iu_mm_ierat_tid => iu_mm_ierat_tid, + iu_mm_ierat_state => iu_mm_ierat_state, + iu_mm_lmq_empty => iu_mm_lmq_empty, + nclk => a2_nclk, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_oiu, + pc_mm_abist_di_0 => pc_mm_abist_di_0_oiu, + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_oiu, + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_oiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_oiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_oiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_oiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_oiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_oiu, + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_oiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_oiu, + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_oiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_oiu, + pc_mm_abist_wl128_comp_ena => pc_mm_abist_wl128_comp_ena_oiu, + pc_mm_abst_sl_thold_3 => pc_mm_abst_sl_thold_3_oiu, + pc_mm_abst_slp_sl_thold_3 => pc_mm_abst_slp_sl_thold_3_oiu, + pc_mm_ary_nsl_thold_3 => pc_mm_ary_nsl_thold_3_oiu, + pc_mm_ary_slp_nsl_thold_3 => pc_mm_ary_slp_nsl_thold_3_oiu, + pc_mm_bolt_sl_thold_3 => pc_mm_bolt_sl_thold_3_oiu, + pc_mm_bo_enable_3 => pc_mm_bo_enable_3_oiu, + pc_mm_bo_reset => pc_mm_bo_reset_oiu, + pc_mm_bo_unload => pc_mm_bo_unload_oiu, + pc_mm_bo_repair => pc_mm_bo_repair_oiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_oiu, + pc_mm_bo_select => pc_mm_bo_select_oiu, + pc_mm_cfg_sl_thold_3 => pc_mm_cfg_sl_thold_3_oiu, + pc_mm_cfg_slp_sl_thold_3 => pc_mm_cfg_slp_sl_thold_3_oiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_oiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_oiu, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_oiu, + pc_mm_fce_3 => pc_mm_fce_3_oiu, + pc_mm_func_nsl_thold_3 => pc_mm_func_nsl_thold_3_oiu, + pc_mm_func_sl_thold_3 => pc_mm_func_sl_thold_3_oiu, + pc_mm_func_slp_nsl_thold_3 => pc_mm_func_slp_nsl_thold_3_oiu, + pc_mm_func_slp_sl_thold_3 => pc_mm_func_slp_sl_thold_3_oiu, + pc_mm_gptr_sl_thold_3 => pc_mm_gptr_sl_thold_3_oiu, + pc_mm_repr_sl_thold_3 => pc_mm_repr_sl_thold_3_oiu, + pc_mm_sg_3 => pc_mm_sg_3_oiu, + pc_mm_time_sl_thold_3 => pc_mm_time_sl_thold_3_oiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_oiu, + rp_mm_event_bus_enable_q => rp_mm_event_bus_enable_q, + tc_ac_ccflush_dc => pc_mm_ccflush_dc_oiu, + tc_ac_lbist_en_dc => an_ac_lbist_en_dc, + tc_ac_scan_diag_dc => an_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + debug_bus_in => xu_mm_debug_data, + trace_triggers_in => xu_mm_trigger_data, + xu_ex1_flush => xu_s_ex1_flush, + xu_ex2_flush => xu_s_ex2_flush, + xu_ex3_flush => xu_s_ex3_flush, + xu_ex4_flush => xu_s_ex4_flush, + xu_ex5_flush => xu_s_ex5_flush, + mm_xu_cr0_eq => mm_xu_cr0_eq, + mm_xu_cr0_eq_valid => mm_xu_cr0_eq_valid, + xu_mm_derat_epn => xu_mm_derat_epn, + xu_mm_derat_lpid => xu_mm_derat_lpid, + xu_mm_derat_mmucr0 => xu_mm_derat_mmucr0, + xu_mm_derat_mmucr0_we => xu_mm_derat_mmucr0_we, + xu_mm_derat_mmucr1 => xu_mm_derat_mmucr1, + xu_mm_derat_mmucr1_we => xu_mm_derat_mmucr1_we, + xu_mm_derat_req => xu_mm_derat_req, + xu_mm_derat_snoop_ack => xu_mm_derat_snoop_ack, + xu_mm_derat_state => xu_mm_derat_state, + xu_mm_derat_thdid => xu_mm_derat_thdid, + xu_mm_derat_tid => xu_mm_derat_tid, + xu_mm_derat_ttype => xu_mm_derat_ttype, + xu_mm_ex2_eff_addr => xu_mm_ex2_eff_addr, + xu_mm_ex1_rs_is => xu_mm_ex1_rs_is, + xu_mm_ex4_flush => xu_mm_ex4_flush, + xu_mm_ex5_flush => xu_mm_ex5_flush, + xu_mm_ex5_perf_dtlb => xu_mm_ex5_perf_dtlb, + xu_mm_ex5_perf_itlb => xu_mm_ex5_perf_itlb, + xu_mm_hid_mmu_mode => xu_mm_hid_mmu_mode, + xu_mm_hold_ack => xu_mm_hold_ack, + xu_mm_ierat_flush => xu_mm_ierat_flush, + xu_mm_ierat_miss => xu_mm_ierat_miss, + xu_mm_lmq_stq_empty => xu_mm_lmq_stq_empty, + xu_mm_lsu_token => xu_mm_lsu_token, + xu_mm_msr_cm => xu_mm_msr_cm, + xu_mm_msr_ds => xu_mm_msr_ds, + xu_mm_msr_gs => xu_mm_msr_gs, + xu_mm_msr_is => xu_mm_msr_is, + xu_mm_msr_pr => xu_mm_msr_pr, + xu_mm_ex1_is_csync => xu_mm_ex1_is_csync, + xu_mm_ex1_is_isync => xu_mm_ex1_is_isync, + xu_mm_rf1_is_eratilx => xu_mm_rf1_is_eratilx, + xu_mm_rf1_is_erativax => xu_mm_rf1_is_erativax, + xu_mm_rf1_is_tlbilx => xu_mm_rf1_is_tlbilx, + xu_mm_rf1_is_tlbivax => xu_mm_rf1_is_tlbivax, + xu_mm_rf1_is_tlbre => xu_mm_rf1_is_tlbre, + xu_mm_rf1_is_tlbsx => xu_mm_rf1_is_tlbsx, + xu_mm_rf1_is_tlbsxr => xu_mm_rf1_is_tlbsxr, + xu_mm_rf1_is_tlbsrx => xu_mm_rf1_is_tlbsrx, + xu_mm_rf1_is_tlbwe => xu_mm_rf1_is_tlbwe, + xu_mm_rf1_val => xu_mm_rf1_val, + xu_mm_rf1_t => xu_mm_rf1_t, + xu_mm_spr_epcr_dgtmi => xu_mm_spr_epcr_dgtmi, + xu_mm_spr_epcr_dmiuh => xu_mm_spr_epcr_dmiuh, + slowspr_addr_in => xu_mm_slowspr_addr, + slowspr_data_in => xu_mm_slowspr_data, + slowspr_done_in => xu_mm_slowspr_done, + slowspr_etid_in => xu_mm_slowspr_etid, + slowspr_rw_in => xu_mm_slowspr_rw, + slowspr_val_in => xu_mm_slowspr_val, + xu_rf1_flush => xu_s_rf1_flush, + bcfg_scan_out => mm_rp_bcfg_scan_out, + ccfg_scan_out => mm_iu_ccfg_scan_out, + dcfg_scan_out => mm_rp_dcfg_scan_out, + ac_an_gptr_scan_out => ac_an_gptr_scan_out, + ac_an_repr_scan_out => ac_an_repr_scan_out, + ac_an_time_scan_out => ac_an_time_scan_out, + ac_an_back_inv_reject => ac_an_back_inv_reject, + ac_an_lpar_id => ac_an_lpar_id, + mm_iu_barrier_done => mm_iu_barrier_done, + mm_iu_ierat_mmucr0_0 => mm_iu_ierat_mmucr0_0, + mm_iu_ierat_mmucr0_1 => mm_iu_ierat_mmucr0_1, + mm_iu_ierat_mmucr0_2 => mm_iu_ierat_mmucr0_2, + mm_iu_ierat_mmucr0_3 => mm_iu_ierat_mmucr0_3, + mm_iu_ierat_mmucr1 => mm_iu_ierat_mmucr1, + mm_iu_ierat_pid0 => mm_iu_ierat_pid0, + mm_iu_ierat_pid1 => mm_iu_ierat_pid1, + mm_iu_ierat_pid2 => mm_iu_ierat_pid2, + mm_iu_ierat_pid3 => mm_iu_ierat_pid3, + mm_iu_ierat_rel_data => mm_iu_ierat_rel_data, + mm_iu_ierat_rel_val => mm_iu_ierat_rel_val, + mm_iu_ierat_snoop_attr => mm_iu_ierat_snoop_attr, + mm_iu_ierat_snoop_coming => mm_iu_ierat_snoop_coming, + mm_iu_ierat_snoop_val => mm_iu_ierat_snoop_val, + mm_iu_ierat_snoop_vpn => mm_iu_ierat_snoop_vpn, + slowspr_addr_out => mm_iu_slowspr_addr, + slowspr_data_out => mm_iu_slowspr_data, + slowspr_done_out => mm_iu_slowspr_done, + slowspr_etid_out => mm_iu_slowspr_etid, + slowspr_rw_out => mm_iu_slowspr_rw, + slowspr_val_out => mm_iu_slowspr_val, + debug_bus_out => ac_an_debug_bus_int, + trace_triggers_out => ac_an_trace_triggers, + mm_pc_bo_diagout => mm_pc_bo_diagout_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_iiu, + mm_pc_event_data => mm_pc_event_data_iiu, + mm_xu_derat_mmucr0_0 => mm_xu_derat_mmucr0_0, + mm_xu_derat_mmucr0_1 => mm_xu_derat_mmucr0_1, + mm_xu_derat_mmucr0_2 => mm_xu_derat_mmucr0_2, + mm_xu_derat_mmucr0_3 => mm_xu_derat_mmucr0_3, + mm_xu_derat_mmucr1 => mm_xu_derat_mmucr1, + mm_xu_derat_pid0 => mm_xu_derat_pid0, + mm_xu_derat_pid1 => mm_xu_derat_pid1, + mm_xu_derat_pid2 => mm_xu_derat_pid2, + mm_xu_derat_pid3 => mm_xu_derat_pid3, + mm_xu_derat_rel_data => mm_xu_derat_rel_data, + mm_xu_derat_rel_val => mm_xu_derat_rel_val, + mm_xu_derat_snoop_attr => mm_xu_derat_snoop_attr, + mm_xu_derat_snoop_coming => mm_xu_derat_snoop_coming, + mm_xu_derat_snoop_val => mm_xu_derat_snoop_val, + mm_xu_derat_snoop_vpn => mm_xu_derat_snoop_vpn, + mm_xu_eratmiss_done => mm_xu_eratmiss_done, + mm_xu_esr_pt => mm_xu_esr_pt, + mm_xu_esr_data => mm_xu_esr_data, + mm_xu_esr_epid => mm_xu_esr_epid, + mm_xu_esr_st => mm_xu_esr_st, + mm_xu_ex3_flush_req => mm_xu_ex3_flush_req, + mm_xu_hold_done => mm_xu_hold_done, + mm_xu_hold_req => mm_xu_hold_req, + mm_xu_hv_priv => mm_xu_hv_priv, + mm_xu_illeg_instr => mm_xu_illeg_instr, + mm_xu_local_snoop_reject => mm_xu_local_snoop_reject, + mm_xu_lrat_miss => mm_xu_lrat_miss, + mm_xu_lsu_addr => mm_xu_lsu_addr, + mm_xu_lsu_lpid => mm_xu_lsu_lpid, + mm_xu_lsu_lpidr => mm_xu_lsu_lpidr, + mm_xu_lsu_gs => mm_xu_lsu_gs, + mm_xu_lsu_ind => mm_xu_lsu_ind, + mm_xu_lsu_lbit => mm_xu_lsu_lbit, + mm_xu_lsu_req => mm_xu_lsu_req, + mm_xu_lsu_ttype => mm_xu_lsu_ttype, + mm_xu_lsu_u => mm_xu_lsu_u, + mm_xu_lsu_wimge => mm_xu_lsu_wimge, + mm_xu_pt_fault => mm_xu_pt_fault, + mm_xu_quiesce => mm_xu_quiesce, + mm_xu_tlb_inelig => mm_xu_tlb_inelig, + mm_xu_tlb_miss => mm_xu_tlb_miss, + mm_xu_tlb_multihit_err => mm_xu_tlb_multihit_err, + mm_xu_tlb_par_err => mm_xu_tlb_par_err, + mm_xu_lru_par_err => mm_xu_lru_par_err, + + an_ac_reld_data_coming => an_ac_reld_data_coming, + an_ac_reld_l1_dump => an_ac_reld_l1_dump, + an_ac_grffence_en_dc => an_ac_camfence_en_dc, + an_ac_stcx_complete => an_ac_stcx_complete, + an_ac_abist_mode_dc => an_ac_abist_mode_dc, + an_ac_abist_start_test => an_ac_abist_start_test, + an_ac_atpg_en_dc => an_ac_atpg_en_dc, + an_ac_ccflush_dc => an_ac_ccflush_dc, + an_ac_reset_1_complete => an_ac_reset_1_complete, + an_ac_reset_2_complete => an_ac_reset_2_complete, + an_ac_reset_3_complete => an_ac_reset_3_complete, + an_ac_reset_wd_complete => an_ac_reset_wd_complete, + an_ac_debug_stop => an_ac_debug_stop, + an_ac_lbist_en_dc => an_ac_lbist_en_dc, + an_ac_pm_thread_stop => an_ac_pm_thread_stop, + an_ac_regf_scan_in => an_ac_regf_scan_in, + an_ac_scan_diag_dc => an_ac_scan_diag_dc, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b, + an_ac_scom_cch => an_ac_scom_cch, + an_ac_scom_dch => an_ac_scom_dch, + an_ac_checkstop => an_ac_checkstop, + an_ac_back_inv_omm => an_ac_back_inv_omm, + an_ac_back_inv_addr_omm => an_ac_back_inv_addr_omm, + an_ac_back_inv_target_omm_iua => an_ac_back_inv_target_omm_iua, + an_ac_back_inv_target_omm_iub => an_ac_back_inv_target_omm_iub, + an_ac_reld_core_tag_omm => an_ac_reld_core_tag_omm, + an_ac_reld_data_omm => an_ac_reld_data_omm, + an_ac_reld_data_vld_omm => an_ac_reld_data_vld_omm, + an_ac_reld_ecc_err_omm => an_ac_reld_ecc_err_omm, + an_ac_reld_ecc_err_ue_omm => an_ac_reld_ecc_err_ue_omm, + an_ac_reld_qw_omm => an_ac_reld_qw_omm, + an_ac_reld_ditc_omm => an_ac_reld_ditc_omm, + an_ac_reld_crit_qw_omm => an_ac_reld_crit_qw_omm, + an_ac_reld_data_coming_omm => an_ac_reld_data_coming_omm, + an_ac_reld_l1_dump_omm => an_ac_reld_l1_dump_omm, + an_ac_grffence_en_dc_omm => an_ac_camfence_en_dc_omm, + an_ac_stcx_complete_omm => an_ac_stcx_complete_omm, + an_ac_abist_mode_dc_omm => an_ac_abist_mode_dc_omm, + an_ac_abist_start_test_omm => an_ac_abist_start_test_omm, + an_ac_abst_scan_in_omm_iu => an_ac_abst_scan_in_omm_iu, + an_ac_abst_scan_in_omm_xu => an_ac_abst_scan_in_omm_xu, + an_ac_atpg_en_dc_omm => an_ac_atpg_en_dc_omm, + an_ac_bcfg_scan_in_omm_bit1 => an_ac_bcfg_scan_in_omm_bit1, + an_ac_bcfg_scan_in_omm_bit3 => an_ac_bcfg_scan_in_omm_bit3, + an_ac_bcfg_scan_in_omm_bit4 => an_ac_bcfg_scan_in_omm_bit4, + an_ac_lbist_ary_wrt_thru_dc_omm => an_ac_lbist_ary_wrt_thru_dc_omm, + an_ac_ccflush_dc_omm => an_ac_ccflush_dc_omm, + an_ac_reset_1_complete_omm => an_ac_reset_1_complete_omm, + an_ac_reset_2_complete_omm => an_ac_reset_2_complete_omm, + an_ac_reset_3_complete_omm => an_ac_reset_3_complete_omm, + an_ac_reset_wd_complete_omm => an_ac_reset_wd_complete_omm, + an_ac_dcfg_scan_in_omm => an_ac_dcfg_scan_in_omm, + an_ac_debug_stop_omm => an_ac_debug_stop_omm, + an_ac_func_scan_in_omm_iua => an_ac_func_scan_in_omm_iua, + an_ac_func_scan_in_omm_iub => an_ac_func_scan_in_omm_iub, + an_ac_func_scan_in_omm_xu => an_ac_func_scan_in_omm_xu, + an_ac_lbist_en_dc_omm => an_ac_lbist_en_dc_omm, + an_ac_pm_thread_stop_omm => an_ac_pm_thread_stop_omm, + an_ac_regf_scan_in_omm => an_ac_regf_scan_in_omm, + an_ac_scan_diag_dc_omm => an_ac_scan_diag_dc_omm, + an_ac_scan_dis_dc_b_omm => an_ac_scan_dis_dc_b_omm, + an_ac_scom_cch_omm => an_ac_scom_cch_omm, + an_ac_scom_dch_omm => an_ac_scom_dch_omm, + an_ac_checkstop_omm => an_ac_checkstop_omm, + ac_an_abst_scan_out_imm_iu => ac_an_abst_scan_out_imm_iu, + ac_an_abst_scan_out_imm_xu => ac_an_abst_scan_out_imm_xu, + ac_an_bcfg_scan_out_imm => ac_an_bcfg_scan_out_imm, + ac_an_dcfg_scan_out_imm => ac_an_dcfg_scan_out_imm, + ac_an_func_scan_out_imm_iua => ac_an_func_scan_out_imm_iua, + ac_an_func_scan_out_imm_iub => ac_an_func_scan_out_imm_iub, + ac_an_func_scan_out_imm_xu => ac_an_func_scan_out_imm_xu, + ac_an_reld_ditc_pop_imm => ac_an_reld_ditc_pop_imm, + ac_an_power_managed_imm => ac_an_power_managed_imm, + ac_an_rvwinkle_mode_imm => ac_an_rvwinkle_mode_imm, + ac_an_fu_bypass_events_imm => ac_an_fu_bypass_events_imm, + ac_an_iu_bypass_events_imm => ac_an_iu_bypass_events_imm, + ac_an_mm_bypass_events_imm => ac_an_mm_bypass_events_imm, + ac_an_lsu_bypass_events_imm => ac_an_lsu_bypass_events_imm, + ac_an_event_bus_imm => ac_an_event_bus_imm, + ac_an_pm_thread_running_imm => ac_an_pm_thread_running_imm, + ac_an_recov_err_imm => ac_an_recov_err_imm, + ac_an_regf_scan_out_imm => ac_an_regf_scan_out_imm, + ac_an_scom_cch_imm => ac_an_scom_cch_imm, + ac_an_scom_dch_imm => ac_an_scom_dch_imm, + ac_an_special_attn_imm => ac_an_special_attn_imm, + ac_an_checkstop_imm => ac_an_checkstop_imm, + ac_an_local_checkstop_imm => ac_an_local_checkstop_imm, + ac_an_trace_error_imm => ac_an_trace_error_imm, + ac_an_abst_scan_out => ac_an_abst_scan_out, + ac_an_bcfg_scan_out => ac_an_bcfg_scan_out, + ac_an_dcfg_scan_out => ac_an_dcfg_scan_out, + ac_an_func_scan_out => ac_an_func_scan_out, + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop, + ac_an_power_managed => ac_an_power_managed, + ac_an_rvwinkle_mode => ac_an_rvwinkle_mode, + ac_an_fu_bypass_events => ac_an_fu_bypass_events, + ac_an_iu_bypass_events => ac_an_iu_bypass_events, + ac_an_mm_bypass_events => ac_an_mm_bypass_events, + ac_an_lsu_bypass_events => ac_an_lsu_bypass_events, + ac_an_event_bus => ac_an_event_bus, + ac_an_pm_thread_running => ac_an_pm_thread_running, + ac_an_recov_err => ac_an_recov_err, + ac_an_regf_scan_out => ac_an_regf_scan_out, + ac_an_scom_cch => ac_an_scom_cch, + ac_an_scom_dch => ac_an_scom_dch, + ac_an_special_attn => ac_an_special_attn, + ac_an_checkstop => ac_an_checkstop, + ac_an_local_checkstop => ac_an_local_checkstop, + ac_an_trace_error => ac_an_trace_error, + an_ac_dcr_act => an_ac_dcr_act, + an_ac_dcr_val => an_ac_dcr_val, + an_ac_dcr_read => an_ac_dcr_read, + an_ac_dcr_etid => an_ac_dcr_etid, + an_ac_dcr_data => an_ac_dcr_data, + an_ac_dcr_done => an_ac_dcr_done, + an_ac_crit_interrupt => an_ac_crit_interrupt, + an_ac_ext_interrupt => an_ac_ext_interrupt, + an_ac_flh2l2_gate => an_ac_flh2l2_gate, + an_ac_icbi_ack => an_ac_icbi_ack, + an_ac_icbi_ack_thread => an_ac_icbi_ack_thread, + an_ac_req_ld_pop => an_ac_req_ld_pop, + an_ac_req_spare_ctrl_a1 => an_ac_req_spare_ctrl_a1, + an_ac_req_st_gather => an_ac_req_st_gather, + an_ac_req_st_pop => an_ac_req_st_pop, + an_ac_req_st_pop_thrd => an_ac_req_st_pop_thrd, + an_ac_reservation_vld => an_ac_reservation_vld, + an_ac_sleep_en => an_ac_sleep_en, + an_ac_stcx_pass => an_ac_stcx_pass, + an_ac_sync_ack => an_ac_sync_ack, + an_ac_ary_nsl_thold_7 => an_ac_ary_nsl_thold_7, + an_ac_ccenable_dc => an_ac_ccenable_dc, + an_ac_coreid => an_ac_coreid, + an_ac_external_mchk => an_ac_external_mchk, + an_ac_fce_7 => an_ac_fce_7, + an_ac_func_nsl_thold_7 => an_ac_func_nsl_thold_7, + an_ac_func_sl_thold_7 => an_ac_func_sl_thold_7, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc, + an_ac_gptr_scan_in => an_ac_gptr_scan_in, + an_ac_hang_pulse => an_ac_hang_pulse, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc, + an_ac_malf_alert => an_ac_malf_alert, + an_ac_perf_interrupt => an_ac_perf_interrupt, + an_ac_psro_enable_dc => an_ac_psro_enable_dc, + an_ac_repr_scan_in => an_ac_repr_scan_in, + an_ac_rtim_sl_thold_7 => an_ac_rtim_sl_thold_7, + an_ac_scan_type_dc => an_ac_scan_type_dc, + an_ac_scom_sat_id => an_ac_scom_sat_id, + an_ac_sg_7 => an_ac_sg_7, + an_ac_tb_update_enable => an_ac_tb_update_enable, + an_ac_tb_update_pulse => an_ac_tb_update_pulse, + an_ac_time_scan_in => an_ac_time_scan_in, + an_ac_crit_interrupt_omm => an_ac_crit_interrupt_omm, + an_ac_ext_interrupt_omm => an_ac_ext_interrupt_omm, + an_ac_flh2l2_gate_omm => an_ac_flh2l2_gate_omm, + an_ac_icbi_ack_omm => an_ac_icbi_ack_omm, + an_ac_icbi_ack_thread_omm => an_ac_icbi_ack_thread_omm, + an_ac_req_ld_pop_omm => an_ac_req_ld_pop_omm, + an_ac_req_spare_ctrl_a1_omm => an_ac_req_spare_ctrl_a1_omm, + an_ac_req_st_gather_omm => an_ac_req_st_gather_omm, + an_ac_req_st_pop_omm => an_ac_req_st_pop_omm, + an_ac_req_st_pop_thrd_omm => an_ac_req_st_pop_thrd_omm, + an_ac_reservation_vld_omm => an_ac_reservation_vld_omm, + an_ac_sleep_en_omm => an_ac_sleep_en_omm, + an_ac_stcx_pass_omm => an_ac_stcx_pass_omm, + an_ac_sync_ack_omm => an_ac_sync_ack_omm, + an_ac_ary_nsl_thold_7_omm => an_ac_ary_nsl_thold_7_omm, + an_ac_ccenable_dc_omm => an_ac_ccenable_dc_iiu, + an_ac_coreid_omm => an_ac_coreid_omm, + an_ac_external_mchk_omm => an_ac_external_mchk_omm, + an_ac_fce_7_omm => an_ac_fce_7_omm, + an_ac_func_nsl_thold_7_omm => an_ac_func_nsl_thold_7_omm, + an_ac_func_sl_thold_7_omm => an_ac_func_sl_thold_7_omm, + an_ac_gsd_test_enable_dc_omm => an_ac_gsd_test_enable_dc_omm, + an_ac_gsd_test_acmode_dc_omm => an_ac_gsd_test_acmode_dc_omm, + an_ac_gptr_scan_in_omm => an_ac_gptr_scan_in_omm, + an_ac_hang_pulse_omm => an_ac_hang_pulse_omm, + an_ac_lbist_ac_mode_dc_omm => an_ac_lbist_ac_mode_dc_omm, + an_ac_lbist_ip_dc_omm => an_ac_lbist_ip_dc_omm, + an_ac_malf_alert_omm => an_ac_malf_alert_omm, + an_ac_perf_interrupt_omm => an_ac_perf_interrupt_omm, + an_ac_psro_enable_dc_omm => an_ac_psro_enable_dc_omm, + an_ac_repr_scan_in_omm => an_ac_repr_scan_in_omm, + an_ac_rtim_sl_thold_7_omm => an_ac_rtim_sl_thold_7_omm, + an_ac_scan_type_dc_omm => an_ac_scan_type_dc_omm, + an_ac_scom_sat_id_omm => an_ac_scom_sat_id_omm, + an_ac_sg_7_omm => an_ac_sg_7_omm, + an_ac_tb_update_enable_omm => an_ac_tb_update_enable_omm, + an_ac_tb_update_pulse_omm => an_ac_tb_update_pulse_omm, + an_ac_time_scan_in_omm => an_ac_time_scan_in_omm, + + ac_an_box_empty_imm => ac_an_box_empty_imm, + ac_an_machine_check_imm => ac_an_machine_check_imm, + ac_an_req_imm => ac_an_req_imm, + ac_an_req_endian_imm => ac_an_req_endian_imm, + ac_an_req_ld_core_tag_imm => ac_an_req_ld_core_tag_imm, + ac_an_req_ld_xfr_len_imm => ac_an_req_ld_xfr_len_imm, + ac_an_req_pwr_token_imm => ac_an_req_pwr_token_imm, + ac_an_req_ra_imm => ac_an_req_ra_imm, + ac_an_req_spare_ctrl_a0_imm => ac_an_req_spare_ctrl_a0_imm, + ac_an_req_thread_imm => ac_an_req_thread_imm, + ac_an_req_ttype_imm => ac_an_req_ttype_imm, + ac_an_req_user_defined_imm => ac_an_req_user_defined_imm, + ac_an_req_wimg_g_imm => ac_an_req_wimg_g_imm, + ac_an_req_wimg_i_imm => ac_an_req_wimg_i_imm, + ac_an_req_wimg_m_imm => ac_an_req_wimg_m_imm, + ac_an_req_wimg_w_imm => ac_an_req_wimg_w_imm, + ac_an_st_byte_enbl_imm => ac_an_st_byte_enbl_imm, + ac_an_st_data_imm => ac_an_st_data_imm, + ac_an_st_data_pwr_token_imm => ac_an_st_data_pwr_token_imm, + ac_an_abist_done_dc_imm => ac_an_abist_done_dc_oiu, + ac_an_debug_trigger_imm => ac_an_debug_trigger_imm, + ac_an_psro_ringsig_imm => ac_an_psro_ringsig_oiu, + ac_an_reset_1_request_imm => ac_an_reset_1_request_imm, + ac_an_reset_2_request_imm => ac_an_reset_2_request_imm, + ac_an_reset_3_request_imm => ac_an_reset_3_request_imm, + ac_an_reset_wd_request_imm => ac_an_reset_wd_request_imm, + + ac_an_box_empty => ac_an_box_empty, + ac_an_machine_check => ac_an_machine_check, + ac_an_req => ac_an_req, + ac_an_req_endian => ac_an_req_endian, + ac_an_req_ld_core_tag => ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len => ac_an_req_ld_xfr_len, + ac_an_req_pwr_token => ac_an_req_pwr_token, + ac_an_req_ra => ac_an_req_ra, + ac_an_req_spare_ctrl_a0 => ac_an_req_spare_ctrl_a0, + ac_an_req_thread => ac_an_req_thread, + ac_an_req_ttype => ac_an_req_ttype, + ac_an_req_user_defined => ac_an_req_user_defined, + ac_an_req_wimg_g => ac_an_req_wimg_g, + ac_an_req_wimg_i => ac_an_req_wimg_i, + ac_an_req_wimg_m => ac_an_req_wimg_m, + ac_an_req_wimg_w => ac_an_req_wimg_w, + ac_an_st_byte_enbl => ac_an_st_byte_enbl, + ac_an_st_data => ac_an_st_data, + ac_an_st_data_pwr_token => ac_an_st_data_pwr_token, + ac_an_abist_done_dc => ac_an_abist_done_dc, + ac_an_debug_trigger => ac_an_debug_trigger, + ac_an_psro_ringsig => ac_an_psro_ringsig, + ac_an_reset_1_request => ac_an_reset_1_request, + ac_an_reset_2_request => ac_an_reset_2_request, + ac_an_reset_3_request => ac_an_reset_3_request, + ac_an_reset_wd_request => ac_an_reset_wd_request, + ac_an_dcr_act => ac_an_dcr_act, + ac_an_dcr_val => ac_an_dcr_val, + ac_an_dcr_read => ac_an_dcr_read, + ac_an_dcr_user => ac_an_dcr_user, + ac_an_dcr_etid => ac_an_dcr_etid, + ac_an_dcr_addr => ac_an_dcr_addr, + ac_an_dcr_data => ac_an_dcr_data, + + debug_bus_out_int => debug_bus_out_int, + + bg_ac_an_func_scan_ns_imm => bg_ac_an_func_scan_ns_q, + bg_ac_an_abst_scan_ns_imm => bg_ac_an_abst_scan_ns_q, + bg_ac_an_func_scan_ns => bg_ac_an_func_scan_ns, + bg_ac_an_abst_scan_ns => bg_ac_an_abst_scan_ns, + bg_pc_l1p_abist_di_0_imm => bg_pc_l1p_abist_di_0_q, + bg_pc_l1p_abist_g8t1p_renb_0_imm => bg_pc_l1p_abist_g8t1p_renb_0_q, + bg_pc_l1p_abist_g8t_bw_0_imm => bg_pc_l1p_abist_g8t_bw_0_q, + bg_pc_l1p_abist_g8t_bw_1_imm => bg_pc_l1p_abist_g8t_bw_1_q, + bg_pc_l1p_abist_g8t_dcomp_imm => bg_pc_l1p_abist_g8t_dcomp_q, + bg_pc_l1p_abist_g8t_wenb_imm => bg_pc_l1p_abist_g8t_wenb_q, + bg_pc_l1p_abist_raddr_0_imm => bg_pc_l1p_abist_raddr_0_q, + bg_pc_l1p_abist_waddr_0_imm => bg_pc_l1p_abist_waddr_0_q, + bg_pc_l1p_abist_wl128_comp_ena_imm => bg_pc_l1p_abist_wl128_comp_ena_q, + bg_pc_l1p_abist_wl32_comp_ena_imm => bg_pc_l1p_abist_wl32_comp_ena_q, + bg_pc_l1p_abist_di_0 => bg_pc_l1p_abist_di_0, + bg_pc_l1p_abist_g8t1p_renb_0 => bg_pc_l1p_abist_g8t1p_renb_0, + bg_pc_l1p_abist_g8t_bw_0 => bg_pc_l1p_abist_g8t_bw_0, + bg_pc_l1p_abist_g8t_bw_1 => bg_pc_l1p_abist_g8t_bw_1, + bg_pc_l1p_abist_g8t_dcomp => bg_pc_l1p_abist_g8t_dcomp, + bg_pc_l1p_abist_g8t_wenb => bg_pc_l1p_abist_g8t_wenb, + bg_pc_l1p_abist_raddr_0 => bg_pc_l1p_abist_raddr_0, + bg_pc_l1p_abist_waddr_0 => bg_pc_l1p_abist_waddr_0, + bg_pc_l1p_abist_wl128_comp_ena => bg_pc_l1p_abist_wl128_comp_ena, + bg_pc_l1p_abist_wl32_comp_ena => bg_pc_l1p_abist_wl32_comp_ena, + bg_pc_l1p_gptr_sl_thold_2_imm => bg_pc_l1p_gptr_sl_thold_2_imm, + bg_pc_l1p_time_sl_thold_2_imm => bg_pc_l1p_time_sl_thold_2_imm, + bg_pc_l1p_repr_sl_thold_2_imm => bg_pc_l1p_repr_sl_thold_2_imm, + bg_pc_l1p_abst_sl_thold_2_imm => bg_pc_l1p_abst_sl_thold_2_imm, + bg_pc_l1p_func_sl_thold_2_imm => bg_pc_l1p_func_sl_thold_2_imm, + bg_pc_l1p_func_slp_sl_thold_2_imm => bg_pc_l1p_func_slp_sl_thold_2_imm, + bg_pc_l1p_bolt_sl_thold_2_imm => bg_pc_l1p_bolt_sl_thold_2_imm, + bg_pc_l1p_ary_nsl_thold_2_imm => bg_pc_l1p_ary_nsl_thold_2_imm, + bg_pc_l1p_sg_2_imm => bg_pc_l1p_sg_2_imm, + bg_pc_l1p_fce_2_imm => bg_pc_l1p_fce_2_imm, + bg_pc_l1p_bo_enable_2_imm => bg_pc_l1p_bo_enable_2_imm, + bg_pc_l1p_gptr_sl_thold_2 => bg_pc_l1p_gptr_sl_thold_2, + bg_pc_l1p_time_sl_thold_2 => bg_pc_l1p_time_sl_thold_2, + bg_pc_l1p_repr_sl_thold_2 => bg_pc_l1p_repr_sl_thold_2, + bg_pc_l1p_abst_sl_thold_2 => bg_pc_l1p_abst_sl_thold_2, + bg_pc_l1p_func_sl_thold_2 => bg_pc_l1p_func_sl_thold_2, + bg_pc_l1p_func_slp_sl_thold_2 => bg_pc_l1p_func_slp_sl_thold_2, + bg_pc_l1p_bolt_sl_thold_2 => bg_pc_l1p_bolt_sl_thold_2, + bg_pc_l1p_ary_nsl_thold_2 => bg_pc_l1p_ary_nsl_thold_2, + bg_pc_l1p_sg_2 => bg_pc_l1p_sg_2, + bg_pc_l1p_fce_2 => bg_pc_l1p_fce_2, + bg_pc_l1p_bo_enable_2 => bg_pc_l1p_bo_enable_2, + bg_pc_bo_unload_imm => bg_pc_bo_unload_oiu, + bg_pc_bo_load_imm => bg_pc_bo_load_oiu, + bg_pc_bo_repair_imm => bg_pc_bo_repair_oiu, + bg_pc_bo_reset_imm => bg_pc_bo_reset_oiu, + bg_pc_bo_shdata_imm => bg_pc_bo_shdata_oiu, + bg_pc_bo_select_imm => bg_pc_bo_select_oiu, + bg_pc_l1p_ccflush_dc_imm => bg_pc_l1p_ccflush_dc_oiu, + bg_pc_l1p_abist_ena_dc_imm => bg_pc_l1p_abist_ena_dc_oiu, + bg_pc_l1p_abist_raw_dc_b_imm => bg_pc_l1p_abist_raw_dc_b_oiu, + bg_pc_bo_unload => bg_pc_bo_unload, + bg_pc_bo_load => bg_pc_bo_load, + bg_pc_bo_repair => bg_pc_bo_repair, + bg_pc_bo_reset => bg_pc_bo_reset, + bg_pc_bo_shdata => bg_pc_bo_shdata, + bg_pc_bo_select => bg_pc_bo_select, + bg_pc_l1p_ccflush_dc => bg_pc_l1p_ccflush_dc, + bg_pc_l1p_abist_ena_dc => bg_pc_l1p_abist_ena_dc, + bg_pc_l1p_abist_raw_dc_b => bg_pc_l1p_abist_raw_dc_b, + bg_an_ac_func_scan_sn => bg_an_ac_func_scan_sn, + bg_an_ac_abst_scan_sn => bg_an_ac_abst_scan_sn, + bg_an_ac_func_scan_sn_omm => bg_an_ac_func_scan_sn_omm, + bg_an_ac_abst_scan_sn_omm => bg_an_ac_abst_scan_sn_omm, + bg_pc_bo_fail => bg_pc_bo_fail, + bg_pc_bo_diagout => bg_pc_bo_diagout, + bg_pc_bo_fail_omm => bg_pc_bo_fail_omm, + bg_pc_bo_diagout_omm => bg_pc_bo_diagout_omm, xu_mm_xucr4_mmu_mchk => xu_mm_xucr4_mmu_mchk, - - gnd => gnd, - vcs => vcs, - vdd => vdd + + gnd => gnd, + vcs => vcs, + vdd => vdd ); - -a_pcq: entity work.pcq - generic map(expand_type => expand_type, regmode => regmode) - port map ( - abst_scan_in => iu_pc_abst_scan_out, - bcfg_scan_in => rp_pc_bcfg_scan_out_q, - ccfg_scan_in => iu_pc_ccfg_scan_out, - dcfg_scan_in => rp_pc_dcfg_scan_out_q, - func_scan_in => rp_pc_func_scan_in_q(0 to 1), - gptr_scan_in => iu_pc_gptr_scan_out, - bx_pc_err_inbox_ue => bx_pc_err_inbox_ue_ofu, - bx_pc_err_outbox_ue => bx_pc_err_outbox_ue_ofu, - fu_pc_event_data => fu_pc_event_data, - fu_pc_ram_data => fu_pc_ram_data, - fu_pc_ram_done => fu_pc_ram_done, - iu_pc_err_icache_parity => iu_pc_err_icache_parity, - iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, - iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, - fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, - fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, - iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, - iu_pc_event_data => iu_pc_event_data, - slowspr_addr_in => iu_pc_slowspr_addr, - slowspr_data_in => iu_pc_slowspr_data, - slowspr_done_in => iu_pc_slowspr_done, - slowspr_etid_in => iu_pc_slowspr_etid, - slowspr_rw_in => iu_pc_slowspr_rw, - slowspr_val_in => iu_pc_slowspr_val, - xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary_ofu, - xu_pc_err_ierat_parity => xu_pc_err_ierat_parity_ofu, - xu_pc_err_derat_parity => xu_pc_err_derat_parity_ofu, - xu_pc_err_tlb_parity => xu_pc_err_tlb_parity_ofu, - xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity_ofu, - xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit_ofu, - xu_pc_err_derat_multihit => xu_pc_err_derat_multihit_ofu, - xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit_ofu, - xu_pc_err_ext_mchk => xu_pc_err_ext_mchk_ofu, - xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun_ofu, - xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject_ofu, - mm_pc_event_data => mm_pc_event_data_oiu, - nclk => a2_nclk, - an_ac_rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, - an_ac_func_sl_thold_6 => rp_pc_func_sl_thold_6, - an_ac_func_nsl_thold_6 => rp_pc_func_nsl_thold_6, - an_ac_ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, - an_ac_sg_6 => rp_pc_sg_6, - an_ac_fce_6 => rp_pc_fce_6, - an_ac_abist_start_test => rp_pc_abist_start_test_q, - an_ac_ccenable_dc => an_ac_ccenable_dc_oiu, - an_ac_ccflush_dc => an_ac_ccflush_dc_oiu, - an_ac_debug_stop => rp_pc_debug_stop_q, - an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc_oiu, - an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc_oiu, - an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, - an_ac_lbist_ip_dc => an_ac_lbist_ip_dc_oiu, - an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc_oiu, - an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, - an_ac_malf_alert => an_ac_malf_alert_oiu, - an_ac_pm_thread_stop => rp_pc_pm_thread_stop_q, - an_ac_psro_enable_dc => an_ac_psro_enable_dc_oiu, - an_ac_reset_1_complete => rp_pc_reset_1_complete_q, - an_ac_reset_2_complete => rp_pc_reset_2_complete_q, - an_ac_reset_3_complete => rp_pc_reset_3_complete_q, - an_ac_reset_wd_complete => rp_pc_reset_wd_complete_q, - an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, - an_ac_scan_type_dc => an_ac_scan_type_dc_oiu, - an_ac_scom_cch => rp_pc_scom_cch_q, - an_ac_scom_dch => rp_pc_scom_dch_q, - an_ac_scom_sat_id => an_ac_scom_sat_id_oiu, - an_ac_checkstop => rp_pc_checkstop_q, - debug_bus_in => fu_pc_debug_data, - trace_triggers_in => fu_pc_trigger_data, - xu_pc_err_attention_instr => xu_pc_err_attention_instr_ofu, - xu_pc_err_dcache_parity => xu_pc_err_dcache_parity_ofu, - xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity_ofu, - xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit_ofu, - xu_pc_err_debug_event => xu_pc_err_debug_event_ofu, - bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc_ofu, - xu_pc_err_invld_reld => xu_pc_err_invld_reld_ofu, - xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc_ofu, - xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue_ofu, - xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun_ofu, - xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt_ofu, - xu_pc_err_llbust_failed => xu_pc_err_llbust_failed_ofu, - xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr_ofu, - bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc_ofu, - xu_pc_err_regfile_parity => xu_pc_err_regfile_parity_ofu, - xu_pc_err_regfile_ue => xu_pc_err_regfile_ue_ofu, - xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc_ofu, - xu_pc_err_sprg_ue => xu_pc_err_sprg_ue_ofu, - xu_pc_err_wdt_reset => xu_pc_err_wdt_reset_ofu, - xu_pc_event_data => xu_pc_event_data_ofu, - lsu_pc_event_data => xu_pc_lsu_event_data_ofu, - ac_pc_trace_to_perfcntr => rp_pc_trace_to_perfcntr_q, - xu_pc_ram_data => xu_pc_ram_data_ofu, - xu_pc_ram_done => xu_pc_ram_done_ofu, - xu_pc_ram_interrupt => xu_pc_ram_interrupt_ofu, - xu_pc_running => xu_pc_running_ofu, - xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme_ofu, - xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we_ofu, - xu_pc_step_done => xu_pc_step_done_ofu, - xu_pc_stop_dbg_event => xu_pc_stop_dbg_event_ofu, - an_ac_bo_enable => an_ac_bo_enable, - an_ac_bo_go => an_ac_bo_go, - an_ac_bo_cntlclk => an_ac_bo_cntlclk, - an_ac_bo_ccflush => an_ac_bo_ccflush, - an_ac_bo_reset => an_ac_bo_reset, - an_ac_bo_data => an_ac_bo_data, - an_ac_bo_shcntl => an_ac_bo_shcntl, - an_ac_bo_shdata => an_ac_bo_shdata, - an_ac_bo_exe => an_ac_bo_exe, - an_ac_bo_sysrepair => an_ac_bo_sysrepair, - an_ac_bo_donein => an_ac_bo_donein, - an_ac_bo_sdin => an_ac_bo_sdin, - an_ac_bo_waitin => an_ac_bo_waitin, - an_ac_bo_failin => an_ac_bo_failin, - an_ac_bo_fcshdata => an_ac_bo_fcshdata, - an_ac_bo_fcreset => an_ac_bo_fcreset, - ac_an_bo_doneout => ac_an_bo_doneout, - ac_an_bo_sdout => ac_an_bo_sdout, - ac_an_bo_diagloopout => ac_an_bo_diagloopout, - ac_an_bo_waitout => ac_an_bo_waitout, - ac_an_bo_failout => ac_an_bo_failout, - pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, - pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, - pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, - pc_bx_bo_enable_3 => pc_bx_bo_enable_3, - pc_bx_bo_unload => pc_bx_bo_unload, - pc_bx_bo_repair => pc_bx_bo_repair, - pc_bx_bo_reset => pc_bx_bo_reset, - pc_bx_bo_shdata => pc_bx_bo_shdata, - pc_bx_bo_select => pc_bx_bo_select, - bx_pc_bo_fail => bx_pc_bo_fail_ofu, - bx_pc_bo_diagout => bx_pc_bo_diagout_ofu, - pc_fu_bo_enable_3 => pc_fu_bo_enable_3, - pc_fu_bo_unload => pc_fu_bo_unload, - pc_fu_bo_load => pc_fu_bo_load, - pc_fu_bo_reset => pc_fu_bo_reset, - pc_fu_bo_shdata => pc_fu_bo_shdata, - pc_fu_bo_select => pc_fu_bo_select, - fu_pc_bo_fail => fu_pc_bo_fail, - fu_pc_bo_diagout => fu_pc_bo_diagout, - pc_iu_bo_enable_4 => pc_iu_bo_enable_4, - pc_iu_bo_unload => pc_iu_bo_unload, - pc_iu_bo_repair => pc_iu_bo_repair, - pc_iu_bo_reset => pc_iu_bo_reset, - pc_iu_bo_shdata => pc_iu_bo_shdata, - pc_iu_bo_select => pc_iu_bo_select, - iu_pc_bo_fail => iu_pc_bo_fail, - iu_pc_bo_diagout => iu_pc_bo_diagout, - pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, - pc_mm_bo_unload => pc_mm_bo_unload_iiu, - pc_mm_bo_repair => pc_mm_bo_repair_iiu, - pc_mm_bo_reset => pc_mm_bo_reset_iiu, - pc_mm_bo_shdata => pc_mm_bo_shdata_iiu, - pc_mm_bo_select => pc_mm_bo_select_iiu, - mm_pc_bo_fail => mm_pc_bo_fail_oiu, - mm_pc_bo_diagout => mm_pc_bo_diagout_oiu, - pc_xu_bo_enable_3 => pc_xu_bo_enable_3, - pc_xu_bo_unload => pc_xu_bo_unload, - pc_xu_bo_load => pc_xu_bo_load, - pc_xu_bo_repair => pc_xu_bo_repair, - pc_xu_bo_reset => pc_xu_bo_reset, - pc_xu_bo_shdata => pc_xu_bo_shdata, - pc_xu_bo_select => pc_xu_bo_select, - xu_pc_bo_fail => xu_pc_bo_fail_ofu, - xu_pc_bo_diagout => xu_pc_bo_diagout_ofu, - ac_an_power_managed => pc_rp_power_managed, - ac_an_rvwinkle_mode => pc_rp_rvwinkle_mode, - ac_an_fu_bypass_events => pc_rp_fu_bypass_events, - ac_an_iu_bypass_events => pc_rp_iu_bypass_events, - ac_an_mm_bypass_events => pc_rp_mm_bypass_events, - ac_an_lsu_bypass_events => pc_rp_lsu_bypass_events, - ac_an_event_bus => pc_rp_event_bus, - ac_an_abist_done_dc => ac_an_abist_done_dc_iiu, - ac_an_local_checkstop => pc_rp_local_checkstop, - ac_an_pm_thread_running => pc_rp_pm_thread_running, - ac_an_psro_ringsig => ac_an_psro_ringsig_iiu, - ac_an_recov_err => pc_rp_recov_err, - ac_an_scom_cch => pc_rp_scom_cch, - ac_an_scom_dch => pc_rp_scom_dch, - ac_an_special_attn => pc_rp_special_attn, - ac_an_checkstop => pc_rp_checkstop, - ac_an_trace_error => pc_rp_trace_error, - debug_bus_out => pc_iu_debug_data, - trace_triggers_out => pc_iu_trigger_data, - abst_scan_out => pc_rp_abst_scan_out, - bcfg_scan_out => pc_rp_bcfg_scan_out, - ccfg_scan_out => pc_rp_ccfg_scan_out, - dcfg_scan_out => pc_rp_dcfg_scan_out, - func_scan_out => pc_rp_func_scan_out(0 to 1), - gptr_scan_out => pc_fu_gptr_scan_out, - pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), - pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, - pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, - pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, - pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, - pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), - pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, - pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), - pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, - pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), - pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_comp_ena, - pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), - pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), - pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, - pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, - pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, - pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, - pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, - pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), - pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), - pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, - pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), - pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), - pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, - pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), - pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), - pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), - pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, - pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), - pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, - pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, - pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, - pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, - pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), - pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, - pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), - pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, - pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), - pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_comp_ena, - pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, - pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_comp_ena, - pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_iiu(0 to 3), - pc_mm_abist_di_0 => pc_mm_abist_di_0_iiu(0 to 3), - pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_iiu(0 to 3), - pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_iiu, - pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_iiu, - pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_iiu, - pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_iiu, - pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_iiu, - pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_iiu(0 to 3), - pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_iiu, - pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_iiu(0 to 9), - pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_iiu, - pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_iiu(0 to 9), - pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_comp_ena_iiu, - pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), - pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), - pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), - pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), - pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, - pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), - pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, - pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, - pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, - pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, - pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), - pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, - pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, - pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, - pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, - pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, - pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), - pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), - pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, - pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), - pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), - pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, - pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_comp_ena, - pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, - pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, - pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, - pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, - pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, - pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, - pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, - pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, - pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, - pc_fu_ccflush_dc => pc_fu_ccflush_dc, - pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, - pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, - pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, - pc_fu_event_count_mode => pc_fu_event_count_mode, - pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, - pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, - pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_iiu, - pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, - pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, - pc_fu_event_bus_enable => pc_fu_event_bus_enable, - pc_iu_event_bus_enable => pc_iu_event_bus_enable, - pc_rp_event_bus_enable => pc_rp_event_bus_enable, - pc_xu_event_bus_enable => pc_xu_event_bus_enable, - pc_fu_fce_3 => pc_fu_fce_3, - pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, - pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, - pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, - pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, - pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, - pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, - pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, - pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, - pc_fu_ram_mode => pc_fu_ram_mode, - pc_fu_ram_thread => pc_fu_ram_thread, - pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, - pc_fu_sg_3 => pc_fu_sg_3, - slowspr_addr_out => pc_fu_slowspr_addr, - slowspr_data_out => pc_fu_slowspr_data, - slowspr_done_out => pc_fu_slowspr_done, - slowspr_etid_out => pc_fu_slowspr_etid, - slowspr_rw_out => pc_fu_slowspr_rw, - slowspr_val_out => pc_fu_slowspr_val, - pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, - pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, - pc_iu_ccflush_dc => pc_iu_ccflush_dc, - pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, - pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, - pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, - pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, - pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, - pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, - pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, - pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, - pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, - pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, - pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, - pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, - pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, - pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, - pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, - pc_iu_sg_4 => pc_iu_sg_4, - pc_iu_fce_4 => pc_iu_fce_4, - pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, - pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, - pc_iu_event_count_mode => pc_iu_event_count_mode, - pc_iu_init_reset => pc_iu_init_reset, - pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, - pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, - pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, - pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, - pc_iu_ram_instr => pc_iu_ram_instr, - pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, - pc_iu_ram_mode => pc_iu_ram_mode, - pc_iu_ram_thread => pc_iu_ram_thread, - pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, - pc_mm_ccflush_dc => pc_mm_ccflush_dc_iiu, - pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_iiu, - pc_mm_event_count_mode => pc_mm_event_count_mode_iiu, - pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_iiu, - pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, - pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, - pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, - pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, - pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, - pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, - pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, - pc_xu_ccflush_dc => pc_xu_ccflush_dc, - pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, - pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, - pc_xu_dbg_action => pc_xu_dbg_action, - pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, - pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, - pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, - pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, - pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, - pc_xu_event_count_mode => pc_xu_event_count_mode, - pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, - pc_xu_fce_3 => pc_xu_fce_3, - pc_xu_force_ude => pc_xu_force_ude, - pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, - pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, - pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, - pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, - pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, - pc_xu_init_reset => pc_xu_init_reset, - pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, - pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, - pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, - pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, - pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, - pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, - pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, - pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, - pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, - pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, - pc_xu_msrovride_de => pc_xu_msrovride_de, - pc_xu_msrovride_enab => pc_xu_msrovride_enab, - pc_xu_msrovride_gs => pc_xu_msrovride_gs, - pc_xu_msrovride_pr => pc_xu_msrovride_pr, - pc_xu_ram_execute => pc_xu_ram_execute, - pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, - pc_xu_ram_mode => pc_xu_ram_mode, - pc_xu_ram_thread => pc_xu_ram_thread, - pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, - pc_xu_reset_1_cmplt => pc_xu_reset_1_complete, - pc_xu_reset_2_cmplt => pc_xu_reset_2_complete, - pc_xu_reset_3_cmplt => pc_xu_reset_3_complete, - pc_xu_reset_wd_cmplt => pc_xu_reset_wd_complete, - pc_xu_sg_3 => pc_xu_sg_3, - pc_xu_step => pc_xu_step, - pc_xu_stop => pc_xu_stop, - pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, - pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, - pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, - pc_bx_ccflush_dc => pc_bx_ccflush_dc, - pc_bx_sg_3 => pc_bx_sg_3, - pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, - pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, - pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, - pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, - pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, - pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, - pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, - pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, - - an_ac_scan_diag_dc_opc => an_ac_scan_diag_dc_opc, - an_ac_scan_dis_dc_b_opc => an_ac_scan_dis_dc_b_opc, - - xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled_ofu, - - gnd => gnd, - vdd => vdd + +a_pcq: entity work.pcq + generic map(expand_type => expand_type, regmode => regmode) + port map ( + abst_scan_in => iu_pc_abst_scan_out, + bcfg_scan_in => rp_pc_bcfg_scan_out_q, + ccfg_scan_in => iu_pc_ccfg_scan_out, + dcfg_scan_in => rp_pc_dcfg_scan_out_q, + func_scan_in => rp_pc_func_scan_in_q(0 to 1), + gptr_scan_in => iu_pc_gptr_scan_out, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue_ofu, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue_ofu, + fu_pc_event_data => fu_pc_event_data, + fu_pc_ram_data => fu_pc_ram_data, + fu_pc_ram_done => fu_pc_ram_done, + iu_pc_err_icache_parity => iu_pc_err_icache_parity, + iu_pc_err_icachedir_multihit => iu_pc_err_icachedir_multihit, + iu_pc_err_icachedir_parity => iu_pc_err_icachedir_parity, + fu_pc_err_regfile_parity => fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue => fu_pc_err_regfile_ue, + iu_pc_err_ucode_illegal => iu_pc_err_ucode_illegal, + iu_pc_event_data => iu_pc_event_data, + slowspr_addr_in => iu_pc_slowspr_addr, + slowspr_data_in => iu_pc_slowspr_data, + slowspr_done_in => iu_pc_slowspr_done, + slowspr_etid_in => iu_pc_slowspr_etid, + slowspr_rw_in => iu_pc_slowspr_rw, + slowspr_val_in => iu_pc_slowspr_val, + xu_pc_err_mcsr_summary => xu_pc_err_mcsr_summary_ofu, + xu_pc_err_ierat_parity => xu_pc_err_ierat_parity_ofu, + xu_pc_err_derat_parity => xu_pc_err_derat_parity_ofu, + xu_pc_err_tlb_parity => xu_pc_err_tlb_parity_ofu, + xu_pc_err_tlb_lru_parity => xu_pc_err_tlb_lru_parity_ofu, + xu_pc_err_ierat_multihit => xu_pc_err_ierat_multihit_ofu, + xu_pc_err_derat_multihit => xu_pc_err_derat_multihit_ofu, + xu_pc_err_tlb_multihit => xu_pc_err_tlb_multihit_ofu, + xu_pc_err_ext_mchk => xu_pc_err_ext_mchk_ofu, + xu_pc_err_ditc_overrun => xu_pc_err_ditc_overrun_ofu, + xu_pc_err_local_snoop_reject => xu_pc_err_local_snoop_reject_ofu, + mm_pc_event_data => mm_pc_event_data_oiu, + nclk => a2_nclk, + an_ac_rtim_sl_thold_6 => rp_pc_rtim_sl_thold_6, + an_ac_func_sl_thold_6 => rp_pc_func_sl_thold_6, + an_ac_func_nsl_thold_6 => rp_pc_func_nsl_thold_6, + an_ac_ary_nsl_thold_6 => rp_pc_ary_nsl_thold_6, + an_ac_sg_6 => rp_pc_sg_6, + an_ac_fce_6 => rp_pc_fce_6, + an_ac_abist_start_test => rp_pc_abist_start_test_q, + an_ac_ccenable_dc => an_ac_ccenable_dc_oiu, + an_ac_ccflush_dc => an_ac_ccflush_dc_oiu, + an_ac_debug_stop => rp_pc_debug_stop_q, + an_ac_gsd_test_enable_dc => an_ac_gsd_test_enable_dc_oiu, + an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc_oiu, + an_ac_lbist_en_dc => an_ac_lbist_en_dc_oiu, + an_ac_lbist_ip_dc => an_ac_lbist_ip_dc_oiu, + an_ac_lbist_ac_mode_dc => an_ac_lbist_ac_mode_dc_oiu, + an_ac_abist_mode_dc => an_ac_abist_mode_dc_oiu, + an_ac_malf_alert => an_ac_malf_alert_oiu, + an_ac_pm_thread_stop => rp_pc_pm_thread_stop_q, + an_ac_psro_enable_dc => an_ac_psro_enable_dc_oiu, + an_ac_reset_1_complete => rp_pc_reset_1_complete_q, + an_ac_reset_2_complete => rp_pc_reset_2_complete_q, + an_ac_reset_3_complete => rp_pc_reset_3_complete_q, + an_ac_reset_wd_complete => rp_pc_reset_wd_complete_q, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_oiu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_oiu, + an_ac_scan_type_dc => an_ac_scan_type_dc_oiu, + an_ac_scom_cch => rp_pc_scom_cch_q, + an_ac_scom_dch => rp_pc_scom_dch_q, + an_ac_scom_sat_id => an_ac_scom_sat_id_oiu, + an_ac_checkstop => rp_pc_checkstop_q, + debug_bus_in => fu_pc_debug_data, + trace_triggers_in => fu_pc_trigger_data, + xu_pc_err_attention_instr => xu_pc_err_attention_instr_ofu, + xu_pc_err_dcache_parity => xu_pc_err_dcache_parity_ofu, + xu_pc_err_dcachedir_parity => xu_pc_err_dcachedir_parity_ofu, + xu_pc_err_dcachedir_multihit => xu_pc_err_dcachedir_multihit_ofu, + xu_pc_err_debug_event => xu_pc_err_debug_event_ofu, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc_ofu, + xu_pc_err_invld_reld => xu_pc_err_invld_reld_ofu, + xu_pc_err_l2intrf_ecc => xu_pc_err_l2intrf_ecc_ofu, + xu_pc_err_l2intrf_ue => xu_pc_err_l2intrf_ue_ofu, + xu_pc_err_l2credit_overrun => xu_pc_err_l2credit_overrun_ofu, + xu_pc_err_llbust_attempt => xu_pc_err_llbust_attempt_ofu, + xu_pc_err_llbust_failed => xu_pc_err_llbust_failed_ofu, + xu_pc_err_nia_miscmpr => xu_pc_err_nia_miscmpr_ofu, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc_ofu, + xu_pc_err_regfile_parity => xu_pc_err_regfile_parity_ofu, + xu_pc_err_regfile_ue => xu_pc_err_regfile_ue_ofu, + xu_pc_err_sprg_ecc => xu_pc_err_sprg_ecc_ofu, + xu_pc_err_sprg_ue => xu_pc_err_sprg_ue_ofu, + xu_pc_err_wdt_reset => xu_pc_err_wdt_reset_ofu, + xu_pc_event_data => xu_pc_event_data_ofu, + lsu_pc_event_data => xu_pc_lsu_event_data_ofu, + ac_pc_trace_to_perfcntr => rp_pc_trace_to_perfcntr_q, + xu_pc_ram_data => xu_pc_ram_data_ofu, + xu_pc_ram_done => xu_pc_ram_done_ofu, + xu_pc_ram_interrupt => xu_pc_ram_interrupt_ofu, + xu_pc_running => xu_pc_running_ofu, + xu_pc_spr_ccr0_pme => xu_pc_spr_ccr0_pme_ofu, + xu_pc_spr_ccr0_we => xu_pc_spr_ccr0_we_ofu, + xu_pc_step_done => xu_pc_step_done_ofu, + xu_pc_stop_dbg_event => xu_pc_stop_dbg_event_ofu, + an_ac_bo_enable => an_ac_bo_enable, + an_ac_bo_go => an_ac_bo_go, + an_ac_bo_cntlclk => an_ac_bo_cntlclk, + an_ac_bo_ccflush => an_ac_bo_ccflush, + an_ac_bo_reset => an_ac_bo_reset, + an_ac_bo_data => an_ac_bo_data, + an_ac_bo_shcntl => an_ac_bo_shcntl, + an_ac_bo_shdata => an_ac_bo_shdata, + an_ac_bo_exe => an_ac_bo_exe, + an_ac_bo_sysrepair => an_ac_bo_sysrepair, + an_ac_bo_donein => an_ac_bo_donein, + an_ac_bo_sdin => an_ac_bo_sdin, + an_ac_bo_waitin => an_ac_bo_waitin, + an_ac_bo_failin => an_ac_bo_failin, + an_ac_bo_fcshdata => an_ac_bo_fcshdata, + an_ac_bo_fcreset => an_ac_bo_fcreset, + ac_an_bo_doneout => ac_an_bo_doneout, + ac_an_bo_sdout => ac_an_bo_sdout, + ac_an_bo_diagloopout => ac_an_bo_diagloopout, + ac_an_bo_waitout => ac_an_bo_waitout, + ac_an_bo_failout => ac_an_bo_failout, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3, + pc_fu_bolt_sl_thold_3 => pc_fu_bolt_sl_thold_3, + pc_xu_bolt_sl_thold_3 => pc_xu_bolt_sl_thold_3, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3, + pc_bx_bo_unload => pc_bx_bo_unload, + pc_bx_bo_repair => pc_bx_bo_repair, + pc_bx_bo_reset => pc_bx_bo_reset, + pc_bx_bo_shdata => pc_bx_bo_shdata, + pc_bx_bo_select => pc_bx_bo_select, + bx_pc_bo_fail => bx_pc_bo_fail_ofu, + bx_pc_bo_diagout => bx_pc_bo_diagout_ofu, + pc_fu_bo_enable_3 => pc_fu_bo_enable_3, + pc_fu_bo_unload => pc_fu_bo_unload, + pc_fu_bo_load => pc_fu_bo_load, + pc_fu_bo_reset => pc_fu_bo_reset, + pc_fu_bo_shdata => pc_fu_bo_shdata, + pc_fu_bo_select => pc_fu_bo_select, + fu_pc_bo_fail => fu_pc_bo_fail, + fu_pc_bo_diagout => fu_pc_bo_diagout, + pc_iu_bo_enable_4 => pc_iu_bo_enable_4, + pc_iu_bo_unload => pc_iu_bo_unload, + pc_iu_bo_repair => pc_iu_bo_repair, + pc_iu_bo_reset => pc_iu_bo_reset, + pc_iu_bo_shdata => pc_iu_bo_shdata, + pc_iu_bo_select => pc_iu_bo_select, + iu_pc_bo_fail => iu_pc_bo_fail, + iu_pc_bo_diagout => iu_pc_bo_diagout, + pc_mm_bo_enable_4 => pc_mm_bo_enable_4_iiu, + pc_mm_bo_unload => pc_mm_bo_unload_iiu, + pc_mm_bo_repair => pc_mm_bo_repair_iiu, + pc_mm_bo_reset => pc_mm_bo_reset_iiu, + pc_mm_bo_shdata => pc_mm_bo_shdata_iiu, + pc_mm_bo_select => pc_mm_bo_select_iiu, + mm_pc_bo_fail => mm_pc_bo_fail_oiu, + mm_pc_bo_diagout => mm_pc_bo_diagout_oiu, + pc_xu_bo_enable_3 => pc_xu_bo_enable_3, + pc_xu_bo_unload => pc_xu_bo_unload, + pc_xu_bo_load => pc_xu_bo_load, + pc_xu_bo_repair => pc_xu_bo_repair, + pc_xu_bo_reset => pc_xu_bo_reset, + pc_xu_bo_shdata => pc_xu_bo_shdata, + pc_xu_bo_select => pc_xu_bo_select, + xu_pc_bo_fail => xu_pc_bo_fail_ofu, + xu_pc_bo_diagout => xu_pc_bo_diagout_ofu, + ac_an_power_managed => pc_rp_power_managed, + ac_an_rvwinkle_mode => pc_rp_rvwinkle_mode, + ac_an_fu_bypass_events => pc_rp_fu_bypass_events, + ac_an_iu_bypass_events => pc_rp_iu_bypass_events, + ac_an_mm_bypass_events => pc_rp_mm_bypass_events, + ac_an_lsu_bypass_events => pc_rp_lsu_bypass_events, + ac_an_event_bus => pc_rp_event_bus, + ac_an_abist_done_dc => ac_an_abist_done_dc_iiu, + ac_an_local_checkstop => pc_rp_local_checkstop, + ac_an_pm_thread_running => pc_rp_pm_thread_running, + ac_an_psro_ringsig => ac_an_psro_ringsig_iiu, + ac_an_recov_err => pc_rp_recov_err, + ac_an_scom_cch => pc_rp_scom_cch, + ac_an_scom_dch => pc_rp_scom_dch, + ac_an_special_attn => pc_rp_special_attn, + ac_an_checkstop => pc_rp_checkstop, + ac_an_trace_error => pc_rp_trace_error, + debug_bus_out => pc_iu_debug_data, + trace_triggers_out => pc_iu_trigger_data, + abst_scan_out => pc_rp_abst_scan_out, + bcfg_scan_out => pc_rp_bcfg_scan_out, + ccfg_scan_out => pc_rp_ccfg_scan_out, + dcfg_scan_out => pc_rp_dcfg_scan_out, + func_scan_out => pc_rp_func_scan_out(0 to 1), + gptr_scan_out => pc_fu_gptr_scan_out, + pc_bx_abist_di_0 => pc_bx_abist_di_0(0 to 3), + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp(0 to 3), + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0(0 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0(0 to 9), + pc_bx_abist_wl64_g8t_comp_ena => pc_bx_abist_wl64_comp_ena, + pc_fu_abist_di_0 => pc_fu_abist_di_0(0 to 3), + pc_fu_abist_di_1 => pc_fu_abist_di_1(0 to 3), + pc_fu_abist_ena_dc => pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0 => pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1 => pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0 => pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1 => pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0 => pc_fu_abist_raddr_0(0 to 9), + pc_fu_abist_raddr_1 => pc_fu_abist_raddr_1(0 to 9), + pc_fu_abist_raw_dc_b => pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0 => pc_fu_abist_waddr_0(0 to 9), + pc_fu_abist_waddr_1 => pc_fu_abist_waddr_1(0 to 9), + pc_fu_abist_wl144_comp_ena => pc_fu_abist_wl144_comp_ena, + pc_iu_abist_dcomp_g6t_2r => pc_iu_abist_dcomp_g6t_2r(0 to 3), + pc_iu_abist_di_0 => pc_iu_abist_di_0(0 to 3), + pc_iu_abist_di_g6t_2r => pc_iu_abist_di_g6t_2r(0 to 3), + pc_iu_abist_ena_dc => pc_iu_abist_ena_dc, + pc_iu_abist_g6t_bw => pc_iu_abist_g6t_bw(0 to 1), + pc_iu_abist_g6t_r_wb => pc_iu_abist_g6t_r_wb, + pc_iu_abist_g8t1p_renb_0 => pc_iu_abist_g8t1p_renb_0, + pc_iu_abist_g8t_bw_0 => pc_iu_abist_g8t_bw_0, + pc_iu_abist_g8t_bw_1 => pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_dcomp => pc_iu_abist_g8t_dcomp(0 to 3), + pc_iu_abist_g8t_wenb => pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0 => pc_iu_abist_raddr_0(0 to 9), + pc_iu_abist_raw_dc_b => pc_iu_abist_raw_dc_b, + pc_iu_abist_waddr_0 => pc_iu_abist_waddr_0(0 to 9), + pc_iu_abist_wl128_g8t_comp_ena => pc_iu_abist_wl128_comp_ena, + pc_iu_abist_wl256_comp_ena => pc_iu_abist_wl256_comp_ena, + pc_iu_abist_wl64_g8t_comp_ena => pc_iu_abist_wl64_comp_ena, + pc_mm_abist_dcomp_g6t_2r => pc_mm_abist_dcomp_g6t_2r_iiu(0 to 3), + pc_mm_abist_di_0 => pc_mm_abist_di_0_iiu(0 to 3), + pc_mm_abist_di_g6t_2r => pc_mm_abist_di_g6t_2r_iiu(0 to 3), + pc_mm_abist_ena_dc => pc_mm_abist_ena_dc_iiu, + pc_mm_abist_g6t_r_wb => pc_mm_abist_g6t_r_wb_iiu, + pc_mm_abist_g8t1p_renb_0 => pc_mm_abist_g8t1p_renb_0_iiu, + pc_mm_abist_g8t_bw_0 => pc_mm_abist_g8t_bw_0_iiu, + pc_mm_abist_g8t_bw_1 => pc_mm_abist_g8t_bw_1_iiu, + pc_mm_abist_g8t_dcomp => pc_mm_abist_g8t_dcomp_iiu(0 to 3), + pc_mm_abist_g8t_wenb => pc_mm_abist_g8t_wenb_iiu, + pc_mm_abist_raddr_0 => pc_mm_abist_raddr_0_iiu(0 to 9), + pc_mm_abist_raw_dc_b => pc_mm_abist_raw_dc_b_iiu, + pc_mm_abist_waddr_0 => pc_mm_abist_waddr_0_iiu(0 to 9), + pc_mm_abist_wl128_g8t_comp_ena => pc_mm_abist_wl128_comp_ena_iiu, + pc_xu_abist_dcomp_g6t_2r => pc_xu_abist_dcomp_g6t_2r(0 to 3), + pc_xu_abist_di_0 => pc_xu_abist_di_0(0 to 3), + pc_xu_abist_di_1 => pc_xu_abist_di_1(0 to 3), + pc_xu_abist_di_g6t_2r => pc_xu_abist_di_g6t_2r(0 to 3), + pc_xu_abist_ena_dc => pc_xu_abist_ena_dc, + pc_xu_abist_g6t_bw => pc_xu_abist_g6t_bw(0 to 1), + pc_xu_abist_g6t_r_wb => pc_xu_abist_g6t_r_wb, + pc_xu_abist_g8t1p_renb_0 => pc_xu_abist_g8t1p_renb_0, + pc_xu_abist_g8t_bw_0 => pc_xu_abist_g8t_bw_0, + pc_xu_abist_g8t_bw_1 => pc_xu_abist_g8t_bw_1, + pc_xu_abist_g8t_dcomp => pc_xu_abist_g8t_dcomp(0 to 3), + pc_xu_abist_g8t_wenb => pc_xu_abist_g8t_wenb, + pc_xu_abist_grf_renb_0 => pc_xu_abist_grf_renb_0, + pc_xu_abist_grf_renb_1 => pc_xu_abist_grf_renb_1, + pc_xu_abist_grf_wenb_0 => pc_xu_abist_grf_wenb_0, + pc_xu_abist_grf_wenb_1 => pc_xu_abist_grf_wenb_1, + pc_xu_abist_raddr_0 => pc_xu_abist_raddr_0(0 to 9), + pc_xu_abist_raddr_1 => pc_xu_abist_raddr_1(0 to 9), + pc_xu_abist_raw_dc_b => pc_xu_abist_raw_dc_b, + pc_xu_abist_waddr_0 => pc_xu_abist_waddr_0(0 to 9), + pc_xu_abist_waddr_1 => pc_xu_abist_waddr_1(0 to 9), + pc_xu_abist_wl144_comp_ena => pc_xu_abist_wl144_comp_ena, + pc_xu_abist_wl32_g8t_comp_ena => pc_xu_abist_wl32_comp_ena, + pc_xu_abist_wl512_comp_ena => pc_xu_abist_wl512_comp_ena, + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc, + pc_fu_abst_sl_thold_3 => pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3 => pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3 => pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3 => pc_fu_ary_slp_nsl_thold_3, + pc_fu_ccflush_dc => pc_fu_ccflush_dc, + pc_fu_cfg_sl_thold_3 => pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3 => pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux1_ctrls => pc_fu_debug_mux1_ctrls, + pc_fu_event_count_mode => pc_fu_event_count_mode, + pc_fu_event_mux_ctrls => pc_fu_event_mux_ctrls, + pc_iu_event_mux_ctrls => pc_iu_event_mux_ctrls, + pc_mm_event_mux_ctrls => pc_mm_event_mux_ctrls_iiu, + pc_xu_event_mux_ctrls => pc_xu_event_mux_ctrls, + pc_xu_lsu_event_mux_ctrls => pc_xu_lsu_event_mux_ctrls, + pc_fu_event_bus_enable => pc_fu_event_bus_enable, + pc_iu_event_bus_enable => pc_iu_event_bus_enable, + pc_rp_event_bus_enable => pc_rp_event_bus_enable, + pc_xu_event_bus_enable => pc_xu_event_bus_enable, + pc_fu_fce_3 => pc_fu_fce_3, + pc_fu_func_nsl_thold_3 => pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3 => pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3 => pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3 => pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3 => pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity => pc_fu_inj_regfile_parity, + pc_fu_instr_trace_mode => pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid => pc_fu_instr_trace_tid, + pc_fu_ram_mode => pc_fu_ram_mode, + pc_fu_ram_thread => pc_fu_ram_thread, + pc_fu_repr_sl_thold_3 => pc_fu_repr_sl_thold_3, + pc_fu_sg_3 => pc_fu_sg_3, + slowspr_addr_out => pc_fu_slowspr_addr, + slowspr_data_out => pc_fu_slowspr_data, + slowspr_done_out => pc_fu_slowspr_done, + slowspr_etid_out => pc_fu_slowspr_etid, + slowspr_rw_out => pc_fu_slowspr_rw, + slowspr_val_out => pc_fu_slowspr_val, + pc_fu_time_sl_thold_3 => pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable => pc_fu_trace_bus_enable, + pc_iu_ccflush_dc => pc_iu_ccflush_dc, + pc_iu_gptr_sl_thold_4 => pc_iu_gptr_sl_thold_4, + pc_iu_time_sl_thold_4 => pc_iu_time_sl_thold_4, + pc_iu_repr_sl_thold_4 => pc_iu_repr_sl_thold_4, + pc_iu_abst_sl_thold_4 => pc_iu_abst_sl_thold_4, + pc_iu_abst_slp_sl_thold_4 => pc_iu_abst_slp_sl_thold_4, + pc_iu_bolt_sl_thold_4 => pc_iu_bolt_sl_thold_4, + pc_iu_regf_slp_sl_thold_4 => pc_iu_regf_slp_sl_thold_4, + pc_iu_func_sl_thold_4 => pc_iu_func_sl_thold_4, + pc_iu_func_slp_sl_thold_4 => pc_iu_func_slp_sl_thold_4, + pc_iu_cfg_sl_thold_4 => pc_iu_cfg_sl_thold_4, + pc_iu_cfg_slp_sl_thold_4 => pc_iu_cfg_slp_sl_thold_4, + pc_iu_func_nsl_thold_4 => pc_iu_func_nsl_thold_4, + pc_iu_func_slp_nsl_thold_4 => pc_iu_func_slp_nsl_thold_4, + pc_iu_ary_nsl_thold_4 => pc_iu_ary_nsl_thold_4, + pc_iu_ary_slp_nsl_thold_4 => pc_iu_ary_slp_nsl_thold_4, + pc_iu_sg_4 => pc_iu_sg_4, + pc_iu_fce_4 => pc_iu_fce_4, + pc_iu_debug_mux1_ctrls => pc_iu_debug_mux1_ctrls, + pc_iu_debug_mux2_ctrls => pc_iu_debug_mux2_ctrls, + pc_iu_event_count_mode => pc_iu_event_count_mode, + pc_iu_init_reset => pc_iu_init_reset, + pc_iu_inj_icache_parity => pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity => pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit => pc_iu_inj_icachedir_multihit, + pc_iu_ram_force_cmplt => pc_iu_ram_force_cmplt, + pc_iu_ram_instr => pc_iu_ram_instr, + pc_iu_ram_instr_ext => pc_iu_ram_instr_ext, + pc_iu_ram_mode => pc_iu_ram_mode, + pc_iu_ram_thread => pc_iu_ram_thread, + pc_iu_trace_bus_enable => pc_iu_trace_bus_enable, + pc_mm_ccflush_dc => pc_mm_ccflush_dc_iiu, + pc_mm_debug_mux1_ctrls => pc_mm_debug_mux1_ctrls_iiu, + pc_mm_event_count_mode => pc_mm_event_count_mode_iiu, + pc_mm_trace_bus_enable => pc_mm_trace_bus_enable_iiu, + pc_xu_abst_sl_thold_3 => pc_xu_abst_sl_thold_3, + pc_xu_abst_slp_sl_thold_3 => pc_xu_abst_slp_sl_thold_3, + pc_xu_regf_sl_thold_3 => pc_xu_regf_sl_thold_3, + pc_xu_regf_slp_sl_thold_3 => pc_xu_regf_slp_sl_thold_3, + pc_xu_ary_nsl_thold_3 => pc_xu_ary_nsl_thold_3, + pc_xu_ary_slp_nsl_thold_3 => pc_xu_ary_slp_nsl_thold_3, + pc_xu_cache_par_err_event => pc_xu_cache_par_err_event, + pc_xu_ccflush_dc => pc_xu_ccflush_dc, + pc_xu_cfg_sl_thold_3 => pc_xu_cfg_sl_thold_3, + pc_xu_cfg_slp_sl_thold_3 => pc_xu_cfg_slp_sl_thold_3, + pc_xu_dbg_action => pc_xu_dbg_action, + pc_xu_debug_mux1_ctrls => pc_xu_debug_mux1_ctrls, + pc_xu_debug_mux2_ctrls => pc_xu_debug_mux2_ctrls, + pc_xu_debug_mux3_ctrls => pc_xu_debug_mux3_ctrls, + pc_xu_debug_mux4_ctrls => pc_xu_debug_mux4_ctrls, + pc_xu_decrem_dis_on_stop => pc_xu_decrem_dis_on_stop, + pc_xu_event_count_mode => pc_xu_event_count_mode, + pc_xu_extirpts_dis_on_stop => pc_xu_extirpts_dis_on_stop, + pc_xu_fce_3 => pc_xu_fce_3, + pc_xu_force_ude => pc_xu_force_ude, + pc_xu_func_nsl_thold_3 => pc_xu_func_nsl_thold_3, + pc_xu_func_sl_thold_3 => pc_xu_func_sl_thold_3, + pc_xu_func_slp_nsl_thold_3 => pc_xu_func_slp_nsl_thold_3, + pc_xu_func_slp_sl_thold_3 => pc_xu_func_slp_sl_thold_3, + pc_xu_gptr_sl_thold_3 => pc_xu_gptr_sl_thold_3, + pc_xu_init_reset => pc_xu_init_reset, + pc_xu_inj_dcache_parity => pc_xu_inj_dcache_parity, + pc_xu_inj_dcachedir_parity => pc_xu_inj_dcachedir_parity, + pc_xu_inj_llbust_attempt => pc_xu_inj_llbust_attempt, + pc_xu_inj_llbust_failed => pc_xu_inj_llbust_failed, + pc_xu_inj_sprg_ecc => pc_xu_inj_sprg_ecc, + pc_xu_inj_regfile_parity => pc_xu_inj_regfile_parity, + pc_xu_inj_wdt_reset => pc_xu_inj_wdt_reset, + pc_xu_inj_dcachedir_multihit => pc_xu_inj_dcachedir_multihit, + pc_xu_instr_trace_mode => pc_xu_instr_trace_mode, + pc_xu_instr_trace_tid => pc_xu_instr_trace_tid, + pc_xu_msrovride_de => pc_xu_msrovride_de, + pc_xu_msrovride_enab => pc_xu_msrovride_enab, + pc_xu_msrovride_gs => pc_xu_msrovride_gs, + pc_xu_msrovride_pr => pc_xu_msrovride_pr, + pc_xu_ram_execute => pc_xu_ram_execute, + pc_xu_ram_flush_thread => pc_xu_ram_flush_thread, + pc_xu_ram_mode => pc_xu_ram_mode, + pc_xu_ram_thread => pc_xu_ram_thread, + pc_xu_repr_sl_thold_3 => pc_xu_repr_sl_thold_3, + pc_xu_reset_1_cmplt => pc_xu_reset_1_complete, + pc_xu_reset_2_cmplt => pc_xu_reset_2_complete, + pc_xu_reset_3_cmplt => pc_xu_reset_3_complete, + pc_xu_reset_wd_cmplt => pc_xu_reset_wd_complete, + pc_xu_sg_3 => pc_xu_sg_3, + pc_xu_step => pc_xu_step, + pc_xu_stop => pc_xu_stop, + pc_xu_time_sl_thold_3 => pc_xu_time_sl_thold_3, + pc_xu_timebase_dis_on_stop => pc_xu_timebase_dis_on_stop, + pc_xu_trace_bus_enable => pc_xu_trace_bus_enable, + pc_bx_ccflush_dc => pc_bx_ccflush_dc, + pc_bx_sg_3 => pc_bx_sg_3, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3, + + an_ac_scan_diag_dc_opc => an_ac_scan_diag_dc_opc, + an_ac_scan_dis_dc_b_opc => an_ac_scan_dis_dc_b_opc, + + xu_pc_err_mchk_disabled => xu_pc_err_mchk_disabled_ofu, + + gnd => gnd, + vdd => vdd ); - - -bx: if include_boxes=1 generate begin - a_bxq: entity work.bxq - generic map(expand_type => expand_type, - real_data_add => xu_real_data_add, - regmode => regmode) - PORT map( - xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, - xu_ex2_flush => xu_ex2_flush_ofu, - xu_ex3_flush => xu_ex3_flush_ofu, - xu_ex4_flush => xu_ex4_flush_ofu, - xu_ex5_flush => xu_ex5_flush_ofu, - xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, - xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, - xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, - xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, - xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, - xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , - - bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , - bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , - bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , - - bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, - bx_lsu_ob_req_val => bx_lsu_ob_req_val, - bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, - bx_lsu_ob_thrd => bx_lsu_ob_thrd, - bx_lsu_ob_qw => bx_lsu_ob_qw, - bx_lsu_ob_dest => bx_lsu_ob_dest, - bx_lsu_ob_data => bx_lsu_ob_data, - bx_lsu_ob_addr => bx_lsu_ob_addr, - - ac_an_reld_ditc_pop => ac_an_reld_ditc_pop_int, - - bx_ib_empty => bx_ib_empty_int, - bx_xu_quiesce => bx_xu_quiesce, - - lsu_bx_cmd_avail => lsu_bx_cmd_avail, - lsu_bx_cmd_sent => lsu_bx_cmd_sent, - lsu_bx_cmd_stall => lsu_bx_cmd_stall, - - lsu_reld_data_vld => lsu_reld_data_vld, - lsu_reld_core_tag => lsu_reld_core_tag(3 to 4), - lsu_reld_qw => lsu_reld_qw, - lsu_reld_ditc => lsu_reld_ditc, - lsu_reld_ecc_err => lsu_reld_ecc_err, - lsu_reld_data => lsu_reld_data, - - an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_ofu, - - lsu_req_st_pop => lsu_req_st_pop , - lsu_req_st_pop_thrd => lsu_req_st_pop_thrd , - - slowspr_addr_in => fu_bx_slowspr_addr, - slowspr_data_in => fu_bx_slowspr_data, - slowspr_done_in => fu_bx_slowspr_done, - slowspr_etid_in => fu_bx_slowspr_etid, - slowspr_rw_in => fu_bx_slowspr_rw, - slowspr_val_in => fu_bx_slowspr_val, - slowspr_addr_out => bx_xu_slowspr_addr, - slowspr_data_out => bx_xu_slowspr_data, - slowspr_done_out => bx_xu_slowspr_done, - slowspr_etid_out => bx_xu_slowspr_etid, - slowspr_rw_out => bx_xu_slowspr_rw, - slowspr_val_out => bx_xu_slowspr_val, - - bx_pc_bo_fail => bx_pc_bo_fail, - bx_pc_bo_diagout => bx_pc_bo_diagout, - bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, - bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, - bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, - bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, - pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc_ofu, - pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc_ofu, - - pc_bx_trace_bus_enable => pc_bx_trace_bus_enable_ofu, - pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls_ofu, - trigger_data_in => trigger_start_tiedowns, - debug_data_in => debug_start_tiedowns, - debug_data_out => bx_fu_debug_data, - trigger_data_out => bx_fu_trigger_data, - - vdd => vdd, - gnd => gnd, - vcs => vcs, - nclk => a2_nclk, - - pc_bx_abist_di_0 => pc_bx_abist_di_0_ofu, - pc_bx_abist_ena_dc => pc_bx_abist_ena_dc_ofu, - pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0_ofu, - pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0_ofu, - pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1_ofu, - pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp_ofu, - pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb_ofu, - pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0_ofu(4 to 9), - pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b_ofu, - pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0_ofu(4 to 9), - pc_bx_abist_wl64_comp_ena => pc_bx_abist_wl64_comp_ena_ofu, - pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3_ofu, - pc_bx_bo_enable_3 => pc_bx_bo_enable_3_ofu, - pc_bx_bo_unload => pc_bx_bo_unload_ofu, - pc_bx_bo_repair => pc_bx_bo_repair_ofu, - pc_bx_bo_reset => pc_bx_bo_reset_ofu, - pc_bx_bo_shdata => pc_bx_bo_shdata_ofu, - pc_bx_bo_select => pc_bx_bo_select_ofu, - pc_bx_ccflush_dc => pc_bx_ccflush_dc_ofu, - pc_bx_sg_3 => pc_bx_sg_3_ofu, - pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3_ofu, - pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3_ofu, - pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3_ofu, - pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3_ofu, - pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3_ofu, - pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3_ofu, - pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3_ofu, - pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3_ofu, - an_ac_scan_diag_dc => an_ac_scan_diag_dc_ofu, - an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_ofu, - time_scan_in => fu_bx_time_scan_out, - repr_scan_in => fu_bx_repr_scan_out, - abst_scan_in => rp_fu_bx_abst_scan_in, - time_scan_out => bx_xu_time_scan_out, - repr_scan_out => bx_xu_repr_scan_out, - abst_scan_out => bx_fu_rp_abst_scan_out, - gptr_scan_in => fu_bx_gptr_scan_out, - gptr_scan_out => bx_xu_gptr_scan_out, - func_scan_in => rp_fu_bx_func_scan_in, - func_scan_out => bx_fu_rp_func_scan_out + + +bx: if include_boxes=1 generate begin + a_bxq: entity work.bxq + generic map(expand_type => expand_type, + real_data_add => xu_real_data_add, + regmode => regmode) + PORT map( + xu_bx_ccr2_en_ditc => xu_bx_ccr2_en_ditc, + xu_ex2_flush => xu_ex2_flush_ofu, + xu_ex3_flush => xu_ex3_flush_ofu, + xu_ex4_flush => xu_ex4_flush_ofu, + xu_ex5_flush => xu_ex5_flush_ofu, + xu_bx_ex1_mtdp_val => xu_bx_ex1_mtdp_val, + xu_bx_ex1_mfdp_val => xu_bx_ex1_mfdp_val, + xu_bx_ex1_ipc_thrd => xu_bx_ex1_ipc_thrd, + xu_bx_ex2_ipc_ba => xu_bx_ex2_ipc_ba, + xu_bx_ex2_ipc_sz => xu_bx_ex2_ipc_sz, + xu_bx_ex4_256st_data => xu_bx_ex4_256st_data(128 to 255) , + + bx_xu_ex4_mtdp_cr_status => bx_xu_ex4_mtdp_cr_status , + bx_xu_ex4_mfdp_cr_status => bx_xu_ex4_mfdp_cr_status , + bx_xu_ex5_dp_data => bx_xu_ex5_dp_data , + + bx_lsu_ob_pwr_tok => bx_lsu_ob_pwr_tok, + bx_lsu_ob_req_val => bx_lsu_ob_req_val, + bx_lsu_ob_ditc_val => bx_lsu_ob_ditc_val, + bx_lsu_ob_thrd => bx_lsu_ob_thrd, + bx_lsu_ob_qw => bx_lsu_ob_qw, + bx_lsu_ob_dest => bx_lsu_ob_dest, + bx_lsu_ob_data => bx_lsu_ob_data, + bx_lsu_ob_addr => bx_lsu_ob_addr, + + ac_an_reld_ditc_pop => ac_an_reld_ditc_pop_int, + + bx_ib_empty => bx_ib_empty_int, + bx_xu_quiesce => bx_xu_quiesce, + + lsu_bx_cmd_avail => lsu_bx_cmd_avail, + lsu_bx_cmd_sent => lsu_bx_cmd_sent, + lsu_bx_cmd_stall => lsu_bx_cmd_stall, + + lsu_reld_data_vld => lsu_reld_data_vld, + lsu_reld_core_tag => lsu_reld_core_tag(3 to 4), + lsu_reld_qw => lsu_reld_qw, + lsu_reld_ditc => lsu_reld_ditc, + lsu_reld_ecc_err => lsu_reld_ecc_err, + lsu_reld_data => lsu_reld_data, + + an_ac_lbist_ary_wrt_thru_dc => an_ac_lbist_ary_wrt_thru_dc_ofu, + + lsu_req_st_pop => lsu_req_st_pop , + lsu_req_st_pop_thrd => lsu_req_st_pop_thrd , + + slowspr_addr_in => fu_bx_slowspr_addr, + slowspr_data_in => fu_bx_slowspr_data, + slowspr_done_in => fu_bx_slowspr_done, + slowspr_etid_in => fu_bx_slowspr_etid, + slowspr_rw_in => fu_bx_slowspr_rw, + slowspr_val_in => fu_bx_slowspr_val, + slowspr_addr_out => bx_xu_slowspr_addr, + slowspr_data_out => bx_xu_slowspr_data, + slowspr_done_out => bx_xu_slowspr_done, + slowspr_etid_out => bx_xu_slowspr_etid, + slowspr_rw_out => bx_xu_slowspr_rw, + slowspr_val_out => bx_xu_slowspr_val, + + bx_pc_bo_fail => bx_pc_bo_fail, + bx_pc_bo_diagout => bx_pc_bo_diagout, + bx_pc_err_inbox_ecc => bx_pc_err_inbox_ecc, + bx_pc_err_outbox_ecc => bx_pc_err_outbox_ecc, + bx_pc_err_inbox_ue => bx_pc_err_inbox_ue, + bx_pc_err_outbox_ue => bx_pc_err_outbox_ue, + pc_bx_inj_inbox_ecc => pc_bx_inj_inbox_ecc_ofu, + pc_bx_inj_outbox_ecc => pc_bx_inj_outbox_ecc_ofu, + + pc_bx_trace_bus_enable => pc_bx_trace_bus_enable_ofu, + pc_bx_debug_mux1_ctrls => pc_bx_debug_mux1_ctrls_ofu, + trigger_data_in => trigger_start_tiedowns, + debug_data_in => debug_start_tiedowns, + debug_data_out => bx_fu_debug_data, + trigger_data_out => bx_fu_trigger_data, + + vdd => vdd, + gnd => gnd, + vcs => vcs, + nclk => a2_nclk, + + pc_bx_abist_di_0 => pc_bx_abist_di_0_ofu, + pc_bx_abist_ena_dc => pc_bx_abist_ena_dc_ofu, + pc_bx_abist_g8t1p_renb_0 => pc_bx_abist_g8t1p_renb_0_ofu, + pc_bx_abist_g8t_bw_0 => pc_bx_abist_g8t_bw_0_ofu, + pc_bx_abist_g8t_bw_1 => pc_bx_abist_g8t_bw_1_ofu, + pc_bx_abist_g8t_dcomp => pc_bx_abist_g8t_dcomp_ofu, + pc_bx_abist_g8t_wenb => pc_bx_abist_g8t_wenb_ofu, + pc_bx_abist_raddr_0 => pc_bx_abist_raddr_0_ofu(4 to 9), + pc_bx_abist_raw_dc_b => pc_bx_abist_raw_dc_b_ofu, + pc_bx_abist_waddr_0 => pc_bx_abist_waddr_0_ofu(4 to 9), + pc_bx_abist_wl64_comp_ena => pc_bx_abist_wl64_comp_ena_ofu, + pc_bx_bolt_sl_thold_3 => pc_bx_bolt_sl_thold_3_ofu, + pc_bx_bo_enable_3 => pc_bx_bo_enable_3_ofu, + pc_bx_bo_unload => pc_bx_bo_unload_ofu, + pc_bx_bo_repair => pc_bx_bo_repair_ofu, + pc_bx_bo_reset => pc_bx_bo_reset_ofu, + pc_bx_bo_shdata => pc_bx_bo_shdata_ofu, + pc_bx_bo_select => pc_bx_bo_select_ofu, + pc_bx_ccflush_dc => pc_bx_ccflush_dc_ofu, + pc_bx_sg_3 => pc_bx_sg_3_ofu, + pc_bx_func_sl_thold_3 => pc_bx_func_sl_thold_3_ofu, + pc_bx_func_slp_sl_thold_3 => pc_bx_func_slp_sl_thold_3_ofu, + pc_bx_gptr_sl_thold_3 => pc_bx_gptr_sl_thold_3_ofu, + pc_bx_abst_sl_thold_3 => pc_bx_abst_sl_thold_3_ofu, + pc_bx_time_sl_thold_3 => pc_bx_time_sl_thold_3_ofu, + pc_bx_ary_nsl_thold_3 => pc_bx_ary_nsl_thold_3_ofu, + pc_bx_ary_slp_nsl_thold_3 => pc_bx_ary_slp_nsl_thold_3_ofu, + pc_bx_repr_sl_thold_3 => pc_bx_repr_sl_thold_3_ofu, + an_ac_scan_diag_dc => an_ac_scan_diag_dc_ofu, + an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b_ofu, + time_scan_in => fu_bx_time_scan_out, + repr_scan_in => fu_bx_repr_scan_out, + abst_scan_in => rp_fu_bx_abst_scan_in, + time_scan_out => bx_xu_time_scan_out, + repr_scan_out => bx_xu_repr_scan_out, + abst_scan_out => bx_fu_rp_abst_scan_out, + gptr_scan_in => fu_bx_gptr_scan_out, + gptr_scan_out => bx_xu_gptr_scan_out, + func_scan_in => rp_fu_bx_func_scan_in, + func_scan_out => bx_fu_rp_func_scan_out ); -end generate; - - -nobx: if include_boxes=0 generate begin - bx_xu_ex5_dp_data <= (others=>'0'); - bx_xu_ex4_mtdp_cr_status <= '0'; - bx_xu_ex4_mfdp_cr_status <= '0'; - bx_lsu_ob_pwr_tok <= '0'; - bx_lsu_ob_req_val <= '0'; - bx_lsu_ob_ditc_val <= '0'; - bx_lsu_ob_thrd <= (others=>'0'); - bx_lsu_ob_qw <= (others=>'0'); - bx_lsu_ob_dest <= (others=>'0'); - bx_lsu_ob_data <= (others=>'0'); - bx_lsu_ob_addr <= (others=>'0'); - ac_an_reld_ditc_pop_int <= (others=>'0'); - bx_ib_empty_int <= (others=>'1'); - bx_xu_quiesce <= (others=>'1'); - bx_xu_slowspr_addr <= fu_bx_slowspr_addr; - bx_xu_slowspr_data <= fu_bx_slowspr_data; - bx_xu_slowspr_done <= fu_bx_slowspr_done; - bx_xu_slowspr_etid <= fu_bx_slowspr_etid; - bx_xu_slowspr_rw <= fu_bx_slowspr_rw; - bx_xu_slowspr_val <= fu_bx_slowspr_val; - bx_pc_err_inbox_ecc <= '0'; - bx_pc_err_outbox_ecc <= '0'; - bx_pc_err_inbox_ue <= '0'; - bx_pc_err_outbox_ue <= '0'; - bx_fu_debug_data <= debug_start_tiedowns; - bx_fu_trigger_data <= trigger_start_tiedowns; - bx_xu_time_scan_out <= fu_bx_time_scan_out; - bx_xu_repr_scan_out <= fu_bx_repr_scan_out; - bx_rp_abst_scan_out <= rp_bx_abst_scan_in_q; - fu_bx_gptr_scan_out <= fu_bx_gptr_scan_out; - bx_rp_func_scan_out <= rp_bx_func_scan_in_q; -end generate; - - -END acq_soft; +end generate; + + +nobx: if include_boxes=0 generate begin + bx_xu_ex5_dp_data <= (others=>'0'); + bx_xu_ex4_mtdp_cr_status <= '0'; + bx_xu_ex4_mfdp_cr_status <= '0'; + bx_lsu_ob_pwr_tok <= '0'; + bx_lsu_ob_req_val <= '0'; + bx_lsu_ob_ditc_val <= '0'; + bx_lsu_ob_thrd <= (others=>'0'); + bx_lsu_ob_qw <= (others=>'0'); + bx_lsu_ob_dest <= (others=>'0'); + bx_lsu_ob_data <= (others=>'0'); + bx_lsu_ob_addr <= (others=>'0'); + ac_an_reld_ditc_pop_int <= (others=>'0'); + bx_ib_empty_int <= (others=>'1'); + bx_xu_quiesce <= (others=>'1'); + bx_xu_slowspr_addr <= fu_bx_slowspr_addr; + bx_xu_slowspr_data <= fu_bx_slowspr_data; + bx_xu_slowspr_done <= fu_bx_slowspr_done; + bx_xu_slowspr_etid <= fu_bx_slowspr_etid; + bx_xu_slowspr_rw <= fu_bx_slowspr_rw; + bx_xu_slowspr_val <= fu_bx_slowspr_val; + bx_pc_err_inbox_ecc <= '0'; + bx_pc_err_outbox_ecc <= '0'; + bx_pc_err_inbox_ue <= '0'; + bx_pc_err_outbox_ue <= '0'; + bx_fu_debug_data <= debug_start_tiedowns; + bx_fu_trigger_data <= trigger_start_tiedowns; + bx_xu_time_scan_out <= fu_bx_time_scan_out; + bx_xu_repr_scan_out <= fu_bx_repr_scan_out; + bx_rp_abst_scan_out <= rp_bx_abst_scan_in_q; + fu_bx_gptr_scan_out <= fu_bx_gptr_scan_out; + bx_rp_func_scan_out <= rp_bx_func_scan_in_q; +end generate; + + +END acq_soft; diff --git a/rel/src/vhdl/work/pcq_psro_soft.vhdl b/rel/src/vhdl/work/pcq_psro_soft.vhdl index db8be57..a4b2b8c 100644 --- a/rel/src/vhdl/work/pcq_psro_soft.vhdl +++ b/rel/src/vhdl/work/pcq_psro_soft.vhdl @@ -7,32 +7,32 @@ -- This README will be updated with additional information when OpenPOWER's -- license is available. -library ieee; -use ieee.std_logic_1164.all ; -library support; -use support.power_logic_pkg.all; -library tri; - - -entity pcq_psro_soft is - port ( +library ieee; +use ieee.std_logic_1164.all ; +library support; +use support.power_logic_pkg.all; +library tri; + + +entity pcq_psro_soft is + port ( vdd : inout power_logic; gnd : inout power_logic; pcq_psro_enable : in std_ulogic_vector(0 to 2); psro_pcq_ringsig : out std_ulogic - ); - -end pcq_psro_soft; - - -architecture pcq_psro_soft of pcq_psro_soft is -begin - - pcq_init: entity tri.tri_psro_soft - port map - ( vdd => vdd , - gnd => gnd , - psro_enable => pcq_psro_enable(0 to 2) , - psro_ringsig => psro_pcq_ringsig ); - -end pcq_psro_soft; + ); + +end pcq_psro_soft; + + +architecture pcq_psro_soft of pcq_psro_soft is +begin + + pcq_init: entity tri.tri_psro_soft + port map + ( vdd => vdd , + gnd => gnd , + psro_enable => pcq_psro_enable(0 to 2) , + psro_ringsig => psro_pcq_ringsig ); + +end pcq_psro_soft; diff --git a/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl b/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl index a364d9d..28aa7f6 100644 --- a/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_dir_tag.vhdl @@ -7,1040 +7,1040 @@ -- This README will be updated with additional information when OpenPOWER's -- license is available. - -library ibm, ieee, work, tri, support; -use ibm.std_ulogic_support.all; -use ibm.std_ulogic_function_support.all; -use ibm.std_ulogic_unsigned.all; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use tri.tri_latches_pkg.all; -use support.power_logic_pkg.all; - -entity xuq_lsu_dir_tag is -generic(expand_type : integer := 2; + +library ibm, ieee, work, tri, support; +use ibm.std_ulogic_support.all; +use ibm.std_ulogic_function_support.all; +use ibm.std_ulogic_unsigned.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use tri.tri_latches_pkg.all; +use support.power_logic_pkg.all; + +entity xuq_lsu_dir_tag is +generic(expand_type : integer := 2; dc_size : natural := 14; cl_size : natural := 6; wayDataSize : natural := 35; - parBits : natural := 4; - real_data_add : integer := 42); -port( - - ex2_stg_act :in std_ulogic; - binv2_stg_act :in std_ulogic; - - rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); - rel_way_upd_a :in std_ulogic; - rel_way_upd_b :in std_ulogic; - rel_way_upd_c :in std_ulogic; - rel_way_upd_d :in std_ulogic; - rel_way_upd_e :in std_ulogic; - rel_way_upd_f :in std_ulogic; - rel_way_upd_g :in std_ulogic; - rel_way_upd_h :in std_ulogic; - - inv1_val :in std_ulogic; - - xu_lsu_spr_xucr0_dcdis :in std_ulogic; - - ex1_p_addr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - ex1_p_addr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - ex1_p_addr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - ex1_p_addr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - ex2_ddir_acc_instr :in std_ulogic; - - pc_xu_inj_dcachedir_parity :in std_ulogic; - - dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); - - dir_wr_way :out std_ulogic_vector(0 to 7); - dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); - dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); - - ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); - - ex3_way_tag_par_a :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_b :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_c :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_d :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_e :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_f :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_g :out std_ulogic_vector(0 to parBits-1); - ex3_way_tag_par_h :out std_ulogic_vector(0 to parBits-1); - - ex3_tag_way_perr :out std_ulogic_vector(0 to 7); - - vdd :inout power_logic; - gnd :inout power_logic; - nclk :in clk_logic; - sg_0 :in std_ulogic; - func_sl_thold_0_b :in std_ulogic; - func_sl_force :in std_ulogic; - func_slp_sl_thold_0_b :in std_ulogic; - func_slp_sl_force :in std_ulogic; - d_mode_dc :in std_ulogic; - delay_lclkr_dc :in std_ulogic; - mpw1_dc_b :in std_ulogic; - mpw2_dc_b :in std_ulogic; - scan_in :in std_ulogic; - scan_out :out std_ulogic - ); --- synopsys translate_off --- synopsys translate_on -end xuq_lsu_dir_tag; -architecture xuq_lsu_dir_tag of xuq_lsu_dir_tag is - -constant uprTagBit :natural := 64-real_data_add; -constant lwrTagBit :natural := 63-(dc_size-3); -constant tagSize :natural := lwrTagBit-uprTagBit+1; -constant parExtCalc :natural := 8 - (tagSize mod 8); -constant uprCClassBit :natural := 64-(dc_size-3); -constant lwrCClassBit :natural := 63-cl_size; - -signal arr_wr_addr :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); -signal wayA_wen :std_ulogic; -signal wayB_wen :std_ulogic; -signal wayC_wen :std_ulogic; -signal wayD_wen :std_ulogic; -signal wayE_wen :std_ulogic; -signal wayF_wen :std_ulogic; -signal wayG_wen :std_ulogic; -signal wayH_wen :std_ulogic; -signal arr_wayA_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayB_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayC_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayD_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayE_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayF_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayG_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal arr_wayH_tag :std_ulogic_vector(uprTagBit to lwrTagBit); -signal inval_val_d :std_ulogic; -signal inval_val_q :std_ulogic; -signal arr_rd_addr_01 :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal arr_rd_addr_23 :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal arr_rd_addr_45 :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal arr_rd_addr_67 :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal ex3_en_par_chk_d :std_ulogic_vector(0 to 7); -signal ex3_en_par_chk_q :std_ulogic_vector(0 to 7); -signal spr_xucr0_dcdis_d :std_ulogic; -signal spr_xucr0_dcdis_q :std_ulogic; -signal inj_dcachedir_parity_d :std_ulogic; -signal inj_dcachedir_parity_q :std_ulogic; -signal relu_addr_d :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal relu_addr_q :std_ulogic_vector(uprCClassBit to lwrCClassBit); -signal ex2_par_gen_a_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_a_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_b_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_b_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_c_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_c_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_d_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_d_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_e_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_e_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_f_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_f_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_g_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_g_2b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_h_1b :std_ulogic_vector(0 to parBits-1); -signal ex2_par_gen_h_2b :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_a_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_a_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_a_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_a_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_b_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_b_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_b_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_b_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_c_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_c_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_c_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_c_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_d_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_d_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_d_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_d_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_e_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_e_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_e_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_e_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_f_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_f_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_f_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_f_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_g_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_g_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_g_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_g_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_h_1b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_h_2b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_h_1b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_h_2b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_a :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_b :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_c :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_d :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_e :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_f :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_g :std_ulogic_vector(0 to parBits-1); -signal ex3_par_gen_h :std_ulogic_vector(0 to parBits-1); -signal ex3_perr_det_a :std_ulogic; -signal ex3_perr_det_b :std_ulogic; -signal ex3_perr_det_c :std_ulogic; -signal ex3_perr_det_d :std_ulogic; -signal ex3_perr_det_e :std_ulogic; -signal ex3_perr_det_f :std_ulogic; -signal ex3_perr_det_g :std_ulogic; -signal ex3_perr_det_h :std_ulogic; -signal ex2_binv2_stg_act :std_ulogic; -signal rel_wrt_data_d :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); -signal rel_wrt_data_q :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); -signal ex3_way_tag_par_a_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_a_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_b_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_b_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_c_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_c_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_d_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_d_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_e_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_e_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_f_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_f_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_g_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_g_q :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_h_d :std_ulogic_vector(0 to parBits-1); -signal ex3_way_tag_par_h_q :std_ulogic_vector(0 to parBits-1); -signal my_spare0_lclk :clk_logic; -signal my_spare0_d1clk :std_ulogic; -signal my_spare0_d2clk :std_ulogic; -signal my_spare0_latches_d :std_ulogic_vector(0 to 15); -signal my_spare0_latches_q :std_ulogic_vector(0 to 15); -signal my_spare1_lclk :clk_logic; -signal my_spare1_d1clk :std_ulogic; -signal my_spare1_d2clk :std_ulogic; -signal my_spare1_latches_d :std_ulogic_vector(0 to 15); -signal my_spare1_latches_q :std_ulogic_vector(0 to 15); - -constant inval_val_offset :natural := 0; -constant ex3_en_par_chk_offset :natural := inval_val_offset + 1; -constant spr_xucr0_dcdis_offset :natural := ex3_en_par_chk_offset + 8; -constant inj_dcachedir_parity_offset :natural := spr_xucr0_dcdis_offset + 1; -constant relu_addr_offset :natural := inj_dcachedir_parity_offset + 1; -constant rel_wrt_data_offset :natural := relu_addr_offset + lwrCClassBit-uprCClassBit+1; -constant ex3_par_gen_a_1b_offset :natural := rel_wrt_data_offset + wayDataSize; -constant ex3_par_gen_a_2b_offset :natural := ex3_par_gen_a_1b_offset + parBits; -constant ex3_par_gen_b_1b_offset :natural := ex3_par_gen_a_2b_offset + parBits; -constant ex3_par_gen_b_2b_offset :natural := ex3_par_gen_b_1b_offset + parBits; -constant ex3_par_gen_c_1b_offset :natural := ex3_par_gen_b_2b_offset + parBits; -constant ex3_par_gen_c_2b_offset :natural := ex3_par_gen_c_1b_offset + parBits; -constant ex3_par_gen_d_1b_offset :natural := ex3_par_gen_c_2b_offset + parBits; -constant ex3_par_gen_d_2b_offset :natural := ex3_par_gen_d_1b_offset + parBits; -constant ex3_par_gen_e_1b_offset :natural := ex3_par_gen_d_2b_offset + parBits; -constant ex3_par_gen_e_2b_offset :natural := ex3_par_gen_e_1b_offset + parBits; -constant ex3_par_gen_f_1b_offset :natural := ex3_par_gen_e_2b_offset + parBits; -constant ex3_par_gen_f_2b_offset :natural := ex3_par_gen_f_1b_offset + parBits; -constant ex3_par_gen_g_1b_offset :natural := ex3_par_gen_f_2b_offset + parBits; -constant ex3_par_gen_g_2b_offset :natural := ex3_par_gen_g_1b_offset + parBits; -constant ex3_par_gen_h_1b_offset :natural := ex3_par_gen_g_2b_offset + parBits; -constant ex3_par_gen_h_2b_offset :natural := ex3_par_gen_h_1b_offset + parBits; -constant ex3_way_tag_par_a_offset :natural := ex3_par_gen_h_2b_offset + parBits; -constant ex3_way_tag_par_b_offset :natural := ex3_way_tag_par_a_offset + parBits; -constant ex3_way_tag_par_c_offset :natural := ex3_way_tag_par_b_offset + parBits; -constant ex3_way_tag_par_d_offset :natural := ex3_way_tag_par_c_offset + parBits; -constant ex3_way_tag_par_e_offset :natural := ex3_way_tag_par_d_offset + parBits; -constant ex3_way_tag_par_f_offset :natural := ex3_way_tag_par_e_offset + parBits; -constant ex3_way_tag_par_g_offset :natural := ex3_way_tag_par_f_offset + parBits; -constant ex3_way_tag_par_h_offset :natural := ex3_way_tag_par_g_offset + parBits; -constant my_spare0_latches_offset :natural := ex3_way_tag_par_h_offset + parBits; -constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 16; -constant scan_right :natural := my_spare1_latches_offset + 16 - 1; - -signal tiup :std_ulogic; -signal siv :std_ulogic_vector(0 to scan_right); -signal sov :std_ulogic_vector(0 to scan_right); - -begin - -tiup <= '1'; -ex2_binv2_stg_act <= ex2_stg_act or binv2_stg_act; - -relu_addr_d <= rel_addr_early(uprCClassBit to lwrCClassBit); -wayA_wen <= rel_way_upd_a; -wayB_wen <= rel_way_upd_b; -wayC_wen <= rel_way_upd_c; -wayD_wen <= rel_way_upd_d; -wayE_wen <= rel_way_upd_e; -wayF_wen <= rel_way_upd_f; -wayG_wen <= rel_way_upd_g; -wayH_wen <= rel_way_upd_h; - -inval_val_d <= inv1_val; - -spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; -inj_dcachedir_parity_d <= pc_xu_inj_dcachedir_parity; - - -arr_wr_addr <= relu_addr_q(uprCClassBit to lwrCClassBit); -arr_wr_data <= rel_addr_early(uprTagBit to lwrTagBit); - -arr_rd_addr_01 <= ex1_p_addr_01; -arr_rd_addr_23 <= ex1_p_addr_23; -arr_rd_addr_45 <= ex1_p_addr_45; -arr_rd_addr_67 <= ex1_p_addr_67; - - -l1dcta : entity work.xuq_lsu_dir_tag_arr(xuq_lsu_dir_tag_arr) -GENERIC MAP(expand_type => expand_type, - dc_size => dc_size, - cl_size => cl_size, - wayDataSize => wayDataSize, - parityBits => parBits, - real_data_add => real_data_add) -port map( - - waddr => arr_wr_addr, - wdata => arr_wr_data, - way_wen_a => wayA_wen, - way_wen_b => wayB_wen, - way_wen_c => wayC_wen, - way_wen_d => wayD_wen, - way_wen_e => wayE_wen, - way_wen_f => wayF_wen, - way_wen_g => wayG_wen, - way_wen_h => wayH_wen, - - raddr_01 => arr_rd_addr_01, - raddr_23 => arr_rd_addr_23, - raddr_45 => arr_rd_addr_45, - raddr_67 => arr_rd_addr_67, - inj_parity_err => inj_dcachedir_parity_q, - - dir_arr_rd_addr_01 => dir_arr_rd_addr_01, - dir_arr_rd_addr_23 => dir_arr_rd_addr_23, - dir_arr_rd_addr_45 => dir_arr_rd_addr_45, - dir_arr_rd_addr_67 => dir_arr_rd_addr_67, - dir_arr_rd_data => dir_arr_rd_data, - - dir_wr_way => dir_wr_way, - dir_arr_wr_addr => dir_arr_wr_addr, - dir_arr_wr_data => rel_wrt_data_d, - - way_tag_a => arr_wayA_tag, - way_tag_b => arr_wayB_tag, - way_tag_c => arr_wayC_tag, - way_tag_d => arr_wayD_tag, - way_tag_e => arr_wayE_tag, - way_tag_f => arr_wayF_tag, - way_tag_g => arr_wayG_tag, - way_tag_h => arr_wayH_tag, - - way_arr_par_a => ex3_way_tag_par_a_d, - way_arr_par_b => ex3_way_tag_par_b_d, - way_arr_par_c => ex3_way_tag_par_c_d, - way_arr_par_d => ex3_way_tag_par_d_d, - way_arr_par_e => ex3_way_tag_par_e_d, - way_arr_par_f => ex3_way_tag_par_f_d, - way_arr_par_g => ex3_way_tag_par_g_d, - way_arr_par_h => ex3_way_tag_par_h_d, - - par_gen_a_1b => ex2_par_gen_a_1b, - par_gen_a_2b => ex2_par_gen_a_2b, - par_gen_b_1b => ex2_par_gen_b_1b, - par_gen_b_2b => ex2_par_gen_b_2b, - par_gen_c_1b => ex2_par_gen_c_1b, - par_gen_c_2b => ex2_par_gen_c_2b, - par_gen_d_1b => ex2_par_gen_d_1b, - par_gen_d_2b => ex2_par_gen_d_2b, - par_gen_e_1b => ex2_par_gen_e_1b, - par_gen_e_2b => ex2_par_gen_e_2b, - par_gen_f_1b => ex2_par_gen_f_1b, - par_gen_f_2b => ex2_par_gen_f_2b, - par_gen_g_1b => ex2_par_gen_g_1b, - par_gen_g_2b => ex2_par_gen_g_2b, - par_gen_h_1b => ex2_par_gen_h_1b, - par_gen_h_2b => ex2_par_gen_h_2b -); - - -ex3_en_par_chk_d(0) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(1) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(2) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(3) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(4) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(5) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(6) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; -ex3_en_par_chk_d(7) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; - -ex3_par_gen_a_1b_d <= ex2_par_gen_a_1b; -ex3_par_gen_a_2b_d <= ex2_par_gen_a_2b; -ex3_par_gen_b_1b_d <= ex2_par_gen_b_1b; -ex3_par_gen_b_2b_d <= ex2_par_gen_b_2b; -ex3_par_gen_c_1b_d <= ex2_par_gen_c_1b; -ex3_par_gen_c_2b_d <= ex2_par_gen_c_2b; -ex3_par_gen_d_1b_d <= ex2_par_gen_d_1b; -ex3_par_gen_d_2b_d <= ex2_par_gen_d_2b; -ex3_par_gen_e_1b_d <= ex2_par_gen_e_1b; -ex3_par_gen_e_2b_d <= ex2_par_gen_e_2b; -ex3_par_gen_f_1b_d <= ex2_par_gen_f_1b; -ex3_par_gen_f_2b_d <= ex2_par_gen_f_2b; -ex3_par_gen_g_1b_d <= ex2_par_gen_g_1b; -ex3_par_gen_g_2b_d <= ex2_par_gen_g_2b; -ex3_par_gen_h_1b_d <= ex2_par_gen_h_1b; -ex3_par_gen_h_2b_d <= ex2_par_gen_h_2b; - -ex3_par_gen_a <= ex3_par_gen_a_1b_q xor ex3_par_gen_a_2b_q; -ex3_par_gen_b <= ex3_par_gen_b_1b_q xor ex3_par_gen_b_2b_q; -ex3_par_gen_c <= ex3_par_gen_c_1b_q xor ex3_par_gen_c_2b_q; -ex3_par_gen_d <= ex3_par_gen_d_1b_q xor ex3_par_gen_d_2b_q; -ex3_par_gen_e <= ex3_par_gen_e_1b_q xor ex3_par_gen_e_2b_q; -ex3_par_gen_f <= ex3_par_gen_f_1b_q xor ex3_par_gen_f_2b_q; -ex3_par_gen_g <= ex3_par_gen_g_1b_q xor ex3_par_gen_g_2b_q; -ex3_par_gen_h <= ex3_par_gen_h_1b_q xor ex3_par_gen_h_2b_q; - -ex3_perr_det_a <= or_reduce(ex3_way_tag_par_a_q xor ex3_par_gen_a) and ex3_en_par_chk_q(0); -ex3_perr_det_b <= or_reduce(ex3_way_tag_par_b_q xor ex3_par_gen_b) and ex3_en_par_chk_q(1); -ex3_perr_det_c <= or_reduce(ex3_way_tag_par_c_q xor ex3_par_gen_c) and ex3_en_par_chk_q(2); -ex3_perr_det_d <= or_reduce(ex3_way_tag_par_d_q xor ex3_par_gen_d) and ex3_en_par_chk_q(3); -ex3_perr_det_e <= or_reduce(ex3_way_tag_par_e_q xor ex3_par_gen_e) and ex3_en_par_chk_q(4); -ex3_perr_det_f <= or_reduce(ex3_way_tag_par_f_q xor ex3_par_gen_f) and ex3_en_par_chk_q(5); -ex3_perr_det_g <= or_reduce(ex3_way_tag_par_g_q xor ex3_par_gen_g) and ex3_en_par_chk_q(6); -ex3_perr_det_h <= or_reduce(ex3_way_tag_par_h_q xor ex3_par_gen_h) and ex3_en_par_chk_q(7); - -my_spare0_latches_d <= not my_spare0_latches_q; -my_spare1_latches_d <= not my_spare1_latches_q; - -ex2_wayA_tag <= arr_wayA_tag; -ex2_wayB_tag <= arr_wayB_tag; -ex2_wayC_tag <= arr_wayC_tag; -ex2_wayD_tag <= arr_wayD_tag; -ex2_wayE_tag <= arr_wayE_tag; -ex2_wayF_tag <= arr_wayF_tag; -ex2_wayG_tag <= arr_wayG_tag; -ex2_wayH_tag <= arr_wayH_tag; - -dir_arr_wr_data <= rel_wrt_data_q; - -ex3_way_tag_par_a <= ex3_way_tag_par_a_q; -ex3_way_tag_par_b <= ex3_way_tag_par_b_q; -ex3_way_tag_par_c <= ex3_way_tag_par_c_q; -ex3_way_tag_par_d <= ex3_way_tag_par_d_q; -ex3_way_tag_par_e <= ex3_way_tag_par_e_q; -ex3_way_tag_par_f <= ex3_way_tag_par_f_q; -ex3_way_tag_par_g <= ex3_way_tag_par_g_q; -ex3_way_tag_par_h <= ex3_way_tag_par_h_q; - -ex3_tag_way_perr <= ex3_perr_det_a & ex3_perr_det_b & ex3_perr_det_c & ex3_perr_det_d & - ex3_perr_det_e & ex3_perr_det_f & ex3_perr_det_g & ex3_perr_det_h; - - -inval_val_reg: tri_rlmlatch_p -generic map (init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(inval_val_offset), - scout => sov(inval_val_offset), - din => inval_val_d, - dout => inval_val_q); - -ex3_en_par_chk_reg: tri_rlmreg_p -generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), - scout => sov(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), - din => ex3_en_par_chk_d, - dout => ex3_en_par_chk_q); - -spr_xucr0_dcdis_reg: tri_rlmlatch_p -generic map (init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_sl_thold_0_b, - sg => sg_0, - scin => siv(spr_xucr0_dcdis_offset), - scout => sov(spr_xucr0_dcdis_offset), - din => spr_xucr0_dcdis_d, - dout => spr_xucr0_dcdis_q); - -inj_dcachedir_parity_reg: tri_rlmlatch_p -generic map (init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_sl_thold_0_b, - sg => sg_0, - scin => siv(inj_dcachedir_parity_offset), - scout => sov(inj_dcachedir_parity_offset), - din => inj_dcachedir_parity_d, - dout => inj_dcachedir_parity_q); - -relu_addr_reg: tri_rlmreg_p -generic map (width => lwrCClassBit-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_sl_thold_0_b, - sg => sg_0, - scin => siv(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), - scout => sov(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), - din => relu_addr_d, - dout => relu_addr_q); - -rel_wrt_data_reg: tri_rlmreg_p -generic map (width => wayDataSize, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_sl_thold_0_b, - sg => sg_0, - scin => siv(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), - scout => sov(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), - din => rel_wrt_data_d, - dout => rel_wrt_data_q); - -ex3_par_gen_a_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), - scout => sov(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), - din => ex3_par_gen_a_1b_d, - dout => ex3_par_gen_a_1b_q); - -ex3_par_gen_a_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), - scout => sov(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), - din => ex3_par_gen_a_2b_d, - dout => ex3_par_gen_a_2b_q); - -ex3_par_gen_b_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), - scout => sov(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), - din => ex3_par_gen_b_1b_d, - dout => ex3_par_gen_b_1b_q); - -ex3_par_gen_b_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), - scout => sov(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), - din => ex3_par_gen_b_2b_d, - dout => ex3_par_gen_b_2b_q); - -ex3_par_gen_c_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), - scout => sov(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), - din => ex3_par_gen_c_1b_d, - dout => ex3_par_gen_c_1b_q); - -ex3_par_gen_c_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), - scout => sov(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), - din => ex3_par_gen_c_2b_d, - dout => ex3_par_gen_c_2b_q); - -ex3_par_gen_d_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), - scout => sov(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), - din => ex3_par_gen_d_1b_d, - dout => ex3_par_gen_d_1b_q); - -ex3_par_gen_d_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), - scout => sov(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), - din => ex3_par_gen_d_2b_d, - dout => ex3_par_gen_d_2b_q); - -ex3_par_gen_e_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), - scout => sov(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), - din => ex3_par_gen_e_1b_d, - dout => ex3_par_gen_e_1b_q); - -ex3_par_gen_e_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), - scout => sov(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), - din => ex3_par_gen_e_2b_d, - dout => ex3_par_gen_e_2b_q); - -ex3_par_gen_f_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), - scout => sov(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), - din => ex3_par_gen_f_1b_d, - dout => ex3_par_gen_f_1b_q); - -ex3_par_gen_f_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), - scout => sov(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), - din => ex3_par_gen_f_2b_d, - dout => ex3_par_gen_f_2b_q); - -ex3_par_gen_g_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), - scout => sov(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), - din => ex3_par_gen_g_1b_d, - dout => ex3_par_gen_g_1b_q); - -ex3_par_gen_g_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), - scout => sov(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), - din => ex3_par_gen_g_2b_d, - dout => ex3_par_gen_g_2b_q); - -ex3_par_gen_h_1b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), - scout => sov(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), - din => ex3_par_gen_h_1b_d, - dout => ex3_par_gen_h_1b_q); - -ex3_par_gen_h_2b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), - scout => sov(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), - din => ex3_par_gen_h_2b_d, - dout => ex3_par_gen_h_2b_q); - -ex3_way_tag_par_a_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), - scout => sov(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), - din => ex3_way_tag_par_a_d, - dout => ex3_way_tag_par_a_q); - -ex3_way_tag_par_b_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), - scout => sov(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), - din => ex3_way_tag_par_b_d, - dout => ex3_way_tag_par_b_q); - -ex3_way_tag_par_c_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), - scout => sov(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), - din => ex3_way_tag_par_c_d, - dout => ex3_way_tag_par_c_q); - -ex3_way_tag_par_d_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), - scout => sov(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), - din => ex3_way_tag_par_d_d, - dout => ex3_way_tag_par_d_q); - -ex3_way_tag_par_e_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), - scout => sov(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), - din => ex3_way_tag_par_e_d, - dout => ex3_way_tag_par_e_q); - -ex3_way_tag_par_f_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), - scout => sov(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), - din => ex3_way_tag_par_f_d, - dout => ex3_way_tag_par_f_q); - -ex3_way_tag_par_g_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), - scout => sov(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), - din => ex3_way_tag_par_g_d, - dout => ex3_way_tag_par_g_q); - -ex3_way_tag_par_h_reg: tri_rlmreg_p -generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => ex2_binv2_stg_act, - forcee => func_slp_sl_force, - d_mode => d_mode_dc, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - scin => siv(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), - scout => sov(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), - din => ex3_way_tag_par_h_d, - dout => ex3_way_tag_par_h_q); - -my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) -generic map (expand_type => expand_type) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_slp_sl_force, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - d1clk => my_spare0_d1clk, - d2clk => my_spare0_d2clk, - lclk => my_spare0_lclk); -my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) -generic map (width => 16, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - lclk => my_spare0_lclk, - d1clk => my_spare0_d1clk, - d2clk => my_spare0_d2clk, - scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), - scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), - d => my_spare0_latches_d, - qb => my_spare0_latches_q); - -my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) -generic map (expand_type => expand_type) -port map (vd => vdd, - gd => gnd, - nclk => nclk, - act => tiup, - forcee => func_slp_sl_force, - delay_lclkr => delay_lclkr_dc, - mpw1_b => mpw1_dc_b, - mpw2_b => mpw2_dc_b, - thold_b => func_slp_sl_thold_0_b, - sg => sg_0, - d1clk => my_spare1_d1clk, - d2clk => my_spare1_d2clk, - lclk => my_spare1_lclk); -my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) -generic map (width => 16, expand_type => expand_type, needs_sreset => 1) -port map (vd => vdd, - gd => gnd, - lclk => my_spare1_lclk, - d1clk => my_spare1_d1clk, - d2clk => my_spare1_d2clk, - scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), - scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), - d => my_spare1_latches_d, - qb => my_spare1_latches_q); - -siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; -scan_out <= sov(0); -end xuq_lsu_dir_tag; - + parBits : natural := 4; + real_data_add : integer := 42); +port( + + ex2_stg_act :in std_ulogic; + binv2_stg_act :in std_ulogic; + + rel_addr_early :in std_ulogic_vector(64-real_data_add to 63-cl_size); + rel_way_upd_a :in std_ulogic; + rel_way_upd_b :in std_ulogic; + rel_way_upd_c :in std_ulogic; + rel_way_upd_d :in std_ulogic; + rel_way_upd_e :in std_ulogic; + rel_way_upd_f :in std_ulogic; + rel_way_upd_g :in std_ulogic; + rel_way_upd_h :in std_ulogic; + + inv1_val :in std_ulogic; + + xu_lsu_spr_xucr0_dcdis :in std_ulogic; + + ex1_p_addr_01 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_23 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_45 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex1_p_addr_67 :in std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + ex2_ddir_acc_instr :in std_ulogic; + + pc_xu_inj_dcachedir_parity :in std_ulogic; + + dir_arr_rd_addr_01 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_23 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_45 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_addr_67 :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_rd_data :in std_ulogic_vector(0 to 8*wayDataSize-1); + + dir_wr_way :out std_ulogic_vector(0 to 7); + dir_arr_wr_addr :out std_ulogic_vector(64-(dc_size-3) to 63-cl_size); + dir_arr_wr_data :out std_ulogic_vector(64-real_data_add to 64-real_data_add+wayDataSize-1); + + ex2_wayA_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayB_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayC_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayD_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayE_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayF_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayG_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + ex2_wayH_tag :out std_ulogic_vector(64-real_data_add to 63-(dc_size-3)); + + ex3_way_tag_par_a :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_b :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_c :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_d :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_e :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_f :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_g :out std_ulogic_vector(0 to parBits-1); + ex3_way_tag_par_h :out std_ulogic_vector(0 to parBits-1); + + ex3_tag_way_perr :out std_ulogic_vector(0 to 7); + + vdd :inout power_logic; + gnd :inout power_logic; + nclk :in clk_logic; + sg_0 :in std_ulogic; + func_sl_thold_0_b :in std_ulogic; + func_sl_force :in std_ulogic; + func_slp_sl_thold_0_b :in std_ulogic; + func_slp_sl_force :in std_ulogic; + d_mode_dc :in std_ulogic; + delay_lclkr_dc :in std_ulogic; + mpw1_dc_b :in std_ulogic; + mpw2_dc_b :in std_ulogic; + scan_in :in std_ulogic; + scan_out :out std_ulogic + ); +-- synopsys translate_off +-- synopsys translate_on +end xuq_lsu_dir_tag; +architecture xuq_lsu_dir_tag of xuq_lsu_dir_tag is + +constant uprTagBit :natural := 64-real_data_add; +constant lwrTagBit :natural := 63-(dc_size-3); +constant tagSize :natural := lwrTagBit-uprTagBit+1; +constant parExtCalc :natural := 8 - (tagSize mod 8); +constant uprCClassBit :natural := 64-(dc_size-3); +constant lwrCClassBit :natural := 63-cl_size; + +signal arr_wr_addr :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_wr_data :std_ulogic_vector(uprTagBit to lwrTagBit); +signal wayA_wen :std_ulogic; +signal wayB_wen :std_ulogic; +signal wayC_wen :std_ulogic; +signal wayD_wen :std_ulogic; +signal wayE_wen :std_ulogic; +signal wayF_wen :std_ulogic; +signal wayG_wen :std_ulogic; +signal wayH_wen :std_ulogic; +signal arr_wayA_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayB_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayC_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayD_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayE_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayF_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayG_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal arr_wayH_tag :std_ulogic_vector(uprTagBit to lwrTagBit); +signal inval_val_d :std_ulogic; +signal inval_val_q :std_ulogic; +signal arr_rd_addr_01 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_23 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_45 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal arr_rd_addr_67 :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex3_en_par_chk_d :std_ulogic_vector(0 to 7); +signal ex3_en_par_chk_q :std_ulogic_vector(0 to 7); +signal spr_xucr0_dcdis_d :std_ulogic; +signal spr_xucr0_dcdis_q :std_ulogic; +signal inj_dcachedir_parity_d :std_ulogic; +signal inj_dcachedir_parity_q :std_ulogic; +signal relu_addr_d :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal relu_addr_q :std_ulogic_vector(uprCClassBit to lwrCClassBit); +signal ex2_par_gen_a_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_a_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_b_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_c_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_d_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_e_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_f_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_g_2b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_1b :std_ulogic_vector(0 to parBits-1); +signal ex2_par_gen_h_2b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_1b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h_2b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_a :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_b :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_c :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_d :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_e :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_f :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_g :std_ulogic_vector(0 to parBits-1); +signal ex3_par_gen_h :std_ulogic_vector(0 to parBits-1); +signal ex3_perr_det_a :std_ulogic; +signal ex3_perr_det_b :std_ulogic; +signal ex3_perr_det_c :std_ulogic; +signal ex3_perr_det_d :std_ulogic; +signal ex3_perr_det_e :std_ulogic; +signal ex3_perr_det_f :std_ulogic; +signal ex3_perr_det_g :std_ulogic; +signal ex3_perr_det_h :std_ulogic; +signal ex2_binv2_stg_act :std_ulogic; +signal rel_wrt_data_d :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal rel_wrt_data_q :std_ulogic_vector(uprTagBit to uprTagBit+wayDataSize-1); +signal ex3_way_tag_par_a_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_a_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_b_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_c_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_d_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_e_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_f_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_g_q :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_d :std_ulogic_vector(0 to parBits-1); +signal ex3_way_tag_par_h_q :std_ulogic_vector(0 to parBits-1); +signal my_spare0_lclk :clk_logic; +signal my_spare0_d1clk :std_ulogic; +signal my_spare0_d2clk :std_ulogic; +signal my_spare0_latches_d :std_ulogic_vector(0 to 15); +signal my_spare0_latches_q :std_ulogic_vector(0 to 15); +signal my_spare1_lclk :clk_logic; +signal my_spare1_d1clk :std_ulogic; +signal my_spare1_d2clk :std_ulogic; +signal my_spare1_latches_d :std_ulogic_vector(0 to 15); +signal my_spare1_latches_q :std_ulogic_vector(0 to 15); + +constant inval_val_offset :natural := 0; +constant ex3_en_par_chk_offset :natural := inval_val_offset + 1; +constant spr_xucr0_dcdis_offset :natural := ex3_en_par_chk_offset + 8; +constant inj_dcachedir_parity_offset :natural := spr_xucr0_dcdis_offset + 1; +constant relu_addr_offset :natural := inj_dcachedir_parity_offset + 1; +constant rel_wrt_data_offset :natural := relu_addr_offset + lwrCClassBit-uprCClassBit+1; +constant ex3_par_gen_a_1b_offset :natural := rel_wrt_data_offset + wayDataSize; +constant ex3_par_gen_a_2b_offset :natural := ex3_par_gen_a_1b_offset + parBits; +constant ex3_par_gen_b_1b_offset :natural := ex3_par_gen_a_2b_offset + parBits; +constant ex3_par_gen_b_2b_offset :natural := ex3_par_gen_b_1b_offset + parBits; +constant ex3_par_gen_c_1b_offset :natural := ex3_par_gen_b_2b_offset + parBits; +constant ex3_par_gen_c_2b_offset :natural := ex3_par_gen_c_1b_offset + parBits; +constant ex3_par_gen_d_1b_offset :natural := ex3_par_gen_c_2b_offset + parBits; +constant ex3_par_gen_d_2b_offset :natural := ex3_par_gen_d_1b_offset + parBits; +constant ex3_par_gen_e_1b_offset :natural := ex3_par_gen_d_2b_offset + parBits; +constant ex3_par_gen_e_2b_offset :natural := ex3_par_gen_e_1b_offset + parBits; +constant ex3_par_gen_f_1b_offset :natural := ex3_par_gen_e_2b_offset + parBits; +constant ex3_par_gen_f_2b_offset :natural := ex3_par_gen_f_1b_offset + parBits; +constant ex3_par_gen_g_1b_offset :natural := ex3_par_gen_f_2b_offset + parBits; +constant ex3_par_gen_g_2b_offset :natural := ex3_par_gen_g_1b_offset + parBits; +constant ex3_par_gen_h_1b_offset :natural := ex3_par_gen_g_2b_offset + parBits; +constant ex3_par_gen_h_2b_offset :natural := ex3_par_gen_h_1b_offset + parBits; +constant ex3_way_tag_par_a_offset :natural := ex3_par_gen_h_2b_offset + parBits; +constant ex3_way_tag_par_b_offset :natural := ex3_way_tag_par_a_offset + parBits; +constant ex3_way_tag_par_c_offset :natural := ex3_way_tag_par_b_offset + parBits; +constant ex3_way_tag_par_d_offset :natural := ex3_way_tag_par_c_offset + parBits; +constant ex3_way_tag_par_e_offset :natural := ex3_way_tag_par_d_offset + parBits; +constant ex3_way_tag_par_f_offset :natural := ex3_way_tag_par_e_offset + parBits; +constant ex3_way_tag_par_g_offset :natural := ex3_way_tag_par_f_offset + parBits; +constant ex3_way_tag_par_h_offset :natural := ex3_way_tag_par_g_offset + parBits; +constant my_spare0_latches_offset :natural := ex3_way_tag_par_h_offset + parBits; +constant my_spare1_latches_offset :natural := my_spare0_latches_offset + 16; +constant scan_right :natural := my_spare1_latches_offset + 16 - 1; + +signal tiup :std_ulogic; +signal siv :std_ulogic_vector(0 to scan_right); +signal sov :std_ulogic_vector(0 to scan_right); + +begin + +tiup <= '1'; +ex2_binv2_stg_act <= ex2_stg_act or binv2_stg_act; + +relu_addr_d <= rel_addr_early(uprCClassBit to lwrCClassBit); +wayA_wen <= rel_way_upd_a; +wayB_wen <= rel_way_upd_b; +wayC_wen <= rel_way_upd_c; +wayD_wen <= rel_way_upd_d; +wayE_wen <= rel_way_upd_e; +wayF_wen <= rel_way_upd_f; +wayG_wen <= rel_way_upd_g; +wayH_wen <= rel_way_upd_h; + +inval_val_d <= inv1_val; + +spr_xucr0_dcdis_d <= xu_lsu_spr_xucr0_dcdis; +inj_dcachedir_parity_d <= pc_xu_inj_dcachedir_parity; + + +arr_wr_addr <= relu_addr_q(uprCClassBit to lwrCClassBit); +arr_wr_data <= rel_addr_early(uprTagBit to lwrTagBit); + +arr_rd_addr_01 <= ex1_p_addr_01; +arr_rd_addr_23 <= ex1_p_addr_23; +arr_rd_addr_45 <= ex1_p_addr_45; +arr_rd_addr_67 <= ex1_p_addr_67; + + +l1dcta : entity work.xuq_lsu_dir_tag_arr(xuq_lsu_dir_tag_arr) +GENERIC MAP(expand_type => expand_type, + dc_size => dc_size, + cl_size => cl_size, + wayDataSize => wayDataSize, + parityBits => parBits, + real_data_add => real_data_add) +port map( + + waddr => arr_wr_addr, + wdata => arr_wr_data, + way_wen_a => wayA_wen, + way_wen_b => wayB_wen, + way_wen_c => wayC_wen, + way_wen_d => wayD_wen, + way_wen_e => wayE_wen, + way_wen_f => wayF_wen, + way_wen_g => wayG_wen, + way_wen_h => wayH_wen, + + raddr_01 => arr_rd_addr_01, + raddr_23 => arr_rd_addr_23, + raddr_45 => arr_rd_addr_45, + raddr_67 => arr_rd_addr_67, + inj_parity_err => inj_dcachedir_parity_q, + + dir_arr_rd_addr_01 => dir_arr_rd_addr_01, + dir_arr_rd_addr_23 => dir_arr_rd_addr_23, + dir_arr_rd_addr_45 => dir_arr_rd_addr_45, + dir_arr_rd_addr_67 => dir_arr_rd_addr_67, + dir_arr_rd_data => dir_arr_rd_data, + + dir_wr_way => dir_wr_way, + dir_arr_wr_addr => dir_arr_wr_addr, + dir_arr_wr_data => rel_wrt_data_d, + + way_tag_a => arr_wayA_tag, + way_tag_b => arr_wayB_tag, + way_tag_c => arr_wayC_tag, + way_tag_d => arr_wayD_tag, + way_tag_e => arr_wayE_tag, + way_tag_f => arr_wayF_tag, + way_tag_g => arr_wayG_tag, + way_tag_h => arr_wayH_tag, + + way_arr_par_a => ex3_way_tag_par_a_d, + way_arr_par_b => ex3_way_tag_par_b_d, + way_arr_par_c => ex3_way_tag_par_c_d, + way_arr_par_d => ex3_way_tag_par_d_d, + way_arr_par_e => ex3_way_tag_par_e_d, + way_arr_par_f => ex3_way_tag_par_f_d, + way_arr_par_g => ex3_way_tag_par_g_d, + way_arr_par_h => ex3_way_tag_par_h_d, + + par_gen_a_1b => ex2_par_gen_a_1b, + par_gen_a_2b => ex2_par_gen_a_2b, + par_gen_b_1b => ex2_par_gen_b_1b, + par_gen_b_2b => ex2_par_gen_b_2b, + par_gen_c_1b => ex2_par_gen_c_1b, + par_gen_c_2b => ex2_par_gen_c_2b, + par_gen_d_1b => ex2_par_gen_d_1b, + par_gen_d_2b => ex2_par_gen_d_2b, + par_gen_e_1b => ex2_par_gen_e_1b, + par_gen_e_2b => ex2_par_gen_e_2b, + par_gen_f_1b => ex2_par_gen_f_1b, + par_gen_f_2b => ex2_par_gen_f_2b, + par_gen_g_1b => ex2_par_gen_g_1b, + par_gen_g_2b => ex2_par_gen_g_2b, + par_gen_h_1b => ex2_par_gen_h_1b, + par_gen_h_2b => ex2_par_gen_h_2b +); + + +ex3_en_par_chk_d(0) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(1) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(2) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(3) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(4) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(5) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(6) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; +ex3_en_par_chk_d(7) <= (ex2_ddir_acc_instr or inval_val_q) and not spr_xucr0_dcdis_q; + +ex3_par_gen_a_1b_d <= ex2_par_gen_a_1b; +ex3_par_gen_a_2b_d <= ex2_par_gen_a_2b; +ex3_par_gen_b_1b_d <= ex2_par_gen_b_1b; +ex3_par_gen_b_2b_d <= ex2_par_gen_b_2b; +ex3_par_gen_c_1b_d <= ex2_par_gen_c_1b; +ex3_par_gen_c_2b_d <= ex2_par_gen_c_2b; +ex3_par_gen_d_1b_d <= ex2_par_gen_d_1b; +ex3_par_gen_d_2b_d <= ex2_par_gen_d_2b; +ex3_par_gen_e_1b_d <= ex2_par_gen_e_1b; +ex3_par_gen_e_2b_d <= ex2_par_gen_e_2b; +ex3_par_gen_f_1b_d <= ex2_par_gen_f_1b; +ex3_par_gen_f_2b_d <= ex2_par_gen_f_2b; +ex3_par_gen_g_1b_d <= ex2_par_gen_g_1b; +ex3_par_gen_g_2b_d <= ex2_par_gen_g_2b; +ex3_par_gen_h_1b_d <= ex2_par_gen_h_1b; +ex3_par_gen_h_2b_d <= ex2_par_gen_h_2b; + +ex3_par_gen_a <= ex3_par_gen_a_1b_q xor ex3_par_gen_a_2b_q; +ex3_par_gen_b <= ex3_par_gen_b_1b_q xor ex3_par_gen_b_2b_q; +ex3_par_gen_c <= ex3_par_gen_c_1b_q xor ex3_par_gen_c_2b_q; +ex3_par_gen_d <= ex3_par_gen_d_1b_q xor ex3_par_gen_d_2b_q; +ex3_par_gen_e <= ex3_par_gen_e_1b_q xor ex3_par_gen_e_2b_q; +ex3_par_gen_f <= ex3_par_gen_f_1b_q xor ex3_par_gen_f_2b_q; +ex3_par_gen_g <= ex3_par_gen_g_1b_q xor ex3_par_gen_g_2b_q; +ex3_par_gen_h <= ex3_par_gen_h_1b_q xor ex3_par_gen_h_2b_q; + +ex3_perr_det_a <= or_reduce(ex3_way_tag_par_a_q xor ex3_par_gen_a) and ex3_en_par_chk_q(0); +ex3_perr_det_b <= or_reduce(ex3_way_tag_par_b_q xor ex3_par_gen_b) and ex3_en_par_chk_q(1); +ex3_perr_det_c <= or_reduce(ex3_way_tag_par_c_q xor ex3_par_gen_c) and ex3_en_par_chk_q(2); +ex3_perr_det_d <= or_reduce(ex3_way_tag_par_d_q xor ex3_par_gen_d) and ex3_en_par_chk_q(3); +ex3_perr_det_e <= or_reduce(ex3_way_tag_par_e_q xor ex3_par_gen_e) and ex3_en_par_chk_q(4); +ex3_perr_det_f <= or_reduce(ex3_way_tag_par_f_q xor ex3_par_gen_f) and ex3_en_par_chk_q(5); +ex3_perr_det_g <= or_reduce(ex3_way_tag_par_g_q xor ex3_par_gen_g) and ex3_en_par_chk_q(6); +ex3_perr_det_h <= or_reduce(ex3_way_tag_par_h_q xor ex3_par_gen_h) and ex3_en_par_chk_q(7); + +my_spare0_latches_d <= not my_spare0_latches_q; +my_spare1_latches_d <= not my_spare1_latches_q; + +ex2_wayA_tag <= arr_wayA_tag; +ex2_wayB_tag <= arr_wayB_tag; +ex2_wayC_tag <= arr_wayC_tag; +ex2_wayD_tag <= arr_wayD_tag; +ex2_wayE_tag <= arr_wayE_tag; +ex2_wayF_tag <= arr_wayF_tag; +ex2_wayG_tag <= arr_wayG_tag; +ex2_wayH_tag <= arr_wayH_tag; + +dir_arr_wr_data <= rel_wrt_data_q; + +ex3_way_tag_par_a <= ex3_way_tag_par_a_q; +ex3_way_tag_par_b <= ex3_way_tag_par_b_q; +ex3_way_tag_par_c <= ex3_way_tag_par_c_q; +ex3_way_tag_par_d <= ex3_way_tag_par_d_q; +ex3_way_tag_par_e <= ex3_way_tag_par_e_q; +ex3_way_tag_par_f <= ex3_way_tag_par_f_q; +ex3_way_tag_par_g <= ex3_way_tag_par_g_q; +ex3_way_tag_par_h <= ex3_way_tag_par_h_q; + +ex3_tag_way_perr <= ex3_perr_det_a & ex3_perr_det_b & ex3_perr_det_c & ex3_perr_det_d & + ex3_perr_det_e & ex3_perr_det_f & ex3_perr_det_g & ex3_perr_det_h; + + +inval_val_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(inval_val_offset), + scout => sov(inval_val_offset), + din => inval_val_d, + dout => inval_val_q); + +ex3_en_par_chk_reg: tri_rlmreg_p +generic map (width => 8, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + scout => sov(ex3_en_par_chk_offset to ex3_en_par_chk_offset + ex3_en_par_chk_d'length-1), + din => ex3_en_par_chk_d, + dout => ex3_en_par_chk_q); + +spr_xucr0_dcdis_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(spr_xucr0_dcdis_offset), + scout => sov(spr_xucr0_dcdis_offset), + din => spr_xucr0_dcdis_d, + dout => spr_xucr0_dcdis_q); + +inj_dcachedir_parity_reg: tri_rlmlatch_p +generic map (init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(inj_dcachedir_parity_offset), + scout => sov(inj_dcachedir_parity_offset), + din => inj_dcachedir_parity_d, + dout => inj_dcachedir_parity_q); + +relu_addr_reg: tri_rlmreg_p +generic map (width => lwrCClassBit-uprCClassBit+1, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + scout => sov(relu_addr_offset to relu_addr_offset + relu_addr_d'length-1), + din => relu_addr_d, + dout => relu_addr_q); + +rel_wrt_data_reg: tri_rlmreg_p +generic map (width => wayDataSize, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_sl_thold_0_b, + sg => sg_0, + scin => siv(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + scout => sov(rel_wrt_data_offset to rel_wrt_data_offset + rel_wrt_data_d'length-1), + din => rel_wrt_data_d, + dout => rel_wrt_data_q); + +ex3_par_gen_a_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + scout => sov(ex3_par_gen_a_1b_offset to ex3_par_gen_a_1b_offset + ex3_par_gen_a_1b_d'length-1), + din => ex3_par_gen_a_1b_d, + dout => ex3_par_gen_a_1b_q); + +ex3_par_gen_a_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + scout => sov(ex3_par_gen_a_2b_offset to ex3_par_gen_a_2b_offset + ex3_par_gen_a_2b_d'length-1), + din => ex3_par_gen_a_2b_d, + dout => ex3_par_gen_a_2b_q); + +ex3_par_gen_b_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + scout => sov(ex3_par_gen_b_1b_offset to ex3_par_gen_b_1b_offset + ex3_par_gen_b_1b_d'length-1), + din => ex3_par_gen_b_1b_d, + dout => ex3_par_gen_b_1b_q); + +ex3_par_gen_b_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + scout => sov(ex3_par_gen_b_2b_offset to ex3_par_gen_b_2b_offset + ex3_par_gen_b_2b_d'length-1), + din => ex3_par_gen_b_2b_d, + dout => ex3_par_gen_b_2b_q); + +ex3_par_gen_c_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + scout => sov(ex3_par_gen_c_1b_offset to ex3_par_gen_c_1b_offset + ex3_par_gen_c_1b_d'length-1), + din => ex3_par_gen_c_1b_d, + dout => ex3_par_gen_c_1b_q); + +ex3_par_gen_c_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + scout => sov(ex3_par_gen_c_2b_offset to ex3_par_gen_c_2b_offset + ex3_par_gen_c_2b_d'length-1), + din => ex3_par_gen_c_2b_d, + dout => ex3_par_gen_c_2b_q); + +ex3_par_gen_d_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + scout => sov(ex3_par_gen_d_1b_offset to ex3_par_gen_d_1b_offset + ex3_par_gen_d_1b_d'length-1), + din => ex3_par_gen_d_1b_d, + dout => ex3_par_gen_d_1b_q); + +ex3_par_gen_d_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + scout => sov(ex3_par_gen_d_2b_offset to ex3_par_gen_d_2b_offset + ex3_par_gen_d_2b_d'length-1), + din => ex3_par_gen_d_2b_d, + dout => ex3_par_gen_d_2b_q); + +ex3_par_gen_e_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + scout => sov(ex3_par_gen_e_1b_offset to ex3_par_gen_e_1b_offset + ex3_par_gen_e_1b_d'length-1), + din => ex3_par_gen_e_1b_d, + dout => ex3_par_gen_e_1b_q); + +ex3_par_gen_e_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + scout => sov(ex3_par_gen_e_2b_offset to ex3_par_gen_e_2b_offset + ex3_par_gen_e_2b_d'length-1), + din => ex3_par_gen_e_2b_d, + dout => ex3_par_gen_e_2b_q); + +ex3_par_gen_f_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + scout => sov(ex3_par_gen_f_1b_offset to ex3_par_gen_f_1b_offset + ex3_par_gen_f_1b_d'length-1), + din => ex3_par_gen_f_1b_d, + dout => ex3_par_gen_f_1b_q); + +ex3_par_gen_f_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + scout => sov(ex3_par_gen_f_2b_offset to ex3_par_gen_f_2b_offset + ex3_par_gen_f_2b_d'length-1), + din => ex3_par_gen_f_2b_d, + dout => ex3_par_gen_f_2b_q); + +ex3_par_gen_g_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + scout => sov(ex3_par_gen_g_1b_offset to ex3_par_gen_g_1b_offset + ex3_par_gen_g_1b_d'length-1), + din => ex3_par_gen_g_1b_d, + dout => ex3_par_gen_g_1b_q); + +ex3_par_gen_g_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + scout => sov(ex3_par_gen_g_2b_offset to ex3_par_gen_g_2b_offset + ex3_par_gen_g_2b_d'length-1), + din => ex3_par_gen_g_2b_d, + dout => ex3_par_gen_g_2b_q); + +ex3_par_gen_h_1b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + scout => sov(ex3_par_gen_h_1b_offset to ex3_par_gen_h_1b_offset + ex3_par_gen_h_1b_d'length-1), + din => ex3_par_gen_h_1b_d, + dout => ex3_par_gen_h_1b_q); + +ex3_par_gen_h_2b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + scout => sov(ex3_par_gen_h_2b_offset to ex3_par_gen_h_2b_offset + ex3_par_gen_h_2b_d'length-1), + din => ex3_par_gen_h_2b_d, + dout => ex3_par_gen_h_2b_q); + +ex3_way_tag_par_a_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + scout => sov(ex3_way_tag_par_a_offset to ex3_way_tag_par_a_offset + ex3_way_tag_par_a_d'length-1), + din => ex3_way_tag_par_a_d, + dout => ex3_way_tag_par_a_q); + +ex3_way_tag_par_b_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + scout => sov(ex3_way_tag_par_b_offset to ex3_way_tag_par_b_offset + ex3_way_tag_par_b_d'length-1), + din => ex3_way_tag_par_b_d, + dout => ex3_way_tag_par_b_q); + +ex3_way_tag_par_c_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + scout => sov(ex3_way_tag_par_c_offset to ex3_way_tag_par_c_offset + ex3_way_tag_par_c_d'length-1), + din => ex3_way_tag_par_c_d, + dout => ex3_way_tag_par_c_q); + +ex3_way_tag_par_d_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + scout => sov(ex3_way_tag_par_d_offset to ex3_way_tag_par_d_offset + ex3_way_tag_par_d_d'length-1), + din => ex3_way_tag_par_d_d, + dout => ex3_way_tag_par_d_q); + +ex3_way_tag_par_e_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + scout => sov(ex3_way_tag_par_e_offset to ex3_way_tag_par_e_offset + ex3_way_tag_par_e_d'length-1), + din => ex3_way_tag_par_e_d, + dout => ex3_way_tag_par_e_q); + +ex3_way_tag_par_f_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + scout => sov(ex3_way_tag_par_f_offset to ex3_way_tag_par_f_offset + ex3_way_tag_par_f_d'length-1), + din => ex3_way_tag_par_f_d, + dout => ex3_way_tag_par_f_q); + +ex3_way_tag_par_g_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + scout => sov(ex3_way_tag_par_g_offset to ex3_way_tag_par_g_offset + ex3_way_tag_par_g_d'length-1), + din => ex3_way_tag_par_g_d, + dout => ex3_way_tag_par_g_q); + +ex3_way_tag_par_h_reg: tri_rlmreg_p +generic map (width => parBits, init => 0, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => ex2_binv2_stg_act, + forcee => func_slp_sl_force, + d_mode => d_mode_dc, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + scin => siv(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + scout => sov(ex3_way_tag_par_h_offset to ex3_way_tag_par_h_offset + ex3_way_tag_par_h_d'length-1), + din => ex3_way_tag_par_h_d, + dout => ex3_way_tag_par_h_q); + +my_spare0_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + lclk => my_spare0_lclk); +my_spare0_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare0_lclk, + d1clk => my_spare0_d1clk, + d2clk => my_spare0_d2clk, + scanin => siv(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + scanout => sov(my_spare0_latches_offset to my_spare0_latches_offset + my_spare0_latches_d'length-1), + d => my_spare0_latches_d, + qb => my_spare0_latches_q); + +my_spare1_lcb : entity tri.tri_lcbnd(tri_lcbnd) +generic map (expand_type => expand_type) +port map (vd => vdd, + gd => gnd, + nclk => nclk, + act => tiup, + forcee => func_slp_sl_force, + delay_lclkr => delay_lclkr_dc, + mpw1_b => mpw1_dc_b, + mpw2_b => mpw2_dc_b, + thold_b => func_slp_sl_thold_0_b, + sg => sg_0, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + lclk => my_spare1_lclk); +my_spare1_latches_reg: entity tri.tri_inv_nlats(tri_inv_nlats) +generic map (width => 16, expand_type => expand_type, needs_sreset => 1) +port map (vd => vdd, + gd => gnd, + lclk => my_spare1_lclk, + d1clk => my_spare1_d1clk, + d2clk => my_spare1_d2clk, + scanin => siv(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + scanout => sov(my_spare1_latches_offset to my_spare1_latches_offset + my_spare1_latches_d'length-1), + d => my_spare1_latches_d, + qb => my_spare1_latches_q); + +siv(0 to scan_right) <= sov(1 to scan_right) & scan_in; +scan_out <= sov(0); +end xuq_lsu_dir_tag; +