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@ -1,12 +0,0 @@
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#-----------------------------------------------------------
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# Vivado v2019.1.3 (64-bit)
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# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
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# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
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# Start of session at: Fri Jun 26 10:16:40 2020
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# Process ID: 89782
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# Current directory: /gsa/pokgsa-h3/15/wtf/github/a2x/rel/build/ip_user/a2x_axi
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# Command line: vivado -mode tcl -source tcl/create_ip_a2x_axi.tcl
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# Log file: /gsa/pokgsa-h3/15/wtf/github/a2x/rel/build/ip_user/a2x_axi/vivado.log
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# Journal file: /gsa/pokgsa-h3/15/wtf/github/a2x/rel/build/ip_user/a2x_axi/vivado.jou
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#-----------------------------------------------------------
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source tcl/create_ip_a2x_axi.tcl
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File diff suppressed because it is too large
Load Diff
@ -8,6 +8,12 @@
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-- license is available.
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-- *!****************************************************************
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-- *! FILENAME : c_scom_addr_decode.vhdl
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-- *! TITLE :
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-- *! DESCRIPTION : Generic SCOM address decoder
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-- *!
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-- *!****************************************************************
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library ieee,ibm,clib,support;
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use ieee.std_logic_1164.all;
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@ -16,18 +22,24 @@ use ibm.std_ulogic_function_support.all;
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use support.power_logic_pkg.all;
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entity c_scom_addr_decode is
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generic( satid_nobits : positive := 5
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generic( satid_nobits : positive := 5 -- should not be set by user
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-- Set the following 3 vectors to generate an SCOM address
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-- HEX >>>>> "0000000000000000111111111111111122222222222222223333333333333333"
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-- ADDR >>>>> "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"
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--
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-- DEC >>>>> "0000000000111111111122222222223333333333444444444455555555556666"
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-- ADDR >>>>> "0123456789012345678901234567890123456789012345678901234567890123"
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; use_addr : std_ulogic_vector := "1"
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; addr_is_rdable : std_ulogic_vector := "1"
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; addr_is_wrable : std_ulogic_vector := "1"
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);
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port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1)
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; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1)
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; sc_req : in std_ulogic
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; sc_r_nw : in std_ulogic
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; scaddr_nvld : out std_ulogic
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; sc_wr_nvld : out std_ulogic
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; sc_rd_nvld : out std_ulogic
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port( sc_addr : in std_ulogic_vector(0 to 11-satid_nobits-1) -- binary coded scom address
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; scaddr_dec : out std_ulogic_vector(0 to use_addr'length-1) -- one hot coded scom address; not latched
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; sc_req : in std_ulogic -- scom request
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; sc_r_nw : in std_ulogic -- read / not write bit
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; scaddr_nvld : out std_ulogic -- scom address not valid; not latched
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; sc_wr_nvld : out std_ulogic -- scom write not allowed; not latched
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; sc_rd_nvld : out std_ulogic -- scom read not allowed; not latched
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; vd : inout power_logic
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; gd : inout power_logic
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);
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@ -48,4 +60,3 @@ begin
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sc_wr_nvld <= not or_reduce(address and addr_is_wrable) and sc_req and not sc_r_nw;
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sc_rd_nvld <= not or_reduce(address and addr_is_rdable) and sc_req and sc_r_nw;
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end c_scom_addr_decode;
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@ -7,6 +7,52 @@
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-- This README will be updated with additional information when OpenPOWER's
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-- license is available.
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-- ttypes handled:
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-- 00 ifetch
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-- 01 ifetch pre (may not occur?)
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-- 08 load
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-- 09 larx
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-- 20 store
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-- 29 stcx
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-- 2A lwsync
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-- 2B hwsync
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-- 3A tlbsync (lwsync version)
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-- 3F dcbi
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-- 08 larx
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-- OB larx w/hint
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-- ttypes not handled:
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-- 02 mmu_read (is it diff from load?)
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-- 04 icbt
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-- 05 dcbtst
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-- 07 dcbt
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-- 0D dcbtst
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-- 0F dcbtls
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-- 14 icbtls
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-- 15 dcbtstls
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--- 17 dcbtls
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-- 21 dcbz
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-- 22 ditc
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-- 24 icblc
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-- 25 dcblc
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-- 26 icswx
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-- 27 icswx.
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-- 2C mtspr_trace
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-- 2D msgsnd
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-- 2E ici
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-- 2F dci
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-- 32 mbar
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-- 33 ptesync
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-- 34 l1_load_hit
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-- 35 dcbst
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-- 36 dcbf
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-- 37 dcbf
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-- 3C tlbivax
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-- 3D tlbi
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-- 3E icbi
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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@ -19,9 +65,9 @@ entity a2l2_axi is
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generic (
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threads : integer := 4;
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xu_real_data_add : integer := 42;
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st_data_32b_mode : integer := 1;
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st_data_32b_mode : integer := 1; -- proc data/be size
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ac_st_data_32b_mode : integer := 1;
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stores_32B : boolean := false;
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stores_32B : boolean := false; -- does proc gen 32B stores
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lpid_width : integer := 8;
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ld_queue_size : integer := 4;
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st_queue_size : integer := 16;
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@ -125,7 +171,7 @@ architecture a2l2_axi of a2l2_axi is
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signal reload_d: A2L2RELOAD;
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signal reload_q: A2L2RELOAD;
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signal rld_seq_d : std_logic_vector(0 to 4);
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signal rld_seq_q : std_logic_vector(0 to 4);
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signal rld_dseq_d : std_logic_vector(0 to 3);
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@ -220,13 +266,11 @@ signal axi_store_data_ready : std_logic;
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signal axi_store_data_valid : std_logic;
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signal axi_store_data : std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
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signal axi_store_data_be : std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0);
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signal axi_store_rsp_ready : std_logic;
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signal axi_store_rsp_valid : std_logic;
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signal axi_store_rsp_id : std_logic_vector(C_M00_AXI_ID_WIDTH-1 downto 0);
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signal axi_store_rsp_resp : std_logic_vector(1 downto 0);
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signal store_complete : std_logic;
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signal store_data_in : std_logic_vector(0 to 127);
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signal store_be_in : std_logic_vector(0 to 15);
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@ -457,8 +501,12 @@ end if;
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end process FF;
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------------------------------------------------------------------------------------------------------------
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-- Init
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-- credits are initially set in core
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------------------------------------------------------------------------------------------------------------
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-- Process request
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req_pwr_d <= ac_an_req_pwr_token;
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@ -478,6 +526,61 @@ req_in.wimg <= ac_an_req_wimg_w & ac_an_req_wimg_i & ac_an_req_wimg_m & ac_an_re
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req_in.hwsync <= req_in.spec;
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--tbl ReqDcd
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--
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--n req_in.valid req_in_load
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--n | req_in.ttype |req_in_store
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--n | | req_in.thread ||req_in_spec
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--n | | | |||
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--n | | | ||| larx_t
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--n | | | ||| | stcx_t
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--n | | | ||| | | store_t
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--n | | | ||| | | |
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--n | | | ||| | | |
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--n | | | ||| | | |
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--b | 012345 01 ||| 0123 0123 0123
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--t i iiiiii ii ooo oooo oooo oooo
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--*-------------------------------------------------------------------------------------------------------------------
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--s 0 ------ -- 000 0000 0000 0000
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--* Loads ------------------------------------------------------------------------------------------------------------
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--s 1 000000 -- 100 0000 0000 0000 * ifetch
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--s 1 000001 -- 100 0000 0000 0000 * ifetch pre
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--s 1 001000 -- 100 0000 0000 0000 * load
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--* Stores -----------------------------------------------------------------------------------------------------------
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--s 1 100000 00 010 0000 0000 1000 * store
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--s 1 100000 01 010 0000 0000 0100 * store
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--s 1 100000 10 010 0000 0000 0010 * store
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--s 1 100000 11 010 0000 0000 0001 * store
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--* Larx/Stcx --------------------------------------------------------------------------------------------------------
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--s 1 001001 00 100 1000 0000 0000 * larx
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--s 1 001001 01 100 0100 0000 0000 * larx
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--s 1 001001 10 100 0010 0000 0000 * larx
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--s 1 001001 11 100 0001 0000 0000 * larx
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--* 1 001011 00 000 1000 0000 0000 * larx hint
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--* 1 001011 01 000 0100 0000 0000 * larx hint
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--* 1 001011 10 000 0010 0000 0000 * larx hint
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--* 1 001011 11 000 0001 0000 0000 * larx hint
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--s 1 101001 00 010 0000 1000 0000 * stcx
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--s 1 101001 01 010 0000 0100 0000 * stcx
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--s 1 101001 10 010 0000 0010 0000 * stcx
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--s 1 101001 11 010 0000 0001 0000 * stcx
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--* Specials ---------------------------------------------------------------------------------------------------------
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--s 1 101010 -- 011 0000 0000 0000 * lwsync
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--s 1 101011 -- 011 0000 0000 0000 * hwsync
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--s 1 111010 -- 011 0000 0000 0000 * tlbsync
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--s 1 111111 -- 011 0000 0000 0000 * dcbi
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--*-------------------------------------------------------------------------------------------------------------------
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--
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--tbl ReqDcd
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------------------------------------------------------------------------------------------------------------
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-- Load Request
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--
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-- push load to load queue
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-- head: oldest
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-- send: next to send
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-- data: next to receive data
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-- tail: next to write
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with req_in_load select
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ldq_tail_d <= inc(ldq_tail_q) when '1',
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@ -485,12 +588,13 @@ with req_in_load select
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ldq_write_sel <= req_in_load & ldq_tail_q;
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-- feedback
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gen_load_queue_fb: for i in 0 to 3 generate
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load_queue_fb(i).valid <= load_queue_q(i).valid and not ldq_valid_rst(i);
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load_queue_fb(i).sent <= (load_queue_q(i).sent or ldq_sent_set(i)) and not ldq_valid_rst(i);
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load_queue_fb(i).data <= (load_queue_q(i).data or ldq_data_set(i)) and not ldq_data_rst(i);
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load_queue_fb(i).dseq <= "000";
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load_queue_fb(i).dseq <= "000"; -- might use if interleaving data returns
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load_queue_fb(i).endian <= load_queue_q(i).endian;
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load_queue_fb(i).tag <= load_queue_q(i).tag;
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load_queue_fb(i).len <= load_queue_q(i).len;
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@ -505,7 +609,6 @@ gen_load_queue_fb: for i in 0 to 3 generate
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load_dep_d(i) <= gate_and(load_queue_set_dep(i), lhs_entry) or
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gate_and(not load_queue_set_dep(i) and not load_queue_rst_dep(i), load_dep_q(i));
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end generate;
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@ -536,8 +639,10 @@ with ldq_send_q select
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load_dep_q(2) when "10",
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load_dep_q(3) when others;
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-- send next available load to axi if ready and no stall
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axi_load_valid <= ld_req.valid and not ld_req.sent and not ld_req_stall;
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-- i=0 is always 64B; i=1 uses len
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axi_load_ra_hi <= ld_req.ra(64-C_M00_AXI_ADDR_WIDTH to 57);
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with ld_req.wimg(1) select
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axi_load_ra_lo <= "000000" when '0',
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@ -560,6 +665,7 @@ with ld_req.wimg(1) select
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axi_load_taken <= axi_load_valid and axi_load_ready;
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-- sent: set when req accepted by axi
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ldq_sent_set(0) <= axi_load_taken and eq(ldq_send_q, "00");
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ldq_sent_set(1) <= axi_load_taken and eq(ldq_send_q, "01");
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ldq_sent_set(2) <= axi_load_taken and eq(ldq_send_q, "10");
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@ -569,6 +675,7 @@ with axi_load_taken select
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ldq_send_d <= inc(ldq_send_q) when '1',
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ldq_send_q when others;
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-- data: set when last xfer received from axi
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ldq_data_set(0) <= axi_load_data_last and eq(ldq_data_q, "00");
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ldq_data_set(1) <= axi_load_data_last and eq(ldq_data_q, "01");
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ldq_data_set(2) <= axi_load_data_last and eq(ldq_data_q, "10");
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@ -591,6 +698,11 @@ with ldq_count_sel select
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ldq_oflow <= eq(ldq_count_q, "100") and eq(ldq_count_sel, "10");
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ldq_uflow <= eq(ldq_count_q, "000") and eq(ldq_count_sel, "01");
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------------------------------------------------------------------------------------------------------------
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-- Load Data Receive
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--
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-- head: next to send
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-- tail: next to write
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load_data_ready_d <= '1';
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axi_load_data_ready <= load_data_ready_q;
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@ -600,6 +712,7 @@ with axi_load_data_valid select
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rdataq_tail_q when others;
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-- axi_load_data_resp: check
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gen_load_load_data_queue: for i in 0 to 63 generate
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rdataq_write_sel(i) <= axi_load_data_valid and eq(rdataq_tail_q, i);
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@ -608,6 +721,20 @@ gen_load_load_data_queue: for i in 0 to 63 generate
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load_data_queue_q(i) when others;
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end generate;
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------------------------------------------------------------------------------------------------------------
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-- Load Data Send
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--
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-- each 16B xfer uses top 4 entries, swizzled for LE/BE if necessary
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-- a2l2 supports 2 main modes of return: alternating or consecutive; it also allows variable gaps between pairs of xfers for 64B
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-- crit qw can be returned first; only certain qw ordering is allowed (pairs must be consecutive):
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-- 0-1-2-3, 0-1-3-2
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-- 1-0-2-3, 1-0-3-2
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-- 2-3-0-1, 2-3-1-0
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-- 3-2-0-1, 3-2-1-0
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-- gaps can be filled with other xfers
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--
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-- use 'consecutive' mode and crit first
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-- ra(58:59) selects first rdataq to send; then use 0-1-2-3, 1-0-2-3, 2-3-0-1, 3-2-0-1 patterns
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with ldq_head_q select
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rld_data_valid <= load_queue_q(0).valid and load_queue_q(0).data when "00",
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@ -638,16 +765,127 @@ reload_d.ue <= '0';
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reload_d.ee <= '0';
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reload_d.dump <= '0';
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rld_ready <= axi_load_data_last or rld_data_valid;
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rld_ready <= rld_data_valid; -- fastpath needs to look at next entry if b2b: axi_load_data_last
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-- data: reset in d-1
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ldq_data_rst(0) <= start_rld_data and eq(ldq_head_q, "00");
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ldq_data_rst(1) <= start_rld_data and eq(ldq_head_q, "01");
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ldq_data_rst(2) <= start_rld_data and eq(ldq_head_q, "10");
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ldq_data_rst(3) <= start_rld_data and eq(ldq_head_q, "11");
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--tbl RldSeq
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--
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--n rld_seq_q rld_seq_d
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--n | |
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--n | rld_ready | reload_d.coming
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--n | | rld_crit_qw | |reload_d.valid
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--n | | | rld_single | ||reload_d.qw
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--n | | | | | ||| reload_d.crit
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--n | | | | | ||| | start_rld_data
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--n | | | | | ||| | |
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--n | | | | | ||| | | rld_seq_err
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--b | | | | | ||55| | |
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--b 01234 | 01 | 01234 ||89| | |
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--t iiiii i ii i ooooo ooooo o o
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--*-------------------------------------------------------------------------------------------------------------------
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--*-- Idle -----------------------------------------------------------------------------------------------------------
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--s 11111 0 -- - 11111 00000 0 0
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--s 11111 1 00 0 10000 10000 0 0
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--s 11111 1 01 0 10010 10000 0 0
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--s 11111 1 10 0 10100 10000 0 0
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--s 11111 1 11 0 10110 10000 0 0
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--s 11111 1 -- 1 00001 10000 0 0
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--*-- Single a -------------------------------------------------------------------------------------------------------
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--s 00001 - -- - 00010 01000 0 0 * d-3
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--*-- Single b -------------------------------------------------------------------------------------------------------
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--s 00010 - -- - 00011 00000 0 0 * d-2
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--*-- Single c -------------------------------------------------------------------------------------------------------
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--s 00011 - -- - 11111 00000 1 0 * d-1
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--*-- Crit 0a --------------------------------------------------------------------------------------------------------
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--s 10000 - -- - 10001 01001 0 0 * d-3
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--*-- Crit 0b --------------------------------------------------------------------------------------------------------
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--s 10001 - -- - 11010 11010 0 0 * d-2
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--*-- Crit 1a --------------------------------------------------------------------------------------------------------
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--s 10010 - -- - 10011 01011 0 0 * d-3
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--*-- Crit 1b --------------------------------------------------------------------------------------------------------
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--s 10011 - -- - 11010 11000 0 0 * d-2
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--*-- Crit 2a --------------------------------------------------------------------------------------------------------
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--s 10100 - -- - 10101 01101 0 0 * d-3
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--*-- Crit 2b --------------------------------------------------------------------------------------------------------
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--s 10101 - -- - 11000 11110 0 0 * d-2
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--*-- Crit 3a --------------------------------------------------------------------------------------------------------
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--s 10110 - -- - 10111 01111 0 0 * d-3
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--*-- Crit 3b --------------------------------------------------------------------------------------------------------
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--s 10111 - -- - 11000 11100 0 0 * d-2
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--*-- 2nd 01a --------------------------------------------------------------------------------------------------------
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--s 11000 - -- - 11001 01000 1 0 * d-1
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--*-- 2nd 01b --------------------------------------------------------------------------------------------------------
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--s 11001 - -- - 11111 01010 0 0 * d+0
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--*-- 2nd 23a --------------------------------------------------------------------------------------------------------
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--s 11010 - -- - 11011 01100 1 0 * d-1
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--*-- 2nd 23b --------------------------------------------------------------------------------------------------------
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--s 11011 - -- - 11111 01110 0 0 * d+0
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--*-- ERROR ----------------------------------------------------------------------------------------------------------
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--s 00000 - -- - 00000 00000 0 1
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--s 00100 - -- - 00100 00000 0 1
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--s 00101 - -- - 00101 00000 0 1
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--s 00110 - -- - 00110 00000 0 1
|
||||
--s 00111 - -- - 00111 00000 0 1
|
||||
--s 11100 - -- - 11100 00000 0 1
|
||||
--s 11101 - -- - 11101 00000 0 1
|
||||
--s 11110 - -- - 11110 00000 0 1
|
||||
--*-------------------------------------------------------------------------------------------------------------------
|
||||
--tbl RldSeq
|
||||
|
||||
--tbl RldDataSeq
|
||||
--
|
||||
--n rld_dseq_q rld_dseq_d
|
||||
--n | |
|
||||
--n | start_rld_data | rld_data_qw
|
||||
--n | | rld_crit_qw | | rld_complete
|
||||
--n | | | rld_single | | |
|
||||
--n | | | | | | |
|
||||
--n | | | | | | |
|
||||
--n | | | | | | |
|
||||
--n | | | | | | |
|
||||
--n | | | | | | | rld_dseq_err
|
||||
--b 0123 | 01 | 0123 01 | |
|
||||
--t iiii i ii i oooo oo o o
|
||||
--*-------------------------------------------------------------------------------------------------------------------
|
||||
--*-- Idle -----------------------------------------------------------------------------------------------------------
|
||||
--s 1111 0 -- - 1111 00 0 0 * zzz..zzz....
|
||||
--s 1111 1 00 0 0001 00 0 0 * 0-1-2-3
|
||||
--s 1111 1 01 0 0010 01 0 0 * 1-0-2-3
|
||||
--s 1111 1 10 0 0011 10 0 0 * 2-3-0-1
|
||||
--s 1111 1 11 0 0100 11 0 0 * 3-2-0-1
|
||||
--s 1111 1 -- 1 1111 00 1 0 * single xfer
|
||||
--*-- 2nd 01 ---------------------------------------------------------------------------------------------------------
|
||||
--s 0001 - -- - 1011 01 0 0 * d+0
|
||||
--*-- 2nd 10 ---------------------------------------------------------------------------------------------------------
|
||||
--s 0010 - -- - 1011 00 0 0 * d+0
|
||||
--*-- 2nd 23 ---------------------------------------------------------------------------------------------------------
|
||||
--s 0011 - -- - 1001 11 0 0 * d+0
|
||||
--*-- 2nd 32 ---------------------------------------------------------------------------------------------------------
|
||||
--s 0100 - -- - 1001 10 0 0 * d+0
|
||||
--*-- 3rd 01 ---------------------------------------------------------------------------------------------------------
|
||||
--s 1001 - -- - 1010 00 0 0 * d+1
|
||||
--*-- 4th 01 ---------------------------------------------------------------------------------------------------------
|
||||
--s 1010 - -- - 1111 01 1 0 * d+2
|
||||
--*-- 3rd 23 ---------------------------------------------------------------------------------------------------------
|
||||
--s 1011 - -- - 1100 10 0 0 * d+1
|
||||
--*-- 4th 23 ---------------------------------------------------------------------------------------------------------
|
||||
--s 1100 - -- - 1111 11 1 0 * d+2
|
||||
--*-- ERROR ----------------------------------------------------------------------------------------------------------
|
||||
--s 0000 - -- - 0000 00 0 1
|
||||
--s 0101 - -- - 0101 00 0 1
|
||||
--s 0110 - -- - 0110 00 0 1
|
||||
--s 0111 - -- - 0111 00 0 1
|
||||
--s 1000 - -- - 1000 00 0 1
|
||||
--s 1101 - -- - 1101 00 0 1
|
||||
--s 1110 - -- - 1110 00 0 1
|
||||
--*-------------------------------------------------------------------------------------------------------------------
|
||||
--tbl RldDataSeq
|
||||
|
||||
|
||||
load_complete <= rld_complete;
|
||||
|
||||
ldq_valid_rst(0) <= rld_complete and eq(ldq_head_q, "00");
|
||||
@ -657,6 +895,7 @@ ldq_valid_rst(3) <= rld_complete and eq(ldq_head_q, "11");
|
||||
|
||||
status_d.ld_pop <= rld_complete;
|
||||
|
||||
-- send reload
|
||||
an_ac_reld_data_coming <= reload_q.coming;
|
||||
an_ac_reld_data_vld <= reload_q.valid;
|
||||
an_ac_reld_core_tag <= reload_q.tag;
|
||||
@ -667,6 +906,7 @@ an_ac_reld_ecc_err_ue <= reload_q.ue;
|
||||
an_ac_reld_l1_dump <= reload_q.dump;
|
||||
an_ac_reld_data <= reload_q.data;
|
||||
|
||||
-- misc outputs
|
||||
an_ac_req_ld_pop <= status_q.ld_pop;
|
||||
an_ac_req_st_pop <= status_q.st_pop;
|
||||
an_ac_req_st_pop_thrd <= status_q.st_pop_thrd;
|
||||
@ -710,6 +950,16 @@ with rld_data_qw select
|
||||
rld_data_qw2 when "10",
|
||||
rld_data_qw3 when others;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- Store Request
|
||||
--
|
||||
-- push store to store queue
|
||||
-- head: oldest
|
||||
-- send: next to send
|
||||
-- data: next to send data
|
||||
-- tail: next to write
|
||||
--
|
||||
-- special stores are not sent to axi directly
|
||||
|
||||
store_pwr_d <= ac_an_st_data_pwr_token;
|
||||
|
||||
@ -717,6 +967,7 @@ with req_in_store select
|
||||
stq_tail_d <= inc(stq_tail_q) when '1',
|
||||
stq_tail_q when others;
|
||||
|
||||
-- feedback
|
||||
gen_store_queue_fb: for i in 0 to st_queue_size-1 generate
|
||||
|
||||
store_queue_fb(i).valid <= store_queue_q(i).valid and not stq_valid_rst(i);
|
||||
@ -740,6 +991,7 @@ gen_store_queue_fb: for i in 0 to st_queue_size-1 generate
|
||||
|
||||
end generate;
|
||||
|
||||
-- store queue
|
||||
gen_store_queue: for i in 0 to st_queue_size-1 generate
|
||||
|
||||
store_queue_d(i) <= req_in when b(req_in_store and eq(stq_tail_q, i)) else store_queue_fb(i);
|
||||
@ -751,17 +1003,25 @@ axi_store_id <= "0000";
|
||||
st_req_send <= mux_queue(store_queue_q, stq_send_q);
|
||||
st_dep <= mux_queue(store_dep_q, stq_send_q);
|
||||
|
||||
-- send next available store to axi if ready and no stall
|
||||
axi_store_valid <= st_req_send.valid and not st_req_send.spec and not st_req_send.sent;
|
||||
axi_store_mod <= "000000000000";
|
||||
|
||||
-- all 16B stores for now
|
||||
axi_store_ra <= st_req_send.ra(64-C_M00_AXI_ADDR_WIDTH to 59) & "0000";
|
||||
|
||||
-- assume even if using 32B interface, all stores are 16B or less
|
||||
-- so can mux lo/hi data/be
|
||||
-- it appears the mux'ing is not necessary; the data is dup'd hi/lo (so far at least);
|
||||
-- BUT, the BE need to be looked at across all bits (need to mux based on bit 59)
|
||||
|
||||
gen_store_len_16B: if st_data_32b_mode = 0 generate
|
||||
store_data_in <= ac_an_st_data;
|
||||
store_be_in <= ac_an_st_byte_enbl;
|
||||
end generate;
|
||||
gen_store_len_32B: if st_data_32b_mode = 1 generate
|
||||
-- a2 only gens 16B stores
|
||||
-- but need to still pick data/BE from proper bytes
|
||||
with req_in.ra(59) select
|
||||
store_data_in <= ac_an_st_data(128 to 255) when '1',
|
||||
ac_an_st_data(0 to 127) when others;
|
||||
@ -770,6 +1030,17 @@ gen_store_len_32B: if st_data_32b_mode = 1 generate
|
||||
ac_an_st_byte_enbl(0 to 15) when others;
|
||||
end generate;
|
||||
|
||||
-- special store handling
|
||||
--
|
||||
-- syncs:
|
||||
-- go through valid-send-data stages, then autocomplete
|
||||
-- hwsync:
|
||||
-- dep vs ldq (wait for older loads)
|
||||
-- stall self until head (wait for older stores)
|
||||
-- hold send pointer until complete (no younger store will be sent)
|
||||
--
|
||||
-- dcbi:
|
||||
-- like normal lwsync
|
||||
|
||||
store_spec_valid <= st_req_send.valid and st_req_send.spec;
|
||||
|
||||
@ -781,6 +1052,7 @@ lwsync_valid <= store_spec_valid and
|
||||
eq(st_req_send.ttype, TLBSYNC) or
|
||||
eq(st_req_send.ttype, DCBI));
|
||||
|
||||
-- store to axi, or spec
|
||||
store_taken <= ((axi_store_valid and axi_store_ready) or store_spec_valid) and not st_req_stall;
|
||||
|
||||
gen_stq_sent: for i in 0 to st_queue_size-1 generate
|
||||
@ -789,10 +1061,14 @@ end generate;
|
||||
|
||||
store_advance <= (store_taken and not hwsync_valid) or hwsync_complete;
|
||||
|
||||
-- inc to next entry
|
||||
with store_advance select
|
||||
stq_send_d <= inc(stq_send_q) when '1',
|
||||
stq_send_q when others;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- Store Data
|
||||
--
|
||||
|
||||
gen_store_data_queue: for i in 0 to st_queue_size-1 generate
|
||||
store_data_queue_d(i) <= (data => store_data_in, be => store_be_in) when b(req_in_store and eq(stq_tail_q, i)) else store_data_queue_q(i);
|
||||
@ -801,6 +1077,7 @@ end generate;
|
||||
st_req_data <= mux_queue(store_queue_q, stq_data_q);
|
||||
st_data <= mux_queue(store_data_queue_q, stq_data_q);
|
||||
|
||||
-- send next available store data to axi if ready
|
||||
axi_store_data_valid <= st_req_data.valid and st_req_data.data and not st_req_data.spec;
|
||||
|
||||
axi_store_data_taken <= axi_store_data_valid and axi_store_data_ready;
|
||||
@ -813,7 +1090,7 @@ st_data_xfer_d <= gate_and(st_data_xfer_inc, inc(st_data_xfer_q)) or
|
||||
gate_and(st_data_xfer_done, "000") or
|
||||
gate_and(st_data_xfer_hold, st_data_xfer_q);
|
||||
|
||||
|
||||
-- this can be done smarter if BE are examined; transfer 4/8/16 based on hi/lo be
|
||||
gen_store_data_16B: if not stores_32B generate
|
||||
|
||||
axi_store_len <= "0010000";
|
||||
@ -869,14 +1146,19 @@ gen_store_data_rst: for i in 0 to st_queue_size-1 generate
|
||||
stq_data_rst(i) <= st_data_xfer_done and eq(stq_data_q, i);
|
||||
end generate;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- Store Resp
|
||||
|
||||
store_rsp_ready_d <= '1';
|
||||
axi_store_rsp_ready <= store_rsp_ready_q;
|
||||
|
||||
-- special ops, auto-resp
|
||||
lwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and not st_req_data.hwsync;
|
||||
hwsync_complete <= st_req_data.valid and st_req_data.data and st_req_data.spec and st_req_data.hwsync and not st_req_stall;
|
||||
store_spec_complete <= lwsync_complete or hwsync_complete;
|
||||
|
||||
-- check resp, pop stq entry, return credit
|
||||
-- spec complete can occur concurrently with normal responses, so need to send delayed when necessary
|
||||
store_rsp_complete <= (axi_store_rsp_valid and eq(axi_store_rsp_resp, "00"));
|
||||
store_complete <= store_rsp_complete or store_spec_complete;
|
||||
|
||||
@ -889,8 +1171,8 @@ with store_pop_pending_sel select
|
||||
store_pop_pending_q when others;
|
||||
|
||||
status_d.st_pop <= store_complete or store_pop_delayed;
|
||||
status_d.st_pop_thrd <= "000";
|
||||
status_d.gather <= '0';
|
||||
status_d.st_pop_thrd <= "000"; -- ditc only
|
||||
status_d.gather <= '0'; -- if store was merged into existing stq entry, use this to return credit
|
||||
|
||||
with store_complete select
|
||||
stq_head_d <= inc(stq_head_q) when '1',
|
||||
@ -909,9 +1191,18 @@ end generate;
|
||||
stq_oflow <= eq(stq_count_q, st_queue_size) and req_in_store;
|
||||
stq_uflow <= eq(stq_count_q, 0) and store_complete;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Specials
|
||||
|
||||
|
||||
|
||||
-- larx/stcx
|
||||
-- larx bypasses L1 cache (i.e. data is not used if it hits in the L1)
|
||||
-- if larx hits L1, then core invalidates line automatically, therefore, the L2 does NOT need to send back-invalidate for larx
|
||||
-- larx address is specifed to the 64B cache line; reservation granule is the 64B cacheline
|
||||
-- core will not send any newer instructions following larx from the same thread to L2 until larx is completed
|
||||
-- L2 tracks one reservation per thread
|
||||
-- reservation is set before core receives reload data
|
||||
-- reservation_vld signal (used for fast wake-up from wait state) must be visible at the A2 before lwarx data is returned
|
||||
|
||||
stcx_store_t(0) <= stcx_t(0) or store_t(0);
|
||||
stcx_store_t(1) <= stcx_t(1) or store_t(1);
|
||||
@ -970,71 +1261,90 @@ status_d.stcx_pass(1) <= stcx_t(1) and resv_q(1).valid and resv_ra_hit(1);
|
||||
status_d.stcx_pass(2) <= stcx_t(2) and resv_q(2).valid and resv_ra_hit(2);
|
||||
status_d.stcx_pass(3) <= stcx_t(3) and resv_q(3).valid and resv_ra_hit(3);
|
||||
|
||||
-- sync ack
|
||||
|
||||
status_d.sync_ack(0) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "00");
|
||||
status_d.sync_ack(1) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "01");
|
||||
status_d.sync_ack(2) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "10");
|
||||
status_d.sync_ack(3) <= hwsync_complete and eq(st_req_data.ttype, HWSYNC) and eq(st_req_data.thread, "11");
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- Load/Store Ordering/Barriers
|
||||
|
||||
|
||||
req_p1_d <= req_in;
|
||||
|
||||
ld_p1_entry_d <= req_in_load & ldq_head_q;
|
||||
st_p1_entry_d <= req_in_store & stq_head_q;
|
||||
-- save entry loaded, for setting dependency
|
||||
ld_p1_entry_d <= req_in_load & ldq_tail_q;
|
||||
st_p1_entry_d <= req_in_store & stq_tail_q;
|
||||
|
||||
-- ld hit st
|
||||
gen_dep_addr_cmp_l: for i in 0 to st_queue_size-1 generate
|
||||
|
||||
req_p1_addr_hit_lhs(i) <= ld_p1_entry_q(0) and
|
||||
address_check(req_p1_q, store_queue_q(i)) and
|
||||
(not stq_valid_rst(i));
|
||||
req_p1_addr_hit_lhs(i) <= ld_p1_entry_q(0) and -- ld req
|
||||
address_check(req_p1_q, store_queue_q(i)) and -- stq hit
|
||||
(not stq_valid_rst(i)); -- stq not completing
|
||||
|
||||
req_p1_sync_lhs(i) <= ld_p1_entry_q(0) and
|
||||
store_queue_q(i).valid and
|
||||
store_queue_q(i).hwsync and
|
||||
(not stq_valid_rst(i));
|
||||
req_p1_sync_lhs(i) <= ld_p1_entry_q(0) and -- ld req
|
||||
store_queue_q(i).valid and -- entry valid
|
||||
store_queue_q(i).hwsync and -- hwsync
|
||||
(not stq_valid_rst(i)); -- stq not completing
|
||||
|
||||
req_p1_any_lhs(i) <= req_p1_addr_hit_lhs(i) or req_p1_sync_lhs(i);
|
||||
|
||||
end generate;
|
||||
|
||||
-- rotate to order
|
||||
lhs_ordered <= rotl(req_p1_any_lhs, ldq_head_q);
|
||||
|
||||
-- pick youngest
|
||||
lhs_ordered_youngest <= right_one(lhs_ordered);
|
||||
|
||||
-- rotate back to entry
|
||||
lhs_youngest <= rotr(lhs_ordered_youngest, ldq_head_q);
|
||||
|
||||
-- encode
|
||||
lhs_entry <= gate_and(or_reduce(lhs_youngest), '1' & enc(lhs_youngest));
|
||||
|
||||
-- st hit ld
|
||||
gen_dep_addr_cmp_s: for i in 0 to ld_queue_size-1 generate
|
||||
|
||||
req_p1_addr_hit_shl(i) <= st_p1_entry_q(0) and
|
||||
not req_p1_q.spec and
|
||||
address_check(req_p1_q, load_queue_q(i)) and
|
||||
(not ldq_valid_rst(i));
|
||||
req_p1_addr_hit_shl(i) <= st_p1_entry_q(0) and -- st req
|
||||
not req_p1_q.spec and -- not special op
|
||||
address_check(req_p1_q, load_queue_q(i)) and -- ldq hit
|
||||
(not ldq_valid_rst(i)); -- ldq not completing
|
||||
|
||||
req_p1_sync_shl(i) <= st_p1_entry_q(0) and
|
||||
load_queue_q(i).valid and
|
||||
req_p1_q.hwsync and
|
||||
(not ldq_valid_rst(i));
|
||||
req_p1_sync_shl(i) <= st_p1_entry_q(0) and -- st req
|
||||
load_queue_q(i).valid and -- entry valid
|
||||
req_p1_q.hwsync and -- hwsync
|
||||
(not ldq_valid_rst(i)); -- ldq not completing
|
||||
|
||||
req_p1_any_shl(i) <= req_p1_addr_hit_shl(i) or req_p1_sync_shl(i);
|
||||
|
||||
end generate;
|
||||
|
||||
-- rotate to order
|
||||
shl_ordered <= rotl(req_p1_any_shl, stq_head_q);
|
||||
|
||||
-- pick youngest
|
||||
shl_ordered_youngest <= right_one(shl_ordered);
|
||||
|
||||
-- rotate back to entry
|
||||
shl_youngest <= rotr(shl_ordered_youngest, stq_head_q);
|
||||
|
||||
-- encode
|
||||
shl_entry <= gate_and(or_reduce(shl_youngest), '1' & enc(shl_youngest));
|
||||
|
||||
-- addr_hit/barrier ops:
|
||||
-- 1. block current cycle valid if req_p1 is head this cycle
|
||||
-- 2. set dep of req_p1 in queue to youngest hit of other queue
|
||||
-- 3. block head to axi if entry.dep set
|
||||
-- 4. reset entry.dep(s) when corresponding entry completes
|
||||
|
||||
ld_req_stall <= lhs_entry(0) or ld_dep(0);
|
||||
st_req_stall <= shl_entry(0) or st_dep(0) or
|
||||
(st_req_data.hwsync and not eq(stq_send_q, stq_head_q));
|
||||
(st_req_data.hwsync and not eq(stq_send_q, stq_head_q)); -- hwsync waits until it is head
|
||||
|
||||
-- set: reqp1 cycle
|
||||
gen_ldq_set_dep: for i in 0 to ld_queue_size-1 generate
|
||||
load_queue_set_dep(i) <= ld_p1_entry_q(0) and eq(ld_p1_entry_q(1 to clog2(ld_queue_size)), std_logic_vector(to_unsigned(i, 2))) and lhs_entry(0);
|
||||
end generate;
|
||||
@ -1043,6 +1353,7 @@ gen_stq_set_dep: for i in 0 to st_queue_size-1 generate
|
||||
store_queue_set_dep(i) <= st_p1_entry_q(0) and eq(st_p1_entry_q(1 to clog2(st_queue_size)), std_logic_vector(to_unsigned(i, 2))) and shl_entry(0);
|
||||
end generate;
|
||||
|
||||
-- rst: comp cycle
|
||||
gen_ldq_rst_dep: for i in 0 to ld_queue_size-1 generate
|
||||
load_queue_rst_dep(i) <= store_complete and load_dep_q(i)(0) and eq(load_dep_q(i)(1 to clog2(st_queue_size)), stq_head_q);
|
||||
end generate;
|
||||
@ -1051,7 +1362,10 @@ gen_stq_rst_dep: for i in 0 to st_queue_size-1 generate
|
||||
store_queue_rst_dep(i) <= load_complete and store_dep_q(i)(0) and eq(store_dep_q(i)(1 to clog2(ld_queue_size)), ldq_head_q);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------------------
|
||||
-- AXI Interface
|
||||
|
||||
-- read req
|
||||
|
||||
axi_load_ready <= m00_axi_arready;
|
||||
m00_axi_arvalid <= axi_load_valid;
|
||||
@ -1059,24 +1373,26 @@ m00_axi_arid <= axi_load_id;
|
||||
m00_axi_araddr <= axi_load_ra;
|
||||
|
||||
with axi_load_len select
|
||||
m00_axi_arlen <= x"00" when "0000001",
|
||||
x"00" when "0000010",
|
||||
x"00" when "0000100",
|
||||
x"01" when "0001000",
|
||||
x"03" when "0010000",
|
||||
x"07" when "0100000",
|
||||
x"0F" when "1000000",
|
||||
m00_axi_arlen <= x"00" when "0000001", -- 1B
|
||||
x"00" when "0000010", -- 2B
|
||||
x"00" when "0000100", -- 4B
|
||||
x"01" when "0001000", -- 8B
|
||||
x"03" when "0010000", -- 16B
|
||||
x"07" when "0100000", -- 32B
|
||||
x"0F" when "1000000", -- 64B
|
||||
x"00" when others;
|
||||
|
||||
m00_axi_arsize <= "010";
|
||||
m00_axi_arburst <= "01";
|
||||
|
||||
-- axi_read_mod stuff
|
||||
m00_axi_arlock <= '0';
|
||||
m00_axi_arcache <= "0011";
|
||||
m00_axi_arprot <= "000";
|
||||
m00_axi_arqos <= x"0";
|
||||
m00_axi_aruser <= (others => '1');
|
||||
|
||||
-- read resp
|
||||
|
||||
m00_axi_rready <= axi_load_data_ready;
|
||||
axi_load_data_valid <= m00_axi_rvalid;
|
||||
@ -1085,6 +1401,7 @@ axi_load_data <= m00_axi_rdata;
|
||||
axi_load_data_resp <= m00_axi_rresp;
|
||||
axi_load_data_last <= m00_axi_rlast;
|
||||
|
||||
-- store req
|
||||
|
||||
axi_store_ready <= m00_axi_awready;
|
||||
m00_axi_awvalid <= axi_store_valid;
|
||||
@ -1092,19 +1409,21 @@ m00_axi_awid <= axi_store_id;
|
||||
m00_axi_awaddr <= axi_store_ra;
|
||||
|
||||
with axi_store_len select
|
||||
m00_axi_awlen <= x"03" when "0010000",
|
||||
x"07" when "0100000",
|
||||
m00_axi_awlen <= x"03" when "0010000", -- 16B
|
||||
x"07" when "0100000", -- 32B
|
||||
x"00" when others;
|
||||
|
||||
m00_axi_awsize <= "010";
|
||||
m00_axi_awburst <= "01";
|
||||
|
||||
-- mod stuff
|
||||
m00_axi_awlock <= '0';
|
||||
m00_axi_awcache <= "0010";
|
||||
m00_axi_awprot <= "000";
|
||||
m00_axi_awqos <= x"0";
|
||||
m00_axi_awuser <= (others => '1');
|
||||
|
||||
-- store data
|
||||
|
||||
axi_store_data_ready <= m00_axi_wready;
|
||||
m00_axi_wvalid <= axi_store_data_valid;
|
||||
@ -1113,12 +1432,15 @@ m00_axi_wstrb <= axi_store_data_be;
|
||||
m00_axi_wlast <= axi_store_data_last;
|
||||
m00_axi_wuser <= (others => '0');
|
||||
|
||||
-- store resp
|
||||
|
||||
m00_axi_bready <= axi_store_rsp_ready;
|
||||
axi_store_rsp_valid <= m00_axi_bvalid;
|
||||
axi_store_rsp_id <= m00_axi_bid;
|
||||
axi_store_rsp_resp <= m00_axi_bresp;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- Misc
|
||||
|
||||
err_d(0) <= ldq_uflow;
|
||||
err_d(1) <= ldq_oflow;
|
||||
@ -1127,7 +1449,10 @@ err_d(3) <= stq_oflow;
|
||||
|
||||
err <= err_q;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
-- move along.
|
||||
|
||||
--vtable ReqDcd
|
||||
req_in_load <=
|
||||
(req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5)) or
|
||||
(req_in.valid and not req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and req_in.ttype(5)) or
|
||||
@ -1178,7 +1503,9 @@ store_t(2) <=
|
||||
(req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and not req_in.thread(1));
|
||||
store_t(3) <=
|
||||
(req_in.valid and req_in.ttype(0) and not req_in.ttype(1) and not req_in.ttype(2) and not req_in.ttype(3) and not req_in.ttype(4) and not req_in.ttype(5) and req_in.thread(0) and req_in.thread(1));
|
||||
--vtable ReqDcd
|
||||
|
||||
--vtable RldSeq
|
||||
rld_seq_d(0) <=
|
||||
(rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and not rld_ready) or
|
||||
(rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and rld_seq_q(4) and rld_ready and not rld_crit_qw(0) and not rld_crit_qw(1) and not rld_single) or
|
||||
@ -1320,7 +1647,9 @@ rld_seq_err <=
|
||||
(rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and not rld_seq_q(4)) or
|
||||
(rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and not rld_seq_q(3) and rld_seq_q(4)) or
|
||||
(rld_seq_q(0) and rld_seq_q(1) and rld_seq_q(2) and rld_seq_q(3) and not rld_seq_q(4));
|
||||
--vtable RldSeq
|
||||
|
||||
--vtable RldDataSeq
|
||||
rld_dseq_d(0) <=
|
||||
(rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and not start_rld_data) or
|
||||
(rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and rld_dseq_q(3) and start_rld_data and rld_single) or
|
||||
@ -1400,6 +1729,7 @@ rld_dseq_err <=
|
||||
(rld_dseq_q(0) and not rld_dseq_q(1) and not rld_dseq_q(2) and not rld_dseq_q(3)) or
|
||||
(rld_dseq_q(0) and rld_dseq_q(1) and not rld_dseq_q(2) and rld_dseq_q(3)) or
|
||||
(rld_dseq_q(0) and rld_dseq_q(1) and rld_dseq_q(2) and not rld_dseq_q(3));
|
||||
--vtable RldDataSeq
|
||||
|
||||
|
||||
end a2l2_axi;
|
||||
|
||||
@ -7,7 +7,8 @@
|
||||
-- This README will be updated with additional information when OpenPOWER's
|
||||
-- license is available.
|
||||
|
||||
|
||||
-- a2i core plus a2l2_axi
|
||||
-- use this for the core-level wrapper
|
||||
|
||||
library ieee; use ieee.std_logic_1164.all;
|
||||
library ibm;
|
||||
@ -34,29 +35,29 @@ entity a2x_axi is
|
||||
|
||||
clk : in std_logic;
|
||||
clk2x : in std_logic;
|
||||
reset_n : in std_logic;
|
||||
thold : in std_logic;
|
||||
reset_n : in std_logic; -- active low
|
||||
thold : in std_logic; -- normally 0
|
||||
|
||||
core_id : in std_logic_vector(0 to 7);
|
||||
thread_stop : in std_logic_vector(0 to 3);
|
||||
thread_running : out std_logic_vector(0 to 3);
|
||||
core_id : in std_logic_vector(0 to 7); -- for multicore
|
||||
thread_stop : in std_logic_vector(0 to 3); -- control
|
||||
thread_running : out std_logic_vector(0 to 3); -- status
|
||||
|
||||
ext_mchk : in std_logic_vector(0 to 3);
|
||||
ext_checkstop : in std_logic;
|
||||
debug_stop : in std_logic;
|
||||
mchk : out std_logic_vector(0 to 3);
|
||||
recov_err : out std_logic_vector(0 to 2);
|
||||
checkstop : out std_logic_vector(0 to 2);
|
||||
a2l2_axi_err : out std_logic_vector(0 to 3);
|
||||
ext_mchk : in std_logic_vector(0 to 3); -- machine check
|
||||
ext_checkstop : in std_logic; -- checkstop
|
||||
debug_stop : in std_logic; -- thread stop
|
||||
mchk : out std_logic_vector(0 to 3); -- machine check
|
||||
recov_err : out std_logic_vector(0 to 2); -- recoverable
|
||||
checkstop : out std_logic_vector(0 to 2); -- checkstop
|
||||
a2l2_axi_err : out std_logic_vector(0 to 3); --
|
||||
|
||||
crit_interrupt : in std_logic_vector(0 to 3);
|
||||
ext_interrupt : in std_logic_vector(0 to 3);
|
||||
perf_interrupt : in std_logic_vector(0 to 3);
|
||||
crit_interrupt : in std_logic_vector(0 to 3); -- critical
|
||||
ext_interrupt : in std_logic_vector(0 to 3); -- external
|
||||
perf_interrupt : in std_logic_vector(0 to 3); -- performance
|
||||
|
||||
tb_update_enable : in std_logic;
|
||||
tb_update_pulse : in std_logic;
|
||||
tb_update_enable : in std_logic; -- normally 1
|
||||
tb_update_pulse : in std_logic; -- tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)
|
||||
|
||||
scom_sat_id : in std_logic_vector(0 to 3);
|
||||
scom_sat_id : in std_logic_vector(0 to 3); -- could split into acq and axi
|
||||
scom_dch_in : in std_logic;
|
||||
scom_cch_in : in std_logic;
|
||||
scom_dch_out : out std_logic;
|
||||
@ -113,11 +114,14 @@ end a2x_axi;
|
||||
|
||||
architecture a2x_axi of a2x_axi is
|
||||
|
||||
-- Common
|
||||
constant expand_type : integer := 1;
|
||||
constant threads : integer := 4;
|
||||
-- XU
|
||||
constant xu_real_data_add : integer := 42;
|
||||
constant st_data_32b_mode : integer := 1;
|
||||
constant ac_st_data_32b_mode : integer := 1;
|
||||
-- MM
|
||||
constant error_width : integer := 3;
|
||||
constant expand_tlb_type : integer := 2;
|
||||
constant extclass_width : integer := 2;
|
||||
@ -128,7 +132,7 @@ architecture a2x_axi of a2x_axi is
|
||||
constant real_addr_width : integer := 42;
|
||||
|
||||
signal a2_nclk : clk_logic;
|
||||
|
||||
|
||||
signal an_ac_sg_7 : std_logic;
|
||||
signal an_ac_back_inv : std_logic;
|
||||
signal an_ac_back_inv_addr : std_logic_vector(22 to 63);
|
||||
@ -304,6 +308,7 @@ scdis_b <= tidn;
|
||||
an_ac_ccenable_dc <= tiup;
|
||||
an_ac_scan_type_dc <= tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup & tiup;
|
||||
|
||||
-- most/all of this can be removed from all logic for fpga
|
||||
an_ac_func_scan_in <= (others => '0');
|
||||
an_ac_regf_scan_in <= (others => '0');
|
||||
an_ac_bcfg_scan_in <= (others => '0');
|
||||
@ -329,23 +334,25 @@ an_ac_scan_diag_dc <= '0';
|
||||
an_ac_psro_enable_dc <= (others => '0');
|
||||
an_ac_ccflush_dc <= '0';
|
||||
|
||||
-- misc
|
||||
an_ac_flh2l2_gate <= flh2l2_gate;
|
||||
an_ac_external_mchk <= ext_mchk;
|
||||
an_ac_checkstop <= ext_checkstop;
|
||||
an_ac_debug_stop <= debug_stop;
|
||||
an_ac_hang_pulse <= hang_pulse;
|
||||
thread_running <= ac_an_pm_thread_running;
|
||||
|
||||
-- errors
|
||||
mchk <= ac_an_machine_check;
|
||||
recov_err <= ac_an_recov_err;
|
||||
checkstop <= ac_an_local_checkstop;
|
||||
|
||||
-- scom
|
||||
an_ac_scom_sat_id <= scom_sat_id;
|
||||
node_scom_dch_in <= scom_dch_in;
|
||||
node_scom_cch_in <= scom_cch_in;
|
||||
scom_dch_out <= node_scom_dch_out;
|
||||
scom_cch_out <= node_scom_cch_out;
|
||||
|
||||
-- smp and other a2l2_axi stuff
|
||||
an_ac_user_defined <= (others => '0');
|
||||
an_ac_req_spare_ctrl_a1 <= (others => '0');
|
||||
|
||||
@ -459,8 +466,7 @@ acq: entity work.acq_soft(acq_soft)
|
||||
an_ac_dcfg_scan_in => an_ac_dcfg_scan_in,
|
||||
an_ac_debug_stop => an_ac_debug_stop,
|
||||
an_ac_external_mchk => an_ac_external_mchk,
|
||||
an_ac_fce_7 => an_ac_fce_7,
|
||||
|
||||
an_ac_fce_7 => an_ac_fce_7,
|
||||
an_ac_func_scan_in => an_ac_func_scan_in,
|
||||
an_ac_gptr_scan_in => an_ac_gptr_scan_in,
|
||||
an_ac_gsd_test_acmode_dc => an_ac_gsd_test_acmode_dc,
|
||||
@ -596,21 +602,21 @@ port map(
|
||||
m00_axi_awaddr => m00_axi_awaddr,
|
||||
m00_axi_awlen => m00_axi_awlen,
|
||||
m00_axi_awsize => m00_axi_awsize,
|
||||
m00_axi_awburst => m00_axi_awburst,
|
||||
m00_axi_awburst => m00_axi_awburst,
|
||||
m00_axi_awlock => m00_axi_awlock,
|
||||
m00_axi_awcache => m00_axi_awcache,
|
||||
m00_axi_awcache => m00_axi_awcache,
|
||||
m00_axi_awprot => m00_axi_awprot,
|
||||
m00_axi_awqos => m00_axi_awqos,
|
||||
m00_axi_awuser => m00_axi_awuser,
|
||||
m00_axi_awvalid => m00_axi_awvalid,
|
||||
m00_axi_awready => m00_axi_awready,
|
||||
m00_axi_awvalid => m00_axi_awvalid,
|
||||
m00_axi_awready => m00_axi_awready,
|
||||
m00_axi_wdata => m00_axi_wdata,
|
||||
m00_axi_wstrb => m00_axi_wstrb,
|
||||
m00_axi_wlast => m00_axi_wlast,
|
||||
m00_axi_wuser => m00_axi_wuser,
|
||||
m00_axi_wvalid => m00_axi_wvalid,
|
||||
m00_axi_wready => m00_axi_wready,
|
||||
m00_axi_bid => m00_axi_bid,
|
||||
m00_axi_bid => m00_axi_bid,
|
||||
m00_axi_bresp => m00_axi_bresp,
|
||||
m00_axi_buser => m00_axi_buser,
|
||||
m00_axi_bvalid => m00_axi_bvalid,
|
||||
@ -619,15 +625,15 @@ port map(
|
||||
m00_axi_araddr => m00_axi_araddr,
|
||||
m00_axi_arlen => m00_axi_arlen,
|
||||
m00_axi_arsize => m00_axi_arsize,
|
||||
m00_axi_arburst => m00_axi_arburst,
|
||||
m00_axi_arburst => m00_axi_arburst,
|
||||
m00_axi_arlock => m00_axi_arlock,
|
||||
m00_axi_arcache => m00_axi_arcache,
|
||||
m00_axi_arcache => m00_axi_arcache,
|
||||
m00_axi_arprot => m00_axi_arprot,
|
||||
m00_axi_arqos => m00_axi_arqos,
|
||||
m00_axi_aruser => m00_axi_aruser,
|
||||
m00_axi_arvalid => m00_axi_arvalid,
|
||||
m00_axi_arready => m00_axi_arready,
|
||||
m00_axi_rid => m00_axi_rid,
|
||||
m00_axi_arvalid => m00_axi_arvalid,
|
||||
m00_axi_arready => m00_axi_arready,
|
||||
m00_axi_rid => m00_axi_rid,
|
||||
m00_axi_rdata => m00_axi_rdata,
|
||||
m00_axi_rresp => m00_axi_rresp,
|
||||
m00_axi_rlast => m00_axi_rlast,
|
||||
|
||||
@ -21,7 +21,7 @@ constant c_st_queue_size : integer := 16;
|
||||
constant c_st_queue_bits : integer := 4;
|
||||
constant c_max_pointer : integer := 2;
|
||||
|
||||
|
||||
-- A2L2 ttypes
|
||||
constant IFETCH : std_logic_vector(0 to 5) := "000000";
|
||||
constant IFETCHPRE : std_logic_vector(0 to 5) := "000001";
|
||||
constant LOAD : std_logic_vector(0 to 5) := "001000";
|
||||
@ -125,10 +125,10 @@ end record;
|
||||
|
||||
type LOADQUEUE is array(0 to c_ld_queue_size-1) of A2L2REQUEST;
|
||||
type LOADDATAQUEUE is array(0 to 63) of std_logic_vector(0 to 31);
|
||||
type LOADQUEUEDEP is array(0 to c_ld_queue_size-1) of std_logic_vector(0 to c_st_queue_bits);
|
||||
type LOADQUEUEDEP is array(0 to c_ld_queue_size-1) of std_logic_vector(0 to c_st_queue_bits); -- 0: valid
|
||||
type STOREQUEUE is array(0 to c_st_queue_size-1) of A2L2REQUEST;
|
||||
type STOREDATAQUEUE is array(0 to c_st_queue_size-1) of A2L2STOREDATA;
|
||||
type STOREQUEUEDEP is array(0 to c_st_queue_size-1) of std_logic_vector(0 to c_ld_queue_bits);
|
||||
type STOREQUEUEDEP is array(0 to c_st_queue_size-1) of std_logic_vector(0 to c_ld_queue_bits); -- 0: valid
|
||||
type RESVARRAY is array(0 to 3) of A2L2RESV;
|
||||
|
||||
function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic;
|
||||
@ -145,6 +145,8 @@ end a2x_pkg;
|
||||
|
||||
package body a2x_pkg is
|
||||
|
||||
----------------------------------------------------------------------
|
||||
-- Functions
|
||||
|
||||
function or_reduce(slv: in std_logic_vector) return std_logic is
|
||||
variable res: std_logic := '0';
|
||||
@ -444,6 +446,9 @@ begin
|
||||
return res;
|
||||
end function;
|
||||
|
||||
-- compare requests to determine if they overlap
|
||||
-- ra : start addr, byte-aligned
|
||||
-- len: number of bytes
|
||||
function address_check(a: in A2L2REQUEST; b: in A2L2REQUEST) return std_logic is
|
||||
variable res: std_logic := '0';
|
||||
variable a_start, a_end, b_start, b_end : unsigned(0 to a.ra'length-1);
|
||||
@ -479,4 +484,3 @@ begin
|
||||
end;
|
||||
|
||||
end a2x_pkg;
|
||||
|
||||
|
||||
@ -20,7 +20,7 @@ library ieee,ibm,support,tri,work;
|
||||
library clib ;
|
||||
|
||||
entity fuq_alg_add is
|
||||
generic( expand_type : integer := 2 );
|
||||
generic( expand_type : integer := 2 ); -- 0 - ibm tech, 1 - other );
|
||||
port(
|
||||
|
||||
vdd : inout power_logic;
|
||||
@ -52,23 +52,23 @@ port(
|
||||
ex1_lvl2_shdcd008 :out std_ulogic ;
|
||||
ex1_lvl2_shdcd012 :out std_ulogic ;
|
||||
|
||||
ex1_lvl3_shdcd000 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd016 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd032 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd048 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd064 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd080 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd096 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd112 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd128 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd144 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd160 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd176 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd192 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd208 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd224 :out std_ulogic ;
|
||||
ex1_lvl3_shdcd240 :out std_ulogic
|
||||
);
|
||||
ex1_lvl3_shdcd000 :out std_ulogic ;-- 0000 +000
|
||||
ex1_lvl3_shdcd016 :out std_ulogic ;-- 0001 +016
|
||||
ex1_lvl3_shdcd032 :out std_ulogic ;-- 0010 +032
|
||||
ex1_lvl3_shdcd048 :out std_ulogic ;-- 0011 +048
|
||||
ex1_lvl3_shdcd064 :out std_ulogic ;-- 0100 +064
|
||||
ex1_lvl3_shdcd080 :out std_ulogic ;-- 0101 +080
|
||||
ex1_lvl3_shdcd096 :out std_ulogic ;-- 0110 +096
|
||||
ex1_lvl3_shdcd112 :out std_ulogic ;-- 0111 +112
|
||||
ex1_lvl3_shdcd128 :out std_ulogic ;-- 1000 +128
|
||||
ex1_lvl3_shdcd144 :out std_ulogic ;-- 1001 +144
|
||||
ex1_lvl3_shdcd160 :out std_ulogic ;-- 1010 +160
|
||||
ex1_lvl3_shdcd176 :out std_ulogic ;-- 1011
|
||||
ex1_lvl3_shdcd192 :out std_ulogic ;-- 1100 -064
|
||||
ex1_lvl3_shdcd208 :out std_ulogic ;-- 1101 -048
|
||||
ex1_lvl3_shdcd224 :out std_ulogic ;-- 1110 -032
|
||||
ex1_lvl3_shdcd240 :out std_ulogic -- 1111 -016
|
||||
); -------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
@ -212,38 +212,14 @@ architecture fuq_alg_add of fuq_alg_add is
|
||||
signal ex1_ack_s :std_ulogic_vector(1 to 13);
|
||||
signal ex1_ack_c :std_ulogic_vector(1 to 12);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------
|
||||
-- FOR simulation only : will not generate any logic
|
||||
-------------------------------------------------------
|
||||
|
||||
|
||||
ex1_bsha_sim_p(1 to 12) <= ex1_alg_sx(1 to 12) xor ex1_alg_cx(1 to 12);
|
||||
@ -267,152 +243,168 @@ begin
|
||||
ex1_bsha_sim_c( 2) <= ex1_bsha_sim_g( 2) or (ex1_bsha_sim_p( 2) and ex1_bsha_sim_c( 3) );
|
||||
|
||||
|
||||
--==##############################################################
|
||||
--# ex1 logic
|
||||
--==##############################################################
|
||||
-- for MADD operations SHA = (Ea+Ec+!Eb) + 1 -bias + 56
|
||||
-- (Ea+Ec+!Eb) + 57 +!bias + 1
|
||||
-- (Ea+Ec+!Eb) + 58 +!bias
|
||||
-- 0_0011_1111_1111 bias = 1023
|
||||
-- 1_1100_0000_0000 !bias
|
||||
-- 11_1010 58
|
||||
-- -----------------------
|
||||
-- 1_1100_0011_1010 ( !bias + 58 )
|
||||
--
|
||||
-- leading bit [1] is a sign bit, but the compressor creates bit 0.
|
||||
-- 13 bits should be enough to hold the entire result, therefore throw away bit 0.
|
||||
|
||||
|
||||
a32_inv: ex1_a_expo_b(2 to 13) <= not f_byp_alg_ex1_a_expo(2 to 13);
|
||||
c32_inv: ex1_c_expo_b(2 to 13) <= not f_byp_alg_ex1_c_expo(2 to 13);
|
||||
b32_inv: ex1_b_expo_b(1 to 13) <= not f_byp_alg_ex1_b_expo(1 to 13);
|
||||
|
||||
sx01: ex1_ack_s( 1) <= not( f_byp_alg_ex1_a_expo( 1) xor f_byp_alg_ex1_c_expo( 1) );
|
||||
sx02: ex1_ack_s( 2) <= not( f_byp_alg_ex1_a_expo( 2) xor f_byp_alg_ex1_c_expo( 2) );
|
||||
sx03: ex1_ack_s( 3) <= not( f_byp_alg_ex1_a_expo( 3) xor f_byp_alg_ex1_c_expo( 3) );
|
||||
sx04: ex1_ack_s( 4) <= ( f_byp_alg_ex1_a_expo( 4) xor f_byp_alg_ex1_c_expo( 4) );
|
||||
sx05: ex1_ack_s( 5) <= ( f_byp_alg_ex1_a_expo( 5) xor f_byp_alg_ex1_c_expo( 5) );
|
||||
sx06: ex1_ack_s( 6) <= ( f_byp_alg_ex1_a_expo( 6) xor f_byp_alg_ex1_c_expo( 6) );
|
||||
sx07: ex1_ack_s( 7) <= ( f_byp_alg_ex1_a_expo( 7) xor f_byp_alg_ex1_c_expo( 7) );
|
||||
sx08: ex1_ack_s( 8) <= not( f_byp_alg_ex1_a_expo( 8) xor f_byp_alg_ex1_c_expo( 8) );
|
||||
sx09: ex1_ack_s( 9) <= not( f_byp_alg_ex1_a_expo( 9) xor f_byp_alg_ex1_c_expo( 9) );
|
||||
sx10: ex1_ack_s(10) <= not( f_byp_alg_ex1_a_expo(10) xor f_byp_alg_ex1_c_expo(10) );
|
||||
sx11: ex1_ack_s(11) <= ( f_byp_alg_ex1_a_expo(11) xor f_byp_alg_ex1_c_expo(11) );
|
||||
sx12: ex1_ack_s(12) <= not( f_byp_alg_ex1_a_expo(12) xor f_byp_alg_ex1_c_expo(12) );
|
||||
sx13: ex1_ack_s(13) <= ( f_byp_alg_ex1_a_expo(13) xor f_byp_alg_ex1_c_expo(13) );
|
||||
sx01: ex1_ack_s( 1) <= not( f_byp_alg_ex1_a_expo( 1) xor f_byp_alg_ex1_c_expo( 1) ); --K[ 1]==1
|
||||
sx02: ex1_ack_s( 2) <= not( f_byp_alg_ex1_a_expo( 2) xor f_byp_alg_ex1_c_expo( 2) ); --K[ 2]==1
|
||||
sx03: ex1_ack_s( 3) <= not( f_byp_alg_ex1_a_expo( 3) xor f_byp_alg_ex1_c_expo( 3) ); --K[ 3]==1
|
||||
sx04: ex1_ack_s( 4) <= ( f_byp_alg_ex1_a_expo( 4) xor f_byp_alg_ex1_c_expo( 4) ); --K[ 4]==0
|
||||
sx05: ex1_ack_s( 5) <= ( f_byp_alg_ex1_a_expo( 5) xor f_byp_alg_ex1_c_expo( 5) ); --K[ 5]==0
|
||||
sx06: ex1_ack_s( 6) <= ( f_byp_alg_ex1_a_expo( 6) xor f_byp_alg_ex1_c_expo( 6) ); --K[ 6]==0
|
||||
sx07: ex1_ack_s( 7) <= ( f_byp_alg_ex1_a_expo( 7) xor f_byp_alg_ex1_c_expo( 7) ); --K[ 7]==0
|
||||
sx08: ex1_ack_s( 8) <= not( f_byp_alg_ex1_a_expo( 8) xor f_byp_alg_ex1_c_expo( 8) ); --K[ 8]==1
|
||||
sx09: ex1_ack_s( 9) <= not( f_byp_alg_ex1_a_expo( 9) xor f_byp_alg_ex1_c_expo( 9) ); --K[ 9]==1 1
|
||||
sx10: ex1_ack_s(10) <= not( f_byp_alg_ex1_a_expo(10) xor f_byp_alg_ex1_c_expo(10) ); --K[10]==1 1
|
||||
sx11: ex1_ack_s(11) <= ( f_byp_alg_ex1_a_expo(11) xor f_byp_alg_ex1_c_expo(11) ); --K[11]==0
|
||||
sx12: ex1_ack_s(12) <= not( f_byp_alg_ex1_a_expo(12) xor f_byp_alg_ex1_c_expo(12) ); --K[12]==1
|
||||
sx13: ex1_ack_s(13) <= ( f_byp_alg_ex1_a_expo(13) xor f_byp_alg_ex1_c_expo(13) ); --K[13]==0
|
||||
|
||||
|
||||
|
||||
cx01: ex1_ack_c( 1) <= not( ex1_a_expo_b( 2) and ex1_c_expo_b( 2) );
|
||||
cx02: ex1_ack_c( 2) <= not( ex1_a_expo_b( 3) and ex1_c_expo_b( 3) );
|
||||
cx03: ex1_ack_c( 3) <= not( ex1_a_expo_b( 4) or ex1_c_expo_b( 4) );
|
||||
cx04: ex1_ack_c( 4) <= not( ex1_a_expo_b( 5) or ex1_c_expo_b( 5) );
|
||||
cx05: ex1_ack_c( 5) <= not( ex1_a_expo_b( 6) or ex1_c_expo_b( 6) );
|
||||
cx06: ex1_ack_c( 6) <= not( ex1_a_expo_b( 7) or ex1_c_expo_b( 7) );
|
||||
cx07: ex1_ack_c( 7) <= not( ex1_a_expo_b( 8) and ex1_c_expo_b( 8) );
|
||||
cx08: ex1_ack_c( 8) <= not( ex1_a_expo_b( 9) and ex1_c_expo_b( 9) );
|
||||
cx09: ex1_ack_c( 9) <= not( ex1_a_expo_b(10) and ex1_c_expo_b(10) );
|
||||
cx10: ex1_ack_c(10) <= not( ex1_a_expo_b(11) or ex1_c_expo_b(11) );
|
||||
cx11: ex1_ack_c(11) <= not( ex1_a_expo_b(12) and ex1_c_expo_b(12) );
|
||||
cx12: ex1_ack_c(12) <= not( ex1_a_expo_b(13) or ex1_c_expo_b(13) );
|
||||
-- cx00: ex1_ack_c( 0) <= not( ex1_a_expo_b( 1) and ex1_c_expo_b( 1) ); --K[ 1]==1 +or
|
||||
cx01: ex1_ack_c( 1) <= not( ex1_a_expo_b( 2) and ex1_c_expo_b( 2) ); --K[ 2]==1 +or
|
||||
cx02: ex1_ack_c( 2) <= not( ex1_a_expo_b( 3) and ex1_c_expo_b( 3) ); --K[ 3]==1 +or
|
||||
cx03: ex1_ack_c( 3) <= not( ex1_a_expo_b( 4) or ex1_c_expo_b( 4) ); --K[ 4]==0 +and
|
||||
cx04: ex1_ack_c( 4) <= not( ex1_a_expo_b( 5) or ex1_c_expo_b( 5) ); --K[ 5]==0 +and
|
||||
cx05: ex1_ack_c( 5) <= not( ex1_a_expo_b( 6) or ex1_c_expo_b( 6) ); --K[ 6]==0 +and
|
||||
cx06: ex1_ack_c( 6) <= not( ex1_a_expo_b( 7) or ex1_c_expo_b( 7) ); --K[ 7]==0 +and
|
||||
cx07: ex1_ack_c( 7) <= not( ex1_a_expo_b( 8) and ex1_c_expo_b( 8) ); --K[ 8]==1 +or
|
||||
cx08: ex1_ack_c( 8) <= not( ex1_a_expo_b( 9) and ex1_c_expo_b( 9) ); --K[ 9]==1 +or
|
||||
cx09: ex1_ack_c( 9) <= not( ex1_a_expo_b(10) and ex1_c_expo_b(10) ); --K[10]==1 +or
|
||||
cx10: ex1_ack_c(10) <= not( ex1_a_expo_b(11) or ex1_c_expo_b(11) ); --K[11]==0 +and
|
||||
cx11: ex1_ack_c(11) <= not( ex1_a_expo_b(12) and ex1_c_expo_b(12) ); --K[12]==1 +or
|
||||
cx12: ex1_ack_c(12) <= not( ex1_a_expo_b(13) or ex1_c_expo_b(13) ); --K[13]==0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
sha32_01: entity clib.c_prism_csa32 port map(
|
||||
sha32_01: entity clib.c_prism_csa32 port map( -- fuq_csa32s_h2 MLT32_X1_A12TH
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(1) ,
|
||||
b => ex1_ack_s(1) ,
|
||||
c => ex1_ack_c(1) ,
|
||||
sum => ex1_alg_sx(1) ,
|
||||
car => ex1_alg_cx(0) );
|
||||
a => ex1_b_expo_b(1) ,--i--
|
||||
b => ex1_ack_s(1) ,--i--
|
||||
c => ex1_ack_c(1) ,--i--
|
||||
sum => ex1_alg_sx(1) ,--o--
|
||||
car => ex1_alg_cx(0) );--o--
|
||||
sha32_02: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(2) ,
|
||||
b => ex1_ack_s(2) ,
|
||||
c => ex1_ack_c(2) ,
|
||||
sum => ex1_alg_sx(2) ,
|
||||
car => ex1_alg_cx(1) );
|
||||
a => ex1_b_expo_b(2) ,--i--
|
||||
b => ex1_ack_s(2) ,--i--
|
||||
c => ex1_ack_c(2) ,--i--
|
||||
sum => ex1_alg_sx(2) ,--o--
|
||||
car => ex1_alg_cx(1) );--o--
|
||||
sha32_03: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(3) ,
|
||||
b => ex1_ack_s(3) ,
|
||||
c => ex1_ack_c(3) ,
|
||||
sum => ex1_alg_sx(3) ,
|
||||
car => ex1_alg_cx(2) );
|
||||
a => ex1_b_expo_b(3) ,--i--
|
||||
b => ex1_ack_s(3) ,--i--
|
||||
c => ex1_ack_c(3) ,--i--
|
||||
sum => ex1_alg_sx(3) ,--o--
|
||||
car => ex1_alg_cx(2) );--o--
|
||||
sha32_04: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(4) ,
|
||||
b => ex1_ack_s(4) ,
|
||||
c => ex1_ack_c(4) ,
|
||||
sum => ex1_alg_sx(4) ,
|
||||
car => ex1_alg_cx(3) );
|
||||
a => ex1_b_expo_b(4) ,--i--
|
||||
b => ex1_ack_s(4) ,--i--
|
||||
c => ex1_ack_c(4) ,--i--
|
||||
sum => ex1_alg_sx(4) ,--o--
|
||||
car => ex1_alg_cx(3) );--o--
|
||||
sha32_05: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(5) ,
|
||||
b => ex1_ack_s(5) ,
|
||||
c => ex1_ack_c(5) ,
|
||||
sum => ex1_alg_sx(5) ,
|
||||
car => ex1_alg_cx(4) );
|
||||
a => ex1_b_expo_b(5) ,--i--
|
||||
b => ex1_ack_s(5) ,--i--
|
||||
c => ex1_ack_c(5) ,--i--
|
||||
sum => ex1_alg_sx(5) ,--o--
|
||||
car => ex1_alg_cx(4) );--o--
|
||||
sha32_06: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(6) ,
|
||||
b => ex1_ack_s(6) ,
|
||||
c => ex1_ack_c(6) ,
|
||||
sum => ex1_alg_sx(6) ,
|
||||
car => ex1_alg_cx(5) );
|
||||
a => ex1_b_expo_b(6) ,--i--
|
||||
b => ex1_ack_s(6) ,--i--
|
||||
c => ex1_ack_c(6) ,--i--
|
||||
sum => ex1_alg_sx(6) ,--o--
|
||||
car => ex1_alg_cx(5) );--o--
|
||||
sha32_07: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(7) ,
|
||||
b => ex1_ack_s(7) ,
|
||||
c => ex1_ack_c(7) ,
|
||||
sum => ex1_alg_sx(7) ,
|
||||
car => ex1_alg_cx(6) );
|
||||
a => ex1_b_expo_b(7) ,--i--
|
||||
b => ex1_ack_s(7) ,--i--
|
||||
c => ex1_ack_c(7) ,--i--
|
||||
sum => ex1_alg_sx(7) ,--o--
|
||||
car => ex1_alg_cx(6) );--o--
|
||||
sha32_08: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(8) ,
|
||||
b => ex1_ack_s(8) ,
|
||||
c => ex1_ack_c(8) ,
|
||||
sum => ex1_alg_sx(8) ,
|
||||
car => ex1_alg_cx(7) );
|
||||
a => ex1_b_expo_b(8) ,--i--
|
||||
b => ex1_ack_s(8) ,--i--
|
||||
c => ex1_ack_c(8) ,--i--
|
||||
sum => ex1_alg_sx(8) ,--o--
|
||||
car => ex1_alg_cx(7) );--o--
|
||||
sha32_09: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(9) ,
|
||||
b => ex1_ack_s(9) ,
|
||||
c => ex1_ack_c(9) ,
|
||||
sum => ex1_alg_sx(9) ,
|
||||
car => ex1_alg_cx(8) );
|
||||
a => ex1_b_expo_b(9) ,--i--
|
||||
b => ex1_ack_s(9) ,--i--
|
||||
c => ex1_ack_c(9) ,--i--
|
||||
sum => ex1_alg_sx(9) ,--o--
|
||||
car => ex1_alg_cx(8) );--o--
|
||||
sha32_10: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(10) ,
|
||||
b => ex1_ack_s(10) ,
|
||||
c => ex1_ack_c(10) ,
|
||||
sum => ex1_alg_sx(10) ,
|
||||
car => ex1_alg_cx(9) );
|
||||
a => ex1_b_expo_b(10) ,--i--
|
||||
b => ex1_ack_s(10) ,--i--
|
||||
c => ex1_ack_c(10) ,--i--
|
||||
sum => ex1_alg_sx(10) ,--o--
|
||||
car => ex1_alg_cx(9) );--o--
|
||||
sha32_11: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(11) ,
|
||||
b => ex1_ack_s(11) ,
|
||||
c => ex1_ack_c(11) ,
|
||||
sum => ex1_alg_sx(11) ,
|
||||
car => ex1_alg_cx(10) );
|
||||
a => ex1_b_expo_b(11) ,--i--
|
||||
b => ex1_ack_s(11) ,--i--
|
||||
c => ex1_ack_c(11) ,--i--
|
||||
sum => ex1_alg_sx(11) ,--o--
|
||||
car => ex1_alg_cx(10) );--o--
|
||||
sha32_12: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(12) ,
|
||||
b => ex1_ack_s(12) ,
|
||||
c => ex1_ack_c(12) ,
|
||||
sum => ex1_alg_sx(12) ,
|
||||
car => ex1_alg_cx(11) );
|
||||
a => ex1_b_expo_b(12) ,--i--
|
||||
b => ex1_ack_s(12) ,--i--
|
||||
c => ex1_ack_c(12) ,--i--
|
||||
sum => ex1_alg_sx(12) ,--o--
|
||||
car => ex1_alg_cx(11) );--o--
|
||||
sha32_13: entity clib.c_prism_csa32 port map(
|
||||
vd => vdd,
|
||||
gd => gnd,
|
||||
a => ex1_b_expo_b(13) ,
|
||||
b => ex1_ack_s(13) ,
|
||||
c => tidn ,
|
||||
sum => ex1_alg_sx(13) ,
|
||||
car => ex1_alg_cx(12) );
|
||||
a => ex1_b_expo_b(13) ,--i--
|
||||
b => ex1_ack_s(13) ,--i--
|
||||
c => tidn ,--i--
|
||||
sum => ex1_alg_sx(13) ,--o--
|
||||
car => ex1_alg_cx(12) );--o--
|
||||
|
||||
|
||||
-- now finish the add (for sha==0 means shift 0)
|
||||
|
||||
p1_01: ex1_alg_add_p( 1) <= ex1_alg_sx( 1) xor ex1_alg_cx( 1);
|
||||
p1_02: ex1_alg_add_p( 2) <= ex1_alg_sx( 2) xor ex1_alg_cx( 2);
|
||||
@ -451,37 +443,46 @@ t1_09: ex1_alg_add_t_b( 9) <= not( ex1_alg_sx( 9) or ex1_alg_cx( 9) );
|
||||
t1_10: ex1_alg_add_t_b(10) <= not( ex1_alg_sx(10) or ex1_alg_cx(10) );
|
||||
t1_11: ex1_alg_add_t_b(11) <= not( ex1_alg_sx(11) or ex1_alg_cx(11) );
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- 12:13 are a decode group (12,13) are known before adder starts )
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
g2_12: ex1_g02_12 <= not ex1_alg_add_g_b(12);
|
||||
g2_12b: ex1_g02_12_b <= not ex1_g02_12 ;
|
||||
g2_12: ex1_g02_12 <= not ex1_alg_add_g_b(12); -- main carry chain
|
||||
g2_12b: ex1_g02_12_b <= not ex1_g02_12 ; -- main carry chain
|
||||
|
||||
res_13b: ex1_bsha_13_b <= not ex1_alg_sx(13);
|
||||
res_13: ex1_bsha_13 <= not ex1_bsha_13_b ;
|
||||
res_13b: ex1_bsha_13_b <= not ex1_alg_sx(13); -- direct from compressor
|
||||
res_13: ex1_bsha_13 <= not ex1_bsha_13_b ; -- to decoder 0/1/2/3
|
||||
res_12b: ex1_bsha_12_b <= not ex1_alg_add_p(12);
|
||||
res_12: ex1_bsha_12 <= not ex1_bsha_12_b ;
|
||||
res_12: ex1_bsha_12 <= not ex1_bsha_12_b ; -- to decoder 0/1/2/3
|
||||
|
||||
ci11nb: ex1_lv2_ci11n_en_b <= not( ex1_sel_special_b and ex1_g02_12_b );
|
||||
ci11pb: ex1_lv2_ci11p_en_b <= not( ex1_sel_special_b and ex1_g02_12 );
|
||||
ci11n: ex1_lv2_ci11n_en <= not( ex1_lv2_ci11n_en_b );
|
||||
ci11p: ex1_lv2_ci11p_en <= not( ex1_lv2_ci11p_en_b );
|
||||
ci11n: ex1_lv2_ci11n_en <= not( ex1_lv2_ci11n_en_b ); -- to decoder 0/4/8/12
|
||||
ci11p: ex1_lv2_ci11p_en <= not( ex1_lv2_ci11p_en_b ); -- to decoder 0/4/8/12
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- 10:11 are a decode group, do not compute adder result (send signal direct to decode)
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
g2_10: ex1_g02_10 <= not( ex1_alg_add_g_b(10) and (ex1_alg_add_t_b(10) or ex1_alg_add_g_b(11)) );
|
||||
t2_10: ex1_t02_10 <= not( ex1_alg_add_t_b(10) or ex1_alg_add_t_b(11) );
|
||||
g4_10: ex1_g04_10_b <= not( ex1_g02_10 or (ex1_t02_10 and ex1_g02_12 ) );
|
||||
g2_10: ex1_g02_10 <= not( ex1_alg_add_g_b(10) and (ex1_alg_add_t_b(10) or ex1_alg_add_g_b(11)) );--main carry chain
|
||||
t2_10: ex1_t02_10 <= not( ex1_alg_add_t_b(10) or ex1_alg_add_t_b(11) );--main carry chain
|
||||
g4_10: ex1_g04_10_b <= not( ex1_g02_10 or (ex1_t02_10 and ex1_g02_12 ) );--main carry chain
|
||||
|
||||
g11x: ex1_lv2_g11_x <= not( ex1_alg_add_g_b(11) );
|
||||
g11b: ex1_lv2_g11_b <= not( ex1_lv2_g11_x );
|
||||
g11: ex1_lv2_g11 <= not( ex1_lv2_g11_b );
|
||||
g11: ex1_lv2_g11 <= not( ex1_lv2_g11_b ); -- to decoder 0/4/8/12
|
||||
k11x: ex1_lv2_k11_b <= not( ex1_alg_add_t_b(11) );
|
||||
k11: ex1_lv2_k11 <= not( ex1_lv2_k11_b );
|
||||
k11: ex1_lv2_k11 <= not( ex1_lv2_k11_b ); -- to decoder 0/4/8/12
|
||||
p11b: ex1_lv2_p11_b <= not( ex1_alg_add_p(11) );
|
||||
p11: ex1_lv2_p11 <= not( ex1_lv2_p11_b );
|
||||
p10b: ex1_lv2_p10_b <= not( ex1_alg_add_p(10) );
|
||||
p10: ex1_lv2_p10 <= not( ex1_lv2_p10_b );
|
||||
p11: ex1_lv2_p11 <= not( ex1_lv2_p11_b ); -- to decoder 0/4/8/12
|
||||
p10b: ex1_lv2_p10_b <= not( ex1_alg_add_p(10) ); -- to decoder 0/4/8/12
|
||||
p10: ex1_lv2_p10 <= not( ex1_lv2_p10_b ); -- to decoder 0/4/8/12
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- 6:9 are a decode group, not used until next cycle: (get add result then decode)
|
||||
------------------------------------------------------------------------
|
||||
|
||||
g4x_10: ex1_g04_10 <= not ex1_g04_10_b ;
|
||||
g4x_10: ex1_g04_10 <= not ex1_g04_10_b ; -- use this buffered of version to finish the local carry chain
|
||||
|
||||
g2_06: ex1_g02_6 <= not( ex1_alg_add_g_b(6) and (ex1_alg_add_t_b(6) or ex1_alg_add_g_b(7)) );
|
||||
g2_07: ex1_g02_7 <= not( ex1_alg_add_g_b(7) and (ex1_alg_add_t_b(7) or ex1_alg_add_g_b(8)) );
|
||||
@ -501,7 +502,7 @@ t4_07b: ex1_t04_7_b <= not( ex1_t02_7 and ex1_t
|
||||
t4_08b: ex1_t04_8_b <= not( ex1_t02_8 );
|
||||
t4_09b: ex1_t04_9_b <= not( ex1_t02_9 );
|
||||
|
||||
g8_06: ex1_g08_6 <= not( ex1_g04_6_b and (ex1_t04_6_b or ex1_g04_10_b ) );
|
||||
g8_06: ex1_g08_6 <= not( ex1_g04_6_b and (ex1_t04_6_b or ex1_g04_10_b ) );--main carry chain
|
||||
g4_07: ex1_g04_7 <= not( ex1_g04_7_b );
|
||||
g4_08: ex1_g04_8 <= not( ex1_g04_8_b );
|
||||
g4_09: ex1_g04_9 <= not( ex1_g04_9_b );
|
||||
@ -514,10 +515,10 @@ c08: ex1_alg_add_c_b(8) <= not( ex1_g04_8 or (ex1_t04_8 and ex1_g04_10) );
|
||||
c09: ex1_alg_add_c_b(9) <= not( ex1_g04_9 or (ex1_t04_9 and ex1_g04_10) );
|
||||
c10: ex1_alg_add_c_b(10) <= not( ex1_g04_10 );
|
||||
|
||||
res_6: ex1_bsha_6 <= not( ex1_alg_add_p(6) xor ex1_alg_add_c_b(7) );
|
||||
res_7: ex1_bsha_7 <= not( ex1_alg_add_p(7) xor ex1_alg_add_c_b(8) );
|
||||
res_8: ex1_bsha_8 <= not( ex1_alg_add_p(8) xor ex1_alg_add_c_b(9) );
|
||||
res_9: ex1_bsha_9 <= not( ex1_alg_add_p(9) xor ex1_alg_add_c_b(10) );
|
||||
res_6: ex1_bsha_6 <= not( ex1_alg_add_p(6) xor ex1_alg_add_c_b(7) );--to multiple of 16 decoder
|
||||
res_7: ex1_bsha_7 <= not( ex1_alg_add_p(7) xor ex1_alg_add_c_b(8) );--to multiple of 16 decoder
|
||||
res_8: ex1_bsha_8 <= not( ex1_alg_add_p(8) xor ex1_alg_add_c_b(9) );--to multiple of 16 decoder
|
||||
res_9: ex1_bsha_9 <= not( ex1_alg_add_p(9) xor ex1_alg_add_c_b(10) );--to multiple of 16 decoder
|
||||
|
||||
|
||||
res_6i: ex1_bsha_6_i <= not ex1_bsha_6 ;
|
||||
@ -530,31 +531,40 @@ res_7o: ex1_bsha_7_o <= not ex1_bsha_7_i ;
|
||||
res_8o: ex1_bsha_8_o <= not ex1_bsha_8_i ;
|
||||
res_9o: ex1_bsha_9_o <= not ex1_bsha_9_i ;
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
-- Just need to know if 2/3/4/5 != 0000 for unf, produce that signal directly
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
g2_02: ex1_g02_2 <= not( ex1_alg_add_g_b(2) and (ex1_alg_add_t_b(2) or ex1_alg_add_g_b(3)) );
|
||||
g2_04: ex1_g02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_g_b(5)) );
|
||||
g2_02: ex1_g02_2 <= not( ex1_alg_add_g_b(2) and (ex1_alg_add_t_b(2) or ex1_alg_add_g_b(3)) ); --for carry select
|
||||
g2_04: ex1_g02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_g_b(5)) ); --for carry select
|
||||
|
||||
t2_02: ex1_t02_2 <= not( (ex1_alg_add_t_b(2) or ex1_alg_add_t_b(3)) );
|
||||
t2_04: ex1_t02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_t_b(5)) );
|
||||
t2_02: ex1_t02_2 <= not( (ex1_alg_add_t_b(2) or ex1_alg_add_t_b(3)) ); --for carry select
|
||||
t2_04: ex1_t02_4 <= not( ex1_alg_add_g_b(4) and (ex1_alg_add_t_b(4) or ex1_alg_add_t_b(5)) ); --for carry select
|
||||
|
||||
g4_02: ex1_g04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_g02_4 ) );
|
||||
t4_02: ex1_t04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_t02_4 ) );
|
||||
g4_02: ex1_g04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_g02_4 ) ); --for carry select
|
||||
t4_02: ex1_t04_2_b <= not( ex1_g02_2 or (ex1_t02_2 and ex1_t02_4 ) ); --for carry select
|
||||
|
||||
|
||||
ones23: ex1_ones_2t3_b <= not( ex1_alg_add_p(2) and ex1_alg_add_p(3) );
|
||||
ones45: ex1_ones_4t5_b <= not( ex1_alg_add_p(4) and ex1_alg_add_p(5) );
|
||||
ones25: ex1_ones_2t5 <= not( ex1_ones_2t3_b or ex1_ones_4t5_b );
|
||||
ones23: ex1_ones_2t3_b <= not( ex1_alg_add_p(2) and ex1_alg_add_p(3) );-- for unf calculation
|
||||
ones45: ex1_ones_4t5_b <= not( ex1_alg_add_p(4) and ex1_alg_add_p(5) );-- for unf calculation
|
||||
ones25: ex1_ones_2t5 <= not( ex1_ones_2t3_b or ex1_ones_4t5_b );-- for unf calculation
|
||||
ones25_b: ex1_ones_2t5_b <= not( ex1_ones_2t5 );
|
||||
|
||||
z2b: ex1_zero_2_b <= not( ex1_alg_add_p(2) xor ex1_alg_add_t_b(3) );
|
||||
z3b: ex1_zero_3_b <= not( ex1_alg_add_p(3) xor ex1_alg_add_t_b(4) );
|
||||
z4b: ex1_zero_4_b <= not( ex1_alg_add_p(4) xor ex1_alg_add_t_b(5) );
|
||||
z5: ex1_zero_5 <= not( ex1_alg_add_p(5) );
|
||||
z5b: ex1_zero_5_b <= not( ex1_zero_5 );
|
||||
z23: ex1_zero_2t3 <= not( ex1_zero_2_b or ex1_zero_3_b );
|
||||
z45: ex1_zero_4t5 <= not( ex1_zero_4_b or ex1_zero_5_b );
|
||||
z25b: ex1_zero_2t5_b <= not( ex1_zero_2t3 and ex1_zero_4t5 );
|
||||
z2b: ex1_zero_2_b <= not( ex1_alg_add_p(2) xor ex1_alg_add_t_b(3) );-- for unf calc
|
||||
z3b: ex1_zero_3_b <= not( ex1_alg_add_p(3) xor ex1_alg_add_t_b(4) );-- for unf calc
|
||||
z4b: ex1_zero_4_b <= not( ex1_alg_add_p(4) xor ex1_alg_add_t_b(5) );-- for unf calc
|
||||
z5: ex1_zero_5 <= not( ex1_alg_add_p(5) );-- for unf calc
|
||||
z5b: ex1_zero_5_b <= not( ex1_zero_5 );-- for unf calc
|
||||
z23: ex1_zero_2t3 <= not( ex1_zero_2_b or ex1_zero_3_b );-- for unf calc
|
||||
z45: ex1_zero_4t5 <= not( ex1_zero_4_b or ex1_zero_5_b );-- for unf calc
|
||||
z25b: ex1_zero_2t5_b <= not( ex1_zero_2t3 and ex1_zero_4t5 );-- for unf calc
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- [1] is really the sign bit .. needed to indicate ovf/underflow
|
||||
-------------------------------------------------
|
||||
-- finish shift underflow
|
||||
-- if sha > 162 all the bits should become sticky and the aligner output should be zero
|
||||
-- from 163:255 the shifter does this, so just need to detect the upper bits
|
||||
|
||||
pco6: pos_if_pco6 <= ( ex1_alg_add_p(1) xor ex1_t04_2_b );
|
||||
nco6: pos_if_nco6 <= ( ex1_alg_add_p(1) xor ex1_g04_2_b );
|
||||
@ -565,20 +575,47 @@ unifnc: unf_if_nco6_b <= not( pos_if_nco6 and ex1_zero_2t5_b );
|
||||
unifpc: unf_if_pco6_b <= not( pos_if_pco6 and ex1_ones_2t5_b );
|
||||
|
||||
g8_06b: ex1_g08_6_b <= not ex1_g08_6 ;
|
||||
shap: ex1_bsha_pos <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );
|
||||
shovb: ex1_sh_ovf_b <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );
|
||||
shap: ex1_bsha_pos <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );-- same as neg
|
||||
shovb: ex1_sh_ovf_b <= not( (pos_if_pco6_b and ex1_g08_6) or (pos_if_nco6_b and ex1_g08_6_b) );-- same as neg
|
||||
shun: ex1_sh_unf_x <= not( (unf_if_pco6_b and ex1_g08_6) or (unf_if_nco6_b and ex1_g08_6_b) );
|
||||
shan: ex1_bsha_neg <= not( ex1_bsha_pos );
|
||||
shan2: ex1_bsha_neg_o <= not( ex1_bsha_pos );
|
||||
shov: ex1_sh_ovf <= not( ex1_sh_ovf_b );
|
||||
|
||||
|
||||
--==-------------------------------------------------------------------------------
|
||||
--== decode for first level shifter (0/1/2/3)
|
||||
--==-------------------------------------------------------------------------------
|
||||
|
||||
d1_0: ex1_lvl1_shdcd000_b <= not( ex1_bsha_12_b and ex1_bsha_13_b );
|
||||
d1_1: ex1_lvl1_shdcd001_b <= not( ex1_bsha_12_b and ex1_bsha_13 );
|
||||
d1_2: ex1_lvl1_shdcd002_b <= not( ex1_bsha_12 and ex1_bsha_13_b );
|
||||
d1_3: ex1_lvl1_shdcd003_b <= not( ex1_bsha_12 and ex1_bsha_13 );
|
||||
|
||||
--==-------------------------------------------------------------------------------
|
||||
--== decode for second level shifter (0/4/8/12)
|
||||
--==-------------------------------------------------------------------------------
|
||||
-- ex1_lvl2_shdcd000 <= not ex1_bsha(10) and not ex1_bsha(11) ;
|
||||
-- ex1_lvl2_shdcd004 <= not ex1_bsha(10) and ex1_bsha(11) ;
|
||||
-- ex1_lvl2_shdcd008 <= ex1_bsha(10) and not ex1_bsha(11) ;
|
||||
-- ex1_lvl2_shdcd012 <= ex1_bsha(10) and ex1_bsha(11) ;
|
||||
----------------------------------------------------------------------
|
||||
-- p10 (11) ci11 DCD p10 (11) ci11 DCD
|
||||
-- !p k 0 00 !p k 0 00
|
||||
-- !P p 0 01 p g 0 00
|
||||
-- !p g 0 10 P p 1 00
|
||||
--
|
||||
-- p k 0 10 !P p 0 01
|
||||
-- P p 0 11 !p k 1 01
|
||||
-- p g 0 00 p g 1 01
|
||||
--
|
||||
-- !p k 1 01 !p g 0 10
|
||||
-- !P p 1 10 p k 0 10
|
||||
-- !p g 1 11 !P p 1 10
|
||||
--
|
||||
-- p k 1 11 P p 0 11
|
||||
-- P p 1 00 !p g 1 11
|
||||
-- p g 1 01 p k 1 11
|
||||
|
||||
d2_0pg0: ex1_lv2_0pg0_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11n_en );
|
||||
d2_0pg1: ex1_lv2_0pg1_b <= not( ex1_lv2_p10_b and ex1_lv2_g11 and ex1_lv2_ci11p_en );
|
||||
@ -610,6 +647,9 @@ ii2_3: ex1_lvl2_shdcd012 <= not ex1_lvl2_shdcd012_b;
|
||||
|
||||
|
||||
|
||||
--==--------------------------------------------
|
||||
--== decode to control ex2 shifting
|
||||
--==--------------------------------------------
|
||||
|
||||
i3_6: ex1_bsha_6_b <= not ex1_bsha_6 ;
|
||||
i3_7: ex1_bsha_7_b <= not ex1_bsha_7 ;
|
||||
@ -626,26 +666,22 @@ d89_1: ex1_89_dcd01_b <= not( ex1_bsha_8_b and ex1_bsha_9 and ex1_sel_special_
|
||||
d89_2: ex1_89_dcd10_b <= not( ex1_bsha_8 and ex1_bsha_9_b and ex1_sel_special_b );
|
||||
d89_3: ex1_89_dcd11_b <= not( ex1_bsha_8 and ex1_bsha_9 and ex1_sel_special_b );
|
||||
|
||||
d3_00: ex1_lvl3_shdcd000 <= not( ex1_67_dcd00_b or ex1_89_dcd00_b );
|
||||
d3_01: ex1_lvl3_shdcd016 <= not( ex1_67_dcd00_b or ex1_89_dcd01_b );
|
||||
d3_02: ex1_lvl3_shdcd032 <= not( ex1_67_dcd00_b or ex1_89_dcd10_b );
|
||||
d3_03: ex1_lvl3_shdcd048 <= not( ex1_67_dcd00_b or ex1_89_dcd11_b );
|
||||
d3_04: ex1_lvl3_shdcd064 <= not( ex1_67_dcd01_b or ex1_89_dcd00_b );
|
||||
d3_05: ex1_lvl3_shdcd080 <= not( ex1_67_dcd01_b or ex1_89_dcd01_b );
|
||||
d3_06: ex1_lvl3_shdcd096 <= not( ex1_67_dcd01_b or ex1_89_dcd10_b );
|
||||
d3_07: ex1_lvl3_shdcd112 <= not( ex1_67_dcd01_b or ex1_89_dcd11_b );
|
||||
d3_08: ex1_lvl3_shdcd128 <= not( ex1_67_dcd10_b or ex1_89_dcd00_b );
|
||||
d3_09: ex1_lvl3_shdcd144 <= not( ex1_67_dcd10_b or ex1_89_dcd01_b );
|
||||
d3_10: ex1_lvl3_shdcd160 <= not( ex1_67_dcd10_b or ex1_89_dcd10_b );
|
||||
d3_11: ex1_lvl3_shdcd176 <= not( ex1_67_dcd10_b or ex1_89_dcd11_b );
|
||||
d3_12: ex1_lvl3_shdcd192 <= not( ex1_67_dcd11_b or ex1_89_dcd00_b );
|
||||
d3_13: ex1_lvl3_shdcd208 <= not( ex1_67_dcd11_b or ex1_89_dcd01_b );
|
||||
d3_14: ex1_lvl3_shdcd224 <= not( ex1_67_dcd11_b or ex1_89_dcd10_b );
|
||||
d3_15: ex1_lvl3_shdcd240 <= not( ex1_67_dcd11_b or ex1_89_dcd11_b );
|
||||
|
||||
|
||||
end;
|
||||
|
||||
|
||||
d3_00: ex1_lvl3_shdcd000 <= not( ex1_67_dcd00_b or ex1_89_dcd00_b );-- 0000 +000
|
||||
d3_01: ex1_lvl3_shdcd016 <= not( ex1_67_dcd00_b or ex1_89_dcd01_b );-- 0001 +016
|
||||
d3_02: ex1_lvl3_shdcd032 <= not( ex1_67_dcd00_b or ex1_89_dcd10_b );-- 0010 +032
|
||||
d3_03: ex1_lvl3_shdcd048 <= not( ex1_67_dcd00_b or ex1_89_dcd11_b );-- 0011 +048
|
||||
d3_04: ex1_lvl3_shdcd064 <= not( ex1_67_dcd01_b or ex1_89_dcd00_b );-- 0100 +064
|
||||
d3_05: ex1_lvl3_shdcd080 <= not( ex1_67_dcd01_b or ex1_89_dcd01_b );-- 0101 +080
|
||||
d3_06: ex1_lvl3_shdcd096 <= not( ex1_67_dcd01_b or ex1_89_dcd10_b );-- 0110 +096
|
||||
d3_07: ex1_lvl3_shdcd112 <= not( ex1_67_dcd01_b or ex1_89_dcd11_b );-- 0111 +112
|
||||
d3_08: ex1_lvl3_shdcd128 <= not( ex1_67_dcd10_b or ex1_89_dcd00_b );-- 1000 +128
|
||||
d3_09: ex1_lvl3_shdcd144 <= not( ex1_67_dcd10_b or ex1_89_dcd01_b );-- 1001 +144
|
||||
d3_10: ex1_lvl3_shdcd160 <= not( ex1_67_dcd10_b or ex1_89_dcd10_b );-- 1010 +160
|
||||
d3_11: ex1_lvl3_shdcd176 <= not( ex1_67_dcd10_b or ex1_89_dcd11_b );-- 1011
|
||||
d3_12: ex1_lvl3_shdcd192 <= not( ex1_67_dcd11_b or ex1_89_dcd00_b );-- 1100 -064
|
||||
d3_13: ex1_lvl3_shdcd208 <= not( ex1_67_dcd11_b or ex1_89_dcd01_b );-- 1101 -048
|
||||
d3_14: ex1_lvl3_shdcd224 <= not( ex1_67_dcd11_b or ex1_89_dcd10_b );-- 1110 -032
|
||||
d3_15: ex1_lvl3_shdcd240 <= not( ex1_67_dcd11_b or ex1_89_dcd11_b );-- 1111 -016
|
||||
|
||||
|
||||
end; -- fuq_alg_add ARCHITECTURE
|
||||
|
||||
@ -149,6 +149,7 @@ constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := "0111";
|
||||
constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := "0101";
|
||||
constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := "0011";
|
||||
constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := "0001";
|
||||
-- reserved for indirect entries
|
||||
constant ERAT_PgSize_256MB : std_ulogic_vector(0 to 2) := "100";
|
||||
constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := "1001";
|
||||
constant HtwSeq_Idle : std_ulogic_vector(0 to 1) := "00";
|
||||
@ -207,21 +208,25 @@ constant pte1_score_pending_offset : natural := pte1_score_ibit_offset + 1;
|
||||
constant pte1_score_dataval_offset : natural := pte1_score_pending_offset + 1;
|
||||
constant pte_load_ptr_offset : natural := pte1_score_dataval_offset + 1;
|
||||
constant ptereload_ptr_offset : natural := pte_load_ptr_offset + 1;
|
||||
-- ptereload_ptr_offset + 1 phase
|
||||
constant reld_core_tag_tm1_offset : natural := ptereload_ptr_offset + 1;
|
||||
constant reld_qw_tm1_offset : natural := reld_core_tag_tm1_offset + 5;
|
||||
constant reld_crit_qw_tm1_offset : natural := reld_qw_tm1_offset + 2;
|
||||
constant reld_ditc_tm1_offset : natural := reld_crit_qw_tm1_offset + 1;
|
||||
constant reld_data_vld_tm1_offset : natural := reld_ditc_tm1_offset + 1;
|
||||
-- reld_data_vld_tm1_offset + 1 phase
|
||||
constant reld_core_tag_t_offset : natural := reld_data_vld_tm1_offset + 1;
|
||||
constant reld_qw_t_offset : natural := reld_core_tag_t_offset + 5;
|
||||
constant reld_crit_qw_t_offset : natural := reld_qw_t_offset + 2;
|
||||
constant reld_ditc_t_offset : natural := reld_crit_qw_t_offset + 1;
|
||||
constant reld_data_vld_t_offset : natural := reld_ditc_t_offset + 1;
|
||||
-- reld_data_vld_t_offset + 1 phase
|
||||
constant reld_core_tag_tp1_offset : natural := reld_data_vld_t_offset + 1;
|
||||
constant reld_qw_tp1_offset : natural := reld_core_tag_tp1_offset + 5;
|
||||
constant reld_crit_qw_tp1_offset : natural := reld_qw_tp1_offset + 2;
|
||||
constant reld_ditc_tp1_offset : natural := reld_crit_qw_tp1_offset + 1;
|
||||
constant reld_data_vld_tp1_offset : natural := reld_ditc_tp1_offset + 1;
|
||||
-- reld_data_vld_tp1_offset + 1 phase
|
||||
constant reld_core_tag_tp2_offset : natural := reld_data_vld_tp1_offset + 1;
|
||||
constant reld_qw_tp2_offset : natural := reld_core_tag_tp2_offset + 5;
|
||||
constant reld_crit_qw_tp2_offset : natural := reld_qw_tp2_offset + 2;
|
||||
@ -256,6 +261,7 @@ constant tagpos_ltwe : natural := 106;
|
||||
constant tagpos_lpte : natural := 107;
|
||||
constant tagpos_recform : natural := 108;
|
||||
constant tagpos_endflag : natural := 109;
|
||||
-- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
||||
constant tagpos_type_derat : natural := tagpos_type;
|
||||
constant tagpos_type_ierat : natural := tagpos_type+1;
|
||||
constant tagpos_type_tlbsx : natural := tagpos_type+2;
|
||||
@ -264,6 +270,7 @@ constant tagpos_type_snoop : natural := tagpos_type+4;
|
||||
constant tagpos_type_tlbre : natural := tagpos_type+5;
|
||||
constant tagpos_type_tlbwe : natural := tagpos_type+6;
|
||||
constant tagpos_type_ptereload : natural := tagpos_type+7;
|
||||
-- state: 0:pr 1:gs 2:as 3:cm
|
||||
constant tagpos_pr : natural := tagpos_state;
|
||||
constant tagpos_gs : natural := tagpos_state+1;
|
||||
constant tagpos_as : natural := tagpos_state+2;
|
||||
@ -297,6 +304,7 @@ constant ptepos_size : natural := 52;
|
||||
constant ptepos_usxwr : natural := 56;
|
||||
constant ptepos_sw1 : natural := 62;
|
||||
constant ptepos_valid : natural := 63;
|
||||
-- Latch signals
|
||||
signal htw_seq_d, htw_seq_q : std_ulogic_vector(0 to 1);
|
||||
signal htw_inptr_d, htw_inptr_q : std_ulogic_vector(0 to 1);
|
||||
signal htw_lsuptr_d, htw_lsuptr_q : std_ulogic_vector(0 to 1);
|
||||
@ -345,22 +353,26 @@ signal tlb_htw_req3_way_d, tlb_htw_req3_way_q : std_ulogic_vector(tlb_word_
|
||||
signal tlb_htw_req3_tag_act : std_ulogic;
|
||||
-- synopsys translate_off
|
||||
-- synopsys translate_on
|
||||
-- t minus 1 phase
|
||||
signal reld_core_tag_tm1_d, reld_core_tag_tm1_q : std_ulogic_vector(0 to 4);
|
||||
signal reld_qw_tm1_d, reld_qw_tm1_q : std_ulogic_vector(0 to 1);
|
||||
signal reld_crit_qw_tm1_d, reld_crit_qw_tm1_q : std_ulogic;
|
||||
signal reld_ditc_tm1_d, reld_ditc_tm1_q : std_ulogic;
|
||||
signal reld_data_vld_tm1_d, reld_data_vld_tm1_q : std_ulogic;
|
||||
-- t phase
|
||||
signal reld_core_tag_t_d, reld_core_tag_t_q : std_ulogic_vector(0 to 4);
|
||||
signal reld_qw_t_d, reld_qw_t_q : std_ulogic_vector(0 to 1);
|
||||
signal reld_crit_qw_t_d, reld_crit_qw_t_q : std_ulogic;
|
||||
signal reld_ditc_t_d, reld_ditc_t_q : std_ulogic;
|
||||
signal reld_data_vld_t_d, reld_data_vld_t_q : std_ulogic;
|
||||
-- t plus 1 phase
|
||||
signal reld_core_tag_tp1_d, reld_core_tag_tp1_q : std_ulogic_vector(0 to 4);
|
||||
signal reld_qw_tp1_d, reld_qw_tp1_q : std_ulogic_vector(0 to 1);
|
||||
signal reld_crit_qw_tp1_d, reld_crit_qw_tp1_q : std_ulogic;
|
||||
signal reld_ditc_tp1_d, reld_ditc_tp1_q : std_ulogic;
|
||||
signal reld_data_vld_tp1_d, reld_data_vld_tp1_q : std_ulogic;
|
||||
signal reld_data_tp1_d, reld_data_tp1_q : std_ulogic_vector(0 to 127);
|
||||
-- t plus 2 phase
|
||||
signal reld_core_tag_tp2_d, reld_core_tag_tp2_q : std_ulogic_vector(0 to 4);
|
||||
signal reld_qw_tp2_d, reld_qw_tp2_q : std_ulogic_vector(0 to 1);
|
||||
signal reld_crit_qw_tp2_d, reld_crit_qw_tp2_q : std_ulogic;
|
||||
@ -369,6 +381,7 @@ signal reld_data_vld_tp2_d, reld_data_vld_tp2_q : std_ulogic;
|
||||
signal reld_data_tp2_d, reld_data_tp2_q : std_ulogic_vector(0 to 127);
|
||||
signal reld_ecc_err_tp2_d, reld_ecc_err_tp2_q : std_ulogic;
|
||||
signal reld_ecc_err_ue_tp2_d, reld_ecc_err_ue_tp2_q : std_ulogic;
|
||||
-- t plus 3 phase
|
||||
signal pte0_reld_data_tp3_d, pte0_reld_data_tp3_q : std_ulogic_vector(0 to 63);
|
||||
signal pte1_reld_data_tp3_d, pte1_reld_data_tp3_q : std_ulogic_vector(0 to 63);
|
||||
signal htw_tag3_d, htw_tag3_q : std_ulogic_vector(0 to tlb_tag_width-1);
|
||||
@ -377,6 +390,7 @@ signal htw_tag3_clr_resv_term7, htw_tag3_clr_resv_term8, htw_tag3_clr_resv_term9
|
||||
signal htw_tag4_clr_resv_d, htw_tag4_clr_resv_q : std_ulogic_vector(0 to thdid_width-1);
|
||||
signal htw_tag5_clr_resv_d, htw_tag5_clr_resv_q : std_ulogic_vector(0 to thdid_width-1);
|
||||
signal spare_a_q, spare_b_q : std_ulogic_vector(0 to 15);
|
||||
-- logic signals
|
||||
signal htw_seq_idle : std_ulogic;
|
||||
signal htw_seq_load_pteaddr : std_ulogic;
|
||||
signal htw_quiesce_b : std_ulogic_vector(0 to thdid_width-1);
|
||||
@ -461,6 +475,7 @@ signal pte1_reld_act : std_ulogic;
|
||||
signal unused_dc : std_ulogic_vector(0 to 21);
|
||||
-- synopsys translate_off
|
||||
-- synopsys translate_on
|
||||
-- Pervasive
|
||||
signal pc_sg_1 : std_ulogic;
|
||||
signal pc_sg_0 : std_ulogic;
|
||||
signal pc_func_sl_thold_1 : std_ulogic;
|
||||
@ -475,8 +490,12 @@ signal siv_0 : std_ulogic_vector(0 to scan_right_0);
|
||||
signal sov_0 : std_ulogic_vector(0 to scan_right_0);
|
||||
signal siv_1 : std_ulogic_vector(0 to scan_right_1);
|
||||
signal sov_1 : std_ulogic_vector(0 to scan_right_1);
|
||||
BEGIN
|
||||
BEGIN --@@ START OF EXECUTABLE CODE FOR MMQ_HTW
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Logic
|
||||
-----------------------------------------------------------------------
|
||||
-- not quiesced
|
||||
htw_quiesce_b(0 TO thdid_width-1) <=
|
||||
( (0 to thdid_width-1 => tlb_htw_req0_valid_q) and tlb_htw_req0_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or
|
||||
( (0 to thdid_width-1 => tlb_htw_req1_valid_q) and tlb_htw_req1_tag_q(tagpos_thdid to tagpos_thdid+thdid_width-1) ) or
|
||||
@ -489,6 +508,7 @@ tlb_htw_req_valid_vec <= (tlb_htw_req0_valid_q and (pte0_score_pending_q='0' o
|
||||
(tlb_htw_req1_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="01") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="01")) &
|
||||
(tlb_htw_req2_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="10") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="10")) &
|
||||
(tlb_htw_req3_valid_q and (pte0_score_pending_q='0' or pte0_score_ptr_q/="11") and (pte1_score_pending_q='0' or pte1_score_ptr_q/="11"));
|
||||
-- HTW sequencer for servicing indirect tlb entry hits
|
||||
Htw_Sequencer: PROCESS (htw_seq_q, tlb_htw_req_valid_vec, tlb_htw_pte_machines_full, htw_lsu_req_taken)
|
||||
BEGIN
|
||||
htw_seq_load_pteaddr <= '0';
|
||||
@ -518,6 +538,7 @@ CASE htw_seq_q IS
|
||||
END CASE;
|
||||
END PROCESS Htw_Sequencer;
|
||||
htw_seq_idle <= '1' when htw_seq_q=HtwSeq_Idle else '0';
|
||||
-- PTE sequencer for servicing pte data reloads
|
||||
Pte0_Sequencer: PROCESS (pte0_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken,
|
||||
pte0_score_pending_q, pte0_score_dataval_q,
|
||||
pte0_score_error_q, pte0_score_qwbeat_q, pte0_score_ibit_q, spare_b_q(0 to 2))
|
||||
@ -590,6 +611,7 @@ CASE pte0_seq_q IS
|
||||
END CASE;
|
||||
END PROCESS Pte0_Sequencer;
|
||||
pte0_seq_idle <= '1' when pte0_seq_q=PteSeq_Idle else '0';
|
||||
-- PTE sequencer for servicing pte data reloads
|
||||
Pte1_Sequencer: PROCESS (pte1_seq_q, pte_load_ptr_q, ptereload_ptr_q, htw_lsu_req_taken, ptereload_req_taken,
|
||||
pte1_score_pending_q, pte1_score_dataval_q,
|
||||
pte1_score_error_q, pte1_score_qwbeat_q, pte1_score_ibit_q, spare_b_q(0 to 2))
|
||||
@ -662,6 +684,13 @@ CASE pte1_seq_q IS
|
||||
END CASE;
|
||||
END PROCESS Pte1_Sequencer;
|
||||
pte1_seq_idle <= '1' when pte1_seq_q=PteSeq_Idle else '0';
|
||||
-- tlb_way IND=0 IND=1
|
||||
-- 134 UX SPSIZE0
|
||||
-- 135 SX SPSIZE1
|
||||
-- 136 UW SPSIZE2
|
||||
-- 137 SW SPSIZE3
|
||||
-- 138 UR PTRPN
|
||||
-- 139 SR PA52
|
||||
tlb_htw_req0_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00")
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00")
|
||||
@ -670,17 +699,23 @@ tlb_htw_req0_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req0_
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte0_score_ptr_q="00")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_pending_q='1' and pte1_score_ptr_q="00")
|
||||
else tlb_htw_req0_pending_q;
|
||||
-- the rpn part of the tlb way
|
||||
tlb_htw_req0_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00")
|
||||
else tlb_htw_req0_way_q;
|
||||
tlb_htw_req0_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00")
|
||||
else tlb_htw_req0_tag_q(0 to tagpos_wq-1);
|
||||
tlb_htw_req0_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00")
|
||||
else tlb_htw_req0_tag_q(tagpos_wq+2 to tlb_tag_width-1);
|
||||
-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits
|
||||
-- set reservation valid at tlb handoff, clear when ptereload taken..
|
||||
-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates
|
||||
-- or, clear reservation when L2 UE for this reload
|
||||
tlb_htw_req0_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(0)='1' and tlb_tag5_except="0000") or tlb_htw_req0_clr_resv_ue='1')
|
||||
else '1' when (tlb_htw_req_valid='1' and tlb_htw_req0_valid_q='0' and htw_inptr_q="00")
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte0_score_ptr_q="00")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req0_valid_q='1' and pte1_score_ptr_q="00")
|
||||
else tlb_htw_req0_tag_q(tagpos_wq);
|
||||
-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff
|
||||
tlb_htw_req0_tag_d(tagpos_wq+1) <= tlb_htw_req0_tag_q(tagpos_wq+1);
|
||||
tlb_htw_req0_tag_act <= tlb_delayed_act(24+0) or tlb_htw_req0_valid_q;
|
||||
tlb_htw_req0_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"00")) or
|
||||
@ -693,6 +728,7 @@ pte_ra_0_spsize4K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width
|
||||
tlb_htw_req0_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000";
|
||||
pte_ra_0_spsize64K <= tlb_htw_req0_way_q(waypos_rpn to waypos_rpn+rpn_width-4) &
|
||||
tlb_htw_req0_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000";
|
||||
-- select based on SPSIZE
|
||||
pte_ra_0 <= pte_ra_0_spsize64K when tlb_htw_req0_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB
|
||||
else pte_ra_0_spsize4K;
|
||||
tlb_htw_req1_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01")
|
||||
@ -703,17 +739,23 @@ tlb_htw_req1_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req1_
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte0_score_ptr_q="01")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_pending_q='1' and pte1_score_ptr_q="01")
|
||||
else tlb_htw_req1_pending_q;
|
||||
-- the rpn part of the tlb way
|
||||
tlb_htw_req1_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01")
|
||||
else tlb_htw_req1_way_q;
|
||||
tlb_htw_req1_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01")
|
||||
else tlb_htw_req1_tag_q(0 to tagpos_wq-1);
|
||||
tlb_htw_req1_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01")
|
||||
else tlb_htw_req1_tag_q(tagpos_wq+2 to tlb_tag_width-1);
|
||||
-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits
|
||||
-- set reservation valid at tlb handoff, clear when ptereload taken..
|
||||
-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates
|
||||
-- or, clear reservation when L2 UE for this reload
|
||||
tlb_htw_req1_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(1)='1' and tlb_tag5_except="0000") or tlb_htw_req1_clr_resv_ue='1')
|
||||
else '1' when (tlb_htw_req_valid='1' and tlb_htw_req1_valid_q='0' and htw_inptr_q="01")
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte0_score_ptr_q="01")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req1_valid_q='1' and pte1_score_ptr_q="01")
|
||||
else tlb_htw_req1_tag_q(tagpos_wq);
|
||||
-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff
|
||||
tlb_htw_req1_tag_d(tagpos_wq+1) <= tlb_htw_req1_tag_q(tagpos_wq+1);
|
||||
tlb_htw_req1_tag_act <= tlb_delayed_act(24+1) or tlb_htw_req1_valid_q;
|
||||
tlb_htw_req1_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"01")) or
|
||||
@ -736,12 +778,17 @@ tlb_htw_req2_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req2_
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte0_score_ptr_q="10")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req2_pending_q='1' and pte1_score_ptr_q="10")
|
||||
else tlb_htw_req2_pending_q;
|
||||
-- the rpn part of the tlb way
|
||||
tlb_htw_req2_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10")
|
||||
else tlb_htw_req2_way_q;
|
||||
tlb_htw_req2_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10")
|
||||
else tlb_htw_req2_tag_q(0 to tagpos_wq-1);
|
||||
tlb_htw_req2_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10")
|
||||
else tlb_htw_req2_tag_q(tagpos_wq+2 to tlb_tag_width-1);
|
||||
-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits
|
||||
-- set reservation valid at tlb handoff, clear when ptereload taken..
|
||||
-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates
|
||||
-- or, clear reservation when L2 UE for this reload
|
||||
tlb_htw_req2_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(2)='1' and tlb_tag5_except="0000") or tlb_htw_req2_clr_resv_ue='1')
|
||||
else '1' when (tlb_htw_req_valid='1' and tlb_htw_req2_valid_q='0' and htw_inptr_q="10")
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req2_valid_q='1' and pte0_score_ptr_q="10")
|
||||
@ -759,6 +806,7 @@ pte_ra_2_spsize4K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width
|
||||
tlb_htw_req2_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000";
|
||||
pte_ra_2_spsize64K <= tlb_htw_req2_way_q(waypos_rpn to waypos_rpn+rpn_width-4) &
|
||||
tlb_htw_req2_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000";
|
||||
-- select based on SPSIZE
|
||||
pte_ra_2 <= pte_ra_2_spsize64K when tlb_htw_req2_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB
|
||||
else pte_ra_2_spsize4K;
|
||||
tlb_htw_req3_valid_d <= '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11")
|
||||
@ -769,17 +817,23 @@ tlb_htw_req3_pending_d <= '1' when (htw_lsu_req_taken='1' and tlb_htw_req3_
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte0_score_ptr_q="11")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_pending_q='1' and pte1_score_ptr_q="11")
|
||||
else tlb_htw_req3_pending_q;
|
||||
-- the rpn part of the tlb way
|
||||
tlb_htw_req3_way_d <= tlb_htw_req_way when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11")
|
||||
else tlb_htw_req3_way_q;
|
||||
tlb_htw_req3_tag_d(0 TO tagpos_wq-1) <= tlb_htw_req_tag(0 to tagpos_wq-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11")
|
||||
else tlb_htw_req3_tag_q(0 to tagpos_wq-1);
|
||||
tlb_htw_req3_tag_d(tagpos_wq+2 TO tlb_tag_width-1) <= tlb_htw_req_tag(tagpos_wq+2 to tlb_tag_width-1) when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11")
|
||||
else tlb_htw_req3_tag_q(tagpos_wq+2 to tlb_tag_width-1);
|
||||
-- the WQ bits of the tag are re-purposed as reservation valid and duplicate bits
|
||||
-- set reservation valid at tlb handoff, clear when ptereload taken..
|
||||
-- or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates
|
||||
-- or, clear reservation when L2 UE for this reload
|
||||
tlb_htw_req3_tag_d(tagpos_wq) <= '0' when ((htw_tag5_clr_resv_q(3)='1' and tlb_tag5_except="0000") or tlb_htw_req3_clr_resv_ue='1')
|
||||
else '1' when (tlb_htw_req_valid='1' and tlb_htw_req3_valid_q='0' and htw_inptr_q="11")
|
||||
else '0' when (pte0_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte0_score_ptr_q="11")
|
||||
else '0' when (pte1_reload_req_taken='1' and tlb_htw_req3_valid_q='1' and pte1_score_ptr_q="11")
|
||||
else tlb_htw_req3_tag_q(tagpos_wq);
|
||||
-- spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff
|
||||
tlb_htw_req3_tag_d(tagpos_wq+1) <= tlb_htw_req3_tag_q(tagpos_wq+1);
|
||||
tlb_htw_req3_tag_act <= tlb_delayed_act(24+3) or tlb_htw_req3_valid_q;
|
||||
tlb_htw_req3_clr_resv_ue <= (pte0_seq_clr_resv_ue and Eq(pte0_score_ptr_q,"11")) or
|
||||
@ -792,11 +846,37 @@ pte_ra_3_spsize4K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width
|
||||
tlb_htw_req3_tag_q(tagpos_epn+epn_width-8 to tagpos_epn+epn_width-1) & "000";
|
||||
pte_ra_3_spsize64K <= tlb_htw_req3_way_q(waypos_rpn to waypos_rpn+rpn_width-4) &
|
||||
tlb_htw_req3_tag_q(tagpos_epn+epn_width-16 to tagpos_epn+epn_width-5) & "000";
|
||||
-- select based on SPSIZE
|
||||
pte_ra_3 <= pte_ra_3_spsize64K when tlb_htw_req3_way_q(waypos_usxwr to waypos_usxwr+3)=TLB_PgSize_64KB
|
||||
else pte_ra_3_spsize4K;
|
||||
-- tag forwarding from tlb_ctl, for reservation clear compares
|
||||
htw_tag3_d(0 TO tagpos_thdid-1) <= tlb_tag2(0 to tagpos_thdid-1);
|
||||
htw_tag3_d(tagpos_thdid+thdid_width TO tlb_tag_width-1) <= tlb_tag2(tagpos_thdid+thdid_width to tlb_tag_width-1);
|
||||
htw_tag3_d(tagpos_thdid TO tagpos_thdid+thdid_width-1) <= tlb_tag2(tagpos_thdid to tagpos_thdid+thdid_width-1) and not(tlb_ctl_tag2_flush);
|
||||
-- reservation clear:
|
||||
-- (1) proc holding resv executes another tlbsrx. overwriting the old resv
|
||||
-- (2) any tlbivax snoop with gs,as,lpid,pid,sizemasked(epn,mas6.isize) matching resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize)
|
||||
-- (note ind bit is not part of tlbivax criteria!!)
|
||||
-- (3) any proc sets mmucsr0.TLB0_FI=1 with lpidr matching resv.lpid
|
||||
-- (4) any proc executes tlbilx T=0 (all) with mas5.slpid matching resv.lpid
|
||||
-- (5) any proc executes tlbilx T=1 (pid) with mas5.slpid and mas6.spid matching resv.lpid,pid
|
||||
-- (6) any proc executes tlbilx T=3 (vpn) with mas gs,as,slpid,spid,sizemasked(epn,mas6.isize) matching
|
||||
-- resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize)
|
||||
-- (note ind bit is not part of tlbilx criteria!!)
|
||||
-- (7) any proc executes tlbwe not causing exception and with (wq=00 always, or wq=01 and proc holds resv)
|
||||
-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize)
|
||||
-- (8) any page table reload not causing an exception (due to pt fault, tlb inelig, or lrat miss)
|
||||
-- and PTE's tag ind=0,tgs,ts,tlpid,tid,sizemasked(epn,pte.size) match resv.ind=0,gs,as,lpid,pid,sizemasked(epn.pte.size)
|
||||
-- A2-specific non-architected clear states
|
||||
-- (9) any proc executes tlbwe not causing exception and with (wq=10 clear, or wq=11 always (same as 00))
|
||||
-- and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize)
|
||||
-- (basically same as 7,
|
||||
-- (10) any proc executes tlbilx T=2 (gs) with mas5.sgs matching resv.gs
|
||||
-- (11) any proc executes tlbilx T=4 to 7 (class) with T(1:2) matching resv.class
|
||||
-- ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx;
|
||||
-- IS0: Local bit
|
||||
-- IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3
|
||||
-- mas0.wq: 00=ignore reserv write always, 01=write if reserved, 10=clear reserv, 11=same as 00
|
||||
htw_tag3_clr_resv_term2(0) <= '1' when (htw_tag3_q(tagpos_thdid to tagpos_thdid+thdid_width-1)/="0000" and
|
||||
htw_tag3_q(tagpos_type_snoop)='1' and htw_tag3_q(tagpos_is to tagpos_is+3)="0011" and
|
||||
htw_resv0_tag3_lpid_match='1' and htw_resv0_tag3_pid_match='1' and htw_resv0_tag3_gs_match='1' and
|
||||
@ -987,6 +1067,8 @@ htw_resv0_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req0_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB)
|
||||
else '0';
|
||||
-- global match ignores certain upper epn bits that are not tranferred over bus
|
||||
-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb
|
||||
htw_resv0_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req0_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or
|
||||
@ -1003,6 +1085,8 @@ htw_resv1_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req1_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB)
|
||||
else '0';
|
||||
-- global match ignores certain upper epn bits that are not tranferred over bus
|
||||
-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb
|
||||
htw_resv1_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req1_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or
|
||||
@ -1019,6 +1103,8 @@ htw_resv2_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req2_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB)
|
||||
else '0';
|
||||
-- global match ignores certain upper epn bits that are not tranferred over bus
|
||||
-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb
|
||||
htw_resv2_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req2_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or
|
||||
@ -1035,6 +1121,8 @@ htw_resv3_tag3_epn_loc_match <= '1' when (htw_tag3_q(tagpos_epn to tagpos
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-13)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-13) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_16MB) or
|
||||
(htw_tag3_q(tagpos_epn to tagpos_epn+epn_width-19)=tlb_htw_req3_tag_q(tagpos_epn to tagpos_epn+epn_width-19) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1GB)
|
||||
else '0';
|
||||
-- global match ignores certain upper epn bits that are not tranferred over bus
|
||||
-- fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb
|
||||
htw_resv3_tag3_epn_glob_match <= '1' when (htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-1)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-1) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_4KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-5)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-5) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_64KB) or
|
||||
(htw_tag3_q(tagpos_epn+31 to tagpos_epn+epn_width-9)=tlb_htw_req3_tag_q(tagpos_epn+31 to tagpos_epn+epn_width-9) and htw_tag3_q(tagpos_size to tagpos_size+3)=TLB_PgSize_1MB) or
|
||||
@ -1057,6 +1145,8 @@ pte0_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte0_seq_score_
|
||||
pte0_score_pending_d <= '1' when pte0_seq_score_load='1'
|
||||
else '0' when pte0_seq_score_done='1'
|
||||
else pte0_score_pending_q;
|
||||
-- 4 quadword data beats being returned; entire CL repeated if any beat has ecc error
|
||||
-- ...beats need to be set regardless of ecc present..ecc and any qw happen simultaneously
|
||||
pte0_score_qwbeat_d(0) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_retry='1'
|
||||
else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="00")
|
||||
@ -1073,6 +1163,7 @@ pte0_score_qwbeat_d(3) <= '0' when pte0_seq_score_load='1' or pte0_seq_data_r
|
||||
else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag0_Value and reld_qw_tp2_q="11")
|
||||
else pte0_score_qwbeat_q(3);
|
||||
-- ecc error detection: bit0=ECC, bit1=UE, bit2=retry
|
||||
pte0_score_error_d(0) <= '0' when pte0_seq_score_load='1'
|
||||
else '1' when (pte0_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag0_Value
|
||||
@ -1107,6 +1198,8 @@ pte1_score_ibit_d <= tlb_htw_req0_way_q(waypos_wimge+1) when pte1_seq_score_
|
||||
pte1_score_pending_d <= '1' when pte1_seq_score_load='1'
|
||||
else '0' when pte1_seq_score_done='1'
|
||||
else pte1_score_pending_q;
|
||||
-- 4 quadword data beats being returned; entire CL repeated if any beat has ecc error
|
||||
-- ...beats need to be set regardless of ecc present..ecc and any qw happen simultaneously
|
||||
pte1_score_qwbeat_d(0) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_retry='1'
|
||||
else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="00")
|
||||
@ -1123,6 +1216,7 @@ pte1_score_qwbeat_d(3) <= '0' when pte1_seq_score_load='1' or pte1_seq_data_r
|
||||
else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag1_Value and reld_qw_tp2_q="11")
|
||||
else pte1_score_qwbeat_q(3);
|
||||
-- ecc error detection: bit0=ECC, bit1=UE, bit2=retry
|
||||
pte1_score_error_d(0) <= '0' when pte1_seq_score_load='1'
|
||||
else '1' when (pte1_score_pending_q='1' and reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0'
|
||||
and reld_core_tag_tp2_q=Core_Tag1_Value
|
||||
@ -1141,6 +1235,11 @@ pte1_score_dataval_d <= '0' when pte1_seq_score_load='1' or pte1_seq_data_
|
||||
and reld_crit_qw_tp2_q='1' and reld_qw_tp2_q=pte1_score_cl_offset_q(58 to 59)
|
||||
and reld_core_tag_tp2_q=Core_Tag1_Value)
|
||||
else pte1_score_dataval_q;
|
||||
-- pointers:
|
||||
-- htw_inptr: tlb to htw incoming request queue pointer, 4 total
|
||||
-- htw_lsuptr: htw to lru outgoing request queue pointer, 4 total
|
||||
-- pte_load_ptr: pte machine pointer next to load, 2 total
|
||||
-- ptereload_ptr: pte to tlb data reload select, 2 total
|
||||
htw_inptr_d <= "01" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='0' and tlb_htw_req_valid='1'
|
||||
else "10" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='0' and tlb_htw_req_valid='1'
|
||||
else "11" when htw_inptr_q="00" and tlb_htw_req0_valid_q='0' and tlb_htw_req1_valid_q='1' and tlb_htw_req2_valid_q='1' and tlb_htw_req3_valid_q='0' and tlb_htw_req_valid='1'
|
||||
@ -1200,6 +1299,7 @@ ptereload_ptr_d <= '1' when ptereload_ptr_q='0' and ptereload_req_taken='1'
|
||||
else '0' when ptereload_ptr_q='1' and ptereload_req_taken='1'
|
||||
else '0' when ptereload_ptr_q='1' and pte0_reload_req_valid='1' and pte1_reload_req_valid='0'
|
||||
else ptereload_ptr_q;
|
||||
-- 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101
|
||||
htw_lsu_ttype_d <= "11" when (pte_load_ptr_q='1' and htw_seq_load_pteaddr='1')
|
||||
else "10" when htw_seq_load_pteaddr='1'
|
||||
else htw_lsu_ttype_q;
|
||||
@ -1231,11 +1331,14 @@ htw_lsu_ttype <= htw_lsu_ttype_q;
|
||||
htw_lsu_wimge <= htw_lsu_wimge_q;
|
||||
htw_lsu_u <= htw_lsu_u_q;
|
||||
htw_lsu_addr <= htw_lsu_addr_q;
|
||||
-- L2 data reload stages
|
||||
-- t minus 2 phase
|
||||
reld_core_tag_tm1_d <= an_ac_reld_core_tag;
|
||||
reld_qw_tm1_d <= an_ac_reld_qw;
|
||||
reld_crit_qw_tm1_d <= an_ac_reld_crit_qw;
|
||||
reld_ditc_tm1_d <= an_ac_reld_ditc;
|
||||
reld_data_vld_tm1_d <= an_ac_reld_data_vld;
|
||||
-- t minus 1 phase
|
||||
reld_core_tag_t_d <= reld_core_tag_tm1_q;
|
||||
reld_qw_t_d <= reld_qw_tm1_q;
|
||||
reld_crit_qw_t_d <= reld_crit_qw_tm1_q;
|
||||
@ -1247,12 +1350,14 @@ pte0_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_
|
||||
pte1_reld_for_me_tm1 <= '1' when (reld_data_vld_tm1_q='1' and reld_ditc_tm1_q='0' and reld_crit_qw_tm1_q='1'
|
||||
and reld_qw_tm1_q=pte1_score_cl_offset_q(58 to 59) and reld_core_tag_tm1_q=Core_Tag1_Value)
|
||||
else '0';
|
||||
-- t phase
|
||||
reld_core_tag_tp1_d <= reld_core_tag_t_q;
|
||||
reld_qw_tp1_d <= reld_qw_t_q;
|
||||
reld_crit_qw_tp1_d <= reld_crit_qw_t_q;
|
||||
reld_ditc_tp1_d <= reld_ditc_t_q;
|
||||
reld_data_vld_tp1_d <= reld_data_vld_t_q;
|
||||
reld_data_tp1_d <= an_ac_reld_data;
|
||||
-- t plus 1 phase
|
||||
reld_core_tag_tp2_d <= reld_core_tag_tp1_q;
|
||||
reld_qw_tp2_d <= reld_qw_tp1_q;
|
||||
reld_crit_qw_tp2_d <= reld_crit_qw_tp1_q;
|
||||
@ -1261,6 +1366,7 @@ reld_data_vld_tp2_d <= reld_data_vld_tp1_q;
|
||||
reld_data_tp2_d <= reld_data_tp1_q;
|
||||
reld_ecc_err_tp2_d <= an_ac_reld_ecc_err;
|
||||
reld_ecc_err_ue_tp2_d <= an_ac_reld_ecc_err_ue;
|
||||
-- t plus 2 phase
|
||||
pte0_reld_for_me_tp2 <= '1' when (reld_data_vld_tp2_q='1' and reld_ditc_tp2_q='0' and reld_crit_qw_tp2_q='1'
|
||||
and reld_qw_tp2_q=pte0_score_cl_offset_q(58 to 59) and reld_core_tag_tp2_q=Core_Tag0_Value)
|
||||
else '0';
|
||||
@ -1276,6 +1382,7 @@ pte1_reld_data_tp3_d <= reld_data_tp2_q(0 to 63) when (pte1_reld_for_me_tp2
|
||||
reld_act <= (or_reduce(pte0_seq_q) or or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b;
|
||||
pte0_reld_act <= (or_reduce(pte0_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b;
|
||||
pte1_reld_act <= (or_reduce(pte1_seq_q) or mmucr2_act_override) and xu_mm_ccr2_notlb_b;
|
||||
-- ptereload requests to tlb_ctl
|
||||
ptereload_req_valid <= '0' when (htw_tag4_clr_resv_q/="0000" or htw_tag5_clr_resv_q/="0000")
|
||||
else pte1_reload_req_valid when ptereload_ptr_q='1'
|
||||
else pte0_reload_req_valid;
|
||||
@ -1318,6 +1425,7 @@ htw_dbg_pte1_score_pending_q <= pte1_score_pending_q;
|
||||
htw_dbg_pte1_score_ibit_q <= pte1_score_ibit_q;
|
||||
htw_dbg_pte1_score_dataval_q <= pte1_score_dataval_q;
|
||||
htw_dbg_pte1_reld_for_me_tm1 <= pte1_reld_for_me_tm1;
|
||||
-- unused spare signal assignments
|
||||
unused_dc(0) <= or_reduce(LCB_DELAY_LCLKR_DC(1 TO 4));
|
||||
unused_dc(1) <= or_reduce(LCB_MPW1_DC_B(1 TO 4));
|
||||
unused_dc(2) <= PC_FUNC_SL_FORCE;
|
||||
@ -1336,6 +1444,10 @@ unused_dc(14) <= PTE0_RELD_ENABLE_LO_TP2 or PTE0_RELD_ENABLE_HI_TP2;
|
||||
unused_dc(15) <= PTE1_RELD_ENABLE_LO_TP2 or PTE1_RELD_ENABLE_HI_TP2;
|
||||
unused_dc(16 TO 19) <= tlb_htw_req0_pending_q & tlb_htw_req1_pending_q & tlb_htw_req2_pending_q & tlb_htw_req3_pending_q;
|
||||
unused_dc(20 TO 21) <= htw_lsuptr_alt_d;
|
||||
-----------------------------------------------------------------------
|
||||
-- Latches
|
||||
-----------------------------------------------------------------------
|
||||
-- tlb request valid latches
|
||||
tlb_htw_req0_valid_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1353,6 +1465,7 @@ tlb_htw_req0_valid_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req0_valid_offset),
|
||||
din => tlb_htw_req0_valid_d,
|
||||
dout => tlb_htw_req0_valid_q);
|
||||
-- tlb request pending latches.. this req is loaded into a pte machine
|
||||
tlb_htw_req0_pending_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1370,6 +1483,7 @@ tlb_htw_req0_pending_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req0_pending_offset),
|
||||
din => tlb_htw_req0_pending_d,
|
||||
dout => tlb_htw_req0_pending_q);
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req0_tag_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req0_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1387,6 +1501,7 @@ tlb_htw_req0_tag_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req0_tag_offset to tlb_htw_req0_tag_offset+tlb_htw_req0_tag_q'length-1),
|
||||
din => tlb_htw_req0_tag_d,
|
||||
dout => tlb_htw_req0_tag_q );
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req0_way_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req0_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1404,6 +1519,7 @@ tlb_htw_req0_way_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req0_way_offset to tlb_htw_req0_way_offset+tlb_htw_req0_way_q'length-1),
|
||||
din => tlb_htw_req0_way_d,
|
||||
dout => tlb_htw_req0_way_q );
|
||||
-- tlb request valid latches
|
||||
tlb_htw_req1_valid_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1421,6 +1537,7 @@ tlb_htw_req1_valid_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req1_valid_offset),
|
||||
din => tlb_htw_req1_valid_d,
|
||||
dout => tlb_htw_req1_valid_q);
|
||||
-- tlb request pending latches.. this req is loaded into a pte machine
|
||||
tlb_htw_req1_pending_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1438,6 +1555,7 @@ tlb_htw_req1_pending_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req1_pending_offset),
|
||||
din => tlb_htw_req1_pending_d,
|
||||
dout => tlb_htw_req1_pending_q);
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req1_tag_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req1_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1455,6 +1573,7 @@ tlb_htw_req1_tag_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req1_tag_offset to tlb_htw_req1_tag_offset+tlb_htw_req1_tag_q'length-1),
|
||||
din => tlb_htw_req1_tag_d,
|
||||
dout => tlb_htw_req1_tag_q );
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req1_way_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req1_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1472,6 +1591,7 @@ tlb_htw_req1_way_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req1_way_offset to tlb_htw_req1_way_offset+tlb_htw_req1_way_q'length-1),
|
||||
din => tlb_htw_req1_way_d,
|
||||
dout => tlb_htw_req1_way_q );
|
||||
-- tlb request valid latches
|
||||
tlb_htw_req2_valid_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1489,6 +1609,7 @@ tlb_htw_req2_valid_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req2_valid_offset),
|
||||
din => tlb_htw_req2_valid_d,
|
||||
dout => tlb_htw_req2_valid_q);
|
||||
-- tlb request pending latches.. this req is loaded into a pte machine
|
||||
tlb_htw_req2_pending_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1506,6 +1627,7 @@ tlb_htw_req2_pending_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req2_pending_offset),
|
||||
din => tlb_htw_req2_pending_d,
|
||||
dout => tlb_htw_req2_pending_q);
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req2_tag_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req2_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1523,6 +1645,7 @@ tlb_htw_req2_tag_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req2_tag_offset to tlb_htw_req2_tag_offset+tlb_htw_req2_tag_q'length-1),
|
||||
din => tlb_htw_req2_tag_d,
|
||||
dout => tlb_htw_req2_tag_q );
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req2_way_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req2_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1540,6 +1663,7 @@ tlb_htw_req2_way_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req2_way_offset to tlb_htw_req2_way_offset+tlb_htw_req2_way_q'length-1),
|
||||
din => tlb_htw_req2_way_d,
|
||||
dout => tlb_htw_req2_way_q );
|
||||
-- tlb request valid latches
|
||||
tlb_htw_req3_valid_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1574,6 +1698,7 @@ tlb_htw_req3_pending_latch: tri_rlmlatch_p
|
||||
scout => sov_0(tlb_htw_req3_pending_offset),
|
||||
din => tlb_htw_req3_pending_d,
|
||||
dout => tlb_htw_req3_pending_q);
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req3_tag_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req3_tag_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -1591,6 +1716,7 @@ tlb_htw_req3_tag_latch: tri_rlmreg_p
|
||||
scout => sov_0(tlb_htw_req3_tag_offset to tlb_htw_req3_tag_offset+tlb_htw_req3_tag_q'length-1),
|
||||
din => tlb_htw_req3_tag_d,
|
||||
dout => tlb_htw_req3_tag_q );
|
||||
-- tlb request tag latches
|
||||
tlb_htw_req3_way_latch: tri_rlmreg_p
|
||||
generic map (width => tlb_htw_req3_way_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2067,6 +2193,7 @@ ptereload_ptr_latch: tri_rlmlatch_p
|
||||
scout => sov_1(ptereload_ptr_offset),
|
||||
din => ptereload_ptr_d,
|
||||
dout => ptereload_ptr_q);
|
||||
-- t minus 1 phase latches
|
||||
reld_core_tag_tm1_latch: tri_rlmreg_p
|
||||
generic map (width => reld_core_tag_tm1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2152,6 +2279,7 @@ reld_data_vld_tm1_latch: tri_rlmlatch_p
|
||||
scout => sov_1(reld_data_vld_tm1_offset),
|
||||
din => reld_data_vld_tm1_d,
|
||||
dout => reld_data_vld_tm1_q);
|
||||
-- t phase latches
|
||||
reld_core_tag_t_latch: tri_rlmreg_p
|
||||
generic map (width => reld_core_tag_t_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2237,6 +2365,7 @@ reld_data_vld_t_latch: tri_rlmlatch_p
|
||||
scout => sov_1(reld_data_vld_t_offset),
|
||||
din => reld_data_vld_t_d,
|
||||
dout => reld_data_vld_t_q);
|
||||
-- t plus 1 phase latches
|
||||
reld_core_tag_tp1_latch: tri_rlmreg_p
|
||||
generic map (width => reld_core_tag_tp1_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2339,6 +2468,7 @@ reld_data_tp1_latch: tri_rlmreg_p
|
||||
scout => sov_1(reld_data_tp1_offset to reld_data_tp1_offset+reld_data_tp1_q'length-1),
|
||||
din => reld_data_tp1_d,
|
||||
dout => reld_data_tp1_q );
|
||||
-- t plus 2 phase latches
|
||||
reld_core_tag_tp2_latch: tri_rlmreg_p
|
||||
generic map (width => reld_core_tag_tp2_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2475,6 +2605,7 @@ reld_ecc_err_ue_tp2_latch: tri_rlmlatch_p
|
||||
scout => sov_1(reld_ecc_err_ue_tp2_offset),
|
||||
din => reld_ecc_err_ue_tp2_d,
|
||||
dout => reld_ecc_err_ue_tp2_q);
|
||||
-- t plus 3 phase
|
||||
pte0_reld_data_tp3_latch: tri_rlmreg_p
|
||||
generic map (width => pte0_reld_data_tp3_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2577,6 +2708,9 @@ spare_b_latch: tri_rlmreg_p
|
||||
scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1),
|
||||
din => spare_b_q,
|
||||
dout => spare_b_q );
|
||||
--------------------------------------------------
|
||||
-- thold/sg latches
|
||||
--------------------------------------------------
|
||||
perv_2to1_reg: tri_plat
|
||||
generic map (width => 3, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2617,9 +2751,11 @@ perv_lcbor_func_slp_sl: tri_lcbor
|
||||
act_dis => lcb_act_dis_dc,
|
||||
forcee => pc_func_slp_sl_force,
|
||||
thold_b => pc_func_slp_sl_thold_0_b);
|
||||
-----------------------------------------------------------------------
|
||||
-- Scan
|
||||
-----------------------------------------------------------------------
|
||||
siv_0(0 TO scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0);
|
||||
ac_func_scan_out(0) <= sov_0(0);
|
||||
siv_1(0 TO scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1);
|
||||
ac_func_scan_out(1) <= sov_1(0);
|
||||
END MMQ_HTW;
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@ library tri;
|
||||
use tri.tri_latches_pkg.all;
|
||||
|
||||
entity mmq_perv is
|
||||
generic(expand_type : integer := 2 );
|
||||
generic(expand_type : integer := 2 ); -- 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
|
||||
port(
|
||||
vdd : inout power_logic;
|
||||
gnd : inout power_logic;
|
||||
@ -92,6 +92,7 @@ port(
|
||||
g8t_gptr_lcb_mpw2_dc_b : out std_ulogic;
|
||||
|
||||
|
||||
-- abist engine controls for arrays from pervasive
|
||||
pc_mm_abist_dcomp_g6t_2r : in std_ulogic_vector(0 to 3);
|
||||
pc_mm_abist_di_0 : in std_ulogic_vector(0 to 3);
|
||||
pc_mm_abist_di_g6t_2r : in std_ulogic_vector(0 to 3);
|
||||
@ -119,8 +120,9 @@ port(
|
||||
pc_mm_abist_di_g6t_2r_q : out std_ulogic_vector(0 to 3);
|
||||
pc_mm_abist_g6t_r_wb_q : out std_ulogic;
|
||||
|
||||
-- BOLT-ON pervasive for asic
|
||||
pc_mm_bolt_sl_thold_3 : in std_ulogic;
|
||||
pc_mm_bo_enable_3 : in std_ulogic;
|
||||
pc_mm_bo_enable_3 : in std_ulogic; -- general bolt-on enable
|
||||
pc_mm_bolt_sl_thold_0 : out std_ulogic;
|
||||
pc_mm_bo_enable_2 : out std_ulogic;
|
||||
|
||||
@ -147,12 +149,12 @@ port(
|
||||
abst_scan_out_int : in std_ulogic_vector(0 to 1);
|
||||
abst_scan_out : out std_ulogic_vector(0 to 1);
|
||||
|
||||
bcfg_scan_in : in std_ulogic;
|
||||
bcfg_scan_in : in std_ulogic; -- config latches that are setup same on all cores
|
||||
bcfg_scan_in_int : out std_ulogic;
|
||||
bcfg_scan_out_int : in std_ulogic;
|
||||
bcfg_scan_out : out std_ulogic;
|
||||
|
||||
ccfg_scan_in : in std_ulogic;
|
||||
ccfg_scan_in : in std_ulogic; -- config latches that could be setup differently on multiple cores
|
||||
ccfg_scan_in_int : out std_ulogic;
|
||||
ccfg_scan_out_int : in std_ulogic;
|
||||
ccfg_scan_out : out std_ulogic;
|
||||
@ -170,6 +172,7 @@ port(
|
||||
-- synopsys translate_on
|
||||
|
||||
end mmq_perv;
|
||||
----
|
||||
architecture mmq_perv of mmq_perv is
|
||||
|
||||
signal tidn : std_logic;
|
||||
@ -503,6 +506,7 @@ perv_g8t_gptr_lcbctrl: tri_lcbcntl_array_mac
|
||||
mpw2_dc_b => g8t_gptr_lcb_mpw2_dc_b,
|
||||
scan_out => gptr_scan_out_int);
|
||||
|
||||
--never disable act pins, they are used functionally
|
||||
lcb_act_dis_dc <= '0';
|
||||
g8t_gptr_lcb_act_dis_dc <= '0';
|
||||
g6t_gptr_lcb_act_dis_dc <= '0';
|
||||
@ -523,6 +527,7 @@ bcfg_scan_out <= bcfg_scan_out_q and tc_ac_scan_dis_dc_b;
|
||||
ccfg_scan_out <= ccfg_scan_out_q and tc_ac_scan_dis_dc_b;
|
||||
dcfg_scan_out <= dcfg_scan_out_q and tc_ac_scan_dis_dc_b;
|
||||
|
||||
-- LCBs for scan only staging latches
|
||||
slat_force <= pc_sg_0_int;
|
||||
abst_slat_thold_b <= NOT pc_abst_sl_thold_0_int;
|
||||
time_slat_thold_b <= NOT pc_time_sl_thold_0_int;
|
||||
@ -765,6 +770,9 @@ perv_lcbor_abst_sl: tri_lcbor
|
||||
|
||||
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- abist latches
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
abist_reg: tri_rlmreg_p
|
||||
generic map (init => 0, expand_type => expand_type, width => 42, needs_sreset => 0)
|
||||
@ -810,6 +818,7 @@ abist_siv <= abist_sov(1 to abist_sov'right) & abst_scan_in_q(0);
|
||||
abst_scan_in_int(0) <= abist_sov(0);
|
||||
abst_scan_in_int(1) <= abst_scan_in_q(1);
|
||||
|
||||
-- unused spare signal assignments
|
||||
unused_dc(0) <= PC_FCE_0_INT;
|
||||
unused_dc(1) <= PC_CFG_SLP_SL_THOLD_0_INT;
|
||||
unused_dc(2) <= PC_FUNC_NSL_THOLD_0_INT;
|
||||
@ -819,4 +828,3 @@ unused_dc(5) <= or_reduce(PC_FUNC_SLP_SL_FORCE_INT);
|
||||
|
||||
|
||||
end mmq_perv;
|
||||
|
||||
|
||||
@ -9,6 +9,11 @@
|
||||
|
||||
|
||||
|
||||
--********************************************************************
|
||||
--* TITLE: Memory Management Unit Special Purpose Registers
|
||||
--* NAME: mmq_spr.vhdl
|
||||
--*********************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
@ -383,12 +388,21 @@ constant Spr_Addr_LRATPS : std_ulogic_vector(0 to 9) := "0101010111";
|
||||
constant Spr_Addr_EPTCFG : std_ulogic_vector(0 to 9) := "0101011110";
|
||||
constant Spr_Addr_LPER : std_ulogic_vector(0 to 9) := "0000111000";
|
||||
constant Spr_Addr_LPERU : std_ulogic_vector(0 to 9) := "0000111001";
|
||||
-- MMUCFG: 32:35 resv, 36:39 LPIDSIZE=0x8, 40:46 RASIZE=0x2a, 47 LRAT bcfg, 48 TWC bcfg,
|
||||
-- 49:52 resv, 53:57 PIDSIZE=0xd, 58:59 resv, 60:61 NTLBS=0b00, 62:63 MAVN=0b01
|
||||
constant Spr_Data_MMUCFG : std_ulogic_vector(32 to 63) := "00001000010101011000001101000001";
|
||||
-- TLB0CFG: 32:39 ASSOC=0x04, 40:44 resv, 45 PT bcfg, 46 IND bcfg, 47 GTWE bcfg,
|
||||
-- 48 IPROT=1, 49 resv, 50 HES=1, 51 resv, 52:63 NENTRY=0x200
|
||||
constant Spr_Data_TLB0CFG : std_ulogic_vector(32 to 63) := "00000100000000001010001000000000";
|
||||
-- TLB0PS: 32:63 PS31-PS0=0x0010_4444 (PS20, PS14, PS10, PS6, PS2 = 1, others = 0)
|
||||
constant Spr_Data_TLB0PS : std_ulogic_vector(32 to 63) := "00000000000100000100010001000100";
|
||||
-- LRATCFG: 32:39 ASSOC=0x00, 40:46 LASIZE=0x2a, 47:49 resv, 50 LPID=1, 51 resv, 52:63 NENTRY=0x008
|
||||
constant Spr_Data_LRATCFG : std_ulogic_vector(32 to 63) := "00000000010101000010000000001000";
|
||||
-- LRATPS: 32:63 PS31-PS0=0x5154_4400 (PS30, PS28, PS24, PS22, PS20, PS18, PS14, PS10 = 1, others = 0)
|
||||
constant Spr_Data_LRATPS : std_ulogic_vector(32 to 63) := "01010001010101000100010000000000";
|
||||
-- EPTCFG: 32:43 resv, 44:48 PS1=0x12, 49:53 SPS1=0x06, 54:58 PS0=0x0a, 59:63 SPS0=0x02
|
||||
constant Spr_Data_EPTCFG : std_ulogic_vector(32 to 63) := "00000000000010010001100101000010";
|
||||
-- latches scan chain constants
|
||||
constant spr_ctl_in_offset : natural := 0;
|
||||
constant spr_etid_in_offset : natural := spr_ctl_in_offset + spr_ctl_width;
|
||||
constant spr_addr_in_offset : natural := spr_etid_in_offset + spr_etid_width;
|
||||
@ -431,6 +445,7 @@ constant spr_mmu_act_offset : natural := spare_a_offset + 32;
|
||||
constant spr_val_act_offset : natural := spr_mmu_act_offset + thdid_width +1;
|
||||
constant cswitch_offset : natural := spr_val_act_offset + 4;
|
||||
constant scan_right_0 : natural := cswitch_offset + 4 -1;
|
||||
-- MAS register constants
|
||||
constant spr_match_mmucsr0_offset : natural := 0;
|
||||
constant spr_match_mmucfg_offset : natural := spr_match_mmucsr0_offset + 1;
|
||||
constant spr_match_tlb0cfg_offset : natural := spr_match_mmucfg_offset + 1;
|
||||
@ -619,6 +634,7 @@ constant lper_3_lps_offset : natural := lper_3_alpn_offset + real_addr
|
||||
constant spare_b_offset : natural := lper_3_lps_offset + 4;
|
||||
constant cat_emf_act_offset : natural := spare_b_offset + 64;
|
||||
constant scan_right_1 : natural := cat_emf_act_offset + thdid_width -1;
|
||||
-- boot config scan bits
|
||||
constant mmucfg_offset : natural := 0;
|
||||
constant tlb0cfg_offset : natural := mmucfg_offset + 2;
|
||||
constant mmucr1_offset : natural := tlb0cfg_offset + 3;
|
||||
@ -736,6 +752,7 @@ signal spr_match_mas56_64b : std_ulogic;
|
||||
signal spr_match_mas73_64b : std_ulogic;
|
||||
signal spr_match_mas81_64b : std_ulogic;
|
||||
signal spr_match_64b, spr_match_64b_q : std_ulogic;
|
||||
-- added input latches for timing with adding numerous mas regs
|
||||
signal spr_ctl_in_d, spr_ctl_in_q : std_ulogic_vector(0 to spr_ctl_width-1);
|
||||
signal spr_etid_in_d, spr_etid_in_q : std_ulogic_vector(0 to spr_etid_width-1);
|
||||
signal spr_addr_in_d, spr_addr_in_q : std_ulogic_vector(0 to spr_addr_width-1);
|
||||
@ -885,6 +902,7 @@ signal lper_2_alpn_d, lper_2_alpn_q : std_ulogic_vector(64-real_ad
|
||||
signal lper_2_lps_d, lper_2_lps_q : std_ulogic_vector(60 to 63);
|
||||
signal lper_3_alpn_d, lper_3_alpn_q : std_ulogic_vector(64-real_addr_width to 51);
|
||||
signal lper_3_lps_d, lper_3_lps_q : std_ulogic_vector(60 to 63);
|
||||
-- timing nsl's
|
||||
signal iu_mm_ierat_mmucr0_q : std_ulogic_vector(0 to 17);
|
||||
signal iu_mm_ierat_mmucr0_we_q : std_ulogic_vector(0 to thdid_width-1);
|
||||
signal iu_mm_ierat_mmucr1_q : std_ulogic_vector(0 to 3);
|
||||
@ -898,6 +916,7 @@ signal spare_b_q : std_ulogic_vector(0 to 63);
|
||||
signal unused_dc : std_ulogic_vector(0 to 13);
|
||||
-- synopsys translate_off
|
||||
-- synopsys translate_on
|
||||
-- Pervasive
|
||||
signal pc_sg_1 : std_ulogic;
|
||||
signal pc_sg_0 : std_ulogic;
|
||||
signal pc_fce_1 : std_ulogic;
|
||||
@ -960,6 +979,10 @@ spr_val_act <= spr_val_act_q(0) or spr_val_act_q(1) or spr_val_act_q(2) or spr_v
|
||||
spr_match_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(5);
|
||||
spr_match_mas_act <= spr_val_act_q(0) or spr_val_act_q(1) or mmucr2_act_override(6);
|
||||
spr_mas_data_out_act <= spr_val_act_q(0) or mmucr2_act_override(6);
|
||||
-----------------------------------------------------------------------
|
||||
-- slow spr
|
||||
-----------------------------------------------------------------------
|
||||
-- input latches for spr access
|
||||
spr_ctl_in_d(0) <= xu_mm_slowspr_val;
|
||||
spr_ctl_in_d(1) <= xu_mm_slowspr_rw;
|
||||
spr_ctl_in_d(2) <= xu_mm_slowspr_done;
|
||||
@ -967,6 +990,7 @@ spr_etid_in_d <= xu_mm_slowspr_etid;
|
||||
spr_addr_in_d <= xu_mm_slowspr_addr;
|
||||
spr_addr_in_clone_d <= xu_mm_slowspr_addr;
|
||||
spr_data_in_d <= xu_mm_slowspr_data;
|
||||
-- internal select latches for spr access
|
||||
spr_ctl_int_d <= spr_ctl_in_q;
|
||||
spr_etid_int_d <= spr_etid_in_q;
|
||||
spr_addr_int_d <= spr_addr_in_q;
|
||||
@ -1086,6 +1110,7 @@ pid0_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid0_q='1'
|
||||
pid1_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid1_q;
|
||||
pid2_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid2_q;
|
||||
pid3_d <= spr_data_int_q(64-pid_width to 63) when (spr_match_pid3_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else pid3_q;
|
||||
-- mmucr0: 0-ExtClass, 1-TID_NZ, 2:3-GS/TS, 4:5-TLBSel, 6:19-TID
|
||||
mmucr0_0_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_data_int_q(34 to 37) & spr_data_int_q(50 to 63)
|
||||
when (spr_match_mmucr0_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write)
|
||||
else xu_mm_derat_mmucr0_q(0 to 3) & "11" & mmucr0_0_q(6 to 7) & xu_mm_derat_mmucr0_q(6 to 17)
|
||||
@ -1162,6 +1187,14 @@ mmucr0_3_d <= spr_data_int_q(32) & or_reduce(spr_data_int_q(50 to 63)) & spr_
|
||||
else iu_mm_ierat_mmucr0_q(0 to 3) & "10" & mmucr0_3_q(6 to 11) & iu_mm_ierat_mmucr0_q(10 to 17)
|
||||
when iu_mm_ierat_mmucr0_we_q(3)='1'
|
||||
else mmucr0_3_q;
|
||||
-- mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE,
|
||||
-- 4-Disable any context sync inst from invalidating extclass=0 erat entries,
|
||||
-- 5-Disable isync inst from invalidating extclass=0 erat entries,
|
||||
-- 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID,
|
||||
-- 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ,
|
||||
-- 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN
|
||||
-- 2) mmucr1: merge EEN bits into single field, seperate I/D/T ERRDET bits
|
||||
-- 3) mmucr1: add ICTID, ITTID, DCTID, DTTID, TLBI_REJ, and TLBI_MSB bits
|
||||
mmucr1_d(0 to 16) <= spr_data_int_q(32 to 48) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(0 to 16);
|
||||
mmucr1_d(17) <= (spr_data_int_q(49) and not cswitch_q(1)) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(17);
|
||||
mmucr1_d(18 to 19) <= spr_data_int_q(50 to 51) when (spr_match_mmucr1_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr1_q(18 to 19);
|
||||
@ -1183,7 +1216,9 @@ mmucr1_d(23 to 31) <= (others => '0') when (spr_match_mmucr1_q='1' and spr_ct
|
||||
else "0000" & xu_mm_derat_mmucr1_q when (xu_mm_derat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000")
|
||||
else "00000" & iu_mm_ierat_mmucr1_q when (iu_mm_ierat_mmucr1_we_q='1' and mmucr1_q(20 to 22)="000")
|
||||
else mmucr1_q(23 to 31);
|
||||
-- mmucr2:
|
||||
mmucr2_d(0 to 31) <= spr_data_int_q(32 to 63) when (spr_match_mmucr2_q='1' and spr_ctl_int_q(1)=Spr_RW_Write) else mmucr2_q(0 to 31);
|
||||
-- mmucr3:
|
||||
mmucr3_0_d <= spr_data_int_q(64-mmucr3_width to 63) when (spr_match_mmucr3_0_q='1' and spr_ctl_int_q(1)=Spr_RW_Write)
|
||||
else tlb_mmucr3_x & tlb_mmucr3_rc & tlb_mmucr3_extclass & tlb_mmucr3_class & tlb_mmucr3_wlc & tlb_mmucr3_resvattr & '0' & tlb_mmucr3_thdid
|
||||
when ((tlb_mas_tlbsx_hit='1' or tlb_mas_tlbre='1') and tlb_mas_thdid(0)='1')
|
||||
@ -2008,6 +2043,7 @@ mas8_3_tlpid_d <= spr_data_int_q(56 to 63) when (spr_match_mas8_3_q='1'
|
||||
else lrat_mas8_tlpid when ( (lrat_mas_tlbsx_hit='1' or lrat_mas_tlbre='1') and lrat_mas_thdid(3)='1')
|
||||
else mas8_3_tlpid_q;
|
||||
end generate gen64_mas_d;
|
||||
-- 0: val, 1: rw, 2: done
|
||||
spr_ctl_out_d(0) <= spr_ctl_int_q(0);
|
||||
spr_ctl_out_d(1) <= spr_ctl_int_q(1);
|
||||
spr_ctl_out_d(2) <= spr_ctl_int_q(2) or spr_match_any_mmu_q;
|
||||
@ -2204,6 +2240,12 @@ mm_xu_derat_mmucr0_1 <= mmucr0_1_q;
|
||||
mm_xu_derat_mmucr0_2 <= mmucr0_2_q;
|
||||
mm_xu_derat_mmucr0_3 <= mmucr0_3_q;
|
||||
mm_xu_derat_mmucr1 <= mmucr1_q(1) & mmucr1_q(2 to 5) & mmucr1_q(8 to 9) & mmucr1_q(14 to 16);
|
||||
-- mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE,
|
||||
-- 4-Disable any context sync inst from invalidating extclass=0 erat entries,
|
||||
-- 5-Disable isync inst from invalidating extclass=0 erat entries,
|
||||
-- 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID,
|
||||
-- 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ,
|
||||
-- 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN
|
||||
pid0 <= pid0_q;
|
||||
pid1 <= pid1_q;
|
||||
pid2 <= pid2_q;
|
||||
@ -2350,6 +2392,7 @@ mas8_3_tgs <= mas8_3_tgs_q;
|
||||
mas8_3_vf <= mas8_3_vf_q;
|
||||
mas8_3_tlpid <= mas8_3_tlpid_q;
|
||||
mmucsr0_tlb0fi <= mmucsr0_tlb0fi_q;
|
||||
-- debug output formation
|
||||
spr_dbg_slowspr_val_int <= spr_ctl_int_q(0);
|
||||
spr_dbg_slowspr_rw_int <= spr_ctl_int_q(1);
|
||||
spr_dbg_slowspr_etid_int <= spr_etid_int_q;
|
||||
@ -2403,6 +2446,10 @@ unused_dc(10) <= TLB_MAS6_SIND;
|
||||
unused_dc(11) <= or_reduce(LRAT_TAG4_HIT_ENTRY);
|
||||
unused_dc(12) <= or_reduce(bcfg_spare_q);
|
||||
unused_dc(13) <= or_reduce(bcfg_spare_q_b);
|
||||
--------------------------------------------------
|
||||
-- latches
|
||||
--------------------------------------------------
|
||||
-- slow spr daisy-chain latches
|
||||
spr_ctl_in_latch: tri_rlmreg_p
|
||||
generic map (width => spr_ctl_in_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2488,6 +2535,7 @@ spr_data_in_latch: tri_rlmreg_p
|
||||
scout => sov_0(spr_data_in_offset to spr_data_in_offset+spr_data_in_q'length-1),
|
||||
din => spr_data_in_d(64-spr_data_width to 63),
|
||||
dout => spr_data_in_q(64-spr_data_width to 63) );
|
||||
-- these are the spr internal select stage latches below
|
||||
spr_ctl_int_latch: tri_rlmreg_p
|
||||
generic map (width => spr_ctl_int_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2556,6 +2604,7 @@ spr_data_int_latch: tri_rlmreg_p
|
||||
scout => sov_0(spr_data_int_offset to spr_data_int_offset+spr_data_int_q'length-1),
|
||||
din => spr_data_int_d(64-spr_data_width to 63),
|
||||
dout => spr_data_int_q(64-spr_data_width to 63) );
|
||||
-- these are the spr out latches below
|
||||
spr_ctl_out_latch: tri_rlmreg_p
|
||||
generic map (width => spr_ctl_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -2624,6 +2673,7 @@ spr_data_out_latch: tri_rlmreg_p
|
||||
scout => sov_0(spr_data_out_offset to spr_data_out_offset+spr_data_out_q'length-1),
|
||||
din => spr_data_out_d(64-spr_data_width to 63),
|
||||
dout => spr_data_out_q(64-spr_data_width to 63) );
|
||||
-- spr decode match latches for timing
|
||||
spr_match_any_mmu_latch: tri_rlmlatch_p
|
||||
generic map (init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -4120,6 +4170,7 @@ spr_match_64b_latch: tri_rlmlatch_p
|
||||
scout => sov_1(spr_match_64b_offset),
|
||||
din => spr_match_64b,
|
||||
dout => spr_match_64b_q);
|
||||
-- internal mas data output register
|
||||
spr_mas_data_out_latch: tri_rlmreg_p
|
||||
generic map (width => spr_mas_data_out_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -4154,6 +4205,7 @@ spr_match_any_mas_latch: tri_rlmlatch_p
|
||||
scout => sov_1(spr_match_any_mas_offset),
|
||||
din => spr_match_any_mas,
|
||||
dout => spr_match_any_mas_q);
|
||||
-- pid spr's
|
||||
pid0_latch: tri_rlmreg_p
|
||||
generic map (width => pid0_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -6517,6 +6569,10 @@ cswitch_latch: tri_rlmreg_p
|
||||
scout => sov_0(cswitch_offset to cswitch_offset+cswitch_q'length-1),
|
||||
din => cswitch_q,
|
||||
dout => cswitch_q );
|
||||
-- cswitch0: 1=disable side affect of clearing I/D/TERRDET and EEN when reading mmucr1
|
||||
-- cswitch1: 1=disable mmucr1.tlbwe_binv bit (make it look like it is reserved per dd1)
|
||||
-- cswitch2: reserved
|
||||
-- cswitch3: reserved
|
||||
cat_emf_act_latch: tri_rlmreg_p
|
||||
generic map (width => cat_emf_act_q'length, init => 0, needs_sreset => 1, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -6568,6 +6624,7 @@ spare_b_latch: tri_rlmreg_p
|
||||
scout => sov_1(spare_b_offset to spare_b_offset+spare_b_q'length-1),
|
||||
din => spare_b_q,
|
||||
dout => spare_b_q );
|
||||
-- non-scannable timing latches
|
||||
iu_mm_ierat_mmucr0_latch : tri_regk
|
||||
generic map (width => iu_mm_ierat_mmucr0_q'length, init => 0, expand_type => expand_type, needs_sreset => 0)
|
||||
port map (nclk => nclk, vd => vdd, gd => gnd,
|
||||
@ -6654,6 +6711,10 @@ mm_erat_mmucr1_we_latch : tri_regk
|
||||
din(1) => xu_mm_derat_mmucr1_we,
|
||||
dout(0) => iu_mm_ierat_mmucr1_we_q,
|
||||
dout(1) => xu_mm_derat_mmucr1_we_q);
|
||||
--------------------------------------------------
|
||||
-- scan only latches for boot config
|
||||
-- mmucr1, mmucr2, and mmucr3 also in boot config
|
||||
--------------------------------------------------
|
||||
mpg_bcfg_gen: if expand_type /= 1 generate
|
||||
mmucfg_47to48_latch: tri_slat_scan
|
||||
generic map (width => 2, init => std_ulogic_vector( to_unsigned( bcfg_mmucfg_value, 2 ) ),
|
||||
@ -6742,6 +6803,64 @@ bcfg_spare_latch: tri_rlmreg_p
|
||||
din => bcfg_spare_q,
|
||||
dout => bcfg_spare_q );
|
||||
end generate fpga_bcfg_gen;
|
||||
-- Latch counts
|
||||
-- 3319
|
||||
-- spr_ctl_in_q 3
|
||||
-- spr_etid_in_q 2
|
||||
-- spr_addr_in_q 10
|
||||
-- spr_data_in_q 64 79
|
||||
-- spr_ctl_int_q 3
|
||||
-- spr_etid_int_q 2
|
||||
-- spr_addr_int_q 10
|
||||
-- spr_data_int_q 64 79
|
||||
-- spr_ctl_out_q 3
|
||||
-- spr_etid_out_q 2
|
||||
-- spr_addr_out_q 10
|
||||
-- spr_data_out_q 64 79
|
||||
-- lper_ 0:3 _alpn_q 30 x 4
|
||||
-- lper_ 0:3 _lps_q 4 x 4 136
|
||||
-- pid 0:3 _q 14 x 4
|
||||
-- mmucr0_ 0:3 _q 20 x 4
|
||||
-- mmucr1_q 32
|
||||
-- mmucr2_q 32
|
||||
-- mmucr3_ 0:3 _q 15 x 4
|
||||
-- lpidr_q 8
|
||||
-- mmucsr0_tlb0fi_q 1 269
|
||||
-- mas0_<t>_atsel_q 1 x 4 : std_ulogic;
|
||||
-- mas0_<t>_esel_q 3 x 4 : std_ulogic_vector(0 to 2);
|
||||
-- mas0_<t>_hes_q 1 x 4 : std_ulogic;
|
||||
-- mas0_<t>_wq_q 2 x 4 : std_ulogic_vector(0 to 1);
|
||||
-- mas1_<t>_v_q 1 x 4 : std_ulogic;
|
||||
-- mas1_<t>_iprot_q 1 x 4 : std_ulogic;
|
||||
-- mas1_<t>_tid_q 14 x 4 : std_ulogic_vector(0 to 13);
|
||||
-- mas1_<t>_ind_q 1 x 4 : std_ulogic;
|
||||
-- mas1_<t>_ts_q 1 x 4 : std_ulogic;
|
||||
-- mas1_<t>_tsize_q 4 x 4 : std_ulogic_vector(0 to 3);
|
||||
-- mas2_<t>_epn_q 52 x 4 : std_ulogic_vector(64-spr_data_width to 51);
|
||||
-- mas2_<t>_wimge_q 5 x 4 : std_ulogic_vector(0 to 4);
|
||||
-- mas3_<t>_rpnl_q 21 x 4 : std_ulogic_vector(32 to 52);
|
||||
-- mas3_<t>_ubits_q 4 x 4 : std_ulogic_vector(0 to 3);
|
||||
-- mas3_<t>_usxwr_q 6 x 4 : std_ulogic_vector(0 to 5);
|
||||
-- mas4_<t>_indd_q 1 x 4 : std_ulogic;
|
||||
-- mas4_<t>_tsized_q 4 x 4 : std_ulogic_vector(0 to 3);
|
||||
-- mas4_<t>_wimged_q 5 x 4 : std_ulogic_vector(0 to 4);
|
||||
-- mas5_<t>_sgs_q 1 x 4 : std_ulogic;
|
||||
-- mas5_<t>_slpid_q 8 x 4 : std_ulogic_vector(0 to 7);
|
||||
-- mas6_<t>_spid_q 14 x 4 : std_ulogic_vector(0 to 13);
|
||||
-- mas6_<t>_isize_q 4 x 4 : std_ulogic_vector(0 to 3);
|
||||
-- mas6_<t>_sind_q 1 x 4 : std_ulogic;
|
||||
-- mas6_<t>_sas_q 1 x 4 : std_ulogic;
|
||||
-- mas7_<t>_rpnu_q 10 x 4 : std_ulogic_vector(22 to 31);
|
||||
-- mas8_<t>_tgs_q 1 x 4 : std_ulogic;
|
||||
-- mas8_<t>_vf_q 1 x 4 : std_ulogic;
|
||||
-- mas8_<t>_tlpid_q 8 x 4 : std_ulogic_vector(0 to 7);
|
||||
-- subtotal 176 x 4 = 704
|
||||
----------------------------------------------------------------
|
||||
-- total 1346
|
||||
--------------------------------------------------
|
||||
--------------------------------------------------
|
||||
-- thold/sg latches
|
||||
--------------------------------------------------
|
||||
perv_2to1_reg: tri_plat
|
||||
generic map (width => 7, expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -6814,8 +6933,13 @@ perv_lcbor_func_slp_nsl: tri_lcbor
|
||||
act_dis => tidn,
|
||||
forcee => pc_func_slp_nsl_force,
|
||||
thold_b => pc_func_slp_nsl_thold_0_b);
|
||||
-- these terms in the absence of another lcbor component
|
||||
-- that drives the thold_b and force into the bcfg_lcb for slat's
|
||||
pc_cfg_sl_thold_0_b <= NOT pc_cfg_sl_thold_0;
|
||||
pc_cfg_sl_force <= pc_sg_0;
|
||||
--------------------------------------------------
|
||||
-- local clock buffer for boot config
|
||||
--------------------------------------------------
|
||||
bcfg_lcb: tri_lcbs
|
||||
generic map (expand_type => expand_type)
|
||||
port map (vd => vdd,
|
||||
@ -6826,6 +6950,9 @@ bcfg_lcb: tri_lcbs
|
||||
thold_b => pc_cfg_sl_thold_0_b,
|
||||
dclk => lcb_dclk,
|
||||
lclk => lcb_lclk );
|
||||
-----------------------------------------------------------------------
|
||||
-- Scan
|
||||
-----------------------------------------------------------------------
|
||||
siv_0(0 to scan_right_0) <= sov_0(1 to scan_right_0) & ac_func_scan_in(0);
|
||||
ac_func_scan_out(0) <= sov_0(0);
|
||||
siv_1(0 to scan_right_1) <= sov_1(1 to scan_right_1) & ac_func_scan_in(1);
|
||||
@ -6833,4 +6960,3 @@ ac_func_scan_out(1) <= sov_1(0);
|
||||
bsiv(0 to boot_scan_right) <= bsov(1 to boot_scan_right) & ac_bcfg_scan_in;
|
||||
ac_bcfg_scan_out <= bsov(0);
|
||||
end mmq_spr;
|
||||
|
||||
|
||||
@ -7,8 +7,12 @@
|
||||
-- This README will be updated with additional information when OpenPOWER's
|
||||
-- license is available.
|
||||
|
||||
-- Description: XU LSU Compare Logic
|
||||
|
||||
|
||||
-- ###################################################################
|
||||
-- ## Address decoder
|
||||
-- ###################################################################
|
||||
|
||||
|
||||
LIBRARY ieee; USE ieee.std_logic_1164.all;
|
||||
@ -23,7 +27,7 @@ LIBRARY tri; USE tri.tri_latches_pkg.all;
|
||||
LIBRARY clib ;
|
||||
|
||||
entity xuq_lsu_cmp_cmp31 is
|
||||
generic( expand_type: integer := 2 );
|
||||
generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );
|
||||
port(
|
||||
d0 :in std_ulogic_vector(0 to 30);
|
||||
d1 :in std_ulogic_vector(0 to 30);
|
||||
@ -34,7 +38,7 @@ port(
|
||||
|
||||
|
||||
|
||||
end xuq_lsu_cmp_cmp31;
|
||||
end xuq_lsu_cmp_cmp31; -- ENTITY
|
||||
|
||||
architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is
|
||||
constant tiup : std_ulogic := '1';
|
||||
@ -46,12 +50,6 @@ architecture xuq_lsu_cmp_cmp31 of xuq_lsu_cmp_cmp31 is
|
||||
signal eq18_b : std_ulogic_vector(0 to 1);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
@ -80,9 +78,8 @@ begin
|
||||
u_eq18_00: eq18_b( 0) <= not( eq06(0) and eq06(1) and eq06(2) );
|
||||
u_eq18_01: eq18_b( 1) <= not( eq06(3) and eq06(4) and eq06(5) );
|
||||
|
||||
u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) );
|
||||
u_eq36_00: eq <= not( eq18_b( 0) or eq18_b( 1) ); -- output
|
||||
|
||||
|
||||
|
||||
end;
|
||||
|
||||
end; -- xuq_lsu_cmp_cmp31 ARCHITECTURE
|
||||
|
||||
@ -7,8 +7,12 @@
|
||||
-- This README will be updated with additional information when OpenPOWER's
|
||||
-- license is available.
|
||||
|
||||
-- Description: XU LSU Compare Logic
|
||||
|
||||
|
||||
-- ###################################################################
|
||||
-- ## Address decoder
|
||||
-- ###################################################################
|
||||
|
||||
|
||||
LIBRARY ieee; USE ieee.std_logic_1164.all;
|
||||
@ -23,9 +27,9 @@ LIBRARY tri; USE tri.tri_latches_pkg.all;
|
||||
LIBRARY clib ;
|
||||
|
||||
entity xuq_lsu_cmp_cmp36e is
|
||||
generic( expand_type: integer := 2 );
|
||||
generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );
|
||||
port(
|
||||
enable_lsb :in std_ulogic;
|
||||
enable_lsb :in std_ulogic; -- when "0" the LSB is disabled
|
||||
d0 :in std_ulogic_vector(0 to 35);
|
||||
d1 :in std_ulogic_vector(0 to 35);
|
||||
eq :out std_ulogic
|
||||
@ -35,7 +39,7 @@ port(
|
||||
|
||||
|
||||
|
||||
end xuq_lsu_cmp_cmp36e;
|
||||
end xuq_lsu_cmp_cmp36e; -- ENTITY
|
||||
|
||||
architecture xuq_lsu_cmp_cmp36e of xuq_lsu_cmp_cmp36e is
|
||||
constant tiup : std_ulogic := '1';
|
||||
@ -48,13 +52,6 @@ architecture xuq_lsu_cmp_cmp36e of xuq_lsu_cmp_cmp36e is
|
||||
signal eq24_b :std_ulogic_vector(0 to 1);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
@ -100,13 +97,7 @@ begin
|
||||
u_eq_07: eq24_b( 0) <= not( eq08 ( 0) and eq08 ( 1) and eq08 ( 2) );
|
||||
u_eq_23: eq24_b( 1) <= not( eq08 ( 3) and eq08 ( 4) );
|
||||
|
||||
u_eq_15: eq <= not( eq24_b( 0) or eq24_b( 1) );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end;
|
||||
|
||||
u_eq_15: eq <= not( eq24_b( 0) or eq24_b( 1) ); -- output
|
||||
|
||||
|
||||
end; -- xuq_lsu_cmp_cmp36e ARCHITECTURE
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user