diff --git a/.github/workflows/vunit_tests.yml b/.github/workflows/vunit_tests.yml new file mode 100644 index 0000000..3c79f5b --- /dev/null +++ b/.github/workflows/vunit_tests.yml @@ -0,0 +1,13 @@ +name: VUnit Tests +on: [push, pull_request] +jobs: + test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: srt32/git-actions@v0.0.3 + with: + args: git update-index --chmod=+x run.py + - uses: VUnit/vunit_action@master + with: + cmd: python3 ./run.py diff --git a/README.md b/README.md index 54799ad..cf82b46 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,5 @@ +![](https://github.com/openpower-cores/a2i/workflows/VUnit%20Tests/badge.svg) + # A2I ## The Project @@ -8,7 +10,7 @@ See [Project Info](rel/readme.md) for details. ## The Core The [A2I core](rel/doc/A2_BGQ.pdf) was created as a high-frequency four-threaded design, optimized for throughput and targeted for 3+ GHz in 45nm technology. -It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection. +It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection. ## The History @@ -27,7 +29,7 @@ There may be uses for this core where a full feature-set is needed, and its limi The design of the A2L2 interface (core-to-L2/nest) is straightforward, and offers multiple configurable options for data interfacing. There is also some configurability for handling certain Power-specific features (core vs. L2). -The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc. +The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc. ### Technology Scaling diff --git a/rel/sim/unimacro/bram_tdp_macro_mock.vhdl b/rel/sim/unimacro/bram_tdp_macro_mock.vhdl new file mode 100644 index 0000000..7981623 --- /dev/null +++ b/rel/sim/unimacro/bram_tdp_macro_mock.vhdl @@ -0,0 +1,185 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity BRAM_TDP_MACRO is + generic ( + BRAM_SIZE : string; + DEVICE : string; + DOA_REG : integer; + DOB_REG : integer; + INIT_A : bit_vector; + INIT_B : bit_vector; + INIT_FILE : string; + READ_WIDTH_A : integer; + READ_WIDTH_B : integer; + SIM_COLLISION_CHECK : string; + SRVAL_A : bit_vector; + SRVAL_B : bit_vector; + WRITE_MODE_A : string; + WRITE_MODE_B : string; + WRITE_WIDTH_A : integer; + WRITE_WIDTH_B : integer; + INIT_00 : bit_vector; + INIT_01 : bit_vector; + INIT_02 : bit_vector; + INIT_03 : bit_vector; + INIT_04 : bit_vector; + INIT_05 : bit_vector; + INIT_06 : bit_vector; + INIT_07 : bit_vector; + INIT_08 : bit_vector; + INIT_09 : bit_vector; + INIT_0A : bit_vector; + INIT_0B : bit_vector; + INIT_0C : bit_vector; + INIT_0D : bit_vector; + INIT_0E : bit_vector; + INIT_0F : bit_vector; + INIT_10 : bit_vector; + INIT_11 : bit_vector; + INIT_12 : bit_vector; + INIT_13 : bit_vector; + INIT_14 : bit_vector; + INIT_15 : bit_vector; + INIT_16 : bit_vector; + INIT_17 : bit_vector; + INIT_18 : bit_vector; + INIT_19 : bit_vector; + INIT_1A : bit_vector; + INIT_1B : bit_vector; + INIT_1C : bit_vector; + INIT_1D : bit_vector; + INIT_1E : bit_vector; + INIT_1F : bit_vector; + INIT_20 : bit_vector; + INIT_21 : bit_vector; + INIT_22 : bit_vector; + INIT_23 : bit_vector; + INIT_24 : bit_vector; + INIT_25 : bit_vector; + INIT_26 : bit_vector; + INIT_27 : bit_vector; + INIT_28 : bit_vector; + INIT_29 : bit_vector; + INIT_2A : bit_vector; + INIT_2B : bit_vector; + INIT_2C : bit_vector; + INIT_2D : bit_vector; + INIT_2E : bit_vector; + INIT_2F : bit_vector; + INIT_30 : bit_vector; + INIT_31 : bit_vector; + INIT_32 : bit_vector; + INIT_33 : bit_vector; + INIT_34 : bit_vector; + INIT_35 : bit_vector; + INIT_36 : bit_vector; + INIT_37 : bit_vector; + INIT_38 : bit_vector; + INIT_39 : bit_vector; + INIT_3A : bit_vector; + INIT_3B : bit_vector; + INIT_3C : bit_vector; + INIT_3D : bit_vector; + INIT_3E : bit_vector; + INIT_3F : bit_vector; + INIT_40 : bit_vector; + INIT_41 : bit_vector; + INIT_42 : bit_vector; + INIT_43 : bit_vector; + INIT_44 : bit_vector; + INIT_45 : bit_vector; + INIT_46 : bit_vector; + INIT_47 : bit_vector; + INIT_48 : bit_vector; + INIT_49 : bit_vector; + INIT_4A : bit_vector; + INIT_4B : bit_vector; + INIT_4C : bit_vector; + INIT_4D : bit_vector; + INIT_4E : bit_vector; + INIT_4F : bit_vector; + INIT_50 : bit_vector; + INIT_51 : bit_vector; + INIT_52 : bit_vector; + INIT_53 : bit_vector; + INIT_54 : bit_vector; + INIT_55 : bit_vector; + INIT_56 : bit_vector; + INIT_57 : bit_vector; + INIT_58 : bit_vector; + INIT_59 : bit_vector; + INIT_5A : bit_vector; + INIT_5B : bit_vector; + INIT_5C : bit_vector; + INIT_5D : bit_vector; + INIT_5E : bit_vector; + INIT_5F : bit_vector; + INIT_60 : bit_vector; + INIT_61 : bit_vector; + INIT_62 : bit_vector; + INIT_63 : bit_vector; + INIT_64 : bit_vector; + INIT_65 : bit_vector; + INIT_66 : bit_vector; + INIT_67 : bit_vector; + INIT_68 : bit_vector; + INIT_69 : bit_vector; + INIT_6A : bit_vector; + INIT_6B : bit_vector; + INIT_6C : bit_vector; + INIT_6D : bit_vector; + INIT_6E : bit_vector; + INIT_6F : bit_vector; + INIT_70 : bit_vector; + INIT_71 : bit_vector; + INIT_72 : bit_vector; + INIT_73 : bit_vector; + INIT_74 : bit_vector; + INIT_75 : bit_vector; + INIT_76 : bit_vector; + INIT_77 : bit_vector; + INIT_78 : bit_vector; + INIT_79 : bit_vector; + INIT_7A : bit_vector; + INIT_7B : bit_vector; + INIT_7C : bit_vector; + INIT_7D : bit_vector; + INIT_7E : bit_vector; + INIT_7F : bit_vector; + INITP_00 : bit_vector; + INITP_01 : bit_vector; + INITP_02 : bit_vector; + INITP_03 : bit_vector; + INITP_04 : bit_vector; + INITP_05 : bit_vector; + INITP_06 : bit_vector; + INITP_07 : bit_vector; + INITP_08 : bit_vector; + INITP_09 : bit_vector; + INITP_0A : bit_vector; + INITP_0B : bit_vector; + INITP_0C : bit_vector; + INITP_0D : bit_vector; + INITP_0E : bit_vector; + INITP_0F : bit_vector + ); +port ( + DOA : out std_logic_vector; + DOB : out std_logic_vector; + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector; + DIB : in std_logic_vector; + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + ); +end entity; diff --git a/rel/sim/unimacro/unimacro_vcomp_mock.vhdl b/rel/sim/unimacro/unimacro_vcomp_mock.vhdl new file mode 100644 index 0000000..8c60f5e --- /dev/null +++ b/rel/sim/unimacro/unimacro_vcomp_mock.vhdl @@ -0,0 +1,187 @@ +library ieee; +use ieee.std_logic_1164.all; + +package vcomponents is + component BRAM_TDP_MACRO + generic ( + BRAM_SIZE : string; + DEVICE : string; + DOA_REG : integer; + DOB_REG : integer; + INIT_A : bit_vector; + INIT_B : bit_vector; + INIT_FILE : string; + READ_WIDTH_A : integer; + READ_WIDTH_B : integer; + SIM_COLLISION_CHECK : string; + SRVAL_A : bit_vector; + SRVAL_B : bit_vector; + WRITE_MODE_A : string; + WRITE_MODE_B : string; + WRITE_WIDTH_A : integer; + WRITE_WIDTH_B : integer; + INIT_00 : bit_vector; + INIT_01 : bit_vector; + INIT_02 : bit_vector; + INIT_03 : bit_vector; + INIT_04 : bit_vector; + INIT_05 : bit_vector; + INIT_06 : bit_vector; + INIT_07 : bit_vector; + INIT_08 : bit_vector; + INIT_09 : bit_vector; + INIT_0A : bit_vector; + INIT_0B : bit_vector; + INIT_0C : bit_vector; + INIT_0D : bit_vector; + INIT_0E : bit_vector; + INIT_0F : bit_vector; + INIT_10 : bit_vector; + INIT_11 : bit_vector; + INIT_12 : bit_vector; + INIT_13 : bit_vector; + INIT_14 : bit_vector; + INIT_15 : bit_vector; + INIT_16 : bit_vector; + INIT_17 : bit_vector; + INIT_18 : bit_vector; + INIT_19 : bit_vector; + INIT_1A : bit_vector; + INIT_1B : bit_vector; + INIT_1C : bit_vector; + INIT_1D : bit_vector; + INIT_1E : bit_vector; + INIT_1F : bit_vector; + INIT_20 : bit_vector; + INIT_21 : bit_vector; + INIT_22 : bit_vector; + INIT_23 : bit_vector; + INIT_24 : bit_vector; + INIT_25 : bit_vector; + INIT_26 : bit_vector; + INIT_27 : bit_vector; + INIT_28 : bit_vector; + INIT_29 : bit_vector; + INIT_2A : bit_vector; + INIT_2B : bit_vector; + INIT_2C : bit_vector; + INIT_2D : bit_vector; + INIT_2E : bit_vector; + INIT_2F : bit_vector; + INIT_30 : bit_vector; + INIT_31 : bit_vector; + INIT_32 : bit_vector; + INIT_33 : bit_vector; + INIT_34 : bit_vector; + INIT_35 : bit_vector; + INIT_36 : bit_vector; + INIT_37 : bit_vector; + INIT_38 : bit_vector; + INIT_39 : bit_vector; + INIT_3A : bit_vector; + INIT_3B : bit_vector; + INIT_3C : bit_vector; + INIT_3D : bit_vector; + INIT_3E : bit_vector; + INIT_3F : bit_vector; + INIT_40 : bit_vector; + INIT_41 : bit_vector; + INIT_42 : bit_vector; + INIT_43 : bit_vector; + INIT_44 : bit_vector; + INIT_45 : bit_vector; + INIT_46 : bit_vector; + INIT_47 : bit_vector; + INIT_48 : bit_vector; + INIT_49 : bit_vector; + INIT_4A : bit_vector; + INIT_4B : bit_vector; + INIT_4C : bit_vector; + INIT_4D : bit_vector; + INIT_4E : bit_vector; + INIT_4F : bit_vector; + INIT_50 : bit_vector; + INIT_51 : bit_vector; + INIT_52 : bit_vector; + INIT_53 : bit_vector; + INIT_54 : bit_vector; + INIT_55 : bit_vector; + INIT_56 : bit_vector; + INIT_57 : bit_vector; + INIT_58 : bit_vector; + INIT_59 : bit_vector; + INIT_5A : bit_vector; + INIT_5B : bit_vector; + INIT_5C : bit_vector; + INIT_5D : bit_vector; + INIT_5E : bit_vector; + INIT_5F : bit_vector; + INIT_60 : bit_vector; + INIT_61 : bit_vector; + INIT_62 : bit_vector; + INIT_63 : bit_vector; + INIT_64 : bit_vector; + INIT_65 : bit_vector; + INIT_66 : bit_vector; + INIT_67 : bit_vector; + INIT_68 : bit_vector; + INIT_69 : bit_vector; + INIT_6A : bit_vector; + INIT_6B : bit_vector; + INIT_6C : bit_vector; + INIT_6D : bit_vector; + INIT_6E : bit_vector; + INIT_6F : bit_vector; + INIT_70 : bit_vector; + INIT_71 : bit_vector; + INIT_72 : bit_vector; + INIT_73 : bit_vector; + INIT_74 : bit_vector; + INIT_75 : bit_vector; + INIT_76 : bit_vector; + INIT_77 : bit_vector; + INIT_78 : bit_vector; + INIT_79 : bit_vector; + INIT_7A : bit_vector; + INIT_7B : bit_vector; + INIT_7C : bit_vector; + INIT_7D : bit_vector; + INIT_7E : bit_vector; + INIT_7F : bit_vector; + INITP_00 : bit_vector; + INITP_01 : bit_vector; + INITP_02 : bit_vector; + INITP_03 : bit_vector; + INITP_04 : bit_vector; + INITP_05 : bit_vector; + INITP_06 : bit_vector; + INITP_07 : bit_vector; + INITP_08 : bit_vector; + INITP_09 : bit_vector; + INITP_0A : bit_vector; + INITP_0B : bit_vector; + INITP_0C : bit_vector; + INITP_0D : bit_vector; + INITP_0E : bit_vector; + INITP_0F : bit_vector + ); + port ( + DOA : out std_logic_vector; + DOB : out std_logic_vector; + ADDRA : in std_logic_vector; + ADDRB : in std_logic_vector; + CLKA : in std_ulogic; + CLKB : in std_ulogic; + DIA : in std_logic_vector; + DIB : in std_logic_vector; + ENA : in std_ulogic; + ENB : in std_ulogic; + REGCEA : in std_ulogic; + REGCEB : in std_ulogic; + RSTA : in std_ulogic; + RSTB : in std_ulogic; + WEA : in std_logic_vector; + WEB : in std_logic_vector + ); + end component; +end package vcomponents; diff --git a/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl index aba65a7..5120312 100644 --- a/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_ao_support.vhdl @@ -46,7 +46,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x1 : function is true; attribute pin_bit_information of gate_ao_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), @@ -76,7 +76,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1 : function is 1; + attribute recursive_synthesis of ao_2x1 : function is true; attribute pin_bit_information of ao_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -106,7 +106,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x1 : function is true; attribute pin_bit_information of gate_aoi_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), @@ -136,7 +136,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1 : function is 1; + attribute recursive_synthesis of aoi_2x1 : function is true; attribute pin_bit_information of aoi_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -166,7 +166,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x1 : function is true; attribute pin_bit_information of gate_oa_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), @@ -196,7 +196,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1 : function is 1; + attribute recursive_synthesis of oa_2x1 : function is true; attribute pin_bit_information of oa_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -226,7 +226,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x1 : function is true; attribute pin_bit_information of gate_oai_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_SCALAR"), @@ -256,7 +256,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1 : function is 1; + attribute recursive_synthesis of oai_2x1 : function is true; attribute pin_bit_information of oai_2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -288,7 +288,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2 : function is 1; + attribute recursive_synthesis of gate_ao_2x2 : function is true; attribute pin_bit_information of gate_ao_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -321,7 +321,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2 : function is 1; + attribute recursive_synthesis of ao_2x2 : function is true; attribute pin_bit_information of ao_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -354,7 +354,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2 : function is true; attribute pin_bit_information of gate_aoi_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -387,7 +387,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2 : function is 1; + attribute recursive_synthesis of aoi_2x2 : function is true; attribute pin_bit_information of aoi_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -420,7 +420,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2 : function is 1; + attribute recursive_synthesis of gate_oa_2x2 : function is true; attribute pin_bit_information of gate_oa_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -453,7 +453,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2 : function is 1; + attribute recursive_synthesis of oa_2x2 : function is true; attribute pin_bit_information of oa_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -486,7 +486,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2 : function is 1; + attribute recursive_synthesis of gate_oai_2x2 : function is true; attribute pin_bit_information of gate_oai_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -519,7 +519,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2 : function is 1; + attribute recursive_synthesis of oai_2x2 : function is true; attribute pin_bit_information of oai_2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -558,7 +558,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x1x1 : function is true; attribute pin_bit_information of gate_ao_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -591,7 +591,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1x1 : function is 1; + attribute recursive_synthesis of ao_2x1x1 : function is true; attribute pin_bit_information of ao_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -624,7 +624,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x1x1 : function is true; attribute pin_bit_information of gate_aoi_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -657,7 +657,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1x1 : function is 1; + attribute recursive_synthesis of aoi_2x1x1 : function is true; attribute pin_bit_information of aoi_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -690,7 +690,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x1x1 : function is true; attribute pin_bit_information of gate_oa_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -723,7 +723,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1x1 : function is 1; + attribute recursive_synthesis of oa_2x1x1 : function is true; attribute pin_bit_information of oa_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -756,7 +756,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x1x1 : function is true; attribute pin_bit_information of gate_oai_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -789,7 +789,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1x1 : function is 1; + attribute recursive_synthesis of oai_2x1x1 : function is true; attribute pin_bit_information of oai_2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -824,7 +824,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x2x1 : function is true; attribute pin_bit_information of gate_ao_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -860,7 +860,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x1 : function is 1; + attribute recursive_synthesis of ao_2x2x1 : function is true; attribute pin_bit_information of ao_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -896,7 +896,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2x1 : function is true; attribute pin_bit_information of gate_aoi_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -932,7 +932,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x1 : function is 1; + attribute recursive_synthesis of aoi_2x2x1 : function is true; attribute pin_bit_information of aoi_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -968,7 +968,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x2x1 : function is true; attribute pin_bit_information of gate_oa_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1004,7 +1004,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x1 : function is 1; + attribute recursive_synthesis of oa_2x2x1 : function is true; attribute pin_bit_information of oa_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1040,7 +1040,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x2x1 : function is true; attribute pin_bit_information of gate_oai_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1076,7 +1076,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x1 : function is 1; + attribute recursive_synthesis of oai_2x2x1 : function is true; attribute pin_bit_information of oai_2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1114,7 +1114,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2 : function is 1; + attribute recursive_synthesis of gate_ao_2x2x2 : function is true; attribute pin_bit_information of gate_ao_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1153,7 +1153,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2 : function is 1; + attribute recursive_synthesis of ao_2x2x2 : function is true; attribute pin_bit_information of ao_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1192,7 +1192,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2x2 : function is true; attribute pin_bit_information of gate_aoi_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1231,7 +1231,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2 : function is 1; + attribute recursive_synthesis of aoi_2x2x2 : function is true; attribute pin_bit_information of aoi_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1270,7 +1270,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2 : function is 1; + attribute recursive_synthesis of gate_oa_2x2x2 : function is true; attribute pin_bit_information of gate_oa_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1309,7 +1309,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2 : function is 1; + attribute recursive_synthesis of oa_2x2x2 : function is true; attribute pin_bit_information of oa_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1348,7 +1348,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2 : function is 1; + attribute recursive_synthesis of gate_oai_2x2x2 : function is true; attribute pin_bit_information of gate_oai_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1387,7 +1387,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2 : function is 1; + attribute recursive_synthesis of oai_2x2x2 : function is true; attribute pin_bit_information of oai_2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1430,7 +1430,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x1x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x1x1x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x1x1x1 : function is true; attribute pin_bit_information of gate_ao_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1466,7 +1466,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x1x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x1x1x1 : function is 1; + attribute recursive_synthesis of ao_2x1x1x1 : function is true; attribute pin_bit_information of ao_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1502,7 +1502,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x1x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x1x1x1 : function is true; attribute pin_bit_information of gate_aoi_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1538,7 +1538,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x1x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x1x1x1 : function is 1; + attribute recursive_synthesis of aoi_2x1x1x1 : function is true; attribute pin_bit_information of aoi_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1574,7 +1574,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x1x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x1x1x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x1x1x1 : function is true; attribute pin_bit_information of gate_oa_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1610,7 +1610,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x1x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x1x1x1 : function is 1; + attribute recursive_synthesis of oa_2x1x1x1 : function is true; attribute pin_bit_information of oa_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1646,7 +1646,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x1x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x1x1x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x1x1x1 : function is true; attribute pin_bit_information of gate_oai_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1682,7 +1682,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x1x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x1x1x1 : function is 1; + attribute recursive_synthesis of oai_2x1x1x1 : function is true; attribute pin_bit_information of oai_2x1x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1720,7 +1720,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x1x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x2x1x1 : function is true; attribute pin_bit_information of gate_ao_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1759,7 +1759,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2x1x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x1x1 : function is 1; + attribute recursive_synthesis of ao_2x2x1x1 : function is true; attribute pin_bit_information of ao_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1798,7 +1798,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2x1x1 : function is true; attribute pin_bit_information of gate_aoi_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1837,7 +1837,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2x1x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x1x1 : function is 1; + attribute recursive_synthesis of aoi_2x2x1x1 : function is true; attribute pin_bit_information of aoi_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1876,7 +1876,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x1x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x2x1x1 : function is true; attribute pin_bit_information of gate_oa_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1915,7 +1915,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2x1x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x1x1 : function is 1; + attribute recursive_synthesis of oa_2x2x1x1 : function is true; attribute pin_bit_information of oa_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1954,7 +1954,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x1x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x2x1x1 : function is true; attribute pin_bit_information of gate_oai_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -1993,7 +1993,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2x1x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x1x1 : function is 1; + attribute recursive_synthesis of oai_2x2x1x1 : function is true; attribute pin_bit_information of oai_2x2x1x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2034,7 +2034,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2x1 : function is 1; + attribute recursive_synthesis of gate_ao_2x2x2x1 : function is true; attribute pin_bit_information of gate_ao_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2076,7 +2076,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2x2x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2x1 : function is 1; + attribute recursive_synthesis of ao_2x2x2x1 : function is true; attribute pin_bit_information of ao_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2118,7 +2118,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2x2x1 : function is true; attribute pin_bit_information of gate_aoi_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2160,7 +2160,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2x2x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2x1 : function is 1; + attribute recursive_synthesis of aoi_2x2x2x1 : function is true; attribute pin_bit_information of aoi_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2202,7 +2202,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2x1 : function is 1; + attribute recursive_synthesis of gate_oa_2x2x2x1 : function is true; attribute pin_bit_information of gate_oa_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2244,7 +2244,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2x2x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2x1 : function is 1; + attribute recursive_synthesis of oa_2x2x2x1 : function is true; attribute pin_bit_information of oa_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2286,7 +2286,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2x1 : function is 1; + attribute recursive_synthesis of gate_oai_2x2x2x1 : function is true; attribute pin_bit_information of gate_oai_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2328,7 +2328,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2x2x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2x1 : function is 1; + attribute recursive_synthesis of oai_2x2x2x1 : function is true; attribute pin_bit_information of oai_2x2x2x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2372,7 +2372,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_2x2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_2x2x2x2 : function is 1; + attribute recursive_synthesis of gate_ao_2x2x2x2 : function is true; attribute pin_bit_information of gate_ao_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2417,7 +2417,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_2x2x2x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_2x2x2x2 : function is 1; + attribute recursive_synthesis of ao_2x2x2x2 : function is true; attribute pin_bit_information of ao_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2462,7 +2462,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_2x2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is 1; + attribute recursive_synthesis of gate_aoi_2x2x2x2 : function is true; attribute pin_bit_information of gate_aoi_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2507,7 +2507,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_2x2x2x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_2x2x2x2 : function is 1; + attribute recursive_synthesis of aoi_2x2x2x2 : function is true; attribute pin_bit_information of aoi_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2552,7 +2552,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_2x2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_2x2x2x2 : function is 1; + attribute recursive_synthesis of gate_oa_2x2x2x2 : function is true; attribute pin_bit_information of gate_oa_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2597,7 +2597,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_2x2x2x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_2x2x2x2 : function is 1; + attribute recursive_synthesis of oa_2x2x2x2 : function is true; attribute pin_bit_information of oa_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2642,7 +2642,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_2x2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_2x2x2x2 : function is 1; + attribute recursive_synthesis of gate_oai_2x2x2x2 : function is true; attribute pin_bit_information of gate_oai_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2687,7 +2687,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_2x2x2x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_2x2x2x2 : function is 1; + attribute recursive_synthesis of oai_2x2x2x2 : function is true; attribute pin_bit_information of oai_2x2x2x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2730,7 +2730,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_3x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x1 : function is 1; + attribute recursive_synthesis of gate_ao_3x1 : function is true; attribute pin_bit_information of gate_ao_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2763,7 +2763,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_3x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x1 : function is 1; + attribute recursive_synthesis of ao_3x1 : function is true; attribute pin_bit_information of ao_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2796,7 +2796,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_3x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x1 : function is 1; + attribute recursive_synthesis of gate_aoi_3x1 : function is true; attribute pin_bit_information of gate_aoi_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2829,7 +2829,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_3x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x1 : function is 1; + attribute recursive_synthesis of aoi_3x1 : function is true; attribute pin_bit_information of aoi_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2862,7 +2862,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_3x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x1 : function is 1; + attribute recursive_synthesis of gate_oa_3x1 : function is true; attribute pin_bit_information of gate_oa_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2895,7 +2895,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_3x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x1 : function is 1; + attribute recursive_synthesis of oa_3x1 : function is true; attribute pin_bit_information of oa_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2928,7 +2928,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_3x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x1 : function is 1; + attribute recursive_synthesis of gate_oai_3x1 : function is true; attribute pin_bit_information of gate_oai_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2961,7 +2961,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_3x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x1 : function is 1; + attribute recursive_synthesis of oai_3x1 : function is true; attribute pin_bit_information of oai_3x1 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -2996,7 +2996,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_3x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x2 : function is 1; + attribute recursive_synthesis of gate_ao_3x2 : function is true; attribute pin_bit_information of gate_ao_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3032,7 +3032,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_3x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x2 : function is 1; + attribute recursive_synthesis of ao_3x2 : function is true; attribute pin_bit_information of ao_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3068,7 +3068,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_3x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x2 : function is 1; + attribute recursive_synthesis of gate_aoi_3x2 : function is true; attribute pin_bit_information of gate_aoi_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3104,7 +3104,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_3x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x2 : function is 1; + attribute recursive_synthesis of aoi_3x2 : function is true; attribute pin_bit_information of aoi_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3140,7 +3140,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_3x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x2 : function is 1; + attribute recursive_synthesis of gate_oa_3x2 : function is true; attribute pin_bit_information of gate_oa_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3176,7 +3176,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_3x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x2 : function is 1; + attribute recursive_synthesis of oa_3x2 : function is true; attribute pin_bit_information of oa_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3212,7 +3212,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_3x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x2 : function is 1; + attribute recursive_synthesis of gate_oai_3x2 : function is true; attribute pin_bit_information of gate_oai_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3248,7 +3248,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_3x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x2 : function is 1; + attribute recursive_synthesis of oai_3x2 : function is true; attribute pin_bit_information of oai_3x2 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3286,7 +3286,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_3x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_3x3 : function is 1; + attribute recursive_synthesis of gate_ao_3x3 : function is true; attribute pin_bit_information of gate_ao_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3325,7 +3325,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_3x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_3x3 : function is 1; + attribute recursive_synthesis of ao_3x3 : function is true; attribute pin_bit_information of ao_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3364,7 +3364,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_3x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_3x3 : function is 1; + attribute recursive_synthesis of gate_aoi_3x3 : function is true; attribute pin_bit_information of gate_aoi_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3403,7 +3403,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_3x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_3x3 : function is 1; + attribute recursive_synthesis of aoi_3x3 : function is true; attribute pin_bit_information of aoi_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3442,7 +3442,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_3x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_3x3 : function is 1; + attribute recursive_synthesis of gate_oa_3x3 : function is true; attribute pin_bit_information of gate_oa_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3481,7 +3481,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_3x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_3x3 : function is 1; + attribute recursive_synthesis of oa_3x3 : function is true; attribute pin_bit_information of oa_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3520,7 +3520,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_3x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_3x3 : function is 1; + attribute recursive_synthesis of gate_oai_3x3 : function is true; attribute pin_bit_information of gate_oai_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3559,7 +3559,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_3x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_3x3 : function is 1; + attribute recursive_synthesis of oai_3x3 : function is true; attribute pin_bit_information of oai_3x3 : function is (1 => (" ","A ","SAME","PIN_BIT_VECTOR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3602,7 +3602,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_4x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x1 : function is 1; + attribute recursive_synthesis of gate_ao_4x1 : function is true; attribute pin_bit_information of gate_ao_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3638,7 +3638,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_4x1 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x1 : function is 1; + attribute recursive_synthesis of ao_4x1 : function is true; attribute pin_bit_information of ao_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3674,7 +3674,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_4x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x1 : function is 1; + attribute recursive_synthesis of gate_aoi_4x1 : function is true; attribute pin_bit_information of gate_aoi_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3710,7 +3710,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_4x1 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x1 : function is 1; + attribute recursive_synthesis of aoi_4x1 : function is true; attribute pin_bit_information of aoi_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3746,7 +3746,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_4x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x1 : function is 1; + attribute recursive_synthesis of gate_oa_4x1 : function is true; attribute pin_bit_information of gate_oa_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3782,7 +3782,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_4x1 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x1 : function is 1; + attribute recursive_synthesis of oa_4x1 : function is true; attribute pin_bit_information of oa_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3818,7 +3818,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_4x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x1 : function is 1; + attribute recursive_synthesis of gate_oai_4x1 : function is true; attribute pin_bit_information of gate_oai_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3854,7 +3854,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_4x1 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x1 : function is 1; + attribute recursive_synthesis of oai_4x1 : function is true; attribute pin_bit_information of oai_4x1 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3892,7 +3892,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_4x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x2 : function is 1; + attribute recursive_synthesis of gate_ao_4x2 : function is true; attribute pin_bit_information of gate_ao_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3931,7 +3931,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_4x2 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x2 : function is 1; + attribute recursive_synthesis of ao_4x2 : function is true; attribute pin_bit_information of ao_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -3970,7 +3970,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_4x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x2 : function is 1; + attribute recursive_synthesis of gate_aoi_4x2 : function is true; attribute pin_bit_information of gate_aoi_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4009,7 +4009,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_4x2 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x2 : function is 1; + attribute recursive_synthesis of aoi_4x2 : function is true; attribute pin_bit_information of aoi_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4048,7 +4048,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_4x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x2 : function is 1; + attribute recursive_synthesis of gate_oa_4x2 : function is true; attribute pin_bit_information of gate_oa_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4087,7 +4087,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_4x2 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x2 : function is 1; + attribute recursive_synthesis of oa_4x2 : function is true; attribute pin_bit_information of oa_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4126,7 +4126,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_4x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x2 : function is 1; + attribute recursive_synthesis of gate_oai_4x2 : function is true; attribute pin_bit_information of gate_oai_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4165,7 +4165,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_4x2 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x2 : function is 1; + attribute recursive_synthesis of oai_4x2 : function is true; attribute pin_bit_information of oai_4x2 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4206,7 +4206,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_4x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x3 : function is 1; + attribute recursive_synthesis of gate_ao_4x3 : function is true; attribute pin_bit_information of gate_ao_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4248,7 +4248,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_4x3 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x3 : function is 1; + attribute recursive_synthesis of ao_4x3 : function is true; attribute pin_bit_information of ao_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4290,7 +4290,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_4x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x3 : function is 1; + attribute recursive_synthesis of gate_aoi_4x3 : function is true; attribute pin_bit_information of gate_aoi_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4332,7 +4332,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_4x3 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x3 : function is 1; + attribute recursive_synthesis of aoi_4x3 : function is true; attribute pin_bit_information of aoi_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4374,7 +4374,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_4x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x3 : function is 1; + attribute recursive_synthesis of gate_oa_4x3 : function is true; attribute pin_bit_information of gate_oa_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4416,7 +4416,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_4x3 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x3 : function is 1; + attribute recursive_synthesis of oa_4x3 : function is true; attribute pin_bit_information of oa_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4458,7 +4458,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_4x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x3 : function is 1; + attribute recursive_synthesis of gate_oai_4x3 : function is true; attribute pin_bit_information of gate_oai_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4500,7 +4500,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_4x3 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x3 : function is 1; + attribute recursive_synthesis of oai_4x3 : function is true; attribute pin_bit_information of oai_4x3 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4544,7 +4544,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_ao_4x4 : function is "VHDL-AO" ; - attribute recursive_synthesis of gate_ao_4x4 : function is 1; + attribute recursive_synthesis of gate_ao_4x4 : function is true; attribute pin_bit_information of gate_ao_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4589,7 +4589,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of ao_4x4 : function is "VHDL-AO" ; - attribute recursive_synthesis of ao_4x4 : function is 1; + attribute recursive_synthesis of ao_4x4 : function is true; attribute pin_bit_information of ao_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4634,7 +4634,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_aoi_4x4 : function is "VHDL-AOI" ; - attribute recursive_synthesis of gate_aoi_4x4 : function is 1; + attribute recursive_synthesis of gate_aoi_4x4 : function is true; attribute pin_bit_information of gate_aoi_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4679,7 +4679,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of aoi_4x4 : function is "VHDL-AOI" ; - attribute recursive_synthesis of aoi_4x4 : function is 1; + attribute recursive_synthesis of aoi_4x4 : function is true; attribute pin_bit_information of aoi_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4724,7 +4724,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oa_4x4 : function is "VHDL-OA" ; - attribute recursive_synthesis of gate_oa_4x4 : function is 1; + attribute recursive_synthesis of gate_oa_4x4 : function is true; attribute pin_bit_information of gate_oa_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4769,7 +4769,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oa_4x4 : function is "VHDL-OA" ; - attribute recursive_synthesis of oa_4x4 : function is 1; + attribute recursive_synthesis of oa_4x4 : function is true; attribute pin_bit_information of oa_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4814,7 +4814,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_oai_4x4 : function is "VHDL-OAI" ; - attribute recursive_synthesis of gate_oai_4x4 : function is 1; + attribute recursive_synthesis of gate_oai_4x4 : function is true; attribute pin_bit_information of gate_oai_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), @@ -4859,7 +4859,7 @@ package std_ulogic_ao_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of oai_4x4 : function is "VHDL-OAI" ; - attribute recursive_synthesis of oai_4x4 : function is 1; + attribute recursive_synthesis of oai_4x4 : function is true; attribute pin_bit_information of oai_4x4 : function is (1 => (" ","A ","SAME","PIN_BIT_SCALAR"), 2 => (" ","A ","SAME","PIN_BIT_VECTOR"), diff --git a/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl index b002e1f..a6656a3 100644 --- a/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_function_support.vhdl @@ -77,7 +77,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- Synopsys translate_off attribute btr_name of gate : function is "AND" ; - attribute recursive_synthesis of gate : function is 1 ; + attribute recursive_synthesis of gate : function is true ; attribute pin_bit_information of gate : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_SCALAR"), @@ -90,7 +90,7 @@ package std_ulogic_function_support is return std_ulogic ; -- Synopsys translate_off attribute btr_name of dot_and : function is "VHDL-DOTA" ; - attribute recursive_synthesis of dot_and : function is 1 ; + attribute recursive_synthesis of dot_and : function is true ; attribute pin_bit_information of dot_and : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); @@ -101,7 +101,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of dot_or : function is "VHDL-DOTO" ; - attribute recursive_synthesis of dot_or : function is 1 ; + attribute recursive_synthesis of dot_or : function is true ; attribute pin_bit_information of dot_or : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); @@ -116,7 +116,7 @@ package std_ulogic_function_support is return bit ; -- Synopsys translate_off attribute btr_name of clock_tree_dot : function is "VHDL-CDOT" ; - attribute recursive_synthesis of clock_tree_dot : function is 1 ; + attribute recursive_synthesis of clock_tree_dot : function is true ; attribute pin_bit_information of clock_tree_dot : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","OUT ","SAME","PIN_BIT_SCALAR")); @@ -140,7 +140,7 @@ package std_ulogic_function_support is ); -- synopsys translate_off attribute btr_name of terminator : procedure is "TERMINATOR"; - attribute recursive_synthesis of terminator : procedure is 1 ; + attribute recursive_synthesis of terminator : procedure is true ; attribute pin_bit_information of terminator : procedure is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","PASS "," "," "), @@ -167,7 +167,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of delay : function is "IDENT" ; - attribute recursive_synthesis of delay : function is 1 ; + attribute recursive_synthesis of delay : function is true ; attribute block_data of delay : function is "SUB_FUNC=/DELAY/LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of delay : function is @@ -197,7 +197,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of buff : function is "IDENT" ; - attribute recursive_synthesis of buff : function is 1 ; + attribute recursive_synthesis of buff : function is true ; attribute block_data of buff : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of buff : function is @@ -227,7 +227,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of invert : function is "NOT" ; - attribute recursive_synthesis of invert : function is 1 ; + attribute recursive_synthesis of invert : function is true ; attribute pin_bit_information of invert : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","PASS "," "," "), @@ -257,7 +257,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of compare : function is "VHDL-COMPARE" ; - attribute recursive_synthesis of compare : function is 1 ; + attribute recursive_synthesis of compare : function is true ; attribute pin_bit_information of compare : function is (1 => (" ","A0 ","INCR","PIN_BIT_SCALAR"), 2 => (" ","M0 ","INCR","PIN_BIT_SCALAR"), @@ -278,7 +278,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of parity : function is "XOR" ; - attribute recursive_synthesis of parity : function is 1 ; + attribute recursive_synthesis of parity : function is true ; attribute pin_bit_information of parity : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -296,7 +296,7 @@ package std_ulogic_function_support is -- synopsys translate_off attribute btr_name of parity_map : function is "XOR" ; - attribute recursive_synthesis of parity_map : function is 1 ; + attribute recursive_synthesis of parity_map : function is true ; attribute block_data of parity_map : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of parity_map : function is @@ -318,7 +318,7 @@ package std_ulogic_function_support is -- synopsys translate_off attribute btr_name of parity_gen_odd : function is "XNOR" ; - attribute recursive_synthesis of parity_gen_odd : function is 1; + attribute recursive_synthesis of parity_gen_odd : function is true; attribute pin_bit_information of parity_gen_odd : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -336,7 +336,7 @@ package std_ulogic_function_support is return std_ulogic ; -- Synopsys translate_off attribute btr_name of parity_gen_even : function is "XOR" ; - attribute recursive_synthesis of parity_gen_even : function is 1; + attribute recursive_synthesis of parity_gen_even : function is true; attribute pin_bit_information of parity_gen_even : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -354,7 +354,7 @@ package std_ulogic_function_support is return std_ulogic ; -- Synopsys translate_off attribute btr_name of is_parity_odd : function is "XOR" ; - attribute recursive_synthesis of is_parity_odd : function is 1; + attribute recursive_synthesis of is_parity_odd : function is true; attribute pin_bit_information of is_parity_odd : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -372,7 +372,7 @@ package std_ulogic_function_support is return std_ulogic ; -- Synopsys translate_off attribute btr_name of is_parity_even : function is "XNOR" ; - attribute recursive_synthesis of is_parity_even : function is 1; + attribute recursive_synthesis of is_parity_even : function is true; attribute pin_bit_information of is_parity_even : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -405,7 +405,7 @@ package std_ulogic_function_support is ); -- synopsys translate_off attribute btr_name of full_add : procedure is "VHDL-FA"; - attribute recursive_synthesis of full_add : procedure is 1 ; + attribute recursive_synthesis of full_add : procedure is true ; attribute pin_bit_information of full_add : procedure is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -438,7 +438,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of tie_0 : function is "VHDL-TIDN" ; - attribute recursive_synthesis of tie_0 : function is 1 ; + attribute recursive_synthesis of tie_0 : function is true ; attribute block_data of tie_0 : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of tie_0 : function is @@ -457,7 +457,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of vector_tie_0 : function is "VHDL-TIDN" ; - attribute recursive_synthesis of vector_tie_0 : function is 1 ; + attribute recursive_synthesis of vector_tie_0 : function is true ; attribute block_data of vector_tie_0 : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of vector_tie_0 : function is @@ -476,7 +476,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of tie_1 : function is "VHDL-TIUP" ; - attribute recursive_synthesis of tie_1 : function is 1 ; + attribute recursive_synthesis of tie_1 : function is true ; attribute block_data of tie_1 : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of tie_1 : function is @@ -495,7 +495,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of vector_tie_1 : function is "VHDL-TIUP" ; - attribute recursive_synthesis of vector_tie_1 : function is 1 ; + attribute recursive_synthesis of vector_tie_1 : function is true ; attribute block_data of vector_tie_1 : function is "LOGIC_STYLE=/DIRECT/" ; attribute pin_bit_information of vector_tie_1 : function is @@ -519,7 +519,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of and_reduce : function is "AND" ; - attribute recursive_synthesis of and_reduce : function is 1 ; + attribute recursive_synthesis of and_reduce : function is true ; attribute pin_bit_information of and_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -537,7 +537,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of or_reduce : function is "OR" ; - attribute recursive_synthesis of or_reduce : function is 1 ; + attribute recursive_synthesis of or_reduce : function is true ; attribute pin_bit_information of or_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -555,7 +555,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of nand_reduce : function is "NAND" ; - attribute recursive_synthesis of nand_reduce : function is 1 ; + attribute recursive_synthesis of nand_reduce : function is true ; attribute pin_bit_information of nand_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -573,7 +573,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of nor_reduce : function is "NOR" ; - attribute recursive_synthesis of nor_reduce : function is 1 ; + attribute recursive_synthesis of nor_reduce : function is true ; attribute pin_bit_information of nor_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -591,7 +591,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of xor_reduce : function is "XOR" ; - attribute recursive_synthesis of xor_reduce : function is 1 ; + attribute recursive_synthesis of xor_reduce : function is true ; attribute pin_bit_information of xor_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -609,7 +609,7 @@ package std_ulogic_function_support is return std_ulogic ; -- synopsys translate_off attribute btr_name of xnor_reduce : function is "XNOR" ; - attribute recursive_synthesis of xnor_reduce : function is 1 ; + attribute recursive_synthesis of xnor_reduce : function is true ; attribute pin_bit_information of xnor_reduce : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -647,7 +647,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_and : function is "AND" ; - attribute recursive_synthesis of gate_and : function is 1 ; + attribute recursive_synthesis of gate_and : function is true ; attribute pin_bit_information of gate_and : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -685,7 +685,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_or : function is "OR" ; - attribute recursive_synthesis of gate_or : function is 1 ; + attribute recursive_synthesis of gate_or : function is true ; attribute pin_bit_information of gate_or : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -723,7 +723,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_nand : function is "NAND" ; - attribute recursive_synthesis of gate_nand : function is 1 ; + attribute recursive_synthesis of gate_nand : function is true ; attribute pin_bit_information of gate_nand : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -761,7 +761,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_nor : function is "NOR" ; - attribute recursive_synthesis of gate_nor : function is 1 ; + attribute recursive_synthesis of gate_nor : function is true ; attribute pin_bit_information of gate_nor : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -790,7 +790,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_xor : function is "XOR" ; - attribute recursive_synthesis of gate_xor : function is 1 ; + attribute recursive_synthesis of gate_xor : function is true ; attribute pin_bit_information of gate_xor : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -819,7 +819,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of gate_xnor : function is "XNOR" ; - attribute recursive_synthesis of gate_xnor : function is 1 ; + attribute recursive_synthesis of gate_xnor : function is true ; attribute pin_bit_information of gate_xnor : function is (1 => (" ","IN ","SAME","PIN_BIT_SCALAR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -851,7 +851,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_2 : function is "AND" ; - attribute recursive_synthesis of and_2 : function is 1 ; + attribute recursive_synthesis of and_2 : function is true ; attribute pin_bit_information of and_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -880,7 +880,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_2 : function is "OR" ; - attribute recursive_synthesis of or_2 : function is 1 ; + attribute recursive_synthesis of or_2 : function is true ; attribute pin_bit_information of or_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -909,7 +909,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_2 : function is "NAND" ; - attribute recursive_synthesis of nand_2 : function is 1 ; + attribute recursive_synthesis of nand_2 : function is true ; attribute pin_bit_information of nand_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -938,7 +938,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_2 : function is "NOR" ; - attribute recursive_synthesis of nor_2 : function is 1 ; + attribute recursive_synthesis of nor_2 : function is true ; attribute pin_bit_information of nor_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -967,7 +967,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of xor_2 : function is "XOR" ; - attribute recursive_synthesis of xor_2 : function is 1 ; + attribute recursive_synthesis of xor_2 : function is true ; attribute pin_bit_information of xor_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -996,7 +996,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of xnor_2 : function is "XNOR" ; - attribute recursive_synthesis of xnor_2 : function is 1 ; + attribute recursive_synthesis of xnor_2 : function is true ; attribute pin_bit_information of xnor_2 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1030,7 +1030,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_3 : function is "AND" ; - attribute recursive_synthesis of and_3 : function is 1 ; + attribute recursive_synthesis of and_3 : function is true ; attribute pin_bit_information of and_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1062,7 +1062,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_3 : function is "OR" ; - attribute recursive_synthesis of or_3 : function is 1 ; + attribute recursive_synthesis of or_3 : function is true ; attribute pin_bit_information of or_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1094,7 +1094,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_3 : function is "NAND" ; - attribute recursive_synthesis of nand_3 : function is 1 ; + attribute recursive_synthesis of nand_3 : function is true ; attribute pin_bit_information of nand_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1126,7 +1126,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_3 : function is "NOR" ; - attribute recursive_synthesis of nor_3 : function is 1 ; + attribute recursive_synthesis of nor_3 : function is true ; attribute pin_bit_information of nor_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1158,7 +1158,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of xor_3 : function is "XOR" ; - attribute recursive_synthesis of xor_3 : function is 1 ; + attribute recursive_synthesis of xor_3 : function is true ; attribute pin_bit_information of xor_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1190,7 +1190,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of xnor_3 : function is "XNOR" ; - attribute recursive_synthesis of xnor_3 : function is 1 ; + attribute recursive_synthesis of xnor_3 : function is true ; attribute pin_bit_information of xnor_3 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1226,7 +1226,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_4 : function is "AND" ; - attribute recursive_synthesis of and_4 : function is 1 ; + attribute recursive_synthesis of and_4 : function is true ; attribute pin_bit_information of and_4 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1261,7 +1261,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_4 : function is "OR" ; - attribute recursive_synthesis of or_4 : function is 1 ; + attribute recursive_synthesis of or_4 : function is true ; attribute pin_bit_information of or_4 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1296,7 +1296,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_4 : function is "NAND" ; - attribute recursive_synthesis of nand_4 : function is 1 ; + attribute recursive_synthesis of nand_4 : function is true ; attribute pin_bit_information of nand_4 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1331,7 +1331,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_4 : function is "NOR" ; - attribute recursive_synthesis of nor_4 : function is 1 ; + attribute recursive_synthesis of nor_4 : function is true ; attribute pin_bit_information of nor_4 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1371,7 +1371,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_5 : function is "AND" ; - attribute recursive_synthesis of and_5 : function is 1 ; + attribute recursive_synthesis of and_5 : function is true ; attribute pin_bit_information of and_5 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1409,7 +1409,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_5 : function is "OR" ; - attribute recursive_synthesis of or_5 : function is 1 ; + attribute recursive_synthesis of or_5 : function is true ; attribute pin_bit_information of or_5 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1447,7 +1447,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_5 : function is "NAND" ; - attribute recursive_synthesis of nand_5 : function is 1 ; + attribute recursive_synthesis of nand_5 : function is true ; attribute pin_bit_information of nand_5 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1485,7 +1485,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_5 : function is "NOR" ; - attribute recursive_synthesis of nor_5 : function is 1 ; + attribute recursive_synthesis of nor_5 : function is true ; attribute pin_bit_information of nor_5 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1527,7 +1527,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_6 : function is "AND" ; - attribute recursive_synthesis of and_6 : function is 1 ; + attribute recursive_synthesis of and_6 : function is true ; attribute pin_bit_information of and_6 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1568,7 +1568,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_6 : function is "OR" ; - attribute recursive_synthesis of or_6 : function is 1 ; + attribute recursive_synthesis of or_6 : function is true ; attribute pin_bit_information of or_6 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1609,7 +1609,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_6 : function is "NAND" ; - attribute recursive_synthesis of nand_6 : function is 1 ; + attribute recursive_synthesis of nand_6 : function is true ; attribute pin_bit_information of nand_6 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1650,7 +1650,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_6 : function is "NOR" ; - attribute recursive_synthesis of nor_6 : function is 1 ; + attribute recursive_synthesis of nor_6 : function is true ; attribute pin_bit_information of nor_6 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1696,7 +1696,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_7 : function is "AND" ; - attribute recursive_synthesis of and_7 : function is 1 ; + attribute recursive_synthesis of and_7 : function is true ; attribute pin_bit_information of and_7 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1740,7 +1740,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_7 : function is "OR" ; - attribute recursive_synthesis of or_7 : function is 1 ; + attribute recursive_synthesis of or_7 : function is true ; attribute pin_bit_information of or_7 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1784,7 +1784,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_7 : function is "NAND" ; - attribute recursive_synthesis of nand_7 : function is 1 ; + attribute recursive_synthesis of nand_7 : function is true ; attribute pin_bit_information of nand_7 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1828,7 +1828,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_7 : function is "NOR" ; - attribute recursive_synthesis of nor_7 : function is 1 ; + attribute recursive_synthesis of nor_7 : function is true ; attribute pin_bit_information of nor_7 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1877,7 +1877,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of and_8 : function is "AND" ; - attribute recursive_synthesis of and_8 : function is 1 ; + attribute recursive_synthesis of and_8 : function is true ; attribute pin_bit_information of and_8 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1924,7 +1924,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of or_8 : function is "OR" ; - attribute recursive_synthesis of or_8 : function is 1 ; + attribute recursive_synthesis of or_8 : function is true ; attribute pin_bit_information of or_8 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -1971,7 +1971,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nand_8 : function is "NAND" ; - attribute recursive_synthesis of nand_8 : function is 1 ; + attribute recursive_synthesis of nand_8 : function is true ; attribute pin_bit_information of nand_8 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -2018,7 +2018,7 @@ package std_ulogic_function_support is return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of nor_8 : function is "NOR" ; - attribute recursive_synthesis of nor_8 : function is 1 ; + attribute recursive_synthesis of nor_8 : function is true ; attribute pin_bit_information of nor_8 : function is (1 => (" ","IN ","SAME","PIN_BIT_VECTOR"), 2 => (" ","IN ","SAME","PIN_BIT_VECTOR"), @@ -2048,7 +2048,7 @@ package std_ulogic_function_support is return std_return_4 ; -- synopsys translate_off attribute btr_name of decode_2to4 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_2to4 : function is 1 ; + attribute recursive_synthesis of decode_2to4 : function is true ; attribute pin_bit_information of decode_2to4 : function is (1 => (" ","D1 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -2066,7 +2066,7 @@ package std_ulogic_function_support is return std_return_8 ; -- synopsys translate_off attribute btr_name of decode_3to8 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_3to8 : function is 1 ; + attribute recursive_synthesis of decode_3to8 : function is true ; attribute pin_bit_information of decode_3to8 : function is (1 => (" ","D2 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -2084,7 +2084,7 @@ package std_ulogic_function_support is return std_return_16 ; -- synopsys translate_off attribute btr_name of decode_4to16 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_4to16 : function is 1 ; + attribute recursive_synthesis of decode_4to16 : function is true ; attribute pin_bit_information of decode_4to16 : function is (1 => (" ","D3 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -2102,7 +2102,7 @@ package std_ulogic_function_support is return std_return_32 ; -- synopsys translate_off attribute btr_name of decode_5to32 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_5to32 : function is 1 ; + attribute recursive_synthesis of decode_5to32 : function is true ; attribute pin_bit_information of decode_5to32 : function is (1 => (" ","D4 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), @@ -2120,7 +2120,7 @@ package std_ulogic_function_support is return std_return_64 ; -- synopsys translate_off attribute btr_name of decode_6to64 : function is "VHDL-DECODE"; - attribute recursive_synthesis of decode_6to64 : function is 1 ; + attribute recursive_synthesis of decode_6to64 : function is true ; attribute pin_bit_information of decode_6to64 : function is (1 => (" ","D5 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","PASS "," "," "), diff --git a/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl index dcb5f64..3b78ae1 100644 --- a/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl +++ b/rel/src/vhdl/ibm/std_ulogic_mux_support.vhdl @@ -44,7 +44,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of mux_2to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_2to1 : function is 1; + attribute recursive_synthesis of mux_2to1 : function is true; attribute pin_bit_information of mux_2to1 : function is (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -79,7 +79,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of mux_4to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_4to1 : function is 1; + attribute recursive_synthesis of mux_4to1 : function is true; attribute pin_bit_information of mux_4to1 : function is (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -124,7 +124,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of mux_8to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of mux_8to1 : function is 1; + attribute recursive_synthesis of mux_8to1 : function is true; attribute pin_bit_information of mux_8to1 : function is (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -161,7 +161,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_mux_2to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_2to1 : function is 1; + attribute recursive_synthesis of not_mux_2to1 : function is true; attribute pin_bit_information of not_mux_2to1 : function is (1 => (" ","S0 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -196,7 +196,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_mux_4to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_4to1 : function is 1; + attribute recursive_synthesis of not_mux_4to1 : function is true; attribute pin_bit_information of not_mux_4to1 : function is (1 => (" ","S1 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -241,7 +241,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_mux_8to1 : function is "VHDL-MUX" ; - attribute recursive_synthesis of not_mux_8to1 : function is 1; + attribute recursive_synthesis of not_mux_8to1 : function is true; attribute pin_bit_information of not_mux_8to1 : function is (1 => (" ","S2 ","DECR","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -281,7 +281,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of select_1of2 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of2 : function is 1; + attribute recursive_synthesis of select_1of2 : function is true; attribute pin_bit_information of select_1of2 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -319,7 +319,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of select_1of3 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of3 : function is 1; + attribute recursive_synthesis of select_1of3 : function is true; attribute pin_bit_information of select_1of3 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -363,7 +363,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of select_1of4 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of4 : function is 1; + attribute recursive_synthesis of select_1of4 : function is true; attribute pin_bit_information of select_1of4 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -425,7 +425,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of select_1of8 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of select_1of8 : function is 1; + attribute recursive_synthesis of select_1of8 : function is true; attribute pin_bit_information of select_1of8 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -471,7 +471,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_select_1of2 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of2 : function is 1; + attribute recursive_synthesis of not_select_1of2 : function is true; attribute pin_bit_information of not_select_1of2 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -509,7 +509,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_select_1of3 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of3 : function is 1; + attribute recursive_synthesis of not_select_1of3 : function is true; attribute PIN_BIT_INFORMATION of not_select_1of3 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -553,7 +553,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_select_1of4 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of4 : function is 1; + attribute recursive_synthesis of not_select_1of4 : function is true; attribute pin_bit_information of not_select_1of4 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), @@ -615,7 +615,7 @@ package std_ulogic_mux_support is ) return std_ulogic_vector ; -- synopsys translate_off attribute btr_name of not_select_1of8 : function is "VHDL-SELECT" ; - attribute recursive_synthesis of not_select_1of8 : function is 1; + attribute recursive_synthesis of not_select_1of8 : function is true; attribute pin_bit_information of not_select_1of8 : function is (1 => (" ","S0 ","SAME","PIN_BIT_SCALAR"), 2 => (" ","D0 ","SAME","PIN_BIT_VECTOR"), diff --git a/rel/src/vhdl/tri/ramb16_s18_s18.vhdl b/rel/src/vhdl/tri/ramb16_s18_s18.vhdl index 410d8d5..ad1eb57 100644 --- a/rel/src/vhdl/tri/ramb16_s18_s18.vhdl +++ b/rel/src/vhdl/tri/ramb16_s18_s18.vhdl @@ -15,9 +15,6 @@ library ibm; use ibm.std_ulogic_support.all; use ibm.std_ulogic_function_support.all; -library UNISIM; -use UNISIM.vcomponents.all; - library UNIMACRO; use UNIMACRO.vcomponents.all; diff --git a/rel/src/vhdl/tri/ramb16_s36_s36.vhdl b/rel/src/vhdl/tri/ramb16_s36_s36.vhdl index fc9a359..bb7150a 100644 --- a/rel/src/vhdl/tri/ramb16_s36_s36.vhdl +++ b/rel/src/vhdl/tri/ramb16_s36_s36.vhdl @@ -15,9 +15,6 @@ library ibm; use ibm.std_ulogic_support.all; use ibm.std_ulogic_function_support.all; -library UNISIM; -use UNISIM.vcomponents.all; - library UNIMACRO; use UNIMACRO.vcomponents.all; diff --git a/rel/src/vhdl/tri/ramb16_s9_s9.vhdl b/rel/src/vhdl/tri/ramb16_s9_s9.vhdl index b1d830a..7318252 100644 --- a/rel/src/vhdl/tri/ramb16_s9_s9.vhdl +++ b/rel/src/vhdl/tri/ramb16_s9_s9.vhdl @@ -15,9 +15,6 @@ library ibm; use ibm.std_ulogic_support.all; use ibm.std_ulogic_function_support.all; -library UNISIM; -use UNISIM.vcomponents.all; - library UNIMACRO; use UNIMACRO.vcomponents.all; diff --git a/rel/src/vhdl/tri/tri_boltreg_p.vhdl b/rel/src/vhdl/tri/tri_boltreg_p.vhdl index fe21eb9..cd282fc 100644 --- a/rel/src/vhdl/tri/tri_boltreg_p.vhdl +++ b/rel/src/vhdl/tri/tri_boltreg_p.vhdl @@ -17,7 +17,6 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -library ibm; library support; use support.power_logic_pkg.all; library tri; use tri.tri_latches_pkg.all; diff --git a/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl b/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl index e04f49c..687d529 100644 --- a/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl +++ b/rel/src/vhdl/tri/tri_ser_rlmreg_p.vhdl @@ -7,7 +7,7 @@ -- This README will be updated with additional information when OpenPOWER's -- license is available. -library ieee,ibm,support,tri; +library ieee,support,tri; use ieee.std_logic_1164.all; use support.power_logic_pkg.all; use tri.tri_latches_pkg.all; diff --git a/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl b/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl index 579e9c8..68c4f6a 100644 --- a/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl +++ b/rel/src/vhdl/work/pcq_abist_bolton_stg.vhdl @@ -14,7 +14,7 @@ library ieee; use ieee.std_logic_1164.all; -library ibm,clib; +library ibm; use ibm.std_ulogic_support.all; use ibm.std_ulogic_function_support.all; library support; diff --git a/rel/src/vhdl/work/pcq_regs_fir.vhdl b/rel/src/vhdl/work/pcq_regs_fir.vhdl index ebc47a9..9e0e8c3 100644 --- a/rel/src/vhdl/work/pcq_regs_fir.vhdl +++ b/rel/src/vhdl/work/pcq_regs_fir.vhdl @@ -14,7 +14,7 @@ library ieee; use ieee.std_logic_1164.all; -library ibm,clib; +library ibm; use ibm.std_ulogic_support.all; use ibm.std_ulogic_function_support.all; use ibm.std_ulogic_unsigned.all; diff --git a/rel/src/vhdl/work/xuq_byp_cr.vhdl b/rel/src/vhdl/work/xuq_byp_cr.vhdl index 33a906b..c0d157c 100644 --- a/rel/src/vhdl/work/xuq_byp_cr.vhdl +++ b/rel/src/vhdl/work/xuq_byp_cr.vhdl @@ -9,7 +9,7 @@ -- Description: XU Bypass Unit -- -library ieee,ibm,support,tri,clib,work; +library ieee,ibm,support,tri,work; use ieee.std_logic_1164.all; use ibm.std_ulogic_function_support.all; use tri.tri_latches_pkg.all; diff --git a/rel/src/vhdl/work/xuq_debug_mux32.vhdl b/rel/src/vhdl/work/xuq_debug_mux32.vhdl index fc6b8a4..1bef25f 100644 --- a/rel/src/vhdl/work/xuq_debug_mux32.vhdl +++ b/rel/src/vhdl/work/xuq_debug_mux32.vhdl @@ -9,7 +9,7 @@ -- Description: LSU Debug Event Muxing -- -library ieee,ibm,support,work,tri,clib,work; +library ieee,ibm,support,work,tri,work; use ieee.std_logic_1164.all; use support.power_logic_pkg.all; use ibm.std_ulogic_support.all; diff --git a/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl b/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl index ef745d2..9330884 100644 --- a/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl +++ b/rel/src/vhdl/work/xuq_dec_dcdmrg.vhdl @@ -18,7 +18,6 @@ LIBRARY ibm; LIBRARY support; USE support.power_logic_pkg.all; LIBRARY tri; USE tri.tri_latches_pkg.all; -LIBRARY clib ; LIBRARY work; USE work.xuq_pkg.all; entity xuq_dec_dcdmrg is diff --git a/rel/src/vhdl/work/xuq_fxua_data.vhdl b/rel/src/vhdl/work/xuq_fxua_data.vhdl index fd689b7..9521e10 100644 --- a/rel/src/vhdl/work/xuq_fxua_data.vhdl +++ b/rel/src/vhdl/work/xuq_fxua_data.vhdl @@ -9,7 +9,7 @@ -- Description: XU Exception Handler -- -library ieee,ibm,support,work,tri,clib; +library ieee,ibm,support,work,tri; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use support.power_logic_pkg.all; diff --git a/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl b/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl index a455877..9db97ff 100644 --- a/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_cmp_cmp31.vhdl @@ -24,7 +24,6 @@ LIBRARY ibm; LIBRARY support; USE support.power_logic_pkg.all; LIBRARY tri; USE tri.tri_latches_pkg.all; -LIBRARY clib ; entity xuq_lsu_cmp_cmp31 is generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); diff --git a/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl b/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl index df1ae9f..941528e 100644 --- a/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_cmp_cmp36e.vhdl @@ -24,7 +24,6 @@ LIBRARY ibm; LIBRARY support; USE support.power_logic_pkg.all; LIBRARY tri; USE tri.tri_latches_pkg.all; -LIBRARY clib ; entity xuq_lsu_cmp_cmp36e is generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other ); diff --git a/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl b/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl index ce9ab19..de2b6af 100644 --- a/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_data_rot32_ru.vhdl @@ -19,7 +19,6 @@ LIBRARY ibm; LIBRARY support; USE support.power_logic_pkg.all; LIBRARY tri; USE tri.tri_latches_pkg.all; -LIBRARY clib ; -- ########################################################################################## -- VHDL Contents diff --git a/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl b/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl index c393c31..346bf8f 100644 --- a/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_data_rot32s_ru.vhdl @@ -20,7 +20,6 @@ LIBRARY ibm; LIBRARY support; USE support.power_logic_pkg.all; LIBRARY tri; USE tri.tri_latches_pkg.all; -LIBRARY clib ; -- ########################################################################################## -- VHDL Contents diff --git a/rel/src/vhdl/work/xuq_lsu_debug.vhdl b/rel/src/vhdl/work/xuq_lsu_debug.vhdl index a362ba9..64bbf24 100644 --- a/rel/src/vhdl/work/xuq_lsu_debug.vhdl +++ b/rel/src/vhdl/work/xuq_lsu_debug.vhdl @@ -9,7 +9,7 @@ -- Description: LSU Debug Event Muxing -- -library ieee,ibm,support,work,tri,clib; +library ieee,ibm,support,work,tri; use ieee.std_logic_1164.all; use support.power_logic_pkg.all; use tri.tri_latches_pkg.all; diff --git a/rel/src/vhdl/work/xuq_pkg.vhdl b/rel/src/vhdl/work/xuq_pkg.vhdl index e58028e..6290424 100644 --- a/rel/src/vhdl/work/xuq_pkg.vhdl +++ b/rel/src/vhdl/work/xuq_pkg.vhdl @@ -9,7 +9,7 @@ -- Description: XU Package -- -library ieee,ibm; +library ieee; use ieee.std_logic_1164.all; package xuq_pkg is diff --git a/run.py b/run.py new file mode 100644 index 0000000..a9f9829 --- /dev/null +++ b/run.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 + +"""VUnit run script.""" + +from pathlib import Path +from vunit import VUnit + +prj = VUnit.from_argv() + +_rel = Path(__file__).parent / "rel" + +library_names = ["support", "ibm", "clib", "tri"] +for library_name in library_names: + prj.add_library(library_name).add_source_files( + _rel / f"src/vhdl/{library_name}/*.vhdl" + ) + +# VUnit doesn't accept libraries named work. These files are compiled to the top library +prj.add_library("top").add_source_files(_rel / "src/vhdl/work/*.vhdl") + +# Simulation only library containing VHDL mocks for Verilog UNIMACROs +prj.add_library("unimacro").add_source_files(_rel / "sim/unimacro/*.vhdl") + +prj.main()