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openpower-cores.a2i/rel/sim/unimacro
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Lars Asplund fee9c135cc Added VHDL mocks for used UNIMACROs. 
These mocks allow for a pure VHDL CI environment. The mocks are currently empty and provide no functionality. This is acceptable as long as no testbenches depend on them.
For now their primary purpose is to allow the project to be compiled by GHDL.

Some files also reference the UNISIM library. These references are not used and have been removed.
2021-03-13 22:54:24 +01:00
..
bram_tdp_macro_mock.vhdl
Added VHDL mocks for used UNIMACROs.
2021-03-13 22:54:24 +01:00
unimacro_vcomp_mock.vhdl
Added VHDL mocks for used UNIMACROs.
2021-03-13 22:54:24 +01:00