openpower-cores.a2i

mirror of https://github.com/openpower-cores/a2i.git synced 2026-01-13 15:27:21 +00:00

History

Tristan Gingold 7e700ddc26 Translate off the unused global signals

So that a2x_axi can be imported into the open source yosys tool
using the ghdl frontend.

Signed-off-by: Tristan Gingold <tgingold@free.fr>

2020-07-18 21:20:59 +02:00

build

create

2020-06-28 18:40:39 -04:00

doc

create

2020-06-28 18:40:39 -04:00

fpga

create

2020-06-28 18:40:39 -04:00

src/vhdl

Translate off the unused global signals

2020-07-18 21:20:59 +02:00

readme.md

create

2020-06-28 18:40:39 -04:00

readme.md

Directory Structure

src/vhdl
   clib (low-level components)
   ibm (std_ulogic)
   support (power_logic subtype)
   tri (latches and arrays)
   work (macros)

build
   a2x (project)
   ip_cache (empty until project built)
   ip_repo (empty until IP built/copied)
   ip_user (IP macros to be built)
   tcl (build scripts)
   xdc (constraints)

fpga
   tcl

doc
   core user guide, etc.

Build Process

IP

IP is created in ip_user and copied to ip_repo for use in top level bd.

See build/ip_user/xxx/readme.md.

Core:

a2x_axi

Simple card components:

a2x_axi_reg 
a2x_dbug
a2x_reset

Help Vivado attach to VIO correctly:

reverserator_3
reverserator_4
reverserator_32
reverserator_64

Project

See build/a2x/readme.md.

create project
synth/implement