mirror of
https://github.com/prirun/p50em.git
synced 2026-02-26 00:03:58 +00:00
removed syscom/ directory, clock auto-sets via VCP interface +
SVC always fault - no more emulation of Primos II added support for 102.4 and 3.2us clock ticks
This commit is contained in:
77
em.c
77
em.c
@@ -89,8 +89,6 @@ OK:
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#include <errno.h>
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#include <setjmp.h>
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#include <sys/time.h>
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#include "syscom/keys.ins.cc"
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#include "syscom/errd.ins.cc"
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/* In SR modes, Prime CPU registers are mapped to memory locations
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0-'37, but only 0-7 are user accessible. In the post-P300
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@@ -141,6 +139,9 @@ typedef unsigned int pa_t; /* physical address */
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else if (*(int *)(crs+FLTH) == 0) \
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crs[KEYS] |= 0100;
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/* this is probably incorrect - needs to test 16 more bits for denomalized
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doubles */
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#define SETCC_D SETCC_F
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/* XEXPC is a dummy to indicate that the C-bit may not be set correctly */
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@@ -177,13 +178,13 @@ typedef unsigned int pa_t; /* physical address */
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/* these macros are for the VI-mode branch insructions */
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#define BCLT if (crs[KEYS] & 0200) RPL = iget16(RP); else RPL++
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#define BCLE if (crs[KEYS] & 0300) RPL = iget16(RP); else RPL++
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#define BCEQ if (crs[KEYS] & 0100) RPL = iget16(RP); else RPL++
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#define BCLT if (crs[KEYS] & 0200) RPL = iget16(RP); else RPL++
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#define BCLE if (crs[KEYS] & 0300) RPL = iget16(RP); else RPL++
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#define BCEQ if (crs[KEYS] & 0100) RPL = iget16(RP); else RPL++
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#define BCNE if (!(crs[KEYS] & 0100)) RPL = iget16(RP); else RPL++
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#define BCGE if (!(crs[KEYS] & 0200)) RPL = iget16(RP); else RPL++
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#define BCGT if (!(crs[KEYS] & 0300)) RPL = iget16(RP); else RPL++
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#define BLS if (crs[KEYS] & 020000) RPL = iget16(RP); else RPL++
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#define BLS if (crs[KEYS] & 020000) RPL = iget16(RP); else RPL++
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#define BXNE if (crs[X] != 0) RPL = iget16(RP); else RPL++
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#define BYNE if (crs[Y] != 0) RPL = iget16(RP); else RPL++
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@@ -310,7 +311,7 @@ char gen0nam[][5] = {
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*/
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int traceflags=0; /* each bit is a trace flag */
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int savetraceflags=0; /* see ITLB */
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int savetraceflags=0;
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int traceuser=0; /* OWNERL to trace */
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int numtraceprocs=0;
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#define MAXTRACEPROCS 2
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@@ -335,7 +336,7 @@ unsigned short sswitch = 014114; /* sense switches, set with -ss & -boot*/
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unsigned short cpuid = 27; /* STPM CPU model, set with -cpuid */
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unsigned long instcount=0; /* global instruction count */
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unsigned long instcount=0; /* global instruction count */
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unsigned short inhcount = 0; /* number of instructions to stay inhibited */
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@@ -344,7 +345,7 @@ unsigned int instpermsec = 2000; /* initial assumption for inst/msec */
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jmp_buf jmpbuf; /* for longjumps to the fetch loop */
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/* The standard Prime physical memory limit on early machines is 8MB.
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Later machines have higher memory capacities, up to 1GB, using
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Later machines have higher memory capacities, up to 512M, using
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32-bit page tables.
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NOTE: rev 20 is limited to 32MB on all machines. */
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@@ -2129,6 +2130,11 @@ pxregsave(unsigned short wait) {
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if (crs[OWNERL] == 0 || (crs[KEYS] & 1))
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return;
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/* NB: I think hardware might save the base registers in a predictable
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location in the PCB register save area, rather than compressed in a
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random order, because IIRC, Primos sometimes looks at a waiting
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process' PB to see where it is waiting */
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pcbp = *(unsigned int *)(crs+OWNER);
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regp = pcbp+PCBREGS;
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mask = 0;
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@@ -4085,7 +4091,8 @@ irtn:
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case 000505: /* SVC */
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TRACE(T_FLOW, " SVC\n");
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svc();
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fault(SVCFAULT, 0, 0);
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fatal("Returned from SVC fault");
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continue;
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case 000111: /* CEA */
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@@ -4438,8 +4445,8 @@ irtn:
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long delayusec, actualmsec;
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/* for BDX *-1 loop (backstop process mainly), we want to change
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this to a 10ms sleep so that the emulation host doesn't peg the
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CPU.
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this to a 10ms sleep so that the emulation host's CPU isn't
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pegged the whole time the emulator is running.
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So first, check to see if any device times expire sooner than
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this, and if so, limit the sleep time to the lowest expiration
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@@ -6018,7 +6025,7 @@ keys = 14200, modals=100177
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case 01002:
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if (crs[KEYS] & 010000) { /* V/I mode */
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//traceflags = ~TB_MAP;
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TRACE(T_FLOW|T_PCL, " PCL %s\n", searchloadmap(ea, 'e'));
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//TRACE(T_FLOW|T_PCL, "#%d %o/%o: PCL %o/%o\n", instcount, RPH, RPL-2, ea>>16, ea&0xFFFF);
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if (numtraceprocs > 0 && TRACEUSER)
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for (i=0; i<numtraceprocs; i++)
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@@ -6029,7 +6036,6 @@ keys = 14200, modals=100177
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printf("Enabled trace for %s at sb '%o/%o\n", traceprocs[i].name, crs[SBH], crs[SBL]);
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break;
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}
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TRACE(T_FLOW|T_PCL, " PCL %s\n", searchloadmap(ea, 'e'));
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pcl(ea);
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} else {
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TRACE(T_FLOW, " CREP\n");
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@@ -6491,7 +6497,27 @@ keys = 14200, modals=100177
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}
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}
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/* here for PIO instructions: OCP, SKS, INA, OTA. The instruction
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word is passed in as an argument to handle EIO (Execute I/O) in
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V-mode.
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*/
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pio(unsigned int inst) {
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int class;
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int func;
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int device;
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RESTRICT();
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class = inst >> 14;
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func = (inst >> 6) & 017;
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device = inst & 077;
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TRACE(T_INST, " pio, class=%d, func='%o, device='%o\n", class, func, device);
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devmap[device](class, func, device);
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}
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#if 0
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/* Handle SVC instruction. For real hardware emulation on an R-mode
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such as the P300, SVC would interrupt (JST*) through location '75
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(in vectored mode) or would fault on the P400.
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@@ -7115,23 +7141,4 @@ badsvc:
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printf(" halting on bad svc, class=%o, func=%o\n", class, func);
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fatal(NULL);
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}
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/* here for PIO instructions: OCP, SKS, INA, OTA. The instruction
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word is passed in as an argument to handle EIO (Execute I/O) in
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V-mode.
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*/
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pio(unsigned int inst) {
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int class;
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int func;
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int device;
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RESTRICT();
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class = inst >> 14;
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func = (inst >> 6) & 017;
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device = inst & 077;
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TRACE(T_INST, " pio, class=%d, func='%o, device='%o\n", class, func, device);
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devmap[device](class, func, device);
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}
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#endif
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