From bffaa206bfca74183b03fe35695a4a2a7f9983d1 Mon Sep 17 00:00:00 2001
From: Jim <prirun@gmail.com>
Date: Mon, 8 Aug 2011 19:03:25 -0400
Subject: [PATCH] CPUT4 halt at 10203 reveals that the field length register
 bits 60-64 are the high-order bits of the length, not the low-order bits as I
 had assumed.

---
 em.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/em.c b/em.c
index b068675..7c4c282 100644
--- a/em.c
+++ b/em.c
@@ -3817,8 +3817,8 @@ static sssn() {
 
 /* Character instructions */
 
-#define GETFLR(n) (((crsl[FLR0+2*(n)] >> 11) & 0x1FFFE0) | (crsl[FLR0+2*(n)] & 0x1F))
-#define PUTFLR(n,v) crsl[FLR0+2*(n)] = (((v) << 11) & 0xFFFF0000) | (crsl[FLR0+2*(n)] & 0xF000) | ((v) & 0x1F)
+#define GETFLR(n) ((crsl[FLR0+2*(n)] >> 16) | ((crsl[FLR0+2*(n)] & 0x1F) << 16))
+#define PUTFLR(n,v) crsl[FLR0+2*(n)] = (((v) << 16) | (crsl[FLR0+2*(n)] & 0xF000) | (((v) >> 16) & 0x1F))
 
 static inline unsigned short ldc(int n, unsigned short result) {
   unsigned int utempl;