mirror of
https://github.com/prirun/p50em.git
synced 2026-01-22 18:21:22 +00:00
SSSN serial # hack, share shift procs, DIV/DVL overflow fix
hack to patch Primos 23K on the fly for SSSN check added procs for all shifts so 32I can use them fixed DIV & DVL to handle overflow correctly
This commit is contained in:
Jim
parent
d40c4bad82
commit
d306a85352
531
em.c
531
em.c
@ -646,9 +646,11 @@ pa_t mapva(ea_t ea, short intacc, unsigned short *access, ea_t rp) {
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seg = SEGNO32(ea);
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ring = ((rp | ea) >> 29) & 3; /* current ring | ea ring = access ring */
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/* NOTE: cpu.amgrr expects code executing in seg 0 and data references to
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seg 0 to go through mapping. Probably need to check the mapped I/O bit
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only for DMX I/O requests */
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/* NOTE: cpu.amgrr expects code executing in seg 0 and data
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references to seg 0 to go through mapping. Probably still need
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to check the mapped I/O bit for DMX I/O requests: there are 4
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combinations of segmentation and mapped I/O mode bits */
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if (crs[MODALS] & 4) {
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stlbix = STLBIX(ea);
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stlbp = stlb+stlbix;
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@ -717,7 +719,6 @@ pa_t mapva(ea_t ea, short intacc, unsigned short *access, ea_t rp) {
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/* NOTE: could also take a missing memory check here... */
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}
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/* these are shorthand macros for get/put that use the current program
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counter - the typical usage - or Ring 0, the other typical case.
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The other places the ring field is important are PCL (ring may be
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@ -1907,11 +1908,17 @@ pcl (ea_t ecbea) {
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stackrootseg = get16((*(unsigned int *)(crs+SB)) + 1);
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TRACE(T_PCL, " stack root in ecb was zero, stack root from caller is %o\n", stackrootseg);
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}
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#if 0
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/* NOTE: higher revs of Primos establish stacks in segment zero and
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bomb if this check is enabled */
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if (stackrootseg == 0)
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fatal("Stack base register root segment is zero");
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#endif
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stackfp = get32r(MAKEVA(stackrootseg,0), newrp);
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#if 0
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if (stackfp == 0)
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fatal("Stack free pointer is zero");
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#endif
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TRACE(T_PCL, " stack free pointer: %o/%o, current ring=%o, new ring=%o\n", stackfp>>16, stackfp&0xFFFF, (RPH&RINGMASK16)>>13, (newrp&RINGMASK32)>>29);
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stacksize = ecb[2];
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@ -2693,12 +2700,19 @@ lpsw() {
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}
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}
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#if 0
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/* XXX: hack to disable serial number checking if E32I is enabled.
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/* XXX: hack to disable serial number checking if a cpuid > 4 is used.
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Look for ERA/ANA sequence after illegal shift instruction (SSSN),
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set the ANA operand to zero. */
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ea = MAKEVA(014,040747);
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printf("Current value of 14/40747 is: %o\n", get16(ea));
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put16(0,ea);
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/* patch SBL instruction to clear L instead */
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ea = MAKEVA(014,020104);
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printf("Current value of 14/20104 is: %o\n", get16(ea));
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put16(0140010, ea);
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put16(0140010, ea+1);
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#endif
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}
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@ -2815,6 +2829,151 @@ arfa(int n, int val) {
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}
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/* 32-bit shifts */
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unsigned int lrs(unsigned int val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 32) {
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EXPCL(val & bitmask32[33-scount]);
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return (*(int *)&val) >> scount;
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} else if (val & 0x80000000) {
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SETCL;
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return 0xFFFFFFFF;
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} else
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return 0;
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}
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unsigned int lls(unsigned int val, short scount) {
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int templ;
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount < 32) {
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templ = 0x80000000;
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templ = templ >> scount; /* create mask */
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templ = templ & val; /* grab bits */
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templ = templ >> (31-scount); /* extend them */
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EXPCL(!(templ == -1 || templ == 0));
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return *(int *)&val << scount;
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} else {
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EXPCL(val != 0);
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return 0;
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}
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}
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unsigned int lll(unsigned int val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 32) {
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EXPCL(val & bitmask32[scount]);
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return val << scount;
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} else
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return 0;
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}
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unsigned int lrl(unsigned int val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 32) {
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EXPCL(val & bitmask32[33-scount]);
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return val >> scount;
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} else
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return 0;
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}
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/* 16-bit shifts */
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unsigned short arl (unsigned short val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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EXPCL(val & bitmask16[17-scount]);
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return val >> scount;
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} else {
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return 0;
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}
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}
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unsigned short all (unsigned short val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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EXPCL(val & bitmask16[scount]);
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return val << scount;
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} else {
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return 0;
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}
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}
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unsigned short als (unsigned short val, short scount) {
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short tempa;
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 15) {
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tempa = 0100000;
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tempa = tempa >> scount; /* create mask */
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tempa = tempa & val; /* grab bits */
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tempa = tempa >> (15-scount); /* extend them */
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EXPCL(!(tempa == -1 || tempa == 0));
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return val << scount;
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}
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if (val != 0)
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SETCL;
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return 0;
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}
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unsigned short ars (unsigned short val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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EXPCL(val & bitmask16[17-scount]);
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return (*(short *)&val) >> scount;
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} else if (val & 0x8000) {
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SETCL;
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return 0xFFFF;
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} else
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return 0;
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}
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/* 32-bit rotates */
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unsigned int lrr(unsigned int val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount > 32)
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scount = scount - 32;
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EXPCL(val & bitmask32[33-scount]);
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return (val >> scount) | (val << (32-scount));
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}
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unsigned int llr(unsigned int val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount > 32)
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scount = scount - 32;
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EXPCL(val & bitmask32[scount]);
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return (val << scount) | (val >> (32-scount));
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}
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/* 16-bit rotates */
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unsigned int alr(unsigned short val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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scount = ((scount-1)%16)+1; /* make scount 1-16 */
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EXPCL(val & bitmask16[scount]);
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return (val << scount) | (val >> (16-scount));
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}
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unsigned int arr(unsigned short val, short scount) {
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crs[KEYS] &= ~0120000; /* clear C,L */
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scount = ((scount-1)%16)+1; /* make scount 1-16 */
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EXPCL(val & bitmask16[17-scount]);
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return (val >> scount) | (val << (16-scount));
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}
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/* queue instructions
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NOTE: ABQ is typically used in software to add an item to a
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@ -3080,7 +3239,7 @@ main (int argc, char **argv) {
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short tempa,tempa1,tempa2;
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unsigned short utempa,utempa1,utempa2;
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int templ,templ1,templ2;
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long long templl,templl1, templl2;
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long long templl,templl1,templl2;
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unsigned long long utempll, utempll1, utempll2;
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unsigned int utempl,utempl1,utempl2,utempl3,utempl4;
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float tempf,tempf1,tempf2;
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@ -3239,6 +3398,7 @@ main (int argc, char **argv) {
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if (numtraceprocs >= MAXTRACEPROCS)
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fprintf(stderr,"Only %d trace procs are allowed\n", MAXTRACEPROCS);
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else {
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printf("Request to trace proc %s\n", argv[i]);
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traceprocs[numtraceprocs].oneshot = 1;
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for (j=0; argv[i][j]; j++)
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if (argv[i][j] == '+')
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@ -3468,11 +3628,6 @@ For disk boots, the last 3 digits can be:\n\
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traceflags = 0;
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#endif
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#if 0
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if (instcount > 77500000)
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traceflags = ~TB_MAP;
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#endif
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#if 0
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/* NOTE: this tends to cause a page fault loop if the location
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being monitored isn't wired */
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@ -3505,6 +3660,15 @@ For disk boots, the last 3 digits can be:\n\
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traceflags = 0;
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#endif
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#if 1
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/* NOTE: rev 23.4 halts at inst #75379065 with the error:
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"System Serial Number does not agree with this version of Primos."
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To track this down, turn on tracing just before this instruction. */
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if (75370000 < instcount && instcount < 75380000)
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traceflags = ~TB_MAP;
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#endif
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/* poll any devices that requested a poll */
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for (i=0; i<64; i++)
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@ -3822,7 +3986,7 @@ stfa:
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case 001015:
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TRACE(T_FLOW, " TAK\n");
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newkeys(crs[A] & 0177770);
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newkeys(crs[A] & 0177774);
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continue;
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case 000001:
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@ -5370,32 +5534,15 @@ a1a:
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case 00000: /* LRL */
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TRACE(T_FLOW, " LRL %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 32) {
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utempl = *(unsigned int *)(crs+L);
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EXPCL(utempl & bitmask32[33-scount]);
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*(unsigned int *)(crs+L) = utempl >> scount;
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} else {
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*(unsigned int *)(crs+L) = 0;
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}
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crsl[GR2] = lrl(crsl[GR2], scount);
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break;
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case 00100: /* LRS (different in R & V modes) */
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TRACE(T_FLOW, " LRS %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (crs[KEYS] & 010000) { /* V/I mode */
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if (scount <= 32) {
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templ = *(int *)(crs+L);
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EXPCL(templ & bitmask32[33-scount]);
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templ = templ >> scount;
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*(int *)(crs+L) = templ;
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} else if (crs[A] & 0x8000) {
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*(int *)(crs+L) = 0xFFFFFFFF;
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SETCL;
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} else {
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*(int *)(crs+L) = 0;
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}
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crsl[GR2] = lrs(crsl[GR2], scount);
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} else {
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crs[KEYS] &= ~0120000; /* clear C,L */
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utempa = crs[B] & 0x8000; /* save B bit 1 */
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if (scount <= 31) {
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templ = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
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@ -5414,88 +5561,50 @@ a1a:
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case 00200: /* LRR */
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TRACE(T_FLOW, " LRR %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount > 32)
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scount = scount - 32;
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utempl = *(unsigned int *)(crs+L);
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EXPCL(utempl & bitmask32[33-scount]);
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utempl = (utempl >> scount) | (utempl << (32-scount));
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*(unsigned int *)(crs+L) = utempl;
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crsl[GR2] = lrr(crsl[GR2], scount);
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break;
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case 00300:
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if (inst == 040310) {
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printf("SSSN @ %o/%o\n", RPH, RPL);
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/* savetraceflags = traceflags = ~TB_MAP; /*****/
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TRACE(T_FLOW, " SSSN\n", inst);
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#if 0
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/* NOTE: there is no UII handler for SSSN in higher revs
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of Primos, or it isn't setup early enough, and enabling
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a UII here causes late-rev Primos boots to fail */
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fault(UIIFAULT, RPL, RP);
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#endif
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break;
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}
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goto badshift;
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case 00400: /* ARL */
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TRACE(T_FLOW, " ARL %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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EXPCL(crs[A] & bitmask16[17-scount]);
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crs[A] = crs[A] >> scount;
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} else {
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crs[A] = 0;
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}
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crs[A] = arl(crs[A], scount);
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break;
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case 00500: /* ARS */
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TRACE(T_FLOW, " ARS %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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tempa = *(short *)(crs+A);
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EXPCL(tempa & bitmask16[17-scount]);
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tempa = tempa >> scount;
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*(short *)(crs+A) = tempa;
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} else if (crs[A] & 0x8000) {
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*(short *)(crs+A) = 0xFFFF;
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SETCL;
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} else {
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*(short *)(crs+A) = 0;
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}
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crs[A] = ars(crs[A], scount);
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break;
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case 00600: /* ARR */
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TRACE(T_FLOW, " ARR %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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scount = ((scount-1)%16)+1; /* make scount 1-16 */
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EXPCL(crs[A] & bitmask16[17-scount]);
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crs[A] = (crs[A] >> scount) | (crs[A] << (16-scount));
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crs[A] = arr(crs[A], scount);
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break;
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case 01000: /* LLL */
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TRACE(T_FLOW, " LLL %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 32) {
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utempl = *(unsigned int *)(crs+A);
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EXPCL(utempl & bitmask32[scount]);
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utempl = utempl << scount;
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*(unsigned int *)(crs+A) = utempl;
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} else {
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*(unsigned int *)(crs+A) = 0;
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}
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crsl[GR2] = lll(crsl[GR2], scount);
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break;
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case 01100: /* LLS (different in R/V modes) */
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TRACE(T_FLOW, " LLS %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (crs[KEYS] & 010000) { /* V/I mode */
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if (scount < 32) {
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templ = 0x80000000;
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templ = templ >> scount; /* create mask */
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templ = templ & *(int *)(crs+A); /* grab bits */
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templ = templ >> (31-scount); /* extend them */
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EXPCL(!(templ == -1 || templ == 0));
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*(int *)(crs+A) = *(int *)(crs+A) << scount;
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} else {
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EXPCL(*(int *)(crs+A) != 0);
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*(int *)(crs+A) = 0;
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}
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} else {
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if (crs[KEYS] & 010000) /* V/I mode */
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crsl[GR2] = lls(crsl[GR2], scount);
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else {
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crs[KEYS] &= ~0120000; /* clear C,L */
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utempa = crs[B] & 0x8000; /* save B bit 1 */
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if (scount < 31) {
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utempl = (crs[A]<<16) | ((crs[B] & 0x7FFF)<<1);
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@ -5520,50 +5629,24 @@ a1a:
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case 01200: /* LLR */
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TRACE(T_FLOW, " LLR %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount > 32)
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scount = scount - 32;
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utempl = *(unsigned int *)(crs+A);
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EXPCL(utempl & bitmask32[scount]);
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utempl = (utempl << scount) | (utempl >> (32-scount));
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*(unsigned int *)(crs+A) = utempl;
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crsl[GR2] = llr(crsl[GR2], scount);
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break;
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case 01400: /* ALL */
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TRACE(T_FLOW, " ALL %d\n", scount);
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crs[KEYS] &= ~0120000; /* clear C,L */
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if (scount <= 16) {
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EXPCL(crs[A] & bitmask16[scount]);
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crs[A] = crs[A] << scount;
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} else {
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crs[A] = 0;
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}
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crs[A] = all(crs[A], scount);
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break;
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case 01500: /* ALS */
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TRACE(T_FLOW, " ALS %d\n", scount);
|
||||
crs[KEYS] &= ~0120000; /* clear C,L */
|
||||
if (scount <= 15) {
|
||||
tempa = 0100000;
|
||||
tempa = tempa >> scount; /* create mask */
|
||||
tempa = tempa & crs[A]; /* grab bits */
|
||||
tempa = tempa >> (15-scount); /* extend them */
|
||||
crs[A] = crs[A] << scount;
|
||||
EXPCL(!(tempa == -1 || tempa == 0));
|
||||
} else if (crs[A] != 0) {
|
||||
crs[A] = 0;
|
||||
SETCL;
|
||||
}
|
||||
crs[A] = als(crs[A], scount);
|
||||
if (crs[KEYS] & 0100000)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
|
||||
case 01600: /* ALR */
|
||||
TRACE(T_FLOW, " ALR %d\n", scount);
|
||||
crs[KEYS] &= ~0120000; /* clear C,L */
|
||||
scount = ((scount-1)%16)+1; /* make scount 1-16 */
|
||||
EXPCL(crs[A] & bitmask16[scount]);
|
||||
crs[A] = (crs[A] << scount) | (crs[A] >> (16-scount));
|
||||
crs[A] = alr(crs[A], scount);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -6699,12 +6782,57 @@ keys = 14200, modals=100177
|
||||
|
||||
case 005:
|
||||
TRACE(T_FLOW, " SHL\n");
|
||||
warn("IXX: SHL not implemented");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = lll(crsl[dr], scount);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = all(crs[dr*2], scount);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrl(crsl[dr], scount);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = arl(crs[dr*2], scount);
|
||||
break;
|
||||
default:
|
||||
fatal("SHL?");
|
||||
}
|
||||
continue;
|
||||
|
||||
case 006: /* Special MR FP format */
|
||||
/* DFC, DFL, FC, FL */
|
||||
warn("IXX opcode 006");
|
||||
switch (dr) {
|
||||
case 0:
|
||||
case 2:
|
||||
dr &= 2;
|
||||
TRACE(T_INST, " FL\n");
|
||||
break;
|
||||
|
||||
case 1:
|
||||
case 3:
|
||||
dr &= 2;
|
||||
TRACE(T_INST, " DFL\n");
|
||||
break;
|
||||
|
||||
case 4:
|
||||
case 6:
|
||||
dr &= 2;
|
||||
TRACE(T_INST, " FC\n");
|
||||
break;
|
||||
|
||||
case 5:
|
||||
case 7:
|
||||
dr &= 2;
|
||||
TRACE(T_INST, " DFC\n");
|
||||
break;
|
||||
|
||||
default:
|
||||
fatal("I-mode 006 switch?");
|
||||
}
|
||||
continue;
|
||||
|
||||
case 007:
|
||||
@ -6750,7 +6878,29 @@ keys = 14200, modals=100177
|
||||
|
||||
case 015:
|
||||
TRACE(T_FLOW, " SHA\n");
|
||||
warn("IXX 015");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = lls(crsl[dr], scount);
|
||||
if (crs[KEYS] & 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = als(crs[dr*2], scount);
|
||||
if (crs[KEYS] & 0100400)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrs(crsl[dr], scount);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = ars(crs[dr*2], scount);
|
||||
break;
|
||||
default:
|
||||
fatal("SHA?");
|
||||
}
|
||||
continue;
|
||||
|
||||
case 016: /* Special MR FP format */
|
||||
@ -6795,7 +6945,25 @@ keys = 14200, modals=100177
|
||||
|
||||
case 024:
|
||||
TRACE(T_FLOW, " ROT\n");
|
||||
warn("IXX 024");
|
||||
scount = -ea & 077;
|
||||
if (scount == 0)
|
||||
scount = 0100;
|
||||
switch ((ea >> 14) & 3) {
|
||||
case 0:
|
||||
crsl[dr] = llr(crsl[dr], scount);
|
||||
break;
|
||||
case 1:
|
||||
crs[dr*2] = alr(crs[dr*2], scount);
|
||||
break;
|
||||
case 2:
|
||||
crsl[dr] = lrr(crsl[dr], scount);
|
||||
break;
|
||||
case 3:
|
||||
crs[dr*2] = arr(crs[dr*2], scount);
|
||||
break;
|
||||
default:
|
||||
fatal("ROT?");
|
||||
}
|
||||
continue;
|
||||
|
||||
case 025:
|
||||
@ -6881,11 +7049,10 @@ keys = 14200, modals=100177
|
||||
TRACE(T_FLOW, " M\n");
|
||||
dr &= 6; /* force dr even */
|
||||
if (*(int *)&ea < 0)
|
||||
utempl = immu32;
|
||||
templ = immu32;
|
||||
else
|
||||
utempl = get32(ea);
|
||||
templl = (long long)(*(int *)(crsl+dr)) * (long long)(*(int *)utempl);
|
||||
*(long long *)(crsl+dr) = templl;
|
||||
templ = get32(ea);
|
||||
*(long long *)(crsl+dr) = (long long)templ * (long long)(*(int *)(crsl+dr));
|
||||
CLEARC;
|
||||
continue;
|
||||
|
||||
@ -7023,10 +7190,10 @@ imodepcl:
|
||||
case 052:
|
||||
TRACE(T_FLOW, " MH\n");
|
||||
if (*(int *)&ea < 0)
|
||||
utempa = (immu32 >> 16);
|
||||
tempa = (immu32 >> 16);
|
||||
else
|
||||
utempa = get16(ea);
|
||||
crsl[dr] = *(short *)(crs+dr*2) * *(short *)&utempa;
|
||||
tempa = get16(ea);
|
||||
crsl[dr] = *(short *)(crs+dr*2) * tempa;
|
||||
CLEARC;
|
||||
continue;
|
||||
|
||||
@ -7111,12 +7278,38 @@ imodepcl:
|
||||
|
||||
case 061:
|
||||
TRACE(T_FLOW, " C\n");
|
||||
warn("I 061");
|
||||
if (*(int *)&ea < 0)
|
||||
utempl = immu32;
|
||||
else
|
||||
utempl = get32(ea);
|
||||
crs[KEYS] &= ~020300;
|
||||
utempll = crsl[dr];
|
||||
if ((utempll + (~utempl & 0xFFFFFFFF) + 1) & 0x100000000LL)
|
||||
crs[KEYS] |= 020000;
|
||||
if (crsl[dr] == utempl)
|
||||
crs[KEYS] |= 0100;
|
||||
else if (*(int *)(crsl+dr) < *(int *)&utempl)
|
||||
crs[KEYS] |= 0200;
|
||||
continue;
|
||||
|
||||
case 062:
|
||||
TRACE(T_FLOW, " D\n");
|
||||
warn("I 062");
|
||||
if (*(int *)&ea < 0)
|
||||
templ = immu32;
|
||||
else
|
||||
templ = get32(ea);
|
||||
dr &= 6; /* force dr even */
|
||||
if (templ != 0) {
|
||||
templl1 = *(long long *)(crsl+dr);
|
||||
templl2 = templl1 / templ;
|
||||
crsl[dr] = templl2;
|
||||
crsl[dr+1] = templl1 % templ;
|
||||
if (-2147483648LL <= templl2 && templl2 <= 2147483647LL)
|
||||
CLEARC;
|
||||
else
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
} else
|
||||
mathexception('i', FC_INT_ZDIV, 0);
|
||||
continue;
|
||||
|
||||
case 063:
|
||||
@ -7175,12 +7368,37 @@ imodepcl:
|
||||
|
||||
case 071:
|
||||
TRACE(T_FLOW, " CH\n");
|
||||
warn("I 071");
|
||||
if (*(int *)&ea < 0)
|
||||
utempa = (immu32 >> 16);
|
||||
else
|
||||
utempa = get16(ea);
|
||||
crs[KEYS] &= ~020300;
|
||||
utempl = crs[dr*2];
|
||||
if ((utempl + (~utempa & 0xFFFF) + 1) & 0x10000)
|
||||
crs[KEYS] |= 020000;
|
||||
if (crs[dr*2] == utempa)
|
||||
crs[KEYS] |= 0100;
|
||||
else if (*(short *)(crs+dr*2) < *(short *)&utempa)
|
||||
crs[KEYS] |= 0200;
|
||||
/* IXX should set the L bit like subtract */
|
||||
continue;
|
||||
|
||||
case 072:
|
||||
TRACE(T_FLOW, " DH\n");
|
||||
warn("I 072");
|
||||
if (*(int *)&ea < 0)
|
||||
tempa = (immu32 >> 16);
|
||||
else
|
||||
tempa = get16(ea);
|
||||
if (tempa != 0) {
|
||||
templ1 = *(int *)(crsl+dr);
|
||||
templ2 = templ1 / tempa;
|
||||
crsl[dr] = (templ2 << 16) | (templ1 % tempa);
|
||||
if (-32768 <= templ2 && templ2 <= 32767)
|
||||
CLEARC;
|
||||
else
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
} else
|
||||
mathexception('i', FC_INT_ZDIV, 0);
|
||||
continue;
|
||||
|
||||
case 073:
|
||||
@ -7535,37 +7753,29 @@ nonimode:
|
||||
case 01603:
|
||||
templ = get32(ea);
|
||||
TRACE(T_FLOW, " MPL ='%o/%d\n", templ, *(int *)&templ);
|
||||
templl = (long long)(*(int *)(crs+L)) * (long long)templ;
|
||||
*(long long *)(crs+L) = templl;
|
||||
*(long long *)(crs+L) = (long long)(*(int *)(crs+L)) * (long long)templ;
|
||||
CLEARC;
|
||||
continue;
|
||||
|
||||
case 01700:
|
||||
m = get16(ea);
|
||||
//printf("L='%o/%d, DIV ='%o/%d\n", *(unsigned int *)(crs+L), *(int *)(crs+L), m, *(short *)&m);
|
||||
TRACE(T_FLOW, " DIV ='%o/%d\n", m, *(short *)&m);
|
||||
tempa = get16(ea);
|
||||
TRACE(T_FLOW, " DIV ='%o/%d\n", *(unsigned short *)&tempa, tempa);
|
||||
if (crs[KEYS] & 010000) { /* V/I mode */
|
||||
templ = *(int *)(crs+A);
|
||||
} else { /* R/S mode */
|
||||
templ = *(short *)(crs+A); /* convert to 32-bit signed */
|
||||
} else { /* R/S mode */
|
||||
templ = *(short *)(crs+A); /* convert to 32-bit signed */
|
||||
templ = (templ<<15) | (crs[B] & 0x7FFF);
|
||||
//printf("\nR-mode DIV: A='%o/%d, B='%o/%d, templ='%o/%d\n", crs[A], *(short *)(crs+A), crs[B], *(short *)(crs+B), templ, templ);
|
||||
}
|
||||
if (m == 0)
|
||||
mathexception('i', FC_INT_ZDIV, 0);
|
||||
else if (abs(*(short *)(crs+A)) < abs(*(short *)&m)) {
|
||||
templ2 = templ / *(short *)&m;
|
||||
if (tempa != 0) {
|
||||
templ2 = templ / tempa;
|
||||
crs[A] = templ2;
|
||||
crs[B] = templ % *(short *)&m;
|
||||
//printf("DIV results: m='%o/%d, A='%o/%d, B='%o/%d\n", m, *(short *)&m, crs[A], *(short *)(crs+A), crs[B], *(short *)(crs+B));
|
||||
if ((crs[A] & 0x8000) ^ (templ2 & 0x80000000)>>16)
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
else
|
||||
crs[B] = templ % tempa;
|
||||
if (-32768 <= templ2 && templ2 <= 32767)
|
||||
CLEARC;
|
||||
} else {
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
//printf("DIV overflow\n");
|
||||
}
|
||||
else
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
} else
|
||||
mathexception('i', FC_INT_ZDIV, 0);
|
||||
continue;
|
||||
|
||||
/* NOTE: RESET QVFY, DVL runs okay with cpuid=5 (P750), but
|
||||
@ -7573,12 +7783,16 @@ nonimode:
|
||||
|
||||
case 01703:
|
||||
templ = get32(ea);
|
||||
TRACE(T_FLOW, " DVL ='%o/%d\n", templ, *(int *)&templ);
|
||||
templl = *(long long *)(crs+L);
|
||||
TRACE(T_FLOW, " DVL ='%o/%d\n", templ, templ);
|
||||
if (templ != 0) {
|
||||
*(int *)(crs+L) = templl / templ;
|
||||
*(int *)(crs+E) = templl % templ;
|
||||
CLEARC;
|
||||
templl1 = *(long long *)(crs+L);
|
||||
templl2 = templl1 / templ;
|
||||
*(int *)(crs+L) = templl2;
|
||||
*(int *)(crs+E) = templl1 % templ;
|
||||
if (-2147483648LL <= templl2 && templl2 <= 2147483647LL)
|
||||
CLEARC;
|
||||
else
|
||||
mathexception('i', FC_INT_OFLOW, 0);
|
||||
} else
|
||||
mathexception('i', FC_INT_ZDIV, 0);
|
||||
continue;
|
||||
@ -7802,10 +8016,15 @@ nonimode:
|
||||
case 0201:
|
||||
TRACE(T_FLOW, " FLD\n");
|
||||
utempl = get32(ea);
|
||||
#if 1
|
||||
crs[FLTH] = utempl >> 16;
|
||||
crs[FLTL] = utempl & 0xFF00;
|
||||
crs[FEXP] = utempl & 0xFF;
|
||||
crs[FLTD] = 0;
|
||||
#else
|
||||
crsl[FAC1] = utempl & 0xFFFFFF00;
|
||||
crsl[FAC1+1] = (utempl & 0xFF) << 16;
|
||||
#endif
|
||||
TRACE(T_INST, " FEXP=%d (dec), FLTH='%o, FLTL='%o\n", crs[FEXP], crs[FLTH], crs[FLTL]);
|
||||
continue;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user