From f0983d6ccbd91f347fadb411787b62664cedbac4 Mon Sep 17 00:00:00 2001
From: Jim <prirun@gmail.com>
Date: Tue, 9 Aug 2011 09:04:15 -0400
Subject: [PATCH] Preserve fault and E bits in EAFA instructions to pass CPUT4
 T&M halt at 7753 and 10061.  At 7753, CPUT4 loads -1L into the SB register,
 EAFA 1,SB%, then LDLR '12 to get the FAR1 register value.  It expects it to
 be -1.  For the test at 10061, EAFA was clearing the E-bit in FAR1, but the
 test expected it to be set.  The emulator never uses the E-bit in the FAR (it
 only looks at bitno), so it doesn't matter how the E-bit is set in the
 register.

---
 em.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/em.c b/em.c
index 7c4c282..b13b7fe 100644
--- a/em.c
+++ b/em.c
@@ -5264,7 +5264,7 @@ d_stc1:  /* 001332 */
 d_eafa0:  /* 001300 */
   TRACE(T_FLOW, " EAFA 0\n");
   ea = apea(&eabit);
-  crsl[FAR0] = ea & 0x6FFFFFFF;
+  crsl[FAR0] = ea;
   crsl[FLR0] = (crsl[FLR0] & 0xFFFF0FFF) | (eabit << 12);
   TRACE(T_INST, " FAR0=%o/%o, eabit=%d, FLR=%x\n", crsl[FAR0]>>16, crsl[FAR0]&0xFFFF, eabit, crsl[FLR0]);
   goto fetch;
@@ -5272,7 +5272,7 @@ d_eafa0:  /* 001300 */
 d_eafa1:  /* 001310 */
   TRACE(T_FLOW, " EAFA 1\n");
   ea = apea(&eabit);
-  crsl[FAR1] = ea & 0x6FFFFFFF;
+  crsl[FAR1] = ea;
   crsl[FLR1] = (crsl[FLR1] & 0xFFFF0FFF) | (eabit << 12);
   TRACE(T_INST, " FAR1=%o/%o, eabit=%d, FLR=%x\n", crsl[FAR1]>>16, crsl[FAR1]&0xFFFF, eabit, crsl[FLR1]);
   goto fetch;