It appears that the emulator needs to check for faulted pointers
after indirection in APs used in e.g. EAFA. PASCAL triggers this
issue by using EAFA on an indirect pointer to a DYNT. A two cycle
fault check is done other places, and the approach is repeated here.
As it was in the real world, especially with dialup ports, it is possible
for an emulator AMLC line to get blocked by stray flow control characters.
The blocked port may appear dead to the next user to connect, if they are
not "serial savvy" enough to try sending an XON character.
A large number of vulnerability scanners have found and have been hitting
the public emulators, injecting HTTP transactions or worse into the AMLC
ports and often locking all of them daily.
This workaround injects an XON (DC1, 0221) and a line kill character as
extracted from the DEFKIL field in FIGCOM, into the AMLC line when a new
connection is received.
There is a -dolineclear command line switch to enable the behavior.
Due to the configuration of the tty, the getchar() call in d_hlt
returns nothing. Work around this in the same way the SOC console
code does, by opening it on a separate unit, and reading from that
instead. Without this fix, the code which looks for certain halt
cases and offers "continue or exit" just spins, printing its message
and getting no input.
Deconflict some values of instruction count with some of the
other tracing options by making it require a leading # before
the integer count.
Add/fix support for tracing execution within a designated segno.
Announce to the trace file that tracing is initialized.
system to operate as a HASP station in an RJE environment. This implementation is
compatible with Bisync/HASP emulation in the Hercules IBM mainframe emulator and the
DtCyber CDC mainframe emulator.
PRIMOS2 was built to be relocated after being loaded by BOOT.
The build process rewrote the RVEC in the save file. The SA was anded
with :160000; the result was subtracted from SA and EA in the RVEC,
and stored into RA in the RVEC. The BOOT program knew to add the RA
value during the load process.
This change causes the emulator to recognize such an RVEC when booting
an R-mode executable from unix disk, and to adjust the RVEC before
actually loading the program. This fixes failure to boot *DOS64 from
19.2.9, for example.
The code only makes this adjustment if RA is non-zero, and RP is not
between SA and EA.
Now that instpermsec is being adjusted every second instead of every
5 seconds, the initial value of instpermsec is not so critical. This
benchmark gave wildly varying results on different system and compilers.
Previously iget16 was used for all instruction fetches, with the
assumption that any could trap. But actually, only the first word of
the instruction stream can trap in V mode, which is why these
instructions must be short. Both words of a long R-mode instruction
can trap.
Tested change by booting R19 with and without -DFAST, all other revs
with -DFAST, and basic with trace on in R19 (this executes code from
the DFAC)
In slow mode (compiled without -DFAST), Rev. 19 would crash during
boot. On investigation, the code was branching to '4 after setting
up an instruction there. However, instruction fetch found a '0
instead of the expected instruction.
Instructions might be fetched from registers via trap. Fast iget16()
checks for fault. Slow iget16() does not, and just calls get16() which
does not check.
The initial estimate for instructions per millisec (instpermses) was
much too low for modern CPUs, and was also only updated every 5
seconds. Combined, these were causing the clock to be erratic during
the first 5-15 seconds of system boot.
This was easily noticed by running the MIPS benchmark program right
after a system boot, where instead of delaying 5 seconds, it might
only delay 2 seconds, and then would report a bogus MIPS rating.
Waiting a minute and running it again would give an accurate rating.
Adjusting the instpermsec initial value from 2000 to 40000 and
IPMSTIME time from 5000 ms to 1000 ms (every second vs 5 seconds)
fixes the problem.
The emulator reads SEG load maps for Primos and displays symbolic
names and offsets during tracing. But when running in S/R modes
during initial startup, there is no point in doing a load map lookup
and it's somewhat confusing to see segment 0 symbol names printed for
all effective addresses. A blank name was already printed for
user-mode S/R traces because the segment number is > 01777, usually
04000.
Removed comment about memory needing to be a power of 2. Testing
-mem 9 worked fine with rev 20:
OK, stat sys
System is currently running PRIMOS rev. 20.2.8
Copyright (c) Prime Computer, Inc. 1985
9216K bytes memory in use
It was confusing that MAXMB is the default memory size, so renamed it
to DEFMB. MEMSIZE was not necessary (half of MAXMB) and MEMMASK was
used only in mapva to limit physcal addresses when segmentation was
not enabled. However, this appears to be a bug, because it would
cause memory addresses larger than physical memory to wrap and succeed
rather than generate a missing memory check.
History: when the emulator was first developed on OSX 10.4 (PowerPC),
the inline keyword was added by profiling with Apple's pretty
fantastic Shark profiler. Apple's version of gcc had an -fobey-inline
switch that the makefile used to force gcc to obey the inline keyword.
This macro does the same thing
37.5 Prime MIPS on Linode VM to 42.5 MIPS. gvp-> was faster on the
PowerPC architecture when gvp was kept in a dedicated register, but
that does not apply to Intel.
Old:
Timing CPU, 20.0 ticks per second...
35.3 Prime MIPS for 16-bit ADD loop
40.0 Prime MIPS for 16-bit MPY loop
42.1 Prime MIPS for 16-bit DIV loop
21.4 Prime MIPS for 32-bit ADD loop
30.8 Prime MIPS for 32-bit MPY loop
28.6 Prime MIPS for 32-bit DIV loop
57.1 Prime MIPS for 16-bit X=0 loop
44.4 Prime MIPS for 32-bit X=0 loop
37.5 average Prime MIPS
New:
Timing CPU, 20.0 ticks per second...
42.9 Prime MIPS for 16-bit ADD loop
53.3 Prime MIPS for 16-bit MPY loop
47.1 Prime MIPS for 16-bit DIV loop
24.0 Prime MIPS for 32-bit ADD loop
38.1 Prime MIPS for 32-bit MPY loop
32.0 Prime MIPS for 32-bit DIV loop
57.1 Prime MIPS for 16-bit X=0 loop
44.4 Prime MIPS for 32-bit X=0 loop
42.4 average Prime MIPS
