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ea64v never needs to return a bit offset added devamlc feature to set room available in user's input buffer misc PNC changes (not working yet)
146 lines
4.5 KiB
C
146 lines
4.5 KiB
C
/* this version is derived from the flowchart in the preliminary P400
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release notes */
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inline ea_t ea64v (ea_t earp, unsigned short inst, short x, unsigned short *opcode) {
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ea_t ea; /* full seg/word va */
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unsigned short ea_s; /* eff address segno */
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unsigned short ea_r; /* eff address ring */
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unsigned short ea_w; /* eff address wordno */
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unsigned short br;
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unsigned short live; /* max live register addr */
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unsigned short i;
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unsigned short y;
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unsigned short xok;
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unsigned short a;
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unsigned short ixy;
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unsigned short m;
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unsigned short rph,rpl;
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i = inst & 0100000; /* indirect is bit 1 (left/MS bit) */
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/* rph/rpl (and earp) are usually = RPH/RPL in the register file,
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except for the case of an XEC instruction; in that case, these
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will point to 1 after the instruction being executed */
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rph = earp >> 16;
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rpl = earp & 0xFFFF;
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//TRACE(T_EAV, " inst=%o, rph=%o, rpl=%o\n", inst, rph, rpl);
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if (crs[MODALS] & 4) /* segmentation enabled? */
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live = 010; /* yes, limit register traps */
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else
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live = 040;
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ea_s = rph;
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ea_w = rpl;
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if (inst & 001000) /* sector bit 7 set? */
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if ((inst & 0740) != 0400) { /* PC relative? */
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ea_w = rpl + (((short) (inst << 7)) >> 7); /* yes, sign extend D */
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TRACE(T_EAV, " PC relative, P=%o, new ea_w=%o\n", rpl, ea_w);
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}
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else
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goto labB; /* special cases */
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else if (i) {
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ea_w = (inst & 0777); /* sector 0 */
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TRACE(T_EAV, " Sector 0, new ea_w=%o\n", ea_w);
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if (ea_w < 0100 && x) { /* preindex by X */
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TRACE(T_EAV, " Preindex, ea_w=%o, X='%o/%d\n", ea_w, crs[X], *(short *)(crs+X));
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ea_w += crs[X];
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TRACE(T_EAV, " Preindex, new ea_w=%o\n", ea_w);
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x = 0;
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}
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} else
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goto labA;
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if (i) {
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if (ea_w < live) {
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TRACE(T_EAV, " Indirect through live register '%o\n", ea_w);
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ea_w = get16(0x80000000 | ea_w);
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} else {
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TRACE(T_EAV, " Indirect, ea_s=%o, ea_w=%o\n", ea_s, ea_w);
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ea_w = get16(MAKEVA(ea_s, ea_w));
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}
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TRACE(T_EAV, " After indirect, new ea_w=%o\n", ea_w);
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}
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if (x) {
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TRACE(T_EAV, " Postindex, old ea_w=%o, X='%o/%d\n", ea_w, crs[X], *(short *)(crs+X));
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ea_w += crs[X];
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TRACE(T_EAV, " Postindex, new ea_w=%o\n", ea_w);
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}
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if (ea_w < live) {
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TRACE(T_EAV, " Live register '%o\n", ea_w);
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return 0x80000000 | ea_w;
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}
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return MAKEVA(ea_s, ea_w);
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labA:
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ea_w = (inst & 0777);
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if (x) {
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TRACE(T_EAV, " Postindex, old ea_w=%o, X='%o/%d\n", ea_w, crs[X], *(short *)(crs+X));
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ea_w += crs[X];
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TRACE(T_EAV, " Postindex, new ea_w=%o\n", ea_w);
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}
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if ((inst & 0777) >= 0400) {
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ea_s = crs[LBH] | (ea_s & RINGMASK16);
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ea_w += crs[LBL];
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TRACE(T_EAV, " Short LB relative, LB=%o/%o\n", crs[LBH], crs[LBL]);
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return MAKEVA(ea_s, ea_w);
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}
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if (ea_w < live) {
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TRACE(T_EAV, " Live register '%o\n", ea_w);
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return 0x80000000 | ea_w;
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}
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ea_s = crs[SBH] | (ea_s & RINGMASK16);
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ea_w += crs[SBL];
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TRACE(T_EAV, " Short SB relative, SB=%o/%o\n", crs[SBH], crs[SBL]);
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return MAKEVA(ea_s, ea_w);
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/* here for long, 2-word, V-mode memory reference */
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labB:
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a = iget16(RP);
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RPL++;
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TRACE(T_EAV, " 2-word format, a=%o\n", a);
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y = (inst & 020);
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ixy = ((i != 0)<<2) | ((x != 0)<<1) | (y != 0);
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xok = ((*opcode & 01700) != 01500); /* true if indexing is okay */
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*opcode = *opcode | ((inst >> 2) & 3); /* opcode extension */
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br = (inst & 3);
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TRACE(T_EAV, " new opcode=%5#0o, y=%d, br=%d, ixy=%d, xok=%d\n", *opcode, (y != 0), br, ixy, xok);
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ea_s = crs[PBH+br*2] | (ea_s & RINGMASK16);
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ea_w = crs[PBL+br*2] + a;
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if (xok)
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if (ixy == 1 || ixy == 4)
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ea_w += crs[Y];
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else if (ixy == 2 || ixy == 6)
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ea_w += crs[X];
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if (ixy >= 3) {
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ea = MAKEVA(ea_s, ea_w);
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TRACE(T_EAV, " Long indirect, ea=%o/%o, ea_s=%o, ea_w=%o\n", ea>>16, ea&0xFFFF, ea_s, ea_w);
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m = get16(ea);
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if (m & 0x8000)
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fault(POINTERFAULT, m, ea);
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ea_s = m | (ea_s & RINGMASK16);
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ea_w = get16(INCVA(ea,1));
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#if 0
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if (ea_s & EXTMASK16)
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warn("em: extension bit set in ea64v");
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#endif
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TRACE(T_EAV, " After indirect, ea_s=%o, ea_w=%o\n", ea_s, ea_w);
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}
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if (xok)
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if (ixy == 5)
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ea_w += crs[Y];
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else if (ixy == 7)
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ea_w += crs[X];
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return MAKEVA(ea_s, ea_w);
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}
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