mirror of
https://github.com/prirun/p50em.git
synced 2026-01-18 00:42:32 +00:00
d99d16932d
changed get/put(16,32)r to check for ring change and use regular get/put call if possible, so brp supercache can be used FUTURE: could add separate brp cache entry for R0 accesses changed ea32r64r live register test so normal path is first changed ea64v live register test so normal path is first change ea32i to use INCRP macro instead of RPL++
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
#define IMM_EA 0x80000000
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static inline ea_t ea32i (ea_t earp, unsigned short inst, unsigned long *immu32, unsigned long long *immu64) {
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int tm, sr, br, ring;
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unsigned short d;
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int temp32;
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ea_t ea, ip;
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*immu32 = 0xAAAAAAAA;
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*immu64 = 0xAAAAAAAAAAAAAAAALL;
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tm = (inst >> 5) & 3;
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sr = (inst >> 2) & 7;
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br = inst & 3;
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ring = RP & RINGMASK32;
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TRACE(T_EAI, " tm=%d, sr=%d, dr=%d, br=%d\n", tm, sr, (inst >> 7) & 7, br);
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switch (tm) {
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case 0:
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switch (br) {
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case 0: /* reg-reg */
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*immu32 = crsl[sr];
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return IMM_EA;
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case 1:
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d = iget16(RP);
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RPL++;
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if (sr == 0) /* imm type 1 */
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*immu32 = d << 16;
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else /* imm type 2 */
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*(int *)immu32 = *(short *)&d;
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return IMM_EA;
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case 2:
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switch (sr) {
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case 0: /* imm type 3 */
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d = iget16(RP);
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INCRP;
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*immu64 = (((long long)(d & 0xFF00)) << 48) | (d & 0xFF);
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return IMM_EA;
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case 1: /* FAC0 source */
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*immu64 = *(unsigned long long *)(crsl+FAC0);
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return IMM_EA;
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case 3: /* FAC1 source */
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*immu64 = *(unsigned long long *)(crsl+FAC1);
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return IMM_EA;
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case 2:
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case 4:
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case 5:
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case 6:
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case 7:
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fault(UIIFAULT, RPL, RP);
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fatal("ea32i: return from UII fault!");
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default:
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fatal("ea32i: sr < 0 or > 7?");
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}
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fatal("ea32i: case tm=0 br=2 fall-through");
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case 3: /* GR relative */
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d = iget16(RP);
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INCRP;
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ea = (crsl[sr] & 0xFFFF0000) | ((crsl[sr] + d) & 0xFFFF);
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TRACE(T_EAI, " GRR, d=%x, crsl[sr]=%o/%o, ea=%o/%o\n", d, crsl[sr]>>16, crsl[sr]&0xFFFF, ea>>16, ea&0xFFFF);
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if (ea & 0x80000000)
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fault(POINTERFAULT, ea>>16, ea);
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return ea | ring;
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default:
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fatal("ea32i: tm=0, br < 0 or > 3?");
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}
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fatal("ea32i: tm=0 fall-through");
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case 1: /* TM=1: Direct and Indexed */
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d = iget16(RP);
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INCRP;
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if (sr == 0)
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ea = (crsl[BR+br] & 0xFFFF0000) | ((crsl[BR+br] + d) & 0xFFFF);
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else
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ea = (crsl[BR+br] & 0xFFFF0000) | ((crsl[BR+br] + d + crs[sr*2]) & 0xFFFF);
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return ea | ring;
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case 2: /* TM=2: Indirect and Indirect Preindexed */
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d = iget16(RP);
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INCRP;
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if (sr == 0)
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ea = (crsl[BR+br] & 0xFFFF0000) | ((crsl[BR+br] + d) & 0xFFFF);
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else
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ea = (crsl[BR+br] & 0xFFFF0000) | ((crsl[BR+br] + d + crs[sr*2]) & 0xFFFF);
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ip = get32(ea | ring);
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if (ip & 0x80000000)
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fault(POINTERFAULT, ip>>16, ea);
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return ip | ring;
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case 3: /* TM=3: Indirect and Indirect Postindexed */
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TRACE(T_EAI, " TM=3: Indirect [Postindexed]");
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d = iget16(RP);
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INCRP;
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ea = (crsl[BR+br] & 0xFFFF0000) | ((crsl[BR+br] + d) & 0xFFFF);
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TRACE(T_EAI, " BR[%d]=%o/%o, d=%o, ip ea=%o/%o\n", br, crsl[BR+br]>>16, crsl[BR+br]&0xFFFF, d, ea>>16, ea&0xFFFF);
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ip = get32(ea | ring);
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TRACE(T_EAI, " after indirect, ea=%o/%o\n", ip>>16, ip&0xFFFF);
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if (ip & 0x80000000)
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fault(POINTERFAULT, ip>>16, ea);
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if (sr > 0) {
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ip = (ip & 0xFFFF0000) | ((ip + crs[sr*2]) & 0xFFFF);
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TRACE(T_EAI, " index by crs[%d]='%o/%d, ea=%o/%o\n", sr, crs[sr*2], crs[sr*2], ea>>16, ea&0xFFFF);
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}
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return ip | ring;
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default:
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fatal("ea32i: tm out of range!");
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}
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fatal("ea32i: main switch fall through");
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}
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