mirror of
https://github.com/rcornwell/sims.git
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SEL32: Allow channel address reconfiguration.
SEL32: Add disk definitions for UTX and MPX. SEL32: Add disk initialization for UTX and MPX HSDP & DISK controllers. SEL32: Add read/write track/sector label simulation for UTX & MPX. SEL32: Create revised initialization test files for SIMH.
This commit is contained in:
AZBevier
parent
cde7ef8bb5
commit
18215f0e73
@ -123,6 +123,7 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr);
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t_stat chan_set_devs();
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t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat show_dev_addr(FILE *st, UNIT *uptr, int32 v, CONST void *desc);
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DEVICE *get_dev(UNIT *uptr);
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/* FIFO support */
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/* These are FIFO queues which return an error when full.
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@ -303,7 +304,7 @@ int readfull(CHANP *chp, uint32 maddr, uint32 *word)
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}
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maddr >>= 2; /* get 32 bit word index */
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*word = M[maddr]; /* get the contents */
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sim_debug(DEBUG_EXP, &cpu_dev, "readfull read %08x from addr %08x\n", *word, maddr<<2);
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sim_debug(DEBUG_EXP, &cpu_dev, "READFULL read %08x from addr %08x\n", *word, maddr<<2);
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return 0; /* return OK */
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}
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@ -327,7 +328,7 @@ int readbuff(CHANP *chp)
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addr >>= 2; /* byte to word address */
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chp->chan_buf = M[addr]; /* get 4 bytes */
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sim_debug(DEBUG_DETAIL, &cpu_dev, "readbuff read memory bytes into buffer %02x %06x %08x %08x [",
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sim_debug(DEBUG_DETAIL, &cpu_dev, "readbuff read memory bytes into buffer %02x %06x %06x %04x [",
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chan, chp->ccw_addr & 0xFFFFFC, chp->chan_buf, chp->ccw_count);
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for(k = 24; k >= 0; k -= 8) {
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char ch = (chp->chan_buf >> k) & 0xFF;
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@ -349,13 +350,17 @@ int writebuff(CHANP *chp)
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if ((addr & MASK24) > (MEMSIZE*4)) {
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chp->chan_status |= STATUS_PCHK;
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sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff PCHK addr %08x to big mem %08x status %04x\n", addr, MEMSIZE, chp->chan_status);
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sim_debug(DEBUG_DETAIL, &cpu_dev,
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"writebuff PCHK addr %08x to big mem %08x status %04x\n",
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addr, MEMSIZE, chp->chan_status);
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chp->chan_byte = BUFF_CHNEND;
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irq_pend = 1;
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return 1;
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}
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addr &= MASK24;
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sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff WRITE addr %08x MEMSIZE %08x status %04x\n", addr, MEMSIZE, chp->chan_status);
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sim_debug(DEBUG_DETAIL, &cpu_dev,
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"writebuff WRITE addr %06x DATA %08x status %04x\n",
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addr, chp->chan_buf, chp->chan_status);
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M[addr>>2] = chp->chan_buf;
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return 0;
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}
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@ -372,10 +377,12 @@ int load_ccw(CHANP *chp, int tic_ok)
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CHANP *pchp;
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loop:
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sim_debug(DEBUG_XIO, &cpu_dev, "load_ccw entry chan_status[%04x] %04x\n", chan, chp->chan_status);
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sim_debug(DEBUG_XIO, &cpu_dev,
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"load_ccw entry chan_status[%04x] %04x\n", chan, chp->chan_status);
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/* Abort if we have any errors */
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if (chp->chan_status & 0x3f03) { /* check channel status */
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sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
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if (chp->chan_status & 0x3f03) { /* check channel status */
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sim_debug(DEBUG_EXP, &cpu_dev,
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"load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
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return 1;
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}
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@ -388,13 +395,16 @@ loop:
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/* Read in first or next CCW */
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if (readfull(chp, chp->chan_caw, &word) != 0) { /* read word from memory */
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chp->chan_status |= STATUS_PCHK; /* memory read error, program check */
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sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
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sim_debug(DEBUG_EXP, &cpu_dev,
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"load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
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return 1; /* error return */
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}
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sim_debug(DEBUG_XIO, &cpu_dev, "load_ccw read ccw chan %02x caw %06x IOCD wd 1 %08x\n",
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sim_debug(DEBUG_XIO, &cpu_dev,
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"load_ccw read ccw chan %02x caw %06x IOCD wd 1 %08x\n",
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chan, chp->chan_caw, word);
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sim_debug(DEBUG_XIO, &cpu_dev, "load_ccw read data @ IOCD wd 1 %08x data wd 1 %08x\n",
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sim_debug(DEBUG_XIO, &cpu_dev,
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"load_ccw read data @ IOCD wd 1 %08x data wd 1 %08x\n",
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word, M[(word & 0xffffff)>>2]);
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#ifdef DO_DYNAMIC_DEBUG
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@ -641,8 +651,8 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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return 1; /* return error */
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}
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if (chp->ccw_count == 0) {
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sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte ccw_count is zero ccw_count[%04x] %04x\n",
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chan, chp->ccw_count);
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sim_debug(DEBUG_DETAIL, &cpu_dev, "chan_write_byte ccw_count is zero ccw_count[%04x] %04x\n",
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chan, chp->ccw_count);
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if (chp->chan_byte & BUFF_DIRTY) {
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sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte 2 BUF DIRTY ret\n");
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if (writebuff(chp)) /* write it */
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@ -660,7 +670,8 @@ int chan_write_byte(uint16 chsa, uint8 *data)
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return 1; /* return error */
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}
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}
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sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte non zero ccw_count[%04x]=%04x\n", chan, chp->ccw_count);
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sim_debug(DEBUG_DETAIL, &cpu_dev, "chan_write_byte non zero ccw_count[%04x]=%04x\n",
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chan, chp->ccw_count);
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if (chp->ccw_flags & FLAG_SKIP) {
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chp->ccw_count--;
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chp->chan_byte = BUFF_EMPTY;
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@ -735,8 +746,9 @@ void chan_end(uint16 chsa, uint16 flags) {
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uint32 chan_icb = find_int_icb(chsa); /* get icb address */
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CHANP *chp = find_chanp_ptr(chsa); /* get channel prog pointer */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_end entry chsa %04x flags %04x chan_icb %06x status %04x\n",
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chsa, flags, chan_icb, chp->chan_status);
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_end entry chsa %04x flags %04x chan_icb %06x status %04x\n",
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chsa, flags, chan_icb, chp->chan_status);
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if (chp->chan_byte & BUFF_DIRTY) {
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if (writebuff(chp)) /* write remaining data */
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return; /* error */
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@ -746,8 +758,9 @@ void chan_end(uint16 chsa, uint16 flags) {
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chp->chan_status |= ((uint16)flags); /* add in the callers flags */
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// chp->ccw_cmd = 0; /* reset the completed channel command */
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sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %04x ccw_flags %04x count %04x status %04x\n",
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chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status);
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sim_debug(DEBUG_EXP, &cpu_dev,
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"chan_end SLI test chsa %04x ccw_flags %04x count %04x status %04x\n",
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chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status);
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#ifdef HACK_HACK
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/* hack - rewind had byte count of 1, so triggered this error when it is not */
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/* remove until I figure out what is required */
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@ -876,13 +889,15 @@ t_stat checkxio(uint16 lchsa, uint32 *status) {
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chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */
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chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
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iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */
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tempa = M[(chan_ivl+20)>>2]; /* status is in wd 5 of ICB */
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sim_debug(DEBUG_CMD, &cpu_dev,
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"checkxio busy test chsa %04x cmd %02x iocla %08x flags %04x IOCD1 %08x IOCD2 %08x\n",
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chsa, chp->ccw_cmd, iocla, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]);
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"checkxio busy ck chsa %04x cmd %02x iocla %08x flags %04x IOCD1 %08x IOCD2 %08x status %08x\n",
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chsa, chp->ccw_cmd, iocla, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2], tempa);
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/* check for a Command or data chain operation in progresss */
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if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
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sim_debug(DEBUG_XIO, &cpu_dev, "checkxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
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sim_debug(DEBUG_XIO, &cpu_dev,
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"checkxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
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*status = CC4BIT; /* busy, so CC4 */
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return SCPE_OK; /* just busy CC4 */
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}
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@ -1640,6 +1655,32 @@ uint32 scan_chan(int *ilev) {
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return 0; /* done */
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}
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/* Find_dev pointer for a unit
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Input: uptr = pointer to unit
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Output: dptr = pointer to device
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*/
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DEVICE *get_dev(UNIT *uptr)
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{
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DEVICE *dptr;
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uint32 i, j;
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if (uptr == NULL) /* must be valid unit */
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return NULL;
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if (uptr->dptr) /* get device pointer from unit */
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return uptr->dptr; /* return valid pointer */
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/* the device pointer in the unit is not set up, do it now */
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/* This should never happed as the pointer is setup in first reset call */
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for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* do all devices */
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for (j = 0; j < dptr->numunits; j++) { /* do all units for device */
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if (uptr == (dptr->units + j)) { /* match found? */
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uptr->dptr = dptr; /* set the pointer in unit */
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return dptr; /* return valid pointer */
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}
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}
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}
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return NULL;
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}
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/* set up the devices configured into the simulator */
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/* only devices with a DIB will be processed */
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t_stat chan_set_devs() {
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@ -1652,20 +1693,29 @@ t_stat chan_set_devs() {
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for (i = 0; sim_devices[i] != NULL; i++) {
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DEVICE *dptr = sim_devices[i]; /* get pointer to next configured device */
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UNIT *uptr = dptr->units; /* get pointer to units defined for this device */
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DIB *dibp = (DIB *)dptr->ctxt; /* get pointer to Device Information Block for this device */
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DIB *dibp = (DIB *)dptr->ctxt; /* get pointer to DIB for this device */
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CHANP *chp; /* channel program pointer */
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int chsa; /* addr of device chan & subaddress */
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/* set the device back pointer in the unit structure */
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for (j = 0; j < dptr->numunits; j++) { /* loop through unit entries */
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uptr->dptr = dptr; /* set the device pointer in unit structure */
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uptr++; /* next UNIT pointer */
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}
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uptr = dptr->units; /* get pointer to units again */
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if (dibp == NULL) /* If no DIB, not channel device */
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continue;
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if (dptr->flags & DEV_DIS) { /* Skip disabled devices */
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if (dptr->flags & DEV_DIS) /* Skip disabled devices */
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continue;
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}
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if ((chp = (CHANP *)dibp->chan_prg) == NULL)/* must have channel information for each device */
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continue;
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/* Check if address is in unit or dev entry */
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for (j = 0; j < dptr->numunits; j++) { /* loop through unit entries */
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chsa = GET_UADDR(uptr->u3); /* ch/sa value */
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//printf("Setup device %s%d chsa %04x type %03d dptr %x\n",
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// dptr->name, j, chsa, GET_TYPE(uptr->flags), uptr->dptr);
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/* zero some channel data loc's for device */
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dev_status[chsa] = 0; /* zero device status flags */
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dev_status[chsa&0x7f00] = 0; /* clear the channel status location */
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@ -1678,8 +1728,11 @@ t_stat chan_set_devs() {
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chp->ccw_flags = 0; /* Command chain and supress incorrect length */
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chp->ccw_cmd = 0; /* read command */
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chp->chan_inch_addr = 0; /* clear address of stat dw in memory */
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if ((uptr->flags & UNIT_DIS) == 0) /* is unit marked disabled? */
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if ((uptr->flags & UNIT_DIS) == 0) { /* is unit marked disabled? */
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if (dev_unit[chsa] != 0)
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printf("Channel/SubAddress %04x multiple defined\n", chsa);
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dev_unit[chsa] = dibp; /* no, save the dib address */
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}
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if (dibp->dev_ini != NULL) /* if there is an init routine, call it now */
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dibp->dev_ini(uptr, 1); /* init the channel */
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uptr++; /* next UNIT pointer */
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@ -1691,91 +1744,67 @@ t_stat chan_set_devs() {
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/* Validate and set the device onto a given channel */
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t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
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DEVICE *dptr;
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DIB *dibp;
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t_value newdev;
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t_stat r;
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int i;
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int devaddr;
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DEVICE *dptr; /* device pointer */
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DIB *dibp; /* dib pointer */
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UNIT *tuptr; /* temp unit pointer */
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t_value chan; /* new channel addr */
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t_stat r; /* return status */
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int i; /* temp */
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int chsa; /* dev addr */
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// dptr = uptr->dptr /* get device pointer from unit */
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if (cptr == NULL) /* is there a UNIT name specified */
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return SCPE_ARG; /* no, arg error */
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if (uptr == NULL) /* is there a UNIT pointer */
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return SCPE_IERR; /* no, arg error */
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dptr = find_dev_from_unit(uptr); /* find the device from unit pointer */
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dptr = get_dev(uptr); /* find the device from unit pointer */
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if (dptr == NULL) /* device not found, so error */
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return SCPE_IERR; /* error */
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dibp = (DIB *)dptr->ctxt;
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if (dibp == NULL)
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return SCPE_IERR;
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dibp = (DIB *)dptr->ctxt; /* get dib pointer from device struct */
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if (dibp == NULL) /* we need a DIB */
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return SCPE_IERR; /* no DIB, so error */
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newdev = get_uint(cptr, 16, 0xffff, &r);
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chan = get_uint(cptr, 16, 0xffff, &r); /* get new device address */
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if (r != SCPE_OK) /* need good number */
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return r; /* number error, return error */
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//printf("finding chan %s (%x) with unit address %04x dptr %x\n",
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// cptr, chan, GET_UADDR(uptr->u3), uptr->dptr);
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if (r != SCPE_OK)
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return r;
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// if ((chan == 0) || ((chan & 0x7f00) != chan)) /* is chan 1-7f */
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// return SCPE_ARG; /* no, bad channel # */
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chan &= 0x7f00; /* clean channel address */
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dibp->chan_addr = chan; /* set new parent channel addr */
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if ((newdev >> 8) > channels)
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return SCPE_ARG;
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if (newdev >= MAX_DEV)
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return SCPE_ARG;
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devaddr = GET_UADDR(uptr->u3);
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/* Clear out existing entry */
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if (dptr->flags & DEV_UADDR) {
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dev_unit[devaddr] = NULL;
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} else {
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devaddr &= (dibp->mask | 0x7f00);
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for (i = 0; i < dibp->numunits; i++)
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dev_unit[devaddr + i] = NULL;
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/* change all the unit addresses with the new channel, but keep sub address */
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/* Clear out existing entries for all units on this device */
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tuptr = dptr->units; /* get pointer to units defined for this device */
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/* loop through all units for this device */
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for (i = 0; i < dibp->numunits; i++) {
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chsa = GET_UADDR(tuptr->u3); /* get old chsa for this unit */
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dev_unit[chsa] = NULL; /* clear sa dib pointer */
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dev_unit[chsa&0x7f00] = NULL; /* clear the channel dib address */
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chsa = chan | (chsa & 0xff); /* merge new channel with new sa */
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tuptr->u3 &= ~UNIT_ADDR_MASK; /* clear old chsa for this unit */
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tuptr->u3 |= UNIT_ADDR(chsa); /* clear old chsa for this unit */
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dev_unit[chan&0x7f00] = dibp; /* set the channel dib address */
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dev_unit[chsa] = dibp; /* save the dib address for new chsa */
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fprintf(stderr, "Set dev %04x to %04x\r\n", GET_UADDR(tuptr->u3), chsa);
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tuptr++; /* next unit pointer */
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}
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/* Check if device already at newdev */
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if (dptr->flags & DEV_UADDR) {
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if (dev_unit[newdev] != NULL)
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r = SCPE_ARG;
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} else {
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newdev &= (dibp->mask | 0x7f00);
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for (i = 0; i < dibp->numunits; i++) {
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if (dev_unit[newdev + i] != NULL)
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r = SCPE_ARG;
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}
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}
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/* If not, point to new dev, else restore old */
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if (r == SCPE_OK)
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devaddr = newdev;
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/* Update device entry */
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if (dptr->flags & DEV_UADDR) {
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dev_unit[devaddr] = dibp;
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uptr->u3 &= ~UNIT_ADDR(0x7fff);
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uptr->u3 |= UNIT_ADDR(devaddr);
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fprintf(stderr, "Set dev %04x\r\n", GET_UADDR(uptr->u3));
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} else {
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for (i = 0; i < dibp->numunits; i++) {
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dev_unit[devaddr + i] = dibp;
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uptr = &((dibp->units)[i]);
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uptr->u3 &= ~UNIT_ADDR(0x7fff);
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uptr->u3 |= UNIT_ADDR(devaddr + i);
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fprintf(stderr, "Set dev %04x\r\n", GET_UADDR(uptr->u3));
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}
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}
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return r;
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return SCPE_OK;
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}
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t_stat show_dev_addr(FILE *st, UNIT *uptr, int32 v, CONST void *desc) {
|
||||
DEVICE *dptr;
|
||||
int chsa;
|
||||
|
||||
if (uptr == NULL)
|
||||
return SCPE_IERR;
|
||||
dptr = find_dev_from_unit(uptr);
|
||||
if (dptr == NULL)
|
||||
return SCPE_IERR;
|
||||
chsa = GET_UADDR(uptr->u3);
|
||||
fprintf(st, "CHAN/SA %04x", chsa);
|
||||
return SCPE_OK;
|
||||
if (uptr == NULL) /* valid unit? */
|
||||
return SCPE_IERR; /* no, error return */
|
||||
dptr = get_dev(uptr); /* get the device pointer from unit */
|
||||
if (dptr == NULL) /* valid pointer? */
|
||||
return SCPE_IERR; /* retunr error */
|
||||
chsa = GET_UADDR(uptr->u3); /* get the unit address */
|
||||
fprintf(st, "CHAN/SA %04x", chsa); /* display channel/subaddress */
|
||||
return SCPE_OK; /* we done */
|
||||
}
|
||||
|
||||
@ -35,6 +35,7 @@ extern void chan_end(uint16 chan, uint8 flags);
|
||||
extern int chan_read_byte(uint16 chan, uint8 *data);
|
||||
extern int chan_write_byte(uint16 chan, uint8 *data);
|
||||
extern void set_devwake(uint16 addr, uint8 flags);
|
||||
extern DEVICE *get_dev(UNIT *uptr);
|
||||
|
||||
/* Constants */
|
||||
#define COM_LINES 8 /* max lines */
|
||||
@ -377,7 +378,7 @@ void coml_ini(UNIT *uptr, t_bool f)
|
||||
/* 8-line serial routines */
|
||||
void com_ini(UNIT *uptr, t_bool f)
|
||||
{
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
|
||||
sim_debug(DEBUG_CMD, &com_dev, "COM init device %s controller 0x7e00\n", dptr->name);
|
||||
sim_activate(uptr, 1000); /* time increment */
|
||||
@ -386,7 +387,7 @@ void com_ini(UNIT *uptr, t_bool f)
|
||||
/* called from sel32_chan to start an I/O operation */
|
||||
uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
{
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
int unit = (uptr - dptr->units);
|
||||
uint8 ch;
|
||||
|
||||
|
||||
@ -48,6 +48,7 @@ extern void set_devattn(uint16 addr, uint8 flags);
|
||||
extern void post_extirq(void);
|
||||
extern uint32 attention_trap; /* set when trap is requested */
|
||||
extern void set_devwake(uint16 addr, uint8 flags);
|
||||
extern DEVICE *get_dev(UNIT *uptr);
|
||||
|
||||
#define CMD u3
|
||||
/* Held in u3 is the device command and status */
|
||||
@ -157,7 +158,7 @@ DEVICE con_dev = {
|
||||
/* initialize the console chan/unit */
|
||||
void con_ini(UNIT *uptr, t_bool f) {
|
||||
// int unit = (uptr - con_unit); /* unit 0 */
|
||||
// DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
// DEVICE *dptr = get_dev(uptr);
|
||||
|
||||
// con_data[unit].incnt = 0; /* no input data */
|
||||
con_data[0].incnt = 0; /* no input data */
|
||||
@ -169,7 +170,7 @@ void con_ini(UNIT *uptr, t_bool f) {
|
||||
/* start a console operation */
|
||||
uint8 con_preio(UNIT *uptr, uint16 chan)
|
||||
{
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
int unit = (uptr - dptr->units);
|
||||
|
||||
if ((uptr->CMD & 0xff00) != 0) { /* just return if busy */
|
||||
@ -301,7 +302,6 @@ t_stat con_srvo(UNIT *uptr) {
|
||||
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
|
||||
int cmd = uptr->CMD & CON_MSK;
|
||||
uint8 ch, cp;
|
||||
static uint32 lastch = 0;
|
||||
|
||||
sim_debug(DEBUG_DETAIL, &con_dev, "con_srvo enter chsa %04x cmd = %02x\n", chsa, cmd);
|
||||
if (cmd == 0x0C) { /* unknown has to do nothing */
|
||||
@ -322,6 +322,7 @@ t_stat con_srvo(UNIT *uptr) {
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
// static uint32 lastch = 0;
|
||||
if ((cmd == CON_WR) || (cmd == CON_RWD)) {
|
||||
/* Write to device */
|
||||
if (chan_read_byte(chsa, &ch)) { /* get byte from memory */
|
||||
@ -339,8 +340,8 @@ t_stat con_srvo(UNIT *uptr) {
|
||||
else
|
||||
cp = '^';
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_srvo write %01x: putch 0x%02x %c\n", unit, ch, cp);
|
||||
lastch = (lastch << 8) | cp;
|
||||
#ifdef DO_DYNAMIC_DEBUG
|
||||
lastch = (lastch << 8) | cp;
|
||||
if ((lastch & 0xffff) == 0x6e29) /* check for ion) */
|
||||
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
|
||||
#endif
|
||||
|
||||
@ -1983,9 +1983,11 @@ wait_loop:
|
||||
}
|
||||
redo:
|
||||
if (skipinstr) { /* need to skip interrupt test? */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_TRAP, &cpu_dev,
|
||||
"Skipinstr set to zero PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
skipinstr = 0; /* skip only once */
|
||||
goto skipi; /* skip int test */
|
||||
}
|
||||
@ -2662,9 +2664,11 @@ exec:
|
||||
PSD2 |= 0x00004000; /* set bit 49 only */
|
||||
SPAD[0xf5] = PSD2; /* save the current PSD2 */
|
||||
SPAD[0xf9] = CPUSTATUS; /* save the cpu status in SPAD */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
"BEI skipinstr %x irq_pend %x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
skipinstr, irq_pend, PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
break;
|
||||
case 0x7: /* UEI */
|
||||
if ((modes & PRIVBIT) == 0) { /* must be privileged to UEI */
|
||||
@ -2681,9 +2685,11 @@ exec:
|
||||
PSD2 &= ~0x0000c000; /* clear bit 48 & 49 to be unblocked */
|
||||
SPAD[0xf5] = PSD2; /* save the current PSD2 */
|
||||
SPAD[0xf9] = CPUSTATUS; /* save the cpu status in SPAD */
|
||||
#ifdef NOTNOW
|
||||
sim_debug(DEBUG_IRQ, &cpu_dev,
|
||||
"UEI skipinstr %x irq_pend %x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
skipinstr, irq_pend, PSD1, PSD2, CPUSTATUS);
|
||||
#endif
|
||||
break;
|
||||
case 0x8: /* EAE */
|
||||
PSD1 |= AEXPBIT; /* set the enable AEXP flag in PSD */
|
||||
@ -5950,16 +5956,16 @@ doovr2:
|
||||
if (PSD2 & MAPBIT) {
|
||||
/* set mapped mode in cpu status */
|
||||
CPUSTATUS |= 0x00800000; /* set bit 8 of cpu status */
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"B4 LPSDCM temp %06x TPSD %08x %08x PSD %08x %08x\n",
|
||||
temp, TPSD[0], TPSD[1], PSD1, PSD2);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"B4 LPSDCM BPIX %04x CPIX %04x CPIXPL %04x\n",
|
||||
BPIX, CPIX, CPIXPL);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"B4 LPSDCM OS MAPC[0-5] %08x %08x %08x %08x %08x %08x\n",
|
||||
MAPC[0], MAPC[1], MAPC[2], MAPC[3], MAPC[4], MAPC[5]);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"B4 LPSDCM US MAPC[%x-%x] %08x %08x %08x %08x %08x %08x\n",
|
||||
BPIX, BPIX+5, MAPC[BPIX], MAPC[BPIX+1], MAPC[BPIX+2],
|
||||
MAPC[BPIX+3], MAPC[BPIX+4], MAPC[BPIX+5]);
|
||||
@ -5974,23 +5980,18 @@ doovr2:
|
||||
}
|
||||
#endif
|
||||
if ((PSD2 & RETMBIT) == 0) { /* don't load maps if retain bit set */
|
||||
#ifdef DO_DYNAMIC_DEBUG
|
||||
/* start debugging */
|
||||
if ((PSD1&0xffffff) == 0x11314)
|
||||
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
|
||||
#endif
|
||||
/* we need to load the new maps */
|
||||
TRAPME = load_maps(PSD, 0); /* load maps for new PSD */
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"AF LPSDCM TPSD %08x %08x PSD %08x %08x TRAPME %02x\n",
|
||||
TPSD[0], TPSD[1], PSD1, PSD2, TRAPME);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"AF LPSDCM BPIX %04x CPIX %04x CPIXPL %04x\n",
|
||||
BPIX, CPIX, CPIXPL);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"AF LPSDCM OS MAPC[0-5] %08x %08x %08x %08x %08x %08x\n",
|
||||
MAPC[0], MAPC[1], MAPC[2], MAPC[3], MAPC[4], MAPC[5]);
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_DETAIL, &cpu_dev,
|
||||
"AF LPSDCM US MAPC[%x-%x] %08x %08x %08x %08x %08x %08x\n",
|
||||
BPIX, BPIX+5, MAPC[BPIX], MAPC[BPIX+1], MAPC[BPIX+2],
|
||||
MAPC[BPIX+3], MAPC[BPIX+4], MAPC[BPIX+5]);
|
||||
@ -5998,7 +5999,7 @@ doovr2:
|
||||
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
|
||||
SPAD[0xf5] = PSD2; /* save the current PSD2 */
|
||||
SPAD[0xf9] = CPUSTATUS; /* save the cpu status in SPAD */
|
||||
sim_debug(DEBUG_EXP, &cpu_dev,
|
||||
sim_debug(DEBUG_CMD, &cpu_dev,
|
||||
"LPSDCM MAPS LOADED TRAPME = %02x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
|
||||
TRAPME, PSD1, PSD2, CPUSTATUS);
|
||||
}
|
||||
|
||||
@ -108,11 +108,11 @@
|
||||
#define NUM_UNITS_CON 2 /* 2 console input & output */
|
||||
#define NUM_DEVS_MT 1 /* 1 mag tape controllers */
|
||||
#define NUM_UNITS_MT 4 /* 4 of 8 devices */
|
||||
//#define FOR_UTX
|
||||
#define FOR_UTX
|
||||
#ifdef FOR_UTX
|
||||
#define NUM_DEVS_HSDP 1 /* 1 HSPD disk drive controller */
|
||||
#define NUM_UNITS_HSDP 2 /* 2 disk drive devices */
|
||||
#else
|
||||
//#else
|
||||
#define NUM_DEVS_DISK 1 /* 1 DP02 disk drive controller */
|
||||
#define NUM_UNITS_DISK 2 /* 2 disk drive devices */
|
||||
//#define NUM_UNITS_DISK 4 /* 4 disk drive devices */
|
||||
@ -181,12 +181,12 @@ typedef struct chp {
|
||||
uint32 chan_inch_addr; /* Channel status dw in memory */
|
||||
uint32 chan_caw; /* Channel command address word */
|
||||
uint32 ccw_addr; /* Channel address */
|
||||
uint32 chan_buf; /* Channel data buffer */
|
||||
uint16 ccw_count; /* Channel count */
|
||||
uint8 ccw_cmd; /* Channel command and flags */
|
||||
uint16 ccw_flags; /* Channel flags */
|
||||
uint16 chan_status; /* Channel status */
|
||||
uint16 chan_dev; /* Device on channel */
|
||||
uint32 chan_buf; /* Channel data buffer */
|
||||
uint8 ccw_cmd; /* Channel command and flags */
|
||||
uint8 chan_byte; /* Current byte, dirty/full */
|
||||
} CHANP;
|
||||
|
||||
@ -224,6 +224,13 @@ typedef struct dib {
|
||||
#define GET_DADDR(x) (0x7f & ((x) >> DEV_V_ADDR))
|
||||
#define DEV_ADDR(x) ((x) << DEV_V_ADDR)
|
||||
|
||||
/* allow 255 type disks */
|
||||
#define UNIT_V_TYPE (UNIT_V_UF + 0)
|
||||
#define UNIT_TYPE (0xff << UNIT_V_TYPE)
|
||||
/* get & set disk types */
|
||||
#define GET_TYPE(x) ((UNIT_TYPE & (x)) >> UNIT_V_TYPE)
|
||||
#define SET_TYPE(x) (UNIT_TYPE & ((x) << UNIT_V_TYPE))
|
||||
|
||||
#define UNIT_V_ADDR 16
|
||||
#define UNIT_ADDR_MASK (0x7fff << UNIT_V_ADDR)
|
||||
#define GET_UADDR(x) ((UNIT_ADDR_MASK & x) >> UNIT_V_ADDR)
|
||||
@ -344,34 +351,34 @@ extern DEBTAB dev_debug[];
|
||||
#define BIT1 0x40000000 /* general use for bit 1 testing */
|
||||
#define BIT2 0x20000000 /* general use for bit 2 testing */
|
||||
#define BIT3 0x10000000 /* general use for bit 3 testing */
|
||||
#define BIT4 0x80000000 /* general use for bit 4 testing */
|
||||
#define BIT5 0x40000000 /* general use for bit 5 testing */
|
||||
#define BIT6 0x20000000 /* general use for bit 6 testing */
|
||||
#define BIT7 0x10000000 /* general use for bit 7 testing */
|
||||
#define BIT8 0x80000000 /* general use for bit 8 testing */
|
||||
#define BIT9 0x40000000 /* general use for bit 9 testing */
|
||||
#define BIT10 0x20000000 /* general use for bit 10 testing */
|
||||
#define BIT11 0x10000000 /* general use for bit 11 testing */
|
||||
#define BIT12 0x80000000 /* general use for bit 12 testing */
|
||||
#define BIT13 0x40000000 /* general use for bit 13 testing */
|
||||
#define BIT14 0x20000000 /* general use for bit 14 testing */
|
||||
#define BIT15 0x10000000 /* general use for bit 15 testing */
|
||||
#define BIT16 0x80000000 /* general use for bit 16 testing */
|
||||
#define BIT17 0x40000000 /* general use for bit 17 testing */
|
||||
#define BIT18 0x20000000 /* general use for bit 18 testing */
|
||||
#define BIT19 0x10000000 /* general use for bit 19 testing */
|
||||
#define BIT20 0x80000000 /* general use for bit 20 testing */
|
||||
#define BIT21 0x40000000 /* general use for bit 21 testing */
|
||||
#define BIT22 0x20000000 /* general use for bit 22 testing */
|
||||
#define BIT23 0x10000000 /* general use for bit 23 testing */
|
||||
#define BIT24 0x80000000 /* general use for bit 24 testing */
|
||||
#define BIT25 0x40000000 /* general use for bit 25 testing */
|
||||
#define BIT26 0x20000000 /* general use for bit 26 testing */
|
||||
#define BIT27 0x10000000 /* general use for bit 27 testing */
|
||||
#define BIT28 0x80000000 /* general use for bit 28 testing */
|
||||
#define BIT29 0x40000000 /* general use for bit 29 testing */
|
||||
#define BIT30 0x20000000 /* general use for bit 30 testing */
|
||||
#define BIT31 0x10000000 /* general use for bit 31 testing */
|
||||
#define BIT4 0x08000000 /* general use for bit 4 testing */
|
||||
#define BIT5 0x04000000 /* general use for bit 5 testing */
|
||||
#define BIT6 0x02000000 /* general use for bit 6 testing */
|
||||
#define BIT7 0x01000000 /* general use for bit 7 testing */
|
||||
#define BIT8 0x00800000 /* general use for bit 8 testing */
|
||||
#define BIT9 0x00400000 /* general use for bit 9 testing */
|
||||
#define BIT10 0x00200000 /* general use for bit 10 testing */
|
||||
#define BIT11 0x00100000 /* general use for bit 11 testing */
|
||||
#define BIT12 0x00080000 /* general use for bit 12 testing */
|
||||
#define BIT13 0x00040000 /* general use for bit 13 testing */
|
||||
#define BIT14 0x00020000 /* general use for bit 14 testing */
|
||||
#define BIT15 0x00010000 /* general use for bit 15 testing */
|
||||
#define BIT16 0x00008000 /* general use for bit 16 testing */
|
||||
#define BIT17 0x00004000 /* general use for bit 17 testing */
|
||||
#define BIT18 0x00002000 /* general use for bit 18 testing */
|
||||
#define BIT19 0x00001000 /* general use for bit 19 testing */
|
||||
#define BIT20 0x00000800 /* general use for bit 20 testing */
|
||||
#define BIT21 0x00000400 /* general use for bit 21 testing */
|
||||
#define BIT22 0x00000200 /* general use for bit 22 testing */
|
||||
#define BIT23 0x00000100 /* general use for bit 23 testing */
|
||||
#define BIT24 0x00000080 /* general use for bit 24 testing */
|
||||
#define BIT25 0x00000040 /* general use for bit 25 testing */
|
||||
#define BIT26 0x00000020 /* general use for bit 26 testing */
|
||||
#define BIT27 0x00000010 /* general use for bit 27 testing */
|
||||
#define BIT28 0x00000008 /* general use for bit 28 testing */
|
||||
#define BIT29 0x00000004 /* general use for bit 29 testing */
|
||||
#define BIT30 0x00000002 /* general use for bit 30 testing */
|
||||
#define BIT31 0x00000001 /* general use for bit 31 testing */
|
||||
#define MASK16 0x0000FFFF /* 16 bit address mask */
|
||||
#define MASK19 0x0007FFFF /* 19 bit address mask */
|
||||
#define MASK20 0x000FFFFF /* 20 bit address mask */
|
||||
|
||||
1390
SEL32/sel32_disk.c
1390
SEL32/sel32_disk.c
File diff suppressed because it is too large
Load Diff
1189
SEL32/sel32_hsdp.c
1189
SEL32/sel32_hsdp.c
File diff suppressed because it is too large
Load Diff
@ -39,14 +39,16 @@
|
||||
#include "sel32_defs.h"
|
||||
#include "sim_tape.h"
|
||||
|
||||
extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
|
||||
extern t_stat show_dev_addr(FILE *st, UNIT *uptr, int32 v, CONST void *desc);
|
||||
extern void chan_end(uint16 chan, uint8 flags);
|
||||
extern int chan_read_byte(uint16 chan, uint8 *data);
|
||||
extern int chan_write_byte(uint16 chan, uint8 *data);
|
||||
extern void set_devattn(uint16 addr, uint8 flags);
|
||||
extern t_stat chan_boot(uint16 addr, DEVICE *dptr);
|
||||
extern uint32 SPAD[]; /* cpu SPAD */
|
||||
extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
|
||||
extern t_stat show_dev_addr(FILE *st, UNIT *uptr, int32 v, CONST void *desc);
|
||||
extern void chan_end(uint16 chan, uint8 flags);
|
||||
extern int chan_read_byte(uint16 chan, uint8 *data);
|
||||
extern int chan_write_byte(uint16 chan, uint8 *data);
|
||||
extern void set_devattn(uint16 addr, uint8 flags);
|
||||
extern t_stat chan_boot(uint16 addr, DEVICE *dptr);
|
||||
extern DEVICE *get_dev(UNIT *uptr);
|
||||
|
||||
extern uint32 SPAD[]; /* cpu SPAD */
|
||||
|
||||
#ifdef NUM_DEVS_MT
|
||||
#define BUFFSIZE (64 * 1024)
|
||||
@ -383,6 +385,7 @@ DEVICE mta_dev = {
|
||||
"MTA", mta_unit, NULL, mt_mod,
|
||||
NUM_UNITS_MT, 16, 24, 4, 16, 32,
|
||||
NULL, NULL, &mt_reset, &mt_boot, &mt_attach, &mt_detach,
|
||||
/* ctxt is the DIB pointer */
|
||||
&mta_dib, DEV_BUF_NUM(0) | DEV_DISABLE | DEV_DEBUG | DEV_TAPE, 0, dev_debug,
|
||||
NULL, NULL, &mt_help, NULL, NULL, &mt_description
|
||||
|
||||
@ -433,7 +436,7 @@ DEVICE mtb_dev = {
|
||||
/* start an I/O operation */
|
||||
uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
|
||||
{
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
int unit = (uptr - dptr->units);
|
||||
|
||||
sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd entry chan %04x cmd %02x\n", chan, cmd);
|
||||
@ -565,7 +568,7 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr)
|
||||
t_stat mt_srv(UNIT *uptr)
|
||||
{
|
||||
uint16 addr = GET_UADDR(uptr->CMD);
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
int unit = (uptr - dptr->units);
|
||||
int cmd = uptr->CMD & MT_CMDMSK;
|
||||
int bufnum = GET_DEV_BUF(dptr->flags);
|
||||
@ -1083,7 +1086,7 @@ t_stat mt_srv(UNIT *uptr)
|
||||
/* initialize the tape chan/unit */
|
||||
void mt_ini(UNIT *uptr, t_bool f)
|
||||
{
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
DEVICE *dptr = get_dev(uptr);
|
||||
if (MT_DENS(uptr->dynflags) == 0)
|
||||
uptr->dynflags |= MT_DENS_6250 << UNIT_S_DF_TAPE;
|
||||
|
||||
@ -1091,8 +1094,8 @@ void mt_ini(UNIT *uptr, t_bool f)
|
||||
uptr->SNS = 0; /* clear sense data */
|
||||
uptr->SNS |= (SNS_RDY|SNS_ONLN|SNS_LOAD); /* set initial status */
|
||||
mt_busy[GET_DEV_BUF(dptr->flags)] = 0; /* set not busy */
|
||||
sim_debug(DEBUG_EXP, dptr, "MT init device %s unit %02x\n", dptr->name,
|
||||
GET_UADDR(uptr->CMD));
|
||||
sim_debug(DEBUG_EXP, dptr, "MT init device %s unit %02x\n",
|
||||
dptr->name, GET_UADDR(uptr->CMD));
|
||||
}
|
||||
|
||||
/* reset the mag tape */
|
||||
@ -1106,8 +1109,8 @@ t_stat mt_reset(DEVICE *dptr)
|
||||
/* attach the specified file to the tape device */
|
||||
t_stat mt_attach(UNIT *uptr, CONST char *file)
|
||||
{
|
||||
uint16 addr = GET_UADDR(uptr->CMD); /* get address of mt device */
|
||||
t_stat r;
|
||||
uint16 addr = GET_UADDR(uptr->CMD); /* get address of mt device */
|
||||
t_stat r;
|
||||
|
||||
/* mount the specified file to the MT */
|
||||
if ((r = sim_tape_attach(uptr, file)) != SCPE_OK) {
|
||||
@ -1123,7 +1126,7 @@ t_stat mt_attach(UNIT *uptr, CONST char *file)
|
||||
t_stat mt_detach(UNIT *uptr)
|
||||
{
|
||||
sim_debug(DEBUG_EXP, &mta_dev, "mt_detach\n");
|
||||
uptr->CMD = 0;
|
||||
uptr->CMD &= ~0xffff; /* clear out the flags but leave ch/sa */
|
||||
return sim_tape_detach(uptr);
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,33 +1,45 @@
|
||||
; Set debug output
|
||||
set debug -n sel.log
|
||||
;set RTC 50
|
||||
set RTC 60
|
||||
;set RTC debug=cmd
|
||||
;set ITM debug=cmd
|
||||
;set debug stderr
|
||||
;
|
||||
; CPU type and memory
|
||||
; Bad on UTX
|
||||
;set CPU 32/27 2M
|
||||
;set CPU 32/27 4M
|
||||
;set CPU 32/87 4M
|
||||
;set CPU 32/67 4M
|
||||
;End of Bad
|
||||
;set CPU 32/97 4M
|
||||
set CPU V6 4M
|
||||
;set CPU V6 8M
|
||||
;set CPU V9 4M
|
||||
;set debug stderr
|
||||
;set mta debug=cmd;detail;exp;data
|
||||
;set mta debug=inst;cmd;detail;exp
|
||||
;set inq debug=cmd;detail
|
||||
;set cpu debug=cmd;exp
|
||||
;set cpu debug=exp;irq
|
||||
;set cpu debug=irq
|
||||
;set cpu debug=inst;cmd;exp;irq
|
||||
;set cpu debug=cmd;exp;inst;detail;data
|
||||
;set cpu debug=cmd;exp;inst;detail
|
||||
;set cpu debug=cmd;exp;irq
|
||||
;set con debug=exp
|
||||
;set con debug=cmd;exp
|
||||
;set con debug=cmd;exp;data
|
||||
;set mta debug=cmd;exp;inst;data;detail
|
||||
;set mta debug=cmd;exp
|
||||
;set dma debug=cmd;exp;detail;data
|
||||
;set dma debug=cmd;exp;detail;data
|
||||
;set CPU V9 8M
|
||||
;
|
||||
; CPU debug options
|
||||
;set cpu debug=cmd;exp;inst;detail;trap;xio;irq
|
||||
; Set instruction trace history size
|
||||
;set cpu history=10000
|
||||
; useful options
|
||||
;set cpu debug=cmd;exp
|
||||
;set cpu debug=cmd;exp;irq;trap;xio
|
||||
;set cpu debug=cmd;irq;trap;exp
|
||||
;set cpu debug=irq;trap;exp;xio
|
||||
;set cpu debug=irq;xio
|
||||
;
|
||||
; RTC realtime clock
|
||||
set RTC 50
|
||||
;set RTC 60
|
||||
; RTC debug options
|
||||
;set RTC debug=cmd
|
||||
;
|
||||
; ITM interval timer
|
||||
;set ITM debug=cmd
|
||||
;
|
||||
; IOP
|
||||
;set iop debug=cmd
|
||||
;
|
||||
; COM 8-Line
|
||||
;set com debug=cmd;
|
||||
;set coml0 enable
|
||||
;set coml1 enable
|
||||
;set coml2 enable
|
||||
@ -37,30 +49,119 @@ set CPU V6 4M
|
||||
;set coml6 enable
|
||||
;set coml7 enable
|
||||
;
|
||||
; Enable telnet sessions on port 4747
|
||||
;set comc enable
|
||||
;at comc 4747
|
||||
;
|
||||
;set con debug=CMD
|
||||
; LPR
|
||||
;set lpr debug=cmd;detail
|
||||
set lpr enable
|
||||
; LPR output file
|
||||
at lpr lprout
|
||||
;
|
||||
;set lpr enable
|
||||
;at lpr lprout
|
||||
; CON Console
|
||||
;set con debug=cmd;exp;detail
|
||||
; useful options
|
||||
;set con debug=cmd;exp;
|
||||
;
|
||||
;at mta0 mpxsdt4.tap
|
||||
;at mta0 mpxsdt5.tap
|
||||
;at sda0 diskfile4
|
||||
;at sda1 diskfile5
|
||||
; MTA Buffered tape processor
|
||||
;set mta debug=cmd;exp;detail;data
|
||||
; useful options
|
||||
;set mta debug=cmd;detail;exp
|
||||
;
|
||||
; enable MTA to change channel
|
||||
set mta enable
|
||||
; set mta channel
|
||||
set mta0 dev=1000
|
||||
|
||||
; Attach in/out tape files
|
||||
;at mta0 mpxsdt.tap
|
||||
;at mta0 nbctape.tap
|
||||
;at mta0 utx21a1.tap
|
||||
;at mta0 sim32sdt.tap
|
||||
at mta0 diag.tap
|
||||
;at mta1 temptape.tap
|
||||
;at mta2 output.tap
|
||||
;
|
||||
; DMA disk processor II/UDP
|
||||
; enable DMA to change channel
|
||||
;set dma enable
|
||||
; set disk chan to 0800
|
||||
;set dma0 dev=800
|
||||
; set disk type to MPX MH300
|
||||
;set dma0 type=MH300
|
||||
; set disk type to UTX 9346
|
||||
;set dma0 type=9346
|
||||
;set dma0 type=8155
|
||||
;set dma0 type=8887
|
||||
;set dma0 type=8148
|
||||
;
|
||||
; Attach diskfile
|
||||
;at dma0 utx0disk
|
||||
;at dma0 utx1disk
|
||||
;at dma0 sim32disk
|
||||
;at dma debug=cmd;exp;detail;data
|
||||
;at dma0 diagdisk
|
||||
;bo dma0
|
||||
;set history=10000
|
||||
; useful options
|
||||
;set dma debug=cmd;exp
|
||||
;set dma debug=exp;cmd;detail
|
||||
;
|
||||
; SDA SCFI disk processor
|
||||
;set sda debug=cmd;exp;data;detail
|
||||
; Attach diskfiles
|
||||
;at sda0 diskfile4
|
||||
;at sda1 diskfile5
|
||||
;
|
||||
; DPA high speed disk processor
|
||||
; enable the HSDP to change channel
|
||||
;set dpa enable
|
||||
; set channel addr
|
||||
;set dpa dev=800
|
||||
; set disk type to UTX 8887
|
||||
;set dpa0 type=8887
|
||||
;
|
||||
; Attach diskfiles
|
||||
;at utxdsk.dsk
|
||||
;at dpa0 utx0hsdp
|
||||
;at dpa1 utx1hsdp
|
||||
;
|
||||
;set dpa debug=cmd;detail;exp
|
||||
; useful options
|
||||
;set dpa debug=cmd;exp
|
||||
;
|
||||
; set console switches
|
||||
deposit CSW 0
|
||||
;
|
||||
;UTX boot tape options
|
||||
;set GPR 7 to 0x00 to boot in multi-user mode
|
||||
;set GPR 7 to 0x01 to prompt for unix filename
|
||||
;set GPR 7 to 0x02 to boot in single user mode
|
||||
;set GPR 7 to 0x10 to disable swapping and paging
|
||||
;set GPR 7 to 0x20 to boot from device specified in GPR6
|
||||
;set GPR 7 to 0x40 to allow progress messages on boot
|
||||
;deposit BOOTR[7] 40
|
||||
;deposit BOOTR[7] 52
|
||||
;deposit BOOTR[7] 42
|
||||
;deposit BOOTR[7] 2
|
||||
;deposit BOOTR[6] 800
|
||||
;deposit BOOTR[0] ffffffff
|
||||
|
||||
; Set register content at boot for SEL diagnostics
|
||||
; uncomment next line to get diag loader prompt
|
||||
;deposit bootr[0] ffffffff
|
||||
deposit bootr[1] 0
|
||||
deposit bootr[2] 0
|
||||
;
|
||||
; allow cpu idle
|
||||
set cpu idle
|
||||
; Set expect script for auto time entry on MPX at OPCOM prompt
|
||||
;expect haltafter=20000
|
||||
; wait for expected output from simulator, then enter this text
|
||||
;expect "??" send " %DATE_MM%/%DATE_DD%/%DATE_YY%,%TIME_HH%:%TIME_MM%:%TIME_SS%\r"; GO
|
||||
;
|
||||
; Boot from disk
|
||||
;bo dpa0
|
||||
;bo dma0
|
||||
;
|
||||
; Boot from mag tape
|
||||
bo mta0
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user