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https://github.com/rcornwell/sims.git
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IBM360: Code cleanup and remove more compiler warnings.
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parent
01189480b9
commit
1b6bf8fdc5
@ -1260,7 +1260,7 @@ wait_loop:
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reg1 = R1(reg);
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op = (uint8)(ops[0] >> 8);
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/* Check if RX, RR, SI, RS, SS opcode */
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if (op & 0xc0) {
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if ((op & 0xc0) != 0) {
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ilc = 2;
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if (ReadHalf(PC, &dest))
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goto supress;
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@ -1297,7 +1297,7 @@ opr:
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}
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/* If RX or RS or SS SI etc compute first address */
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if (op & 0xc0) {
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if ((op & 0xc0) != 0) {
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uint32 temp;
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temp = B1(ops[1]);
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@ -2421,10 +2421,6 @@ save_dbl:
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case OP_NC:
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case OP_OC:
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case OP_XC:
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fill = cc;
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cc = 0;
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/* Fall through */
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case OP_MVN:
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case OP_MVZ:
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case OP_MVC:
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@ -2432,12 +2428,12 @@ save_dbl:
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1) || TransAddr(addr1+reg, &src1) ||
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TransAddr(addr2, &src1) || TransAddr(addr2+reg, &src1)) {
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if (op == OP_NC || op == OP_OC || op == OP_XC)
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cc = fill; /* restore CC on abort */
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goto supress;
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}
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}
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/* Fall through */
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if (op == OP_NC || op == OP_OC || op == OP_XC)
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cc = 0;
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do {
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if (ReadByte(addr2, &src1))
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goto supress;
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@ -2465,14 +2461,10 @@ save_dbl:
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case OP_CLC:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+reg, &src1))
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if (TransAddr(addr1, &src1) || TransAddr(addr1+reg, &src1) ||
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TransAddr(addr2, &src1) || TransAddr(addr2+reg, &src1)) {
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goto supress;
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}
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}
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cc = 0;
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do {
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@ -2496,14 +2488,10 @@ save_dbl:
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case OP_TR:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+256, &src1))
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if (TransAddr(addr1, &src1) || TransAddr(addr1+reg, &src1) ||
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TransAddr(addr2, &src1) || TransAddr(addr2+256, &src1)) {
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goto supress;
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}
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}
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do {
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if (ReadByte(addr1, &src1))
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@ -2520,14 +2508,10 @@ save_dbl:
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case OP_TRT:
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if ((cpu_unit[0].flags & FEAT_DAT) != 0) {
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/* Make sure we can access whole area */
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if (TransAddr(addr1, &src1))
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goto supress;
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if (TransAddr(addr1+reg, &src1))
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goto supress;
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if (TransAddr(addr2, &src1))
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goto supress;
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if (TransAddr(addr2+256, &src1))
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if (TransAddr(addr1, &src1) || TransAddr(addr1+reg, &src1) ||
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TransAddr(addr2, &src1) || TransAddr(addr2+256, &src1)) {
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goto supress;
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}
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}
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cc = 0;
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do {
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@ -2866,7 +2850,7 @@ save_dbl:
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storepsw(OPPSW, IRC_EXEC);
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/* Check if RX, RR, SI, RS, SS opcode */
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else {
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if (op & 0xc0) {
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if ((op & 0xc0) != 0) {
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if (ReadHalf(addr1, &dest))
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goto supress;
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ops[1] = dest;
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