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SEL32: Do general cleanup and removal of conditional debug code.

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SEL32: Update and validate ADFW/SUFW, ADFD/SUFD, MPFD, & DVFD fp code.
SEL32: Update readme files.
SEL32:
This commit is contained in:
AZBevier 2020-07-13 19:01:16 -07:00
parent 44a322e395
commit 1f70fc9ba0
19 changed files with 1466 additions and 3216 deletions
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16
README.md
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@ -172,9 +172,9 @@ Support for the following units:
# SEL32 Development Simulator
This is a working copy of a simulator for the SEL Concept/32 computer.
The current test version is for the SEL 32/27, 32/67, 32/87, 32/97 computers.
Support for 32/55, 32/75, V6, and V9 computers may be added in the future.
This is a working simulator for the SEL Concept/32 line of computers. The
current test version is for the SEL 32/27, 32/67, 32/87, 32/97, V6, and V9
computers. Support for 32/55, and 32/75 computers may be added in the future.
This simulator is co-authors with James C. Bevier. I did the initial parts
of the simulator, James took it to a working simulator, I am assisting him
in maintaining and enhancing the simulator. This simulator is running a test
@ -183,8 +183,14 @@ from a SDT tape. The disk image can be booted, initialized, and run many of
the MPX utilities; including OPCOM & TSM. Eight terminals can be used to
access TSM via Telnet port 4747. Initial support has been added for excess
64 floating point arithmetic. More testing is still required. The sim32disk.gz
can be uncompressed and booted with the sel32.27.sim32.disk.ini initialization file.
The sim32sdt.tap.gz file can also be uncompressed and started with the
can be uncompressed and booted with the sel32.27.sim32.disk.ini initialization
file. The sim32sdt.tap.gz file can also be uncompressed and started with the
sel32.27.sim32.tape.ini initialization file to install from tape.
The current version can also install and run UTX 2.1A from an install tape.
It is the SEL version of System V Unix and BSD Unix ported to the V6 and V9
processors. It can run in single or multi user mode. UTX utilizes the basemode
instruction set and a virtual memory system provided by the V6 & V9 CPUs.
There are still some random halts and panics. The system needs further
testing to solidify the SEL32 simulator code.

10
SEL32/README.md
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@ -4,7 +4,7 @@
This is a working copy of a simulator for the SEL Concept/32 computer.
The current test version is for the SEL 32/27, 32/67, 32/77, 32/87,
32/97, V6, and V9 computers. All of the processors except for the
32/77 can run Gould diags. Support for 32/55 computers may be added
32/77 can run the Gould diags. Support for 32/55 computers may be added
in the future.
# SEL Concept/32
@ -77,8 +77,8 @@ diag.tap bootable level one diagnostic tape w/auto testing. Set
Available UTX-21a install tape for testing:
utxtape1.ini command file to start UTX install tape. ./sel32 utxtape1.ini
utx21a1.tap bootable UTX install tape for testing basemode. The current
V6 & V9 will boot UTX into single user mode. You can run a
small subset of the commands that are on the installation tape.
V6 & V9 will boot UTX into single/multi user mode. You can run
the full set of the commands that are on the installation tapes.
Prep, the disk preparation UTX program, can format a disk
drive. Other file systems can be created and saves restored.
All basemode instructions have been tested with the CV.BRD diag.
@ -90,8 +90,8 @@ Other MPX verion support:
I am still looking for an MPX 3.X user or master SDT tape. I have
much of the source, but no loadable code to create a bootable system.
Please keep looking for anyone who can provide these tapes or a
disk image of a bootable system..
disk image of a bootable system.
James C. Bevier
05/19/2020
06/30/2020

518
SEL32/sel32_chan.c
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File diff suppressed because it is too large Load Diff

82
SEL32/sel32_clk.c
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@ -45,7 +45,7 @@ t_stat rtc_show_freq (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
t_stat rtc_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, CONST char *cptr);
const char *rtc_desc(DEVICE *dptr);
extern int irq_pend; /* go scan for pending int or I/O */
extern int irq_pend; /* go scan for pending int or I/O */
extern uint32 INTS[]; /* interrupt control flags */
extern uint32 SPAD[]; /* computer SPAD */
extern uint32 M[]; /* system memory */
@ -57,7 +57,6 @@ int32 rtc_tps = 60; /* rtc ticks/sec */
int32 rtc_lvl = 0x18; /* rtc interrupt level */
/* Clock data structures
rtc_dev RTC device descriptor
rtc_unit RTC unit
rtc_reg RTC register list
@ -94,7 +93,6 @@ DEVICE rtc_dev = {
1, 8, 8, 1, 8, 8,
NULL, NULL, &rtc_reset, /* examine, deposit, reset */
NULL, NULL, NULL, /* boot, attach, detach */
// NULL, 0, 0, NULL, /* dib, dev flags, debug flags, debug */
NULL, DEV_DEBUG|DEV_DISABLE, 0, dev_debug, /* dib, dev flags, debug flags, debug */
NULL, NULL, &rtc_help, /* ?, ?, help */
NULL, NULL, &rtc_desc, /* ?, ?, description */
@ -113,41 +111,29 @@ uint32 grtime = 0;
/* service clock signal from simulator */
t_stat rtc_srv (UNIT *uptr)
{
#ifdef STOP_CLOCK_INTS_FOR_DEXP_TEST
int32 temp;
#ifdef STOP_CLOCK_INTS_FOR_DEXP_TEST_DEBUGGING
/* stop clock interrupts for dexp debugging */
rtc_pie = 0;
#endif
/* id clock sisabled, do not do interrupts */
if (((uptr->flags & DEV_DIS) == 0) && rtc_pie) {
// if (rtc_pie) { /* set pulse intr */
time_t result = time(NULL);
sim_debug(DEBUG_CMD, &rtc_dev, "RT Clock int time %08x\n", (uint32)result);
#ifdef DO_TIME
time_t result = time(NULL);
uint32 tms = sim_os_msec();
uint32 tus = sim_grtime();
if (lastms != 0)
fprintf(stderr, "Clock time %08x ms %d val %x\r\n", (uint32)result, tms-lastms, tms);
// fprintf(stderr, "Clock time %08x ms %d us %d\r\n", (uint32)result, tms-lastms, tus-grtime);
lastms = tms;
grtime = tus;
#endif
if (((INTS[rtc_lvl] & INTS_ENAB) || /* make sure enabled */
(SPAD[rtc_lvl+0x80] & SINT_ENAB)) && /* in spad too */
(((INTS[rtc_lvl] & INTS_ACT) == 0) || /* and not active */
((SPAD[rtc_lvl+0x80] & SINT_ACT) == 0))) { /* in spad too */
//DIAGHELP INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
/* HACK for console I/O stopping */
/* This reduces the number of console I/O stopping errors */
/* need tp find real cause of I/O stopping on clock interrupt */
if ((outbusy==0) && (inbusy==0)) /* skip interrupt if con I/O in busy wait */
INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
irq_pend = 1; /* make sure we scan for int */
}
}
#define FOR_MIKE
#ifndef FOR_MIKE
//Mike rtc_unit.wait = sim_rtcn_calb (rtc_tps, TMR_RTC); /* calibrate */
rtc_unit.wait = sim_rtcn_calb (rtc_tps, TMR_RTC); /* calibrate */
#endif
sim_activate_after (&rtc_unit, 1000000/rtc_tps);/* reactivate 16666 tics / sec */
temp = sim_rtcn_calb(rtc_tps, TMR_RTC); /* timer 0 for RTC */
sim_activate_after(&rtc_unit, 1000000/rtc_tps); /* reactivate 16666 tics / sec */
return SCPE_OK;
}
@ -157,7 +143,6 @@ t_stat rtc_srv (UNIT *uptr)
/* level = interrupt level */
void rtc_setup(uint32 ss, uint32 level)
{
// uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */
uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */
rtc_lvl = level; /* save the interrupt level */
@ -169,16 +154,11 @@ void rtc_setup(uint32 ss, uint32 level)
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock setup enable int %02x rtc_pie %01x ss %01x\n",
rtc_lvl, rtc_pie, ss);
#ifdef DO_DYNAMIC_DEBUG
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
#endif
} else {
INTS[level] &= ~INTS_ENAB; /* make sure disabled */
SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
// INTS[level] &= ~INTS_REQ; /* make sure request not requesting */
/*@41*/ INTS[level] &= ~INTS_ACT; /* make sure request not active */
/*@41*/ SPAD[level+0x80] &= ~SINT_ACT; /* in spad too */
INTS[level] &= ~INTS_ACT; /* make sure request not active */
SPAD[level+0x80] &= ~SINT_ACT; /* in spad too */
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock setup disable int %02x rtc_pie %01x ss %01x\n",
rtc_lvl, rtc_pie, ss);
@ -191,10 +171,6 @@ t_stat rtc_reset(DEVICE *dptr)
{
rtc_pie = 0; /* disable pulse */
/* initialize clock calibration */
#ifndef FOR_MIKE
//Mike rtc_unit.wait = sim_rtcn_init_unit(&rtc_unit, rtc_unit.wait, TMR_RTC);
rtc_unit.wait = sim_rtcn_init_unit(&rtc_unit, rtc_unit.wait, TMR_RTC);
#endif
sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */
return SCPE_OK;
}
@ -260,20 +236,15 @@ t_stat itm_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, CONST char *cptr
const char *itm_desc(DEVICE *dptr);
/* Clock data structures
itm_dev Interval Timer ITM device descriptor
itm_unit Interval Timer ITM unit
itm_reg Interval Timer ITM register list
*/
#ifdef FOR_MIKE
/* Mike suggested I remove the UNIT_IDLE flag from ITM. This causes SEL32 */
/* to use 100% of the CPU instead of waiting and running 10% cpu usage */
//BAD Mike UNIT itm_unit = { UDATA (&itm_srv, 0, 0), 26042, UNIT_ADDR(0x7F04)};
UNIT itm_unit = { UDATA (&itm_srv, 0, 0), 26042, UNIT_ADDR(0x7F04)};
#else
UNIT itm_unit = { UDATA (&itm_srv, UNIT_IDLE, 0), 26042, UNIT_ADDR(0x7F04)};
#endif
REG itm_reg[] = {
{ FLDATA (PIE, itm_pie, 0) },
@ -298,7 +269,6 @@ DEVICE itm_dev = {
1, 8, 8, 1, 8, 8,
NULL, NULL, &itm_reset, /* examine, deposit, reset */
NULL, NULL, NULL, /* boot, attach, detach */
// NULL, 0, 0, NULL, /* dib, ?, ?, debug */
NULL, DEV_DEBUG, 0, dev_debug, /* dib, dev flags, debug flags, debug */
NULL, NULL, &itm_help, /* ?, ?, help */
NULL, NULL, &itm_desc, /* ?, ?, description */
@ -336,15 +306,14 @@ t_stat itm_srv (UNIT *uptr)
/* restart timer with value from user */
if (itm_src) /* use specified src freq */
sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*350000)/rtc_tps);
// sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*400000)/rtc_tps);
// sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*1000000)/rtc_tps);
//DIAG sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*400000)/rtc_tps);
//DIAG sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*1000000)/rtc_tps);
else
sim_activate_after_abs_d(&itm_unit, ((double)itm_cnt*itm_tick_size_x_100)/100.0);
itm_run = 1; /* show timer running */
itm_load = itm_cnt; /* save loaded value */
itm_strt = 0; /* no negative start time */
} else {
// int32 cnt = 26042*1000; /* 0x65ba TRY 1,000,000/38.4 10 secs */
int32 cnt = itm_big; /* 0x65ba TRY 1,000,000/38.4 10 secs */
itm_strt = cnt; /* get negative start time */
sim_debug(DEBUG_CMD, &itm_dev,
@ -422,12 +391,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
case 0x39: /* load timer with new value and start lo rate */
case 0x3a: /* load timer with new value and start hi rate */
case 0x3b: /* load timer with new value and start lo rate */
#ifdef DO_DYNAMIC_DEBUG
if (itm_cmd == 0x38)
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
#endif
// sim_activate_after (&rtc_unit, 1000000/rtc_tps);/* reactivate 16666 tics / sec */
if (itm_run) /* if we were running stop timer */
sim_cancel (&itm_unit); /* cancel timer */
itm_run = 0; /* stop timer running */
@ -436,7 +399,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
/* if bits 30-31 == 20, use RTC freq */
itm_src = (cmd>>1)&1; /* set src */
if (itm_src) /* use specified src freq */
// sim_activate_after_abs_d(&itm_unit, ((double)cnt*400000)/rtc_tps);
/* use clock frequency */
sim_activate_after_abs_d(&itm_unit, ((double)cnt*1000000)/rtc_tps);
else
@ -476,10 +438,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
}
sim_cancel (&itm_unit); /* cancel timer */
}
// if (cmd & 0x40) {
// /* timer value already read into temp */
// ;
// }
if (cmd & 0x08) {
/* use value from user to load timer */
temp = cnt; /* set user count */
@ -489,7 +447,7 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
/* if bits 30-31 == 20, use RTC freq */
itm_src = (cmd>>1)&1; /* set src */
if (itm_src) /* use specified src freq */
// sim_activate_after_abs_d(&itm_unit, ((double)cnt*400000)/rtc_tps);
//DIAG sim_activate_after_abs_d(&itm_unit, ((double)cnt*400000)/rtc_tps);
sim_activate_after_abs_d(&itm_unit, ((double)cnt*1000000)/rtc_tps);
else
sim_activate_after_abs_d(&itm_unit, ((double)cnt*itm_tick_size_x_100)/100.0);
@ -510,21 +468,17 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
/* load timer with new value and start using RTC as source */
case 0x3e: /* load timer with new value and start RTC*/
sim_debug(DEBUG_CMD, &itm_dev, "Intv 0x%2x init value %08x (%d)\n", cmd, cnt, cnt);
//TRY if (itm_run) /* if we were running save curr cnt */
sim_cancel (&itm_unit); /* cancel timer */
sim_cancel (&itm_unit); /* cancel timer */
/* if bits 30-31 == 20, use RTC freq */
itm_src = (cmd>>1)&1; /* set src */
if (itm_src) /* use specified src freq */
sim_activate_after_abs_d(&itm_unit, ((double)cnt*700000)/rtc_tps);
// sim_activate_after_abs_d(&itm_unit, ((double)cnt*1000000)/rtc_tps);
else
sim_activate_after_abs_d(&itm_unit, ((double)cnt*itm_tick_size_x_100)/100.0);
itm_run = 1; /* set timer running */
if (cmd & 0x04) /* do we reload on zero? */
itm_cnt = cnt; /* count reset value */
else
itm_cnt = 0; /* no count reset value */
itm_strt = 0; /* not restarted neg */
itm_load = cnt; /* now loaded */
sim_debug(DEBUG_CMD, &itm_dev, "Intv 0x%02x return value %08x (%08d)\n", cmd, cnt, cnt);
@ -546,7 +500,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
}
sim_debug(DEBUG_CMD, &itm_dev, "Intv 0x40 return value %08x (%d)\n", temp, temp);
return temp;
//TRIED return temp << 6;
break;
case 0x60: /* read and stop timer */
@ -572,11 +525,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
break;
case 0x6a: /* read value & load new one */
#ifdef DO_DYNAMIC_DEBUG
// if (itm_cmd == 0x31)
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
#endif
case 0x68: /* read value & load new one */
case 0x69: /* read value & load new one */
/* get timer value and load new value, do not start timer */

91
SEL32/sel32_com.c
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@ -238,7 +238,6 @@ MTAB com_mod[] = {
UNIT com_unit[] = {
{UDATA(&comi_srv, UNIT_ATTABLE|UNIT_IDLE, 0), COM_WAIT, UNIT_ADDR(0x0000)}, /* 0 */
// {UDATA(&comi_srv, UNIT_ATTABLE|UNIT_IDLE, 0), COM_WAIT, UNIT_ADDR(0x4747)}, /* dummy */
};
//DIB com_dib = {NULL, com_startcmd, NULL, NULL, com_ini, com_unit, com_chp, COM_UNITS, 0x0f, 0x7e00, 0, 0, 0};
@ -362,12 +361,6 @@ DEVICE coml_dev = {
/* 8-line serial routines */
void coml_ini(UNIT *uptr, t_bool f)
{
// int unit;
// uint16 chsa;
// unit = uptr - coml_unit; /* unit # */
// chsa = GET_UADDR(uptr->u3); /* get channel/sub-addr */
/* maybe do someting here on master channel init */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
}
@ -402,7 +395,6 @@ uint16 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u3 |= (0x7f & COM_MSK); /* save 0x7f as INCH cmd command */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_activate(uptr, 20); /* start us up */
// return SNS_CHNEND|SNS_DEVEND; /* all is well */
break;
/* write commands must use address 8-f */
@ -449,7 +441,6 @@ uint16 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & COM_MSK); /* save command */
sim_activate(uptr, 20); /* start us up */
// return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_SNS: /* 0x04 */ /* Sense (8 bytes) */
@ -459,68 +450,36 @@ uint16 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
/* value 5 is Data carrier detected n/u */
sim_debug(DEBUG_CMD, dptr,
"com_startcmd %04x: unit %04x Cmd Sense %02x\n", chan, unit, uptr->u5);
/* Sense byte 0 */
//#define SNS_CMDREJ 0x80000000 /* Command reject */
//#define SNS_INTVENT 0x40000000 /* Unit intervention required (N/U) */
//#define SNS_BOCHK 0x20000000 /* Bus out check (IOP parity error */
//#define SNS_EQUIPCK 0x10000000 /* Equipment check (device error) */
//#define SNS_DATACK 0x08000000 /* Data check */
//#define SNS_OVERRN 0x04000000 /* Overrun (N/U) */
//#define SNS_NUB01 0x02000000 /* Zero (N/U) */
//#define SNS_NUB02 0x01000000 /* Zero (N/U) */
// com_lstat[unit][0] |= (SNS_ASCIICD | SNS_SPCLCD|SNS_RING); /* set char detect status */
// com_lstat[unit][0] |= (SNS_ASCIICD | SNS_SPCLCD); /* set char detect status */
// com_lstat[unit][0] |= (SNS_RING); /* set char detect status */
ch = (com_lstat[unit][0] >> 24) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
/* Sense byte 1 */
//#define SNS_ASCIICD 0x00800000 /* ASCII control char detected interrupt */
//#define SNS_SPCLCD 0x00400000 /* Special char detected interrupt */
//#define SNS_ETX 0x00200000 /* ETX interrupt */
//#define SNS_BREAK 0x00100000 /* X BREAK interrupt */
//#define SNS_ACEFE 0x00080000 /* ACE framing error interrupt */
//#define SNS_ACEPEI 0x00040000 /* ACE parity error interrupt */
//#define SNS_ACEOVR 0x00020000 /* ACE overrun error interrupt */
//#define SNS_RING 0x00010000 /* X Ring character interrupt */
com_lstat[unit][0] |= (SNS_RING); /* set char detect status */
com_lstat[unit][0] |= (SNS_ASCIICD); /* set char detect status */
ch = (com_lstat[unit][0] >> 16) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
/* Sense byte 2 Modem status */
//#define SNS_RLSDS 0x00008000 /* S Received line signal detect status */
//#define SNS_RINGST 0x00004000 /* Ring indicator line status */
//#define SNS_DSRS 0x00002000 /* C DSR Data set ready line status */
//#define SNS_CTSS 0x00001000 /* C CTS Clear to send line status */
//#define SNS_DELTA 0x00000800 /* BS Delta receive line signal detect failure interrupt */
//#define SNS_MRING 0x00000400 /* X RI Modem ring interrupt */
//#define SNS_DELDSR 0x00000200 /* BS Delta data set ready interrupt */
//#define SNS_DELCLR 0x00000100 /* B Delta data set CTS failure interrupt */
com_lstat[unit][0] |= (SNS_CTSS|SNS_DSRS); /* set CTS & DSR status */
com_lstat[unit][0] |= (SNS_CTSS|SNS_DSRS); /* set CTS & DSR status */
com_lstat[unit][0] |= (SNS_MRING); /* set char detect status */
ch = (com_lstat[unit][0] >> 8) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
/* Sense byte 3 Modem Control/Operation status */
//#define SNS_HALFD 0x00000080 /* Half-duplix operation set */
//#define SNS_MRINGE 0x00000040 /* Modem ring enabled (1) */
//#define SNS_ACEDEF 0x00000020 /* ACE parameters defined */
//#define SNS_DIAGM 0x00000010 /* Diagnostic mode set */
//#define SNS_AUXOL2 0x00000008 /* Auxiliary output level 2 */
//#define SNS_AUXOL1 0x00000004 /* Auxiliary output level 1 */
//#define SNS_RTS 0x00000002 /* RTS Request to send set */
//#define SNS_DTR 0x00000001 /* DTR Data terminal ready set */
// com_lstat[unit][0] |= (SNS_RTS|SNS_DTR); /* set RTS & DTR status */
com_lstat[unit][0] |= (SNS_DTR); /* set DTR status */
ch = (com_lstat[unit][0] >> 0) & 0xff;
com_lstat[unit][0] |= (SNS_DTR); /* set DTR status */
ch = (com_lstat[unit][0] >> 0) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
ch = (com_lstat[unit][1] >> 24) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
ch = (com_lstat[unit][1] >> 16) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
ch = (com_lstat[unit][1] >> 8) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
ch = (com_lstat[unit][1] >> 0) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
sim_debug(DEBUG_CMD, dptr,
"com_startcmd Cmd SENSE return chan %04x u5-status %04x ls0 %08x ls1 %08x\n",
chan, uptr->u5, com_lstat[unit][0], com_lstat[unit][1]);
@ -631,14 +590,7 @@ uint16 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u4 |= ((uint32)ch)<<8; /* byte 2 of ACE data */
sim_debug(DEBUG_CMD, dptr, "com_startcmd %04x: Cmd %02x ACE bytes %08x\n",
chan, cmd, uptr->u4);
#ifdef USE_INTERUPT
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & COM_MSK); /* save command */
sim_activate(uptr, 20); /* start us up */
#else
return SNS_CHNEND|SNS_DEVEND; /* good return */
#endif
break;
@ -646,8 +598,7 @@ uint16 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 |= SNS_CMDREJ; /* command rejected */
sim_debug(DEBUG_CMD, dptr, "com_startcmd %04x: Cmd Invald %02x status %02x\n",
chan, cmd, uptr->u5);
// return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
return SNS_CHNEND|STATUS_PCHK;
return SNS_CHNEND|STATUS_PCHK; /* program check */
break;
}
@ -697,17 +648,11 @@ t_stat comi_srv(UNIT *uptr)
newln = tmxr_poll_conn(&com_desc); /* look for connect */
if (newln >= 0) { /* rcv enb pending? */
uint16 chsa = GET_UADDR(coml_unit[newln].u3); /* get channel/sub-addr */
// int chan = ((chsa >> 8) & 0x7f); /* get the channel number */
// UNIT *comlp = coml_unit+ln; /* get uptr for coml line */
// int cmd = comlp->u3 & 0xff; /* get the active cmd */
//fprintf(stderr, "comi_srv poll chsa %04x new line %04x\r\n", chsa, newln);
com_ldsc[newln].rcve = 1; /* enable rcv */
//BAD com_ldsc[newln+8].xmte = 1; /* enable xmt for output line */
com_ldsc[newln].xmte = 1; /* enable xmt for output line */
com_sta[newln] &= ~COML_REP; /* clr pending */
/* send attention to OS here for this channel */
/* need to get chsa here for the channel */
//fprintf(stderr, "comi_srv chsa %04x chan %04x\r\n", chsa, chan);
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
}
/* poll all devices for input */
@ -718,7 +663,6 @@ t_stat comi_srv(UNIT *uptr)
uint16 chsa = GET_UADDR(comlp->u3); /* get channel/sub-addr */
if (com_ldsc[ln].conn) { /* connected? */
if ((c = tmxr_getc_ln(&com_ldsc[ln]))) { /* get char */
//fprintf(stderr, "comi_srv chsa %04x input %02x cmd %02x\r\n", chsa, c, cmd);
ch = c; /* just the char */
/* echo the char out */
tmxr_putc_ln(&com_ldsc[ln], ch); /* output char */
@ -736,12 +680,10 @@ t_stat comi_srv(UNIT *uptr)
/* write byte to memory */
if (chan_write_byte(chsa, &ch)) {
/* done, reading chars */
//fprintf(stderr, "comi_srv chsa %04x input %02x complete cmd %02x\r\n", chsa, c, cmd);
comlp->u3 &= LMASK; /* nothing left, clear cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
} else {
/* more to go, continue */
//fprintf(stderr, "comi_srv chsa %04x input %02x cmd %02x\r\n", chsa, c, cmd);
if (ch == '\r') { /* see if done */
comlp->u3 &= LMASK; /* nothing left, clear cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
@ -753,8 +695,6 @@ t_stat comi_srv(UNIT *uptr)
if (((comlp->u4 & ACE_WAKE) >> 8) == ch) {
/* send attention to OS here for this channel */
/* need to get chsa here for the channel */
// fprintf(stderr, "comi_srv WAKEUP chsa %04x ch %02x wake %04x\r\n",
// chsa, ch, (comlp->u4 & ACE_WAKE)>>8);
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
}
}
@ -836,10 +776,8 @@ endit:
if (done) /* are we done writing */
goto endit; /* done */
/* just dump the char */
// /* xmt disabled, just wait around */
sim_debug(DEBUG_CMD, dptr, "com_srvo write dumping char 0x%02x on line %04x\n", ch, ln);
tmxr_poll_tx(&com_desc); /* poll xmt */
//?? sim_activate(uptr, coml_unit[ln].wait); /* wait */
sim_activate(uptr, uptr->wait); /* wait */
return SCPE_OK;
}
@ -861,12 +799,10 @@ t_stat com_reset (DEVICE *dptr)
{
int32 i;
#ifndef JUNK
if (com_dev.flags & DEV_DIS) /* master disabled? */
com_dev.flags |= DEV_DIS; /* disable lines */
else
com_dev.flags &= ~DEV_DIS;
#endif
if (com_unit[COMC].flags & UNIT_ATT) /* master att? */
sim_clock_coschedule(&com_unit[0], 200); /* activate */
for (i = 0; i < COM_LINES; i++) /* reset lines */
@ -879,11 +815,8 @@ t_stat com_reset (DEVICE *dptr)
t_stat com_attach(UNIT *uptr, CONST char *cptr)
{
DEVICE *dptr = get_dev(uptr);
// uint16 chsa = GET_UADDR(com_unit[COMC].u3); /* get channel/subaddress */
// uint16 chsa = GET_UADDR(uptr->u3); /* get channel/subaddress */
t_stat r;
// chsa = GET_UADDR(com_unit[COMC].u3); /* get channel/subaddress */
r = tmxr_attach(&com_desc, uptr, cptr); /* attach */
if (r != SCPE_OK) /* error? */
return r; /* return error */

148
SEL32/sel32_con.c
View File

@ -1,7 +1,7 @@
/* sel32_con.c: SEL 32 Class F IOP processor console.
Copyright (c) 2018-2020, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -27,11 +27,6 @@
ready to recieve/transmit data when they are activated since
they will transfer their block during chan_cmd. All data is
transmitted as ASCII characters.
Change History:
12/10/2018 - force input chars to upper case if lower case
07/18/2019 - generate interrupt for INCH/NOP commands for UTX
*/
#include "sel32_defs.h"
@ -39,7 +34,6 @@
#if NUM_DEVS_CON > 0
//#define UNIT_CON UNIT_ATTABLE | UNIT_IDLE | UNIT_DISABLE
#define UNIT_CON UNIT_IDLE | UNIT_DISABLE
#define CMD u3
@ -77,7 +71,6 @@
/* sense byte 3 */
#define SNS_RDY 0x80 /* device ready */
#define SNS_ONLN 0x40 /* device online */
//#define SNS_DSR 0x04 /* data set ready */
#define SNS_DSR 0x08 /* data set ready */
#define SNS_DCD 0x04 /* data carrier detect */
@ -98,7 +91,6 @@ con_data[NUM_UNITS_CON];
uint32 atbuf=0; /* attention buffer */
uint32 outbusy = 0; /* output waiting on timeout */
uint32 inbusy = 0; /* input waiting on timeout */
uint32 inskip = 0; /* last wait was on clock */
/* forward definitions */
uint16 con_preio(UNIT *uptr, uint16 chan);
@ -145,8 +137,6 @@ DEVICE con_dev = {
"CON", con_unit, NULL, con_mod,
NUM_UNITS_CON, 8, 15, 1, 8, 8,
NULL, NULL, &con_reset, NULL, NULL, NULL,
// &con_dib, DEV_DISABLE|DEV_DEBUG, 0, dev_debug
// &con_dib, DEV_UADDR|DEV_DISABLE|DEV_DEBUG, 0, dev_debug
&con_dib, DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug
};
@ -156,7 +146,6 @@ DEVICE con_dev = {
/* initialize the console chan/unit */
void con_ini(UNIT *uptr, t_bool f) {
int unit = (uptr - con_unit); /* unit 0 */
// DEVICE *dptr = get_dev(uptr);
uptr->u4 = 0; /* no input count */
con_data[unit].incnt = 0; /* no input data */
@ -166,12 +155,10 @@ void con_ini(UNIT *uptr, t_bool f) {
}
/* start a console operation */
uint16 con_preio(UNIT *uptr, uint16 chan)
{
uint16 con_preio(UNIT *uptr, uint16 chan) {
DEVICE *dptr = get_dev(uptr);
int unit = (uptr - dptr->units);
// if ((uptr->CMD & 0xff00) != 0) { /* just return if busy */
if ((uptr->CMD & CON_MSK) != 0) { /* just return if busy */
sim_debug(DEBUG_CMD, &con_dev, "con_preio unit=%02x BUSY\n", unit);
return SNS_BSY;
@ -203,8 +190,7 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD |= CON_INCH2; /* save INCH command as 0xf0 */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
if (unit == 1)
/*#*/ sim_activate(uptr, 40); /* start us off */
//@41 sim_activate(uptr, 40); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -215,15 +201,13 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD |= (cmd & CON_MSK); /* save command */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
if (unit == 1)
/*#*/ sim_activate(uptr, 30); /* start us off */
//@41 sim_activate(uptr, 40); /* start us off */
sim_activate(uptr, 30); /* start us off */
return 0; /* no status change */
break;
case CON_RD: /* 0x02 */ /* Read command */
case CON_ECHO: /* 0x0a */ /* Read command w/ECHO */
/* if output requested for input device, give error */
// uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD &= ~CON_MSK; /* remove old CMD */
uptr->CMD |= (cmd & CON_MSK); /* save command */
if (cmd == CON_ECHO) /* echo command? */
@ -232,19 +216,16 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
atbuf = 0; /* reset attention buffer */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
if (unit == 1)
/*#*/ sim_activate(uptr, 40); /* start us off */
//@41 sim_activate(uptr, 40); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0;
break;
case CON_NOP: /* 0x03 */ /* NOP has do nothing */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
// uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD &= ~CON_MSK; /* remove old CMD */
uptr->CMD |= (cmd & CON_MSK); /* save command */
if (unit == 1)
/*#*/ sim_activate(uptr, 40); /* start us off */
//@41 sim_activate(uptr, 40); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -253,8 +234,7 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD |= (cmd & CON_MSK); /* save command */
if (unit == 1)
/*#*/ sim_activate(uptr, 40); /* start us off */
//@41 sim_activate(uptr, 40); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -288,28 +268,16 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
sim_debug(DEBUG_CMD, &con_dev,
"con_startcmd %04x: Invalid command %02x Sense %02x\n",
chan, cmd, uptr->SNS);
// return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
return SNS_CHNEND|STATUS_PCHK;
}
#ifdef DO_DYNAMIC_DEBUG
static uint32 last2 = 0;
#endif
#ifdef TRYTHIS
extern uint32 INTS[];
#endif
/* Handle output transfers for console */
t_stat con_srvo(UNIT *uptr) {
uint16 chsa = GET_UADDR(uptr->CMD);
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
int cmd = uptr->CMD & CON_MSK;
CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
#ifdef DO_ALL_CHS
uint8 ch, cp;
#else
uint8 ch;
#endif
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo enter CMD %08x chsa %04x cmd = %02x\n", uptr->CMD, chsa, cmd);
@ -353,14 +321,7 @@ t_stat con_srvo(UNIT *uptr) {
}
if ((cmd == CON_WR) || (cmd == CON_RWD)) {
#ifndef SLOW_WAY
int cnt = 0;
#ifdef TRYTHIS_DIDNOT_WORK
if (INTS[0x18] & INTS_ACT) /* if clock int active, wait */
return sim_activate (uptr, 30); /* come back real soon */
#endif
/* see if write complete */
if (uptr->CMD & CON_OUTPUT) {
/* write is complete, post status */
@ -368,8 +329,8 @@ t_stat con_srvo(UNIT *uptr) {
"con_srvo write CMD %08x chsa %04x cmd %02x complete\n",
uptr->CMD, chsa, cmd);
uptr->CMD &= LMASK; /* nothing left, command complete */
/*RTC*/ outbusy = 0; /* output done */
outbusy = 0; /* output done */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
return SCPE_OK;
}
@ -383,57 +344,9 @@ t_stat con_srvo(UNIT *uptr) {
uptr->CMD |= CON_OUTPUT; /* output command complete */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo write wait %03x CMD %08x chsa %04x cmd %02x to complete\n",
// 23*cnt+29, uptr->CMD, chsa, cmd);
19*cnt+23, uptr->CMD, chsa, cmd);
sim_activate(uptr, 19*cnt+23); /* wait for a while */
outbusy = 1; /* output waiting */
#else /* SLOW_WAY */
/* Write to device */
if (chan_read_byte(chsa, &ch)) { /* get byte from memory */
uptr->CMD &= LMASK; /* nothing left, command complete */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo write %02x CMD %08x chsa %04x cmd %02x complete\n",
ch, uptr->CMD, chsa, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
} else {
/* HACK HACK HACK */
ch &= 0x7f; /* make 7 bit w/o parity */
#ifdef DO_ALL_CHS
/* simh stops outputting chars to debug file if it is passed a null????? */
if (ch == 0) /* do not pass a null char */
//WAS ch = '@'; /* stop simh abort .... */
ch = ' '; /* stop simh abort .... */
#ifndef ALLOW_ESC
if (((ch >= 0x20) && (ch <= 0x7e)) || (ch == '\r') || (ch == '\n'))
cp = ch;
else
cp = '^';
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo write %01x: CMD %08x putch 0x%02x %c\n", unit, uptr->CMD, ch, cp);
sim_putchar(ch); /* output next char to device */
#ifdef DO_DYNAMIC_DEBUG
// last2 = ((last2 << 8) & 0xffff) | cp; /* get last 2 chars */
// if (last2 == 0x503e) { /* check for DXP> */
last2 = ((last2 << 8) & 0xffffff) | cp; /* get last 3 chars */
if (last2 == 0x273637) { /* check for '67 */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
// con_dev.dctrl |= (DEBUG_CMD | DEBUG_EXP | DEBUG_DETAIL);
}
#endif
#else
sim_putchar(ch); /* output next char to device */
#endif
#else
/* do not output to debug file */
sim_putchar(ch); /* output next char to device */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo write %01x: CMD %08x putch 0x%02x\n", unit, uptr->CMD, ch);
#endif
sim_activate(uptr, 30); /* start us off */
// sim_activate(uptr, 20); /* start us off */
}
#endif /* SLOW_WAY */
/*RTC*/ outbusy = 1; /* tell clock output waiting */
}
return SCPE_OK;
}
@ -447,6 +360,9 @@ t_stat con_srvi(UNIT *uptr) {
uint8 ch;
t_stat r;
// sim_clock_coschedule(uptr, tmxr_poll); /* keep polling the input */
sim_clock_coschedule(uptr, 10000); /* keep polling the input */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi enter CMD %08x chsa %04x cmd %02x incnt %02x u4 %02x\n",
uptr->CMD, chsa, cmd, con_data[unit].incnt, uptr->u4);
@ -464,7 +380,6 @@ t_stat con_srvi(UNIT *uptr) {
chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* unit check */
// fall thru return SCPE_OK;
}
// return sim_activate (uptr, 20);
}
if ((cmd == CON_NOP) || (cmd == CON_INCH2)) { /* NOP is do nothing */
@ -476,14 +391,12 @@ t_stat con_srvi(UNIT *uptr) {
int len = chp->ccw_count; /* INCH command count */
uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
//FIXME add code to test return from set_inch
// int i = set_inch(uptr, mema); /* new address */
set_inch(uptr, mema); /* new address */
con_data[unit].incnt = 0; /* buffer empty */
uptr->u4 = 0; /* no I/O yet */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi INCH CMD %08x chsa %04x len %02x inch %06x\n", uptr->CMD, chsa, len, mema);
//TRY228 chan_end(chsa, SNS_CHNEND); /* INCH done */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
} else {
sim_debug(DEBUG_CMD, &con_dev,
@ -491,22 +404,15 @@ t_stat con_srvi(UNIT *uptr) {
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* NOP done */
}
/* drop through to poll input */
// return sim_activate (uptr, 20);
}
switch (cmd) {
case CON_RD: /* 0x02 */ /* read from device */
case CON_ECHO: /* 0x0a */ /* read from device w/ECHO */
#ifdef TRYTHIS_DIDNOTWORK
if (INTS[0x18] & INTS_ACT) /* if clock int active, wait */
return sim_activate (uptr, 30); /* come back real soon */
#endif
if ((uptr->u4 != con_data[unit].incnt) || /* input empty */
(uptr->CMD & CON_INPUT)) { /* input waiting? */
//try051920 inbusy = 1; /* tell clock we are busy */
// if (uptr->CMD & CON_INPUT) { /* input waiting? */
ch = con_data[unit].ibuff[uptr->u4]; /* get char from read buffer */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi readbuf unit %02x: CMD %08x read %02x incnt %02x u4 %02x len %02x\n",
@ -522,7 +428,6 @@ t_stat con_srvi(UNIT *uptr) {
"con_srvi write error unit %02x: CMD %08x read %02x u4 %02x ccw_count %02x\n",
unit, uptr->CMD, ch, uptr->u4, chp->ccw_count);
uptr->CMD &= LMASK; /* nothing left, command complete */
//try051920 inbusy = 0; /* tell clock we are not busy */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
break;
}
@ -544,7 +449,6 @@ t_stat con_srvi(UNIT *uptr) {
/* user wants more, look next time */
if (uptr->u4 == con_data[unit].incnt) { /* input empty */
uptr->CMD &= ~CON_INPUT; /* no input available */
//try051920 inbusy = 0; /* tell clock we are not busy */
}
break;
}
@ -557,7 +461,6 @@ t_stat con_srvi(UNIT *uptr) {
if (uptr->u4 != con_data[unit].incnt) { /* input empty */
uptr->CMD |= CON_INPUT; /* input still available */
}
//try051920 inbusy = 0; /* tell clock we are not busy */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
break;
}
@ -565,18 +468,10 @@ t_stat con_srvi(UNIT *uptr) {
break;
}
if (inskip == 0) {
inskip = 1;
return sim_activate (uptr, 30); /* come back real soon */
}
inskip = 1;
/* check for next input if reading or @@A sequence */
r = sim_poll_kbd(); /* poll for a char */
if (r & SCPE_KFLAG) { /* got a char */
ch = r & 0xff; /* drop any extra bits */
// if (ch == 0x1b) /* esc is bad */
// goto goout; /* skip control char */
// if ((cmd == CON_RD) || (cmd == CON_ECHO)) { /* looking for input? */
if ((uptr->CMD & CON_INPUT) == 0) { /* looking for input? */
atbuf = 0; /* reset attention buffer */
uptr->CMD &= ~CON_ATAT; /* no @@A input */
@ -590,26 +485,22 @@ t_stat con_srvi(UNIT *uptr) {
"con_srvi handle readch unit %02x: CMD %08x read %02x u4 %02x incnt %02x\n",
unit, uptr->CMD, ch, uptr->u4, con_data[unit].incnt);
//MOVED /* see if count at max, if so reset to start */
//AFTER if (con_data[unit].incnt >= sizeof(con_data[unit].ibuff))
//incnt++ con_data[unit].incnt = 0; /* reset buffer cnt */
if (uptr->CMD & CON_EKO) /* ECHO requested */
sim_putchar(ch); /* ECHO the char */
/* put char in buffer */
con_data[unit].ibuff[con_data[unit].incnt++] = ch;
/*GEERT*/ /* see if count at max, if so reset to start */
/*MOVED*/ if (con_data[unit].incnt >= sizeof(con_data[unit].ibuff))
/*HERE**/ con_data[unit].incnt = 0; /* reset buffer cnt */
/* see if count at max, if so reset to start */
if (con_data[unit].incnt >= sizeof(con_data[unit].ibuff))
con_data[unit].incnt = 0; /* reset buffer cnt */
uptr->CMD |= CON_INPUT; /* we have a char available */
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi readch unit %02x: CMD %08x read %02x u4 %02x incnt %02x\n",
unit, uptr->CMD, ch, uptr->u4, con_data[unit].incnt);
return sim_activate (uptr, 30); /* come back real soon */
// return sim_activate (uptr, 300); /* come back real soon */
// return sim_activate (uptr, 30); /* come back real soon */
return SCPE_OK;
}
/* not looking for input, look for attn or wakeup */
if (ch == '?') {
@ -636,7 +527,7 @@ t_stat con_srvi(UNIT *uptr) {
uptr->u4 = 0; /* no input count */
con_data[unit].incnt = 0; /* no input data */
}
goto goout;
return SCPE_OK;
}
/* char not for us, so keep looking */
atbuf = 0; /* reset attention buffer */
@ -664,9 +555,6 @@ t_stat con_srvi(UNIT *uptr) {
"con_srvi readch2 unit %02x: CMD %08x read %02x u4 %02x incnt %02x\n",
unit, uptr->CMD, ch, uptr->u4, con_data[unit].incnt);
}
goout:
// return sim_activate (uptr, 5000);
tmxr_clock_coschedule_tmr(uptr, TMR_RTC, 1); /* come back soon */
return SCPE_OK;
}

569
SEL32/sel32_cpu.c
View File

File diff suppressed because it is too large Load Diff

3
SEL32/sel32_defs.h
View File

@ -231,6 +231,9 @@ typedef struct dib {
uint32 chan_fifo[FIFO_SIZE]; /* interrupt status fifo for each channel */
} DIB;
extern DIB *dib_unit[MAX_DEV]; /* Pointer to Device info block */
extern DIB *dib_chan[MAX_CHAN]; /* Pointer to channel mux dib */
#define DEV_CHAN (1 << DEV_V_UF) /* Device is channel mux if set */
#define DEV_V_UF2 (DEV_V_UF+1) /* current usage */

91
SEL32/sel32_disk.c
View File

@ -446,7 +446,6 @@ uint16 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->CMDu3 |= DSK_INCH2; /* use 0xF0 for inch, just need int */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
@ -461,49 +460,41 @@ uint16 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
"disk_startcmd starting disk seek r/w cmd %02x chsa %04x\n",
cmd, chsa);
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
//@41 sim_activate(uptr, 250); /* start things off */
return 0;
break;
case DSK_NOP: /* NOP 0x03 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_SNS: /* Sense 0x04 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
break;
case DSK_WSL: /* WSL 0x31 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_RSL: /* RSL 0x32 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_WTL: /* WTL 0x51 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_RTL: /* RTL 0x52 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
//@41 sim_activate(uptr, 40); /* start things off */
return 0;
break;
}
@ -514,7 +505,6 @@ uint16 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
if (uptr->SNS & 0xff) /* any other cmd is error */
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK;
sim_activate(uptr, 20); /* start things off */
//@41sim_activate(uptr, 40); /* start things off */
return SNS_CHNEND|SNS_DEVEND;
}
@ -558,8 +548,6 @@ t_stat disk_srv(UNIT *uptr)
case DSK_INCH2: /* used 0xF0 for inch, just need int */
{
uint32 mema; /* memory address */
// uint32 daws[8]; /* drive attribute registers */
// uint32 i, j;
uint32 i;
len = chp->ccw_count; /* INCH command count */
@ -591,7 +579,6 @@ t_stat disk_srv(UNIT *uptr)
/* the next 8 words have drive data for each unit */
/* WARNING 8 drives must be defined for this controller */
/* so we will not have a map fault */
// for (i=0, j=0; i < 36; i++) {
for (i=0; i < 36; i++) {
if (chan_read_byte(chsa, &buf[i])) {
/* we have error, bail out */
@ -607,8 +594,6 @@ t_stat disk_srv(UNIT *uptr)
(buf[2]<<8) | (buf[3]);
else
/* drive attribute registers */
// daws[j++] = (buf[i-3]<<24) | (buf[i-2]<<16)
// | (buf[i-1]<<8) | (buf[i]);
/* may want to use this later */
/* clear warning errors */
tstart = (buf[i-3]<<24) | (buf[i-2]<<16)
@ -630,11 +615,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"disk_srv cmd INCH chsa %04x addr %06x count %04x completed\n",
chsa, mema, chp->ccw_count);
#ifdef FIX4MPX
chan_end(chsa, SNS_CHNEND); /* return just channel end OK */
#else
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
#endif
}
break;
@ -652,7 +633,6 @@ t_stat disk_srv(UNIT *uptr)
/* we have write error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
//XXX goto goout;
return SCPE_OK;
break;
}
@ -662,7 +642,6 @@ t_stat disk_srv(UNIT *uptr)
}
sim_debug(DEBUG_DETAIL, dptr, "\n");
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
//XXXgoout:
break;
case DSK_WTL: /* WTL 0x51 make into NOP */
@ -679,7 +658,6 @@ t_stat disk_srv(UNIT *uptr)
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
//XXX goto goout;
break;
}
if (i == 16)
@ -741,7 +719,6 @@ t_stat disk_srv(UNIT *uptr)
chan_write_byte(chsa, &ch);
/* bytes 8-11 - drive mode register entries from assigned disk */
//051520 ch = disk_type[type].type & 0xff; /* type byte */
ch = disk_type[type].type & 0xfc; /* zero bits 6 & 7 in type byte */
sim_debug(DEBUG_DETAIL, dptr, "disk_srv datr unit=%02x 1 %02x\n",
unit, ch);
@ -809,8 +786,6 @@ t_stat disk_srv(UNIT *uptr)
unit, uptr->STAR >> 16, uptr->CHS >> 16);
uptr->CHS = uptr->STAR; /* we are there */
sim_activate(uptr, 10);
//@41 sim_activate(uptr, 20);
//@41 sim_activate(uptr, 80);
break;
}
}
@ -854,7 +829,6 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"disk_srv STAR unit=%02x star %02x %02x %02x %02x\n",
unit, buf[0], buf[1], buf[2], buf[3]);
//XXXrezero:
sim_debug(DEBUG_DETAIL, dptr,
"disk_srv seek unit=%02x star %02x %02x %02x %02x\n",
unit, buf[0], buf[1], buf[2], buf[3]);
@ -913,7 +887,6 @@ t_stat disk_srv(UNIT *uptr)
"disk_srv seeking unit=%02x to cyl %04x trk %02x sec %02x\n",
unit, cyl, trk, buf[3]);
sim_activate(uptr, 20); /* start us off */
//@41 sim_activate(uptr, 30); /* start us off */
} else {
/* we are on cylinder/track/sector, so go on */
sim_debug(DEBUG_DETAIL, dptr,
@ -978,14 +951,7 @@ t_stat disk_srv(UNIT *uptr)
cyl = STAR2CYL(uptr->CHS); /* get current cyl */
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
#ifdef DO_DYNAMIC_DEBUG
if (cyl == 0 && trk == 0 && sec == 8 &&
chp->ccw_count == 0x2000 && chp->ccw_addr == 0x157c00)
// chp->ccw_count == 0x2000 && chp->ccw_addr == 0x1e7a40)
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
#endif
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
sim_debug(DEBUG_CMD, dptr,
@ -1016,11 +982,7 @@ t_stat disk_srv(UNIT *uptr)
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
return SCPE_OK;
//XXX goto rddone;
}
// sim_debug(DEBUG_DATA, dptr,
// "DISK Read2 %04x bytes leaving %04x from diskfile /%04x/%02x/%02x\n",
// i, chp->ccw_count, cyl, trk, sec);
}
sim_debug(DEBUG_CMD, dptr,
@ -1042,7 +1004,6 @@ t_stat disk_srv(UNIT *uptr)
/* convert sect back to chs value */
uptr->CHS = disksec2star(tstart, type);
/* see if over end of disk */
// if (tstart >= CAPB(type)) {
if (tstart >= (uint32)CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -1058,7 +1019,6 @@ t_stat disk_srv(UNIT *uptr)
"DISK sector read complete, %x bytes to go from diskfile /%04x/%02x/%02x\n",
chp->ccw_count, STAR2CYL(uptr->CHS), ((uptr->CHS) >> 8)&0xff, (uptr->CHS&0xff));
sim_activate(uptr, 10); /* wait to read next sector */
//@41 sim_activate(uptr, 30); /* wait to read next sector */
break;
}
break;
@ -1074,17 +1034,7 @@ t_stat disk_srv(UNIT *uptr)
unit, uptr->CMDu3, chp->ccw_count, chp->ccw_addr, cyl, trk, sec);
}
if (uptr->CMDu3 & DSK_WRITING) { /* see if we are writing data */
#ifdef DO_DYNAMIC_DEBUG
cyl = STAR2CYL(uptr->CHS); /* get current cyl */
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
if (cyl == 10 && trk == 3 && sec == 0 &&
chp->ccw_count == 0x2000 && chp->ccw_addr == 0x152800)
// chp->ccw_count == 0x2000 && chp->ccw_addr == 0x1e7a40)
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
#endif
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
/* process the next sector of data */
@ -1099,7 +1049,6 @@ t_stat disk_srv(UNIT *uptr)
ssize, cyl, trk, sec);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
return SCPE_OK;
//XXX goto wrdone;
}
ch = 0; /* finish out the sector with zero */
len++; /* show we have no more data to write */
@ -1133,7 +1082,6 @@ t_stat disk_srv(UNIT *uptr)
/* convert sect back to chs value */
uptr->CHS = disksec2star(tstart, type);
/* see if over end of disk */
// if (tstart >= CAPB(type)) {
if (tstart >= (uint32)CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -1145,7 +1093,6 @@ t_stat disk_srv(UNIT *uptr)
break;
}
sim_activate(uptr, 10); /* keep writing */
//@41 sim_activate(uptr, 30); /* keep writing */
break;
}
break;
@ -1297,7 +1244,6 @@ t_stat disk_srv(UNIT *uptr)
cyl = disk_type[type].cyl-1; /* last cyl */
trk = disk_type[type].nhds-1; /* last head number */
// sec = disk_type[type].spt-1; /* last sector number */
sim_debug(DEBUG_CMD, dptr,
"disk_srv RTL STAR %04x/%02x/%02x Dmap pointer 0x%08x %d\n",
@ -1316,7 +1262,6 @@ t_stat disk_srv(UNIT *uptr)
/* get sector address of umap table */
/* UMAP 249216 (819/15/0) 0x3cd80 for 9346 - 823/19/16 */
//WAS tstart -= SPT(type); /* calc umap address */
tstart -= (2*SPT(type)); /* calc umap address */
/* the address must be physical for UDP/DPII */
@ -1333,7 +1278,6 @@ t_stat disk_srv(UNIT *uptr)
/* and byte 28 is number of heads. Byte 26 is mode. */
/* Byte 25 is copy of byte 27. */
buf[25] = disk_type[type].spt & 0xff;
//051520 buf[26] = disk_type[type].type & 0xff; /* mode data in UDP/DPII */
buf[26] = disk_type[type].type & 0xfc; /* zero bits 6 & 7 in type byte */
buf[27] = disk_type[type].spt & 0xff;
buf[28] = disk_type[type].nhds & 0xff;
@ -1364,7 +1308,6 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
uptr->SNS |= SNS_CMDREJ;
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SNS_CHNEND|STATUS_PCHK;
break;
}
@ -1423,18 +1366,14 @@ int disk_format(UNIT *uptr) {
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
//WASint32 daddr = vaddr - SPT(type);
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* get sector address of utx flaw data (1 track long) */
/* set trace data to zero */
//WASint32 faddr = daddr - SPT(type);
int32 faddr = (CYL(type)-4) * SPC(type) + (HDS(type)-3) * SPT(type);
/* get sector address of utx flaw map sec 1 pointer */
/* use this address for sec 1 label pointer */
//WASint32 uaddr = daddr - SPT(type);
//WASint32 uaddr = daddr - (2*SPT(type));
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-4) * SPT(type);
/* last user block available */
@ -1450,32 +1389,16 @@ int disk_format(UNIT *uptr) {
0,0x22c2813e,0,0x06020000,0xf4,0,0x431b1c,0,
};
#ifdef USE_FOR_MPX
{
/* some values created by j.vfmt */
// 0xf003d14f,0x8a03cda0,0x9a03cdbf,0x8903cdc0,
// 0x9903d01f,0x8c03d020,0x9c03d14f,0xf4000000,
0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | (daddr + ((2 * tsize) - 1)),
0x89000000 | (daddr + (2 * tsize)),
0x99000000 | ((cap-1)-spc),
0x8c000000 | (cap-spc),
0x9c000000 | (cap-1), 0xf4000000,
};
#endif
/* vendor flaw map in vaddr */
uint32 vmap[2] = {0xf0000004, 0xf4000000};
/* defect map */
uint32 dmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | (cap-1), 0xf4000000};
//TRY 0x9a000000 | (cap-1), 0xf4000008};
/* utx flaw map */
uint32 fmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | ltaddr, 0xf4000000};
//TRY 0x9a000000 | ltaddr, 0xf4000008};
/* see if user wants to initialize the disk */
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
@ -1645,6 +1568,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
uint16 chsa = GET_UADDR(uptr->CMDu3);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
DIB *dibp = 0;
t_stat r;
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
@ -1668,7 +1592,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
detach_unit(uptr); /* if no space, error */
return SCPE_FMT; /* error */
return SCPE_UNATT; /* error */
}
/* see if there is any data on sector zero of disk, if not format it */
@ -1706,6 +1630,17 @@ fmt:
sim_debug(DEBUG_CMD, dptr, "File %s attached to %s\r\n",
file, disk_type[type].name);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr, "ERROR===ERROR\nDISK device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nDISK device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND);
return SCPE_OK;
}

2387
SEL32/sel32_fltpt.c
View File

File diff suppressed because it is too large Load Diff

206
SEL32/sel32_hsdp.c
View File

@ -578,13 +578,9 @@ t_stat hsdp_srv(UNIT *uptr)
DEVICE *dptr = get_dev(uptr);
DIB *dibp = (DIB *)dptr->ctxt; /* get DIB address */
CHANP *chp = (CHANP *)dibp->chan_prg; /* get pointer to channel program */
#ifdef OLDWAY
struct ddata_t *data = (struct ddata_t *)(uptr->DDATA);
#endif
int cmd = uptr->CMD & DSK_CMDMSK;
int type = GET_TYPE(uptr->flags);
uint32 trk, cyl, sec;
// uint32 trk, cyl;
int unit = (uptr - dptr->units);
int len;
int i;
@ -596,7 +592,6 @@ t_stat hsdp_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"hsdp_srv entry unit %02x CMD %08x chsa %04x count %04x %x/%x/%x \n",
// unit, uptr->CMD, chsa, chp->ccw_count, data->cyl, data->tpos, data->spos);
unit, uptr->CMD, chsa, chp->ccw_count,
STAR2CYL(uptr->CHS), (uptr->CHS >> 8)&0xff, (uptr->CHS&0xff));
@ -616,8 +611,6 @@ t_stat hsdp_srv(UNIT *uptr)
case DSK_INCH2: /* use 0xc0 for inch, just need int */
{
uint32 mema; /* memory address */
// uint32 daws[8]; /* drive attribute registers */
// uint32 i, j;
uint32 i;
len = chp->ccw_count; /* INCH command count */
@ -649,7 +642,6 @@ t_stat hsdp_srv(UNIT *uptr)
/* the next 8 words have drive data for each unit */
/* WARNING 8 drives must be defined for this controller */
/* so we will not have a map fault */
// for (i=0, j=0; i < 36; i++) {
for (i=0; i < 36; i++) {
if (chan_read_byte(chsa, &buf[i])) {
/* we have error, bail out */
@ -665,8 +657,6 @@ t_stat hsdp_srv(UNIT *uptr)
(buf[2]<<8) | (buf[3]);
else
/* drive attribute registers */
// daws[j++] = (buf[i-3]<<24) | (buf[i-2]<<16)
// | (buf[i-1]<<8) | (buf[i]);
/* may want to use this later */
/* clear warning errors */
tstart = (buf[i-3]<<24) | (buf[i-2]<<16)
@ -688,11 +678,7 @@ t_stat hsdp_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"hsdp_srv cmd INCH chsa %04x addr %06x count %04x completed\n",
chsa, mema, chp->ccw_count);
#ifdef FIX4MPX
chan_end(chsa, SNS_CHNEND); /* return just channel end OK */
#else
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
#endif
}
break;
@ -1049,27 +1035,6 @@ goout:
"hsdp_srv after READ chsa %04x buffer %06x count %04x\n",
chsa, chp->ccw_addr, chp->ccw_count);
#ifdef LOOK
/* check for 0x280 or 0x308 read count */
sec = chp->ccw_count;
if (sec == 0x308 || sec == 0x280) {
for (i = 0; i < sec; i++) {
if ((i%16) == 0)
sim_debug(DEBUG_CMD, dptr, "\nREAD: %06x", chp->ccw_addr + i);
sim_debug(DEBUG_CMD, dptr, " %02x", buf[i]);
}
sim_debug(DEBUG_CMD, dptr, "\n\n");
}
if (sec == 0x308 || sec == 0x280) {
for (i = sec; i < ssize; i++) {
if (((i-sec)%16) == 0)
sim_debug(DEBUG_CMD, dptr, "\nREAD: %06x", chp->ccw_addr + i - sec);
sim_debug(DEBUG_CMD, dptr, " %02x", buf[i]);
}
sim_debug(DEBUG_CMD, dptr, "\n");
}
#endif
/* process the next sector of data */
for (i=0; i<len; i++) {
ch = buf[i]; /* get a char from buffer */
@ -1102,7 +1067,6 @@ goout:
/* convert sect back to chs value */
uptr->CHS = hsdpsec2star(tstart, type);
/* see of over end of disk */
// if (tstart >= CAPB(type)) {
if (tstart >= (uint32)CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -1135,15 +1099,8 @@ rddone:
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
#ifdef LOOK
/* check for 0x280 or 0x308 read count */
sec = chp->ccw_count;
tstart = chp->ccw_addr;
#endif
/* process the next sector of data */
len = 0; /* used here as a flag for short read */
for (i=0; i<ssize; i++) {
@ -1161,33 +1118,8 @@ rddone:
len++; /* show we have no more data to write */
}
buf2[i] = ch; /* save the char */
#ifdef LOOK
trk = chp->ccw_addr;
#endif
}
#ifdef LOOK
/* check for 0x280 or 0x308 read count */
// sec = chp->ccw_count;
if (sec == 0x308 || sec == 0x280) {
for (i = 0; i < sec; i++) {
if ((i%16) == 0)
sim_debug(DEBUG_CMD, dptr, "\nWRIT: %06x", tstart + i);
sim_debug(DEBUG_CMD, dptr, " %02x", buf[i]);
}
sim_debug(DEBUG_CMD, dptr, "\n\n");
}
if (sec == 0x308 || sec == 0x280) {
tstart = trk - (ssize-sec);
for (i = sec; i < ssize; i++) {
if (((i-sec)%16) == 0)
sim_debug(DEBUG_CMD, dptr, "\nWRIT: %06x", tstart + i - sec);
sim_debug(DEBUG_CMD, dptr, " %02x", buf[i]);
}
sim_debug(DEBUG_CMD, dptr, "\n");
}
#endif
/* write the sector to disk */
if ((i=sim_fwrite(buf2, 1, ssize, uptr->fileref)) != ssize) {
sim_debug(DEBUG_CMD, dptr,
@ -1208,22 +1140,12 @@ rddone:
sim_debug(DEBUG_CMD, dptr,
"DISK WR to sec end %04x bytes end %04x to diskfile cyl %04x hds %02x sec %02x\n",
len, ssize, cyl, trk, sec);
#ifdef LOOK
sec = 0;
for (i = 0; i < ssize; i++) {
if ((i%16) == 0)
sim_debug(DEBUG_CMD, dptr, "\nWRIT %3x:", i);
sim_debug(DEBUG_CMD, dptr, " %02x", buf[i]);
}
sim_debug(DEBUG_CMD, dptr, "\n\n");
#endif
/* tstart has file offset in sectors */
tstart++; /* bump to next sector */
/* convert sect back to chs value */
uptr->CHS = hsdpsec2star(tstart, type);
/* see of over end of disk */
// if (tstart >= CAPB(type)) {
if (tstart >= (uint32)CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -1259,36 +1181,15 @@ wrdone:
/* The UTX med map is pointed to by sector label 1 */
/* simulate pointers here, set wd[3] in label to VDT */
#ifdef OLD
/* get physical sector address of media defect table */
/* VDT 286935 (819/9/0) 0x460f5 for 8887 - 823/10/35 */
/* MDT 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
/* DMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
/* UMAP 286860 (819/6/0) 0x4608c for 8887 - 823/10/35 */
#else
/* get physical sector address of media defect table */
/* VDT 286965 (819/9/0) 0x460f5 for 8887 - 823/10/35 */
// /* MDT 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
/* DMAP 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
// /* DMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
/* UMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
// /* UMAP 286860 (819/6/0) 0x4608c for 8887 - 823/10/35 */
#endif
#ifdef OLD
/* get logical sector address of media defect table */
/* VDT 278766 (819/9/0) 0x440ee for 8887 - 823/10/34 */
/* MDT 278732 (819/8/0) 0x440cc for 8887 - 823/10/34 */
/* DMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 */
/* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
#else
/* get logical sector address of media defect table */
/* VDT 278766 (819/9/0) 0x440ee for 8887 - 823/10/34 */
// /* MDT 278732 (819/8/0) 0x440cc for 8887 - 823/10/34 */
/* DMAP 278732 (819/8/0) 0x440cc for 8887 - 823/10/34 */
// /* DMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 */
/* UMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 Sec 0 ptr */
// /* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
#endif
sim_debug(DEBUG_CMD, dptr, "hsdp_startcmd RSL STAR %08x disk geom %08x\n",
uptr->CHS, GEOM(type));
@ -1306,15 +1207,9 @@ wrdone:
unit, buf[0], buf[1], buf[2], buf[3]);
/* get physical sector address of UMAP */
#ifdef OLD
/* UMAP 286860 (819/6/0) 0x4608c for 8887 - 823/10/35 */
tstart = ((CYL(type)-4) * SPC(type)) +
((HDS(type)-4) * SPT(type));
#else
/* UMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 Sec 0 ptr */
tstart = ((CYL(type)-4) * SPC(type)) +
((HDS(type)-3) * (SPT(type)));
#endif
/* get physical sector address of UMAP */
sim_debug(DEBUG_CMD, dptr,
@ -1323,11 +1218,7 @@ wrdone:
/* on HSDP DMAP is in wd 3 on label 0 */
/* on HSDP UMAP is in wd 4 on label 1 */
#ifdef OLD
/* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
#else
/* UMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 Sec 0 ptr */
#endif
tstart = (tstart * (SPT(type)-1))/SPT(type); /* make logical */
/* the address must be logical for HSDP */
@ -1337,12 +1228,11 @@ wrdone:
buf[14] = (tstart >> 8) & 0xff;
buf[15] = (tstart) & 0xff;
#ifndef NOTNOW
buf[16] = (tstart >> 24) & 0xff; /* UMAP pointer too */
buf[17] = (tstart >> 16) & 0xff;
buf[18] = (tstart >> 8) & 0xff;
buf[19] = (tstart) & 0xff;
#endif
/* the tech doc shows the cyl/trk/sec data is in the first 4 bytes */
/* of the track label, BUT it is really in the configuration data */
/* area are too. That is where UTX looks. Byte 27 is sectors/track */
@ -1424,13 +1314,6 @@ wrdone:
/* The UTX media map is pointed to by sector label 1 */
/* simulate pointers here, set wd[3] in label to VDT */
#ifdef OLD
/* get physical sector address of media defect table */
/* VDT 286935 (819/9/0) 0x460f5 for 8887 - 823/10/35 */
/* MDT 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
/* DMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
/* UMAP 286860 (819/6/0) 0x4608c for 8887 - 823/10/35 */
#else
/* get physical sector address of media defect table */
/* VDT 286965 (819/9/0) 0x460f5 for 8887 - 823/10/35 */
// /* MDT 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
@ -1438,14 +1321,6 @@ wrdone:
// /* DMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
/* UMAP 286895 (819/7/0) 0x460af for 8887 - 823/10/35 */
// /* UMAP 286860 (819/6/0) 0x4608c for 8887 - 823/10/35 */
#endif
#ifdef OLD
/* get logical sector address of media defect table */
/* VDT 278766 (819/9/0) 0x440ee for 8887 - 823/10/34 */
/* MDT 278732 (819/8/0) 0x440cc for 8887 - 823/10/34 */
/* DMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 */
/* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
#else
/* get logical sector address of media defect table */
/* VDT 278766 (819/9/0) 0x440ee for 8887 - 823/10/34 */
// /* MDT 278732 (819/8/0) 0x440cc for 8887 - 823/10/34 */
@ -1453,7 +1328,6 @@ wrdone:
// /* DMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 */
/* UMAP 278698 (819/7/0) 0x440aa for 8887 - 823/10/34 Sec 0 ptr */
// /* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
#endif
tstart = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
@ -1482,7 +1356,6 @@ wrdone:
/* get logical sector address of umap table */
/* UMAP 278664 (819/6/0) 0x44088 for 8887 - 823/10/34 Sec 0 ptr */
tstart -= SPT(type); /* calc utxfmap address */
//BAD tstart -= (2*SPT(type)); /* calc umap address */
/* the address must be logical */
/* 286860 physical becomes 278664 logical */
@ -1532,7 +1405,6 @@ wrdone:
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
uptr->SNS |= SNS_CMDREJ;
uptr->CMD &= ~(0xffff); /* remove old status bits & cmd */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SNS_CHNEND|STATUS_PCHK;
break;
}
@ -1595,7 +1467,6 @@ int hsdp_format(UNIT *uptr) {
int32 logda = daddr*(SPC(type)-1)/(SPC(type));
int32 uaddr = daddr - SPT(type);
//BADnt32 uaddr = daddr - (2*SPT(type));
/* last block available */
int32 luaddr = (CYL(type)-4) * SPC(type);
@ -1604,37 +1475,16 @@ int hsdp_format(UNIT *uptr) {
/* get sector address of utx flaw data (1 track long) */
/* set trace data to zero */
//NOint32 faddr = daddr - SPT(type);
/* make up a UMAP with the partition for 8887 disk */
uint32 umap[256] =
{
//WAS 0x4e554d50,(cap-1),luaddr-1,0,0,0,0,0xe10,
0x4e554d50,logla,logua-1,0,0,0,0,0xe10,
//WAS 0,0x5258,0,0x4e5c,0x3e,luaddr,0,0xd32c,
0,0x5258,0,0x4e5c,0x3e,logua,0,0xd32c,
0x79,0x187cc,0x118,0x14410,0x23f,0,0,0,
0,0x3821a2d6,0,0x1102000,0xf4,0,0,0,
// dec 0x4e554d50,(cap-1),luaddr-1,0,0,0,0,3600,
// dec 0,21080,0,20060,62,luaddr,0,54060,
// dec 121,100300,280,82960,575,0,0,0,
// dec 0,clocksecs,0,17833984,244,0,0,0,
};
#ifdef USEFORMPX
{
/* some values created by j.vfmt */
// 0xf003d14f,0x8a03cda0,0x9a03cdbf,0x8903cdc0,
// 0x9903d01f,0x8c03d020,0x9c03d14f,0xf4000000,
0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | (daddr + ((2 * tsize) - 1)),
0x89000000 | (daddr + (2 * tsize)),
0x99000000 | ((cap-1)-spc),
0x8c000000 | (cap-spc),
0x9c000000 | (cap-1), 0xf4000000,
};
#endif
/* NULL vendor flaw map */
uint32 vmap[2] = {0xf0000004, 0xf4000000};
@ -1643,27 +1493,12 @@ int hsdp_format(UNIT *uptr) {
0x9a000000 | (cap-1), 0xf4000008};
uint32 dmap[4] = {0xf0000000 | logla, 0x8a000000 | logda,
0x9a000000 | logla, 0xf4000008};
//WAS 0x9a000000 | (cap-1), 0xf4000000};
/* see if user wants to initialize the disk */
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
return 1;
}
#ifdef OLD_WAY
/* dmap data */
/* the diag map (dmap) is in last sec of disk */
/* (cyl * trk * sec) - 1 = cap - 1*/
/* 0xf0046531 - 288049 - 822/9/34 */
/* 0x8a0460d2 - 286930 - 819/8/0 */
/* 0x9a046531 - 288049 - 822/9/34 */
/* 0xf4000000 */
dmap[0] = 0xf0000000 | (cap-1); /* 0xf003d14f */
dmap[1] = 0x8a000000 | daddr; /* 0x8a03ccaf */
dmap[2] = 0x9a000000 | (cap-1); /* 0x9a03d14f */
dmap[3] = 0xf4000000;
#endif
/* get physical sector address of media defect table */
/* VDT 286965 (819/9/0) 0x460f5 for 8887 - 823/10/35 */
// /* MDT 286930 (819/8/0) 0x460d2 for 8887 - 823/10/35 Trk 0 ptr */
@ -1786,22 +1621,6 @@ int hsdp_format(UNIT *uptr) {
return 1;
}
#ifdef NOTUSED
/* write dummy DMAP to faddr */
if ((sim_fseek(uptr->fileref, faddr*ssize, SEEK_SET)) != 0) { /* seek DMAP */
sim_debug(DEBUG_CMD, dptr,
"Error on media flaw map seek to sect %06x offset %06x\n",
faddr, faddr*ssize);
return 1;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
"Error writing flaw map to sect %06x offset %06x\n",
faddr, faddr*ssize);
return 1;
}
#endif
/* write UTX umap to uaddr */
if ((sim_fseek(uptr->fileref, uaddr*ssize, SEEK_SET)) != 0) { /* seek UMAP */
sim_debug(DEBUG_CMD, dptr,
@ -1818,10 +1637,6 @@ int hsdp_format(UNIT *uptr) {
printf("writing to vmap sec %x (%d) bytes %x (%d)\n",
vaddr, vaddr, (vaddr)*ssize, (vaddr)*ssize);
#ifdef NOTUSED
printf("writing to flaw map sec %x (%d) bytes %x (%d)\n",
faddr, faddr, (faddr)*ssize, (faddr)*ssize);
#endif
printf("writing dmap to %x %d %x %d dmap to %x %d %x %d\n",
cap-1, cap-1, (cap-1)*ssize, (cap-1)*ssize,
daddr, daddr, daddr*ssize, daddr*ssize);
@ -1839,9 +1654,10 @@ int hsdp_format(UNIT *uptr) {
/* attach the selected file to the disk */
t_stat hsdp_attach(UNIT *uptr, CONST char *file)
{
uint16 addr = GET_UADDR(uptr->CMD);
uint16 chsa = GET_UADDR(uptr->CMD);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
DIB *dibp = 0;
t_stat r;
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
@ -1903,7 +1719,19 @@ fmt:
sim_debug(DEBUG_CMD, dptr, "File %s attached to %s\r\n",
file, hsdp_type[type].name);
set_devattn(addr, SNS_DEVEND);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nHSDP device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nHSDP device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND);
return SCPE_OK;
}

27
SEL32/sel32_iop.c
View File

@ -35,7 +35,6 @@
#if NUM_DEVS_IOP > 0
//#define UNIT_IOP UNIT_ATTABLE | UNIT_IDLE | UNIT_DISABLE
#define UNIT_IOP UNIT_IDLE | UNIT_DISABLE
/* forward definitions */
@ -72,7 +71,6 @@ const char *iop_desc(DEVICE *dptr);
#define SNS_ONLN 0x40 /* device online */
/* std devices. data structures
iop_dev Console device descriptor
iop_unit Console unit descriptor
iop_reg Console register list
@ -120,13 +118,10 @@ DIB iop_dib = {
DEVICE iop_dev = {
"IOP", iop_unit, NULL, iop_mod,
NUM_UNITS_IOP, 8, 15, 1, 8, 8,
NULL, NULL, &iop_reset, /* examine, deposit, reset */
NULL, NULL, NULL, /* boot, attach, detach */
NULL, NULL, &iop_reset, /* examine, deposit, reset */
NULL, NULL, NULL, /* boot, attach, detach */
/* dib ptr, dev flags, debug flags, debug */
// &iop_dib, DEV_CHAN|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
&iop_dib, DEV_CHAN|DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
// NULL, NULL, &iop_help, /* ?, ?, help */
// NULL, NULL, &iop_desc /* ?, ?, description */
};
/* IOP controller routines */
@ -165,11 +160,9 @@ uint16 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
iop_chp[0].chan_inch_addr); /* set inch buffer addr */
iop_chp[0].chan_inch_addr = iop_chp[0].ccw_addr; /* set inch buffer addr */
// set_inch(uptr, iop_chp[0].ccw_addr); /* new address */
uptr->u3 |= IOP_INCH2; /* save INCH command as 0xf0 */
sim_activate(uptr, 20); /* go on */
//@41 sim_activate(uptr, 40); /* go on */
sim_activate(uptr, 40); /* go on */
return 0; /* no status change */
break;
@ -178,8 +171,7 @@ uint16 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save NOP command */
sim_activate(uptr, 20); /* TRY 07-13-19 */
//@41 sim_activate(uptr, 40); /* TRY 07-13-19 */
sim_activate(uptr, 40); /* TRY 07-13-19 */
return 0; /* no status change */
break;
@ -189,8 +181,7 @@ uint16 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
chan, cmd, uptr->u5);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save command */
sim_activate(uptr, 20); /* force interrupt */
//@41 sim_activate(uptr, 40); /* force interrupt */
sim_activate(uptr, 40); /* force interrupt */
return 0; /* no status change */
break;
}
@ -203,10 +194,7 @@ t_stat iop_srv(UNIT *uptr)
{
uint16 chsa = GET_UADDR(uptr->u3);
int cmd = uptr->u3 & IOP_MSK;
// CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
CHANP *chp = &iop_chp[0]; /* find the chanp pointer */
// int i;
// int len = chp->ccw_count; /* INCH command count */
uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
/* test for NOP or INCH cmds */
@ -233,12 +221,9 @@ t_stat iop_srv(UNIT *uptr)
/* the chp->ccw_addr location contains the inch address */
/* call set_inch() to setup inch buffer */
// i = set_inch(uptr, mema); /* new address */
set_inch(uptr, mema); /* new address */
// chp->chan_inch_addr = mema; /* set inch buffer addr */
uptr->u3 &= LMASK; /* clear the cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
// chan_end(chsa, SNS_CHNEND); /* we are done dev|chan end */
}
return SCPE_OK;
}
@ -256,8 +241,6 @@ t_stat iop_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, CONST char *cptr
fprintf(st, "The IOP fields all interrupts and status posting\r\n");
fprintf(st, "for each of the controllers on the system.\r\n");
fprintf(st, "Nothing can be configured for this Channel.\r\n");
// fprint_set_help(st, dptr);
// fprint_show_help(st, dptr);
return SCPE_OK;
}

211
SEL32/sel32_lpr.c
View File

@ -66,18 +66,19 @@ LP.CMD17 DATAW X'37000000' <LF> <LF> <LF> (SPARE)
** LINE PRINTER FORMS CONTROL TABLE
*
LPFCTBL EQU $
P0006C 2B DATAB C'+' 0x2b FORMS CONTROL FOR CR THEN PRINT
P0006D 31 DATAB C'1' 0x31 FORMS CONTROL FOR FF THEN PRINT
P0006E 2D DATAB C'-' 0x2d FORMS CONTROL FOR FF THEN PRINT
P0006F 30 DATAB C'0' 0x30 FORMS CONTROL FOR 2 LF'S THEN PRINT
P00070 20 DATAB C' ' 0x20 FORMS CONTROL FOR LF THEN PRINT
2B DATAB C'+' 0x2b FORMS CONTROL FOR CR THEN PRINT
31 DATAB C'1' 0x31 FORMS CONTROL FOR FF THEN PRINT
2D DATAB C'-' 0x2d FORMS CONTROL FOR FF THEN PRINT
30 DATAB C'0' 0x30 FORMS CONTROL FOR 2 LF'S THEN PRINT
20 DATAB C' ' 0x20 FORMS CONTROL FOR LF THEN PRINT
*/
#if NUM_DEVS_LPR > 0
//#define UNIT_LPR UNIT_ATTABLE | UNIT_IDLE | UNIT_DISABLE
#define UNIT_LPR UNIT_ATTABLE | UNIT_IDLE
#define UNIT_LPR UNIT_ATTABLE | UNIT_IDLE | UNIT_DISABLE
//#define UNIT_LPR UNIT_ATTABLE | UNIT_IDLE
#define CMDu3 u3
/* u3 hold command and status information */
#define LPR_INCH 0x00 /* INCH command */
/* print buffer then CC commands */
@ -107,7 +108,10 @@ P00070 20 DATAB C' ' 0x20 FORMS CONTROL FO
#define LPR_PRE 0x200 /* Apply pre CC */
#define LPR_POST 0x400 /* Apply post CC */
/* u4 holds current line */
#define CNTu4 u4
/* u4 holds current line count */
#define SNSu5 u5
/* in u5 packs sense byte 0,1 and 3 */
/* Sense byte 0 */
#define SNS_CMDREJ 0x80 /* Command reject */
@ -118,6 +122,8 @@ P00070 20 DATAB C' ' 0x20 FORMS CONTROL FO
#define SNS_OVRRUN 0x04 /* Data overrun */
#define SNS_SEQUENCE 0x02 /* Unusual sequence */
#define SNS_BOF 0x01 /* BOF on printer */
#define CBPu6 u6
/* u6 hold buffer position */
/* std devices. data structures
@ -129,7 +135,7 @@ P00070 20 DATAB C' ' 0x20 FORMS CONTROL FO
struct _lpr_data
{
uint8 lbuff[160]; /* Output line buffer */
uint8 lbuff[160]; /* Output line buffer */
}
lpr_data[NUM_DEVS_LPR];
@ -185,8 +191,8 @@ DEVICE lpr_dev = {
NUM_DEVS_LPR, 8, 15, 1, 8, 8,
NULL, NULL, NULL, NULL, &lpr_attach, &lpr_detach,
/* ctxt is the DIB pointer */
// &lpr_dib, DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug
&lpr_dib, DEV_DISABLE | DEV_DEBUG, 0, dev_debug
&lpr_dib, DEV_DISABLE|DEV_DEBUG, 0, dev_debug
// &lpr_dib, DEV_DISABLE|DEV_DEBUG|DEV_DIS, 0, dev_debug
};
/* initialize the line printer */
@ -197,16 +203,16 @@ void lpr_ini(UNIT *uptr, t_bool f) {
/* start an I/O operation */
uint16 lpr_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
{
if ((uptr->u3 & LPR_CMDMSK) != 0) { /* unit busy */
if ((uptr->CMDu3 & LPR_CMDMSK) != 0) { /* unit busy */
return SNS_BSY; /* yes, busy (already tested) */
}
uptr->u3 &= ~(LPR_POST|LPR_PRE); /* set no CC */
uptr->CMDu3 &= ~(LPR_POST|LPR_PRE); /* set no CC */
if (((cmd & 0x03) == 0x03) || (cmd & 0x0f) == 0x0d) {
uptr->u3 |= LPR_PRE; /* apply pre CC */
uptr->CMDu3 |= LPR_PRE; /* apply pre CC */
}
if (((cmd & 0x0f) == 0x05) || (cmd & 0x0f) == 0x0d) {
uptr->u3 |= LPR_POST; /* apply post CC */
uptr->CMDu3 |= LPR_POST; /* apply post CC */
}
sim_debug(DEBUG_CMD, &lpr_dev, "lpr_startcmd Cmd %02x\n", cmd);
@ -215,7 +221,6 @@ uint16 lpr_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case 0x00: /* INCH command */
/* the IOP should already have the inch buffer set, so ignore */
sim_debug(DEBUG_CMD, &lpr_dev, "lpr_startcmd %04x: Cmd INCH\n", chan);
//fprintf(stderr, "lpr_startcmd %04x: Cmd INCH\n", chan);
return SNS_CHNEND|SNS_DEVEND; /* all is well */
break;
@ -241,157 +246,162 @@ uint16 lpr_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case 0x37: /* <LF> <LF> <LF> */
case 0x47: /* <FF> */
/* process the command */
sim_debug(DEBUG_CMD, &lpr_dev, "lpr_startcmd %04x: Cmd %02x print\n", chan, cmd&LPR_CMDMSK);
uptr->u3 &= ~(LPR_CMDMSK); /* zero cmd */
uptr->u3 |= (cmd & LPR_CMDMSK); /* save new command in u3 */
sim_debug(DEBUG_CMD, &lpr_dev,
"lpr_startcmd %04x: Cmd %02x print\n", chan, cmd&LPR_CMDMSK);
uptr->CMDu3 &= ~(LPR_CMDMSK); /* zero cmd */
uptr->CMDu3 |= (cmd & LPR_CMDMSK); /* save new command in CMDu3 */
sim_activate(uptr, 100); /* Start unit off */
uptr->u5 = 0; /* no status */
uptr->u6 = 0; /* start of buffer */
uptr->SNSu5 = 0; /* no status */
uptr->CBPu6 = 0; /* start of buffer */
return 0; /* we are good to go */
case 0x4: /* Sense Status */
sim_debug(DEBUG_CMD, &lpr_dev, "lpr_startcmd %04x: Cmd %02x sense\n", chan, cmd&LPR_CMDMSK);
uptr->u3 &= ~(LPR_CMDMSK); /* zero cmd */
uptr->u3 |= (cmd & LPR_CMDMSK); /* save new command in u3 */
sim_debug(DEBUG_CMD, &lpr_dev,
"lpr_startcmd %04x: Cmd %02x sense\n", chan, cmd&LPR_CMDMSK);
uptr->CMDu3 &= ~(LPR_CMDMSK); /* zero cmd */
uptr->CMDu3 |= (cmd & LPR_CMDMSK); /* save new command in CMDu3 */
sim_activate(uptr, 100); /* Start unit off */
uptr->u5 = 0; /* no status */
uptr->u6 = 0; /* start of buffer */
uptr->SNSu5 = 0; /* no status */
uptr->CBPu6 = 0; /* start of buffer */
return 0; /* we are good to go */
default: /* invalid command */
sim_debug(DEBUG_CMD, &lpr_dev,
"lpr_startcmd %04x: Cmd %02x INVALID\n", chan, cmd&LPR_CMDMSK);
uptr->u5 |= SNS_CMDREJ;
uptr->SNSu5 |= SNS_CMDREJ;
break;
}
if (uptr->u5 & 0xff)
// return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK;
if (uptr->SNSu5 & 0xff)
return SNS_CHNEND|STATUS_PCHK;
return SNS_CHNEND|SNS_DEVEND;
}
/* Handle transfer of data for printer */
t_stat lpr_srv(UNIT *uptr) {
int chsa = GET_UADDR(uptr->u3);
int u = (uptr - lpr_unit);
int cmd = (uptr->u3 & 0xff);
int chsa = GET_UADDR(uptr->CMDu3);
int u = (uptr - lpr_unit);
int cmd = (uptr->CMDu3 & 0xff);
sim_debug(DEBUG_CMD, &lpr_dev, "lpr_srv called chsa %04x cmd %02x u3 %08x cnt %04x\r\n",
chsa, cmd, uptr->u3, uptr->u6);
sim_debug(DEBUG_CMD, &lpr_dev,
"lpr_srv called chsa %04x cmd %02x CMDu3 %08x cnt %04x\r\n",
chsa, cmd, uptr->CMDu3, uptr->CBPu6);
/* FIXME, need IOP lp status bit assignments */
if (cmd == 0x04) { /* sense? */
uint8 ch = uptr->u5; /* get current status */
uptr->u3 &= ~(LPR_CMDMSK); /* clear command */
uint8 ch = uptr->SNSu5; /* get current status */
uptr->CMDu3 &= ~(LPR_CMDMSK); /* clear command */
chan_write_byte(chsa, &ch); /* write the status to memory */
uptr->u6 = 0; /* reset to beginning of buffer */
uptr->CBPu6 = 0; /* reset to beginning of buffer */
chan_end(chsa, SNS_DEVEND|SNS_CHNEND); /* we are done */
return SCPE_OK;
}
/* process any CC before printing buffer */
if ((uptr->u3 & LPR_PRE) && (((cmd & 0x03) == 0x03) || (cmd & 0x0f) == 0x0d)) {
uptr->u3 &= ~LPR_PRE; /* remove pre flag */
if ((uptr->CMDu3 & LPR_PRE) && (((cmd & 0x03) == 0x03) ||
(cmd & 0x0f) == 0x0d)) {
uptr->CMDu3 &= ~LPR_PRE; /* remove pre flag */
/* we have CC to do */
switch ((cmd & 0xf0) >> 4) {
case 0: /* <CR> (0x0d) */
lpr_data[u].lbuff[uptr->u6++] = 0x0d;
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0d;
break;
case 3: /* <LF> <LF> <LF> */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
/* drop thru */
case 2: /* <LF> <LF> */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
/* drop thru */
case 1: /* <LF> (0x0a) */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
break;
case 4: /* <FF> (0x0c) */
lpr_data[u].lbuff[uptr->u6++] = 0x0d; /* add C/R */
lpr_data[u].lbuff[uptr->u6++] = 0x0a; /* add L/F */
lpr_data[u].lbuff[uptr->u6++] = 0x0c; /* add FF */
uptr->u4 = 0; /* restart line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0d; /* add C/R */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a; /* add L/F */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0c; /* add FF */
uptr->CNTu4 = 0; /* restart line count */
break;
}
}
/* Copy next byte from users buffer */
while ((uptr->u3 & LPR_FULL) == 0) { /* copy in a char if not full */
if(chan_read_byte(chsa, &lpr_data[u].lbuff[uptr->u6])) {
uptr->u3 |= LPR_FULL; /* end of buffer or error */
while ((uptr->CMDu3 & LPR_FULL) == 0) { /* copy in a char if not full */
if(chan_read_byte(chsa, &lpr_data[u].lbuff[uptr->CBPu6])) {
uptr->CMDu3 |= LPR_FULL; /* end of buffer or error */
break; /* done reading */
} else {
/* remove nulls */
if (lpr_data[u].lbuff[uptr->u6] == '\0') {
lpr_data[u].lbuff[uptr->u6] = ' ';
if (lpr_data[u].lbuff[uptr->CBPu6] == '\0') {
lpr_data[u].lbuff[uptr->CBPu6] = ' ';
}
/* remove backspace */
if (lpr_data[u].lbuff[uptr->u6] == 0x8) {
lpr_data[u].lbuff[uptr->u6] = ' ';
if (lpr_data[u].lbuff[uptr->CBPu6] == 0x8) {
lpr_data[u].lbuff[uptr->CBPu6] = ' ';
}
uptr->u6++; /* next buffer loc */
uptr->CBPu6++; /* next buffer loc */
}
}
/* remove trailing blanks before we apply trailing carriage control */
while (uptr->u6 > 0) {
if ((lpr_data[u].lbuff[uptr->u6-1] == ' ') ||
(lpr_data[u].lbuff[uptr->u6-1] == '\0')) {
uptr->u6--;
while (uptr->CBPu6 > 0) {
if ((lpr_data[u].lbuff[uptr->CBPu6-1] == ' ') ||
(lpr_data[u].lbuff[uptr->CBPu6-1] == '\0')) {
uptr->CBPu6--;
continue;
}
break;
}
/* process any CC after printing buffer */
if ((uptr->u3 & LPR_FULL) && (uptr->u3 & LPR_POST) && ((cmd & 0x0f) == 0x0d)) {
if ((uptr->CMDu3 & LPR_FULL) && (uptr->CMDu3 & LPR_POST) &&
((cmd & 0x0f) == 0x0d)) {
/* we have CC to do */
uptr->u3 &= ~LPR_POST; /* remove post flag */
lpr_data[u].lbuff[uptr->u6++] = 0x0d; /* just a <CR> */
uptr->CMDu3 &= ~LPR_POST; /* remove post flag */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0d; /* just a <CR> */
}
/* process any CC after printing buffer */
if ((uptr->u3 & LPR_FULL) && (uptr->u3 & LPR_POST) && ((cmd & 0x0f) == 0x05)) {
if ((uptr->CMDu3 & LPR_FULL) && (uptr->CMDu3 & LPR_POST) &&
((cmd & 0x0f) == 0x05)) {
/* we have CC to do */
uptr->u3 &= ~LPR_POST; /* remove post flag */
uptr->CMDu3 &= ~LPR_POST; /* remove post flag */
switch ((cmd & 0xf0) >> 4) {
case 0: /* <CR> (0x0d) */
lpr_data[u].lbuff[uptr->u6++] = 0x0d;
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0d;
break;
case 3: /* <LF> <LF> <LF> */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
/* drop thru */
case 2: /* <LF> <LF> */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
/* drop thru */
case 1: /* <LF> (0x0a) */
lpr_data[u].lbuff[uptr->u6++] = 0x0a;
uptr->u4++; /* increment the line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a;
uptr->CNTu4++; /* increment the line count */
break;
case 4: /* <FF> (0x0c) */
lpr_data[u].lbuff[uptr->u6++] = 0x0d; /* add C/R */
lpr_data[u].lbuff[uptr->u6++] = 0x0a; /* add L/F */
lpr_data[u].lbuff[uptr->u6++] = 0x0c; /* add FF */
uptr->u4 = 0; /* restart line count */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0d; /* add C/R */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0a; /* add L/F */
lpr_data[u].lbuff[uptr->CBPu6++] = 0x0c; /* add FF */
uptr->CNTu4 = 0; /* restart line count */
break;
}
}
/* print the line if buffer is full */
if (uptr->u3 & LPR_FULL || uptr->u6 >= 156) {
lpr_data[u].lbuff[uptr->u6] = 0x00; /* NULL terminate */
sim_fwrite(&lpr_data[u].lbuff, 1, uptr->u6, uptr->fileref); /* Print our buffer */
if (uptr->CMDu3 & LPR_FULL || uptr->CBPu6 >= 156) {
lpr_data[u].lbuff[uptr->CBPu6] = 0x00; /* NULL terminate */
sim_fwrite(&lpr_data[u].lbuff, 1, uptr->CBPu6, uptr->fileref); /* Print our buffer */
sim_debug(DEBUG_DETAIL, &lpr_dev, "LPR %s", (char*)&lpr_data[u].lbuff);
uptr->u3 &= ~(LPR_FULL|LPR_CMDMSK); /* clear old status */
uptr->u6 = 0; /* start at beginning of buffer */
uptr->u4++; /* increment the line count */
if ((uint32)uptr->u4 > uptr->capac) { /* see if at max lines/page */
uptr->u4 = 0; /* yes, restart count */
uptr->CMDu3 &= ~(LPR_FULL|LPR_CMDMSK); /* clear old status */
uptr->CBPu6 = 0; /* start at beginning of buffer */
uptr->CNTu4++; /* increment the line count */
if ((uint32)uptr->CNTu4 > uptr->capac) { /* see if at max lines/page */
uptr->CNTu4 = 0; /* yes, restart count */
chan_end(chsa, SNS_DEVEND|SNS_CHNEND|SNS_UNITEXP); /* we are done */
} else
chan_end(chsa, SNS_DEVEND|SNS_CHNEND); /* we are done */
@ -420,7 +430,7 @@ t_stat lpr_setlpp(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
if (i < 20 || i > 100)
return SCPE_ARG;
uptr->capac = i;
uptr->u4 = 0;
uptr->CNTu4 = 0;
return SCPE_OK;
}
@ -434,15 +444,32 @@ t_stat lpr_getlpp(FILE *st, UNIT *uptr, int32 v, CONST void *desc)
}
/* attach a file to the line printer device */
t_stat lpr_attach(UNIT * uptr, CONST char *file)
t_stat lpr_attach(UNIT *uptr, CONST char *file)
{
t_stat r;
t_stat r;
uint16 chsa = GET_UADDR(uptr->CMDu3); /* get address of lpr device */
DEVICE *dptr = get_dev(uptr); /* get device pointer */
DIB *dibp = 0;
if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r;
uptr->u3 &= ~(LPR_FULL|LPR_CMDMSK);
uptr->u4 = 0;
uptr->u5 = 0;
uptr->CMDu3 &= ~(LPR_FULL|LPR_CMDMSK);
uptr->CNTu4 = 0;
uptr->SNSu5 = 0;
/* check for valid configured lpr */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nLPR device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nLPR device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND); /* ready int???? */
return SCPE_OK;
}

22
SEL32/sel32_mfp.c
View File

@ -1,4 +1,4 @@
/* sel32_mfp.c: SEL-32 Model 8000/8001/8002 MFP processor controller
/* sel32_mfp.c: SEL-32 Model 8002 MFP processor controller
Copyright (c) 2018-2020, James C. Bevier
@ -125,8 +125,6 @@ DEVICE mfp_dev = {
NULL, NULL, NULL, /* boot, attach, detach */
/* dib ptr, dev flags, debug flags, debug */
&mfp_dib, DEV_CHAN|DEV_DIS|DEV_DISABLE|DEV_DEBUG, 0, dev_debug,
// NULL, NULL, &mfp_help, /* ?, ?, help */
// NULL, NULL, &mfp_desc /* ?, ?, description */
};
/* MFP controller routines */
@ -165,10 +163,8 @@ uint16 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
mfp_chp[0].chan_inch_addr); /* set inch buffer addr */
mfp_chp[0].chan_inch_addr = mfp_chp[0].ccw_addr; /* set inch buffer addr */
// set_inch(uptr, mfp_chp[0].ccw_addr); /* new address */
uptr->u3 |= MFP_INCH2; /* save INCH command as 0xf0 */
//@ sim_activate(uptr, 20); /* go on */
sim_activate(uptr, 40); /* go on */
return 0; /* no status change */
break;
@ -178,8 +174,7 @@ uint16 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & MFP_MSK); /* save NOP command */
sim_activate(uptr, 20); /* TRY 07-13-19 */
//@41 sim_activate(uptr, 40); /* TRY 07-13-19 */
sim_activate(uptr, 40); /* TRY 07-13-19 */
return 0; /* no status change */
break;
@ -188,8 +183,7 @@ uint16 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & MFP_MSK); /* save SID command */
sim_activate(uptr, 20); /* TRY 07-13-19 */
//@41 sim_activate(uptr, 40); /* TRY 07-13-19 */
sim_activate(uptr, 40); /* TRY 07-13-19 */
return 0; /* no status change */
break;
@ -199,8 +193,7 @@ uint16 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
chan, cmd, uptr->u5);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & MFP_MSK); /* save command */
sim_activate(uptr, 20); /* force interrupt */
//@41 sim_activate(uptr, 40); /* force interrupt */
sim_activate(uptr, 40); /* force interrupt */
return 0; /* no status change */
break;
}
@ -214,8 +207,6 @@ t_stat mfp_srv(UNIT *uptr)
uint16 chsa = GET_UADDR(uptr->u3);
int cmd = uptr->u3 & MFP_MSK;
CHANP *chp = &mfp_chp[0]; /* find the chanp pointer */
// int i;
// int len = chp->ccw_count; /* INCH command count */
uint32 mema = chp->ccw_addr; /* get inch or buffer addr */
/* test for NOP or INCH cmds */
@ -282,12 +273,9 @@ t_stat mfp_srv(UNIT *uptr)
/* the chp->ccw_addr location contains the inch address */
/* call set_inch() to setup inch buffer */
//FIXME add code to test return
// i = set_inch(uptr, mema); /* new address */
set_inch(uptr, mema); /* new address */
// chp->chan_inch_addr = mema; /* set inch buffer addr */
uptr->u3 &= LMASK; /* clear the cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
// chan_end(chsa, SNS_CHNEND); /* we are done dev|chan end */
}
return SCPE_OK;
}
@ -305,8 +293,6 @@ t_stat mfp_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, CONST char *cptr
fprintf(st, "The MFP fields all interrupts and status posting\r\n");
fprintf(st, "for each of the controllers on the system.\r\n");
fprintf(st, "Nothing can be configured for this Channel.\r\n");
// fprint_set_help(st, dptr);
// fprint_show_help(st, dptr);
return SCPE_OK;
}

196
SEL32/sel32_mt.c
View File

@ -165,7 +165,7 @@ uint8 mt_busy[NUM_DEVS_MT];
/* Gould Buffered Tape Processor (BTP) - Model 8051 */
/* Integrated channel controller */
/* Class F MT BTP I/O device status responce in IOCD address pointer location */
/* Class F MT BTP I/O device status response in IOCD address pointer location */
/* |-------+-------+-------+-------+-------+-------+-------+-------| */
/* |0 0 0 0|0 0 0 0|0 0 1 1|1 1 1 1|1 1 1 1|2 2 2 2|2 2 2 2|2 2 3 3| */
/* |0 1 2 3|4 5 6 7|8 9 0 1|2 3 4 5|6 7 8 9|0 1 2 3|4 5 6 7|8 9 3 1| */
@ -355,7 +355,6 @@ DEVICE mtb_dev = {
"MTB", mtb_unit, NULL, mt_mod,
NUM_UNITS_MT, 8, 15, 1, 8, 8,
NULL, NULL, &mt_reset, &mt_boot, &mt_attach, &mt_detach,
// &mtb_dib, DEV_BUF_NUM(1)|DEV_DIS|DEV_DISABLE|DEV_DEBUG|DEV_TAPE, 0, dev_debug
&mtb_dib, DEV_BUF_NUM(1)|DEV_DISABLE|DEV_DEBUG|DEV_TAPE, 0, dev_debug
NULL, NULL, &mt_help, NULL, NULL, &mt_description
};
@ -368,11 +367,6 @@ uint16 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
DEVICE *dptr = get_dev(uptr);
int unit = (uptr - dptr->units);
CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
#ifdef DO_NO_INT
int i;
uint8 ch;
uint16 len;
#endif
sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd entry chan %04x cmd %02x\n", chan, cmd);
if (mt_busy[GET_DEV_BUF(dptr->flags)] != 0 || (uptr->CMD & MT_CMDMSK) != 0) {
@ -387,10 +381,6 @@ uint16 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case 0x00: /* INCH command */
sim_debug(DEBUG_CMD, dptr, "start INCH command\n");
#ifdef DO_DYNAMIC_DEBUG
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
#endif
sim_debug(DEBUG_CMD, dptr,
"mt_startcmd starting INCH cmd, chsa %04x MemBuf %08x cnt %04x\n",
chsa, chp->ccw_addr, chp->ccw_count);
@ -434,16 +424,7 @@ uint16 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->SNS |= (SNS_EOT); /* tape at EOM */
/* Fall through */
#ifndef DO_NO_INT
case 0x04: /* Sense */
#endif
// case 0x80: /* Unknown diag cmd with byte cnt of 0x0c */
#ifdef DO_DYNAMIC_DEBUG
if ((cmd & 0xff) == 0x80) {
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
}
#endif
uptr->CMD &= ~(MT_CMDMSK); /* clear out last cmd */
uptr->CMD |= cmd & MT_CMDMSK; /* insert new cmd */
CLR_BUF(uptr); /* buffer is empty */
@ -452,49 +433,24 @@ uint16 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd sense %08x return 0 chan %04x cmd %02x\n",
uptr->SNS, chan, cmd);
sim_activate(uptr, 100); /* Start unit off */
//@41 sim_activate(uptr, 150); /* Start unit off */
return 0;
#ifdef DO_NO_INT
case 0x04: /* Sense */
/* write requested status */
len = chp->ccw_count; /* command count */
for (i=0; i<len; i++) {
ch = 0;
if (i<4)
ch = (uptr->SNS >> (24-(i*8))) & 0xff; /* get 8 bits of status */
chan_write_byte(chsa, &ch); /* write zero byte */
sim_debug(DEBUG_CMD, &mta_dev,
"sense unit %02x byte %1x %02x\n", unit, i, ch);
}
uptr->CMD &= ~MT_CMDMSK; /* clear the cmd */
sim_debug(DEBUG_CMD, &mta_dev, "mt_srv SENSE %08x char complete unit=%02x\n",
uptr->SNS, unit);
return SNS_CHNEND|SNS_DEVEND;
break;
#endif
default: /* invalid command */
sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd CMDREJ return chan %04x cmd %02x\n",
chan, cmd);
uptr->SNS |= SNS_CMDREJ;
#ifdef DO_DYNAMIC_DEBUG
if ((cmd & 0xff) == 0x80) {
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
}
#endif
/* send program check */
// return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK|STATUS_PCHK;
// return SNS_CHNEND|SNS_DEVEND|STATUS_PCHK;
return SNS_CHNEND|STATUS_PCHK;
break;
}
#if 0
/* not reached */
if (uptr->SNS & 0xff000000) /* errors? */
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK;
sim_debug(DEBUG_EXP, &mta_dev,
"mt_startcmd ret CHNEND|DEVEND chan %04x unit %04x cmd %02x\n", chan, unit, cmd);
return SNS_CHNEND|SNS_DEVEND;
#endif
}
/* Map simH errors into machine errors */
@ -505,7 +461,7 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr)
switch (r) { /* switch on return value */
case MTSE_OK: /* no error */
/*NEW*/ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
break;
case MTSE_TMK: /* tape mark */
@ -517,7 +473,7 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr)
case MTSE_WRP: /* write protected */
uptr->SNS |= SNS_WRP; /* write protected */
sim_debug(DEBUG_CMD, &mta_dev, "WRITE PROTECT %08x\n", r); /* operator intervention */
/*NEW*/ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
break;
case MTSE_UNATT: /* unattached */
@ -530,13 +486,13 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr)
case MTSE_FMT: /* invalid format */
case MTSE_RECE: /* error in record */
sim_debug(DEBUG_CMD, &mta_dev, "ERROR %08x\n", r);
/*NEW*/ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
break;
case MTSE_BOT: /* beginning of tape */
uptr->SNS |= SNS_LOAD; /* tape at BOT */
sim_debug(DEBUG_CMD, &mta_dev, "BOT\n");
/*NEW*/ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
break;
case MTSE_INVRL: /* invalid rec lnt */
@ -546,7 +502,6 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr)
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
break;
}
//WAS chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done with command */
return SCPE_OK;
}
@ -584,10 +539,6 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"mt_srv starting INCH %06x cmd, chsa %04x MemBuf %06x cnt %04x\n",
mema, addr, chp->ccw_addr, chp->ccw_count);
#ifdef DO_DYNAMIC_DEBUG
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
#endif
if (len == 0) {
/* we have invalid count, error, bail out */
@ -606,27 +557,10 @@ t_stat mt_srv(UNIT *uptr)
}
/* just dump data */
}
#ifdef CHANGE_FOR_UTX_BTP_TEST
/* a BTP uses a 41 word INCH memory buffer */
// for (i=0; i<41; i++) {
for (i=0; i<9; i++) {
int32 data = RMW(mema+(4*i)); /* get data word */
sim_debug(DEBUG_CMD, dptr,
"mt_srv INCH buffer addr %06x, wd %02x data %08x\n",
mema+(4*i), 4*i, data);
/* zero the data */
if (i == 8)
WMW(mema+(4*i),0x00050005); /* show we are a BTP */
else
WMW(mema+(4*i),0); /* zero work location */
}
#endif
/* the chp->ccw_addr location contains the inch address */
/* call set_inch() to setup inch buffer */
i = set_inch(uptr, mema); /* new address */
//FIXME - add back code?
#ifndef NOTYET
if ((i == SCPE_MEM) || (i == SCPE_ARG)) { /* any error */
/* we have error, bail out */
uptr->CMD &= ~(0xffff); /* remove old status bits & cmd */
@ -634,7 +568,6 @@ t_stat mt_srv(UNIT *uptr)
chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
#endif
/* set halfwords 16 & 17 to 5 as default retry count in inch data */
/* UTX uses this value to see if the device is a buffered tape processor */
/* they must be non-zero and equal to be BTP */
@ -648,7 +581,6 @@ t_stat mt_srv(UNIT *uptr)
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
break;
#ifndef FIX_DIAG
case 0x80: /* other? */ /* default to NOP */
sim_debug(DEBUG_CMD, &mta_dev, "mt_srv cmd 80 DIAG unit=%04x SNS %08x\n", unit, uptr->SNS);
ch = (uptr->SNS >> 24) & 0xff; /* get sense byte 0 status */
@ -663,7 +595,6 @@ t_stat mt_srv(UNIT *uptr)
ch = (uptr->SNS >> 0) & 0xff; /* get sense byte 3 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 3 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 3 */
#ifndef NO_HARDWARE_STATUS_FOR_DIAGS
/* write zero extra status */
for (ch=4; ch < 0xc; ch++) {
uint8 zc = 0;
@ -671,33 +602,6 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev,
"sense unit %02x byte %1x %02x\n", unit, ch, zc);
}
#else /* FOR UTX */
/* write status 2 more times */
ch = (uptr->SNS >> 24) & 0xff; /* get sense byte 0 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 0 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 0 */
ch = (uptr->SNS >> 16) & 0xff; /* get sense byte 1 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 1 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 1 */
ch = (uptr->SNS >> 8) & 0xff; /* get sense byte 2 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 2 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 2 */
ch = (uptr->SNS >> 0) & 0xff; /* get sense byte 3 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 3 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 3 */
ch = (uptr->SNS >> 24) & 0xff; /* get sense byte 0 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 0 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 0 */
ch = (uptr->SNS >> 16) & 0xff; /* get sense byte 1 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 1 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 1 */
ch = (uptr->SNS >> 8) & 0xff; /* get sense byte 2 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 2 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 2 */
ch = (uptr->SNS >> 0) & 0xff; /* get sense byte 3 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 3 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 3 */
#endif
uptr->CMD &= ~MT_CMDMSK; /* clear the cmd */
mt_busy[bufnum] &= ~1; /* make our buffer not busy */
sim_debug(DEBUG_CMD, &mta_dev, "mt_srv DIAG SNS %08x char complete unit=%02x\n",
@ -705,7 +609,6 @@ t_stat mt_srv(UNIT *uptr)
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
break;
#endif
case MT_NOP: /* 0x03 */ /* NOP motion command */
uptr->CMD &= ~MT_CMDMSK; /* clear the cmd */
mt_busy[bufnum] &= ~1; /* make our buffer not busy */
@ -773,7 +676,6 @@ t_stat mt_srv(UNIT *uptr)
/* Send dummy character to force SLI */
chan_write_byte(addr, &ch); /* write the byte */
sim_debug(DEBUG_CMD, &mta_dev, "Read unit %02x send dump SLI\n", unit);
//@41 sim_activate(uptr, (uptr->hwmark-uptr->POS) * 10); /* wait again */
sim_activate(uptr, (uptr->hwmark-uptr->POS) * 10); /* wait again */
uptr->CMD |= MT_READDONE; /* read is done */
break;
@ -793,19 +695,10 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev,
"Read too much data unit %02x cnt %04x ch %02x hwm %04x\n",
unit, uptr->POS, ch, uptr->hwmark);
#ifdef UTX_EOF_CHANGE
uptr->CMD &= ~MT_CMDMSK; /* clear the cmd */
mt_busy[bufnum] &= ~1; /* set not busy */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* return end status */
#else
// uptr->SNS |= SNS_OVRRUN; /* data overrun */
uptr->CMD |= MT_READDONE; /* read is done */
sim_activate(uptr, 20); /* wait again */
//@41 sim_activate(uptr, 40); /* wait again */
#endif
sim_activate(uptr, 40); /* wait again */
} else
sim_activate(uptr, 20); /* wait again */
//@41 sim_activate(uptr, 40); /* wait again */
sim_activate(uptr, 40); /* wait again */
}
break;
@ -830,8 +723,7 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x ch %02x\n",
unit, uptr->POS, ch);
uptr->hwmark = uptr->POS; /* set high water mark */
sim_activate(uptr, 20); /* wait time */
//@41 sim_activate(uptr, 40); /* wait again */
sim_activate(uptr, 40); /* wait time */
}
break;
@ -863,8 +755,7 @@ t_stat mt_srv(UNIT *uptr)
unit, uptr->POS, ch);
uptr->hwmark = uptr->POS;
}
sim_activate(uptr, 20);
//@41 sim_activate(uptr, 40);
sim_activate(uptr, 40);
break;
case MT_RDBK: /* 0x0C */ /* Read Backwards */
@ -900,7 +791,6 @@ t_stat mt_srv(UNIT *uptr)
unit, uptr->POS);
/* If not read whole record, skip till end */
if (uptr->POS >= 0) {
//@41 sim_activate(uptr, (uptr->POS) * 20);
sim_activate(uptr, (uptr->POS) * 20);
uptr->CMD |= MT_READDONE;
return SCPE_OK;
@ -916,8 +806,7 @@ t_stat mt_srv(UNIT *uptr)
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
} else
sim_activate(uptr, 20);
//@41 sim_activate(uptr, 40);
sim_activate(uptr, 40);
}
break;
@ -936,7 +825,7 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev, "Write Mark unit=%02x\n", unit);
uptr->CMD &= ~(MT_CMDMSK);
r = sim_tape_wrtmk(uptr);
chan_end(addr, SNS_DEVEND); //NEW chan_end(addr, SNS_CHNEND|SNS_DEVEND);
chan_end(addr, SNS_DEVEND);
mt_busy[bufnum] &= ~1;
}
break;
@ -954,7 +843,6 @@ t_stat mt_srv(UNIT *uptr)
}
uptr->POS++;
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
break;
case 1:
uptr->POS++;
@ -966,11 +854,9 @@ t_stat mt_srv(UNIT *uptr)
uptr->POS++;
sim_debug(DEBUG_CMD, &mta_dev, "MARK\n");
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "Backspace reclen %04x\n", reclen);
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
}
break;
case 2:
@ -1006,25 +892,22 @@ t_stat mt_srv(UNIT *uptr)
uptr->POS++;
sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n");
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else if (r == MTSE_BOT) {
uptr->POS+= 2;
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else {
sim_activate(uptr, 20);
//@41 sim_activate(uptr, 80);
}
break;
case 2: /* File Mark */
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_DEVEND); //NEW chan_end(addr, SNS_CHNEND|SNS_DEVEND);
chan_end(addr, SNS_DEVEND);
break;
case 3: /* BOT */
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_DEVEND); //NEW chan_end(addr, SNS_CHNEND|SNS_DEVEND);
chan_end(addr, SNS_DEVEND);
break;
}
break;
@ -1035,7 +918,6 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev, "Skip rec entry unit=%02x ", unit);
uptr->POS++;
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
break;
case 1:
uptr->POS++;
@ -1046,36 +928,32 @@ t_stat mt_srv(UNIT *uptr)
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
sim_debug(DEBUG_CMD, &mta_dev, "FSR MARK\n");
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else if (r == MTSE_EOM) {
uptr->POS = 4;
uptr->SNS |= SNS_EOT; /* set EOT status */
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "FSR skipped %04x byte record\n",
reclen);
sim_activate(uptr, 10 + (10 * reclen));
//@41 sim_activate(uptr, 10 + (10 * reclen));
}
break;
case 2:
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
sim_debug(DEBUG_CMD, &mta_dev, "Skip record Completed\n");
chan_end(addr, SNS_DEVEND); //NEW chan_end(addr, SNS_CHNEND|SNS_DEVEND);
chan_end(addr, SNS_DEVEND);
break;
case 3:
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOF\n");
chan_end(addr, SNS_DEVEND|SNS_UNITEXP); //NEW chan_end(addr, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP);
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
break;
case 4:
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOT\n");
//BAD chan_end(addr, SNS_DEVEND|SNS_UNITCHK);
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
break;
}
@ -1084,10 +962,10 @@ t_stat mt_srv(UNIT *uptr)
case MT_FSF: /* 0x63 */ /* advance filemark */
switch(uptr->POS) {
case 0:
sim_debug(DEBUG_CMD, &mta_dev, "Skip file entry sense %08x unit %02x\n", uptr->SNS, unit);
sim_debug(DEBUG_CMD, &mta_dev,
"Skip file entry sense %08x unit %02x\n", uptr->SNS, unit);
uptr->POS++;
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
break;
case 1:
sim_debug(DEBUG_CMD, &mta_dev, "Skip file unit=%02x\n", unit);
@ -1097,24 +975,22 @@ t_stat mt_srv(UNIT *uptr)
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
sim_debug(DEBUG_CMD, &mta_dev, "FSF EOF MARK sense %08x\n", uptr->SNS);
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else if (r == MTSE_EOM) {
uptr->SNS |= SNS_EOT; /* set EOT status */
sim_debug(DEBUG_CMD, &mta_dev, "FSF EOT sense %08x\n", uptr->SNS);
uptr->POS+= 2;
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "FSF skipped %04x byte record\n", reclen);
sim_activate(uptr, 50);
//@41 sim_activate(uptr, 80);
}
break;
case 2:
uptr->CMD &= ~(MT_CMDMSK);
mt_busy[bufnum] &= ~1;
uptr->SNS &= ~SNS_LOAD; /* reset BOT */
sim_debug(DEBUG_CMD, &mta_dev, "Skip file done sense %08x unit %02x\n", uptr->SNS, unit);
sim_debug(DEBUG_CMD, &mta_dev,
"Skip file done sense %08x unit %02x\n", uptr->SNS, unit);
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */
break;
case 3:
@ -1122,9 +998,8 @@ t_stat mt_srv(UNIT *uptr)
uptr->SNS &= ~SNS_LOAD; /* reset BOT */
uptr->SNS |= SNS_EOT; /* set EOT status */
mt_busy[bufnum] &= ~1;
sim_debug(DEBUG_CMD, &mta_dev, "Skip file got EOT sense %08x unit %02x\n", uptr->SNS, unit);
//BAD chan_end(addr, SNS_DEVEND|SNS_UNITCHK);
//*##*/ chan_end(addr, SNS_DEVEND|SNS_UNITCHK);
sim_debug(DEBUG_CMD, &mta_dev,
"Skip file got EOT sense %08x unit %02x\n", uptr->SNS, unit);
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
break;
}
@ -1137,12 +1012,10 @@ t_stat mt_srv(UNIT *uptr)
uptr->SNS |= SNS_CMDREJ;
uptr->CMD &= ~MT_CMDMSK;
mt_busy[bufnum] &= ~1;
//BAD chan_end(addr, SNS_DEVEND|SNS_UNITCHK);
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
} else {
uptr->POS ++;
sim_activate(uptr, 500);
//@41 sim_activate(uptr, 200);
}
break;
case 1:
@ -1216,8 +1089,10 @@ t_stat mt_reset(DEVICE *dptr)
/* attach the specified file to the tape device */
t_stat mt_attach(UNIT *uptr, CONST char *file)
{
uint16 addr = GET_UADDR(uptr->CMD); /* get address of mt device */
t_stat r;
uint16 chsa = GET_UADDR(uptr->CMD); /* get address of mt device */
DEVICE *dptr = get_dev(uptr); /* get device pointer */
t_stat r;
DIB *dibp = 0;
/* mount the specified file to the MT */
if ((r = sim_tape_attach(uptr, file)) != SCPE_OK) {
@ -1228,7 +1103,20 @@ t_stat mt_attach(UNIT *uptr, CONST char *file)
uptr->CMD &= ~0xffff; /* clear out the flags but leave ch/sa */
uptr->POS = 0; /* clear position data */
uptr->SNS = 0; /* clear sense data */
set_devattn(addr, SNS_DEVEND); /* ready int???? */
/* check for valid configured tape */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nMT device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nMT device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND); /* ready int???? */
return SCPE_OK; /* return good status */
}

39
SEL32/sel32_scfi.c
View File

@ -223,7 +223,7 @@ scfi_type[] =
/* Class F Disc Devices */
/* MPX SCSI disks for SCFI controller */
{"MH1GB", 1, 192, 40, 34960, 34960, 0x40}, /*0 69920 1000M */
{"SG038", 1, 192, 20, 2190, 2190, 0x40}, /*1 21900 38M */
{"SG038", 1, 192, 20, 21900, 21900, 0x40}, /*1 21900 38M */
{"SG120", 1, 192, 40, 34970, 34970, 0x40}, /*2 69940 1200M */
{"SG076", 1, 192, 20, 46725, 46725, 0x40}, /*3 46725 760M */
{NULL, 0}
@ -550,11 +550,7 @@ t_stat scfi_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"scfi_srv cmd INCH chsa %04x addr %06x count %04x completed\n",
chsa, mema, chp->ccw_count);
#ifdef FIX4MPX
chan_end(chsa, SNS_CHNEND); /* return just channel end OK */
#else
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
#endif
}
break;
@ -746,7 +742,6 @@ rezero:
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
/* read in a sector of data from disk */
@ -783,8 +778,7 @@ rezero:
tstart++; /* bump to next sector */
/* convert sect back to chs value */
uptr->CHS = scfisec2star(tstart, type);
/* see of over end of disk */
// if (tstart >= CAPB(type)) {
/* see if over end of disk */
if (tstart >= CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -830,7 +824,6 @@ rddone:
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
/* process the next sector of data */
@ -877,8 +870,7 @@ rddone:
tstart++; /* bump to next sector */
/* convert sect back to chs value */
uptr->CHS = scfisec2star(tstart, type);
/* see of over end of disk */
// if (tstart >= CAPB(type)) {
/* see if over end of disk */
if (tstart >= CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr,
@ -900,7 +892,6 @@ wrdone:
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
uptr->SNS |= SNS_CMDREJ;
uptr->CMD &= ~(0xffff); /* remove old status bits & cmd */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SNS_CHNEND|STATUS_PCHK;
break;
}
@ -932,7 +923,6 @@ t_stat scfi_reset(DEVICE * dptr)
/* create the disk file for the specified device */
int scfi_format(UNIT *uptr) {
// struct ddata_t *data = (struct ddata_t *)uptr->up7;
uint16 addr = GET_UADDR(uptr->CMD);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
@ -940,7 +930,6 @@ int scfi_format(UNIT *uptr) {
uint32 tsize = scfi_type[type].spt; /* get track size in sectors */
uint32 csize = scfi_type[type].nhds * tsize; /* get cylinder size in sectors */
uint32 cyl = scfi_type[type].cyl; /* get # cyl */
// uint16 spc = scfi_type[type].nhds * scfi_type[type].spt; /* sectors/cyl */
uint32 cap = scfi_type[type].cyl * csize; /* disk capacity in sectors */
uint32 cylv = cyl; /* number of cylinders */
uint8 *buff;
@ -992,15 +981,15 @@ int scfi_format(UNIT *uptr) {
return 1;
}
free(buff); /* free cylinder buffer */
set_devattn(addr, SNS_DEVEND); /* start us up */
return 0;
}
/* attach the selected file to the disk */
t_stat scfi_attach(UNIT *uptr, CONST char *file) {
uint16 addr = GET_UADDR(uptr->CMD);
uint16 chsa = GET_UADDR(uptr->CMD);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
DIB *dibp = 0;
t_stat r;
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
@ -1060,7 +1049,19 @@ fmt:
sim_debug(DEBUG_CMD, &sda_dev, "File %s attached to %s\r\n",
file, scfi_type[type].name);
set_devattn(addr, SNS_DEVEND);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nSCFI device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nSCFI device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND);
return SCPE_OK;
}
@ -1118,8 +1119,7 @@ t_stat scfi_get_type(FILE * st, UNIT *uptr, int32 v, CONST void *desc)
}
/* help information for disk */
t_stat scfi_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
const char *cptr)
t_stat scfi_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
int i;
fprintf (st, "SEL-32 SCFI Disk Processor\r\n");
@ -1148,5 +1148,4 @@ const char *scfi_description (DEVICE *dptr)
{
return "SEL-32 SCFI Disk Processor";
}
#endif

52
SEL32/sel32_scsi.c
View File

@ -524,7 +524,6 @@ t_stat scsi_srv(UNIT *uptr)
CHANP *chp = (CHANP *)dibp->chan_prg; /* get pointer to channel program */
int cmd = uptr->CMD & DSK_CMDMSK;
int type = GET_TYPE(uptr->flags);
// uint32 trk, cyl, sec;
int unit = (uptr - dptr->units);
int bufnum = GET_DEV_BUF(dptr->flags);
int len=0;
@ -556,9 +555,6 @@ t_stat scsi_srv(UNIT *uptr)
case DSK_INCH2: /* use 0xF0 for inch, just need int */
{
uint32 mema; /* memory address */
// uint32 daws[8]; /* drive attribute registers */
// uint32 i, j;
// uint32 i;
len = chp->ccw_count; /* INCH command count */
mema = chp->ccw_addr; /* get inch or buffer addr */
@ -588,9 +584,6 @@ t_stat scsi_srv(UNIT *uptr)
"scsi_srv cmd INCH chsa %04x addr %06x count %04x completed\n",
chsa, mema, chp->ccw_count);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
#ifdef DO_DYNAMIC_DEBUG
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
#endif
}
break;
@ -763,7 +756,6 @@ t_stat scsi_srv(UNIT *uptr)
/* calculate file position in bytes of requested sector */
/* file offset in bytes */
tstart = uptr->STAR * SSB(type);
// uptr->CHS = uptr->STAR;
sim_debug(DEBUG_DETAIL, dptr,
"scsi_srv seek start %04x sector %06x\n",
@ -1075,8 +1067,6 @@ t_stat scsi_srv(UNIT *uptr)
case DSK_TCMD: /* Transfer command packet 0xD3 */
{
uint32 mema; /* memory address */
// uint32 daws[8]; /* drive attribute registers */
// uint32 i, j;
int32 i;
uptr->SNS &= ~SNS_TCMD; /* show not presessing TCMD cmd chain */
@ -1093,11 +1083,11 @@ t_stat scsi_srv(UNIT *uptr)
#ifdef NOTNOW
if (len != 36) {
/* we have invalid count, error, bail out */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
/* we have invalid count, error, bail out */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
#endif
@ -1135,7 +1125,6 @@ t_stat scsi_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
uptr->SNS |= SNS_CMDREJ;
uptr->CMD &= LMASK; /* remove old status bits & cmd */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SNS_CHNEND|STATUS_PCHK;
break;
}
@ -1195,18 +1184,14 @@ int scsi_format(UNIT *uptr) {
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
//WASint32 daddr = vaddr - SPT(type);
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* get sector address of utx flaw data (1 track long) */
/* set trace data to zero */
//WASint32 faddr = daddr - SPT(type);
int32 faddr = (CYL(type)-4) * SPC(type) + (HDS(type)-3) * SPT(type);
/* get sector address of utx flaw map sec 1 pointer */
/* use this address for sec 1 label pointer */
//WASint32 uaddr = daddr - SPT(type);
//WASint32 uaddr = daddr - (2*SPT(type));
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-4) * SPT(type);
/* last user block available */
@ -1242,12 +1227,10 @@ int scsi_format(UNIT *uptr) {
/* defect map */
uint32 dmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | (cap-1), 0xf4000000};
//TRY 0x9a000000 | (cap-1), 0xf4000008};
/* utx flaw map */
uint32 fmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | ltaddr, 0xf4000000};
//TRY 0x9a000000 | ltaddr, 0xf4000008};
/* see if user wants to initialize the disk */
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
@ -1412,9 +1395,10 @@ int scsi_format(UNIT *uptr) {
/* attach the selected file to the disk */
t_stat scsi_attach(UNIT *uptr, CONST char *file) {
uint16 addr = GET_UADDR(uptr->CMD);
uint16 chsa = GET_UADDR(uptr->CMD);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
DIB *dibp = 0;
t_stat r;
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
@ -1432,7 +1416,7 @@ t_stat scsi_attach(UNIT *uptr, CONST char *file) {
ssize = SSB(type); /* get sector size in bytes */
sim_debug(DEBUG_CMD, dptr, "Disk %s %04x cyl %d hds %d sec %d ssiz %d capacity %d\n",
scsi_type[type].name, addr, scsi_type[type].cyl, scsi_type[type].nhds,
scsi_type[type].name, chsa, scsi_type[type].cyl, scsi_type[type].nhds,
scsi_type[type].spt, ssize, uptr->capac); /* disk capacity */
@ -1468,13 +1452,25 @@ fmt:
sim_debug(DEBUG_CMD, dptr,
"Attach %s %04x cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\n",
scsi_type[type].name, addr, CYL(type), HDS(type), SPT(type), SPC(type),
scsi_type[type].name, chsa, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
sim_debug(DEBUG_CMD, dptr, "File %s at addr %04x attached to %s\r\n",
file, addr, scsi_type[type].name);
sim_debug(DEBUG_CMD, dptr, "File %s at chsa %04x attached to %s\r\n",
file, chsa, scsi_type[type].name);
set_devattn(addr, SNS_DEVEND);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nSCSI device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nSCSI device %s not configured on system, aborting\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */
}
set_devattn(chsa, SNS_DEVEND);
return SCPE_OK;
}

8
SEL32/sel32_sys.c
View File

@ -668,7 +668,6 @@ t_opcode optab[] = {
{ 0x2C0E, 0xFC0F, H|TYPE_F, "TRSC", }, /* Transfer Register to Scratchpad # * */
{ 0x2C0F, 0xFC0F, H|TYPE_F, "TSCR", }, /* Transfer Scratchpad to Register # * */
{ 0x3000, 0xFC0F, X|H|TYPE_F, "CALM", }, /* Call Monitor 32/55 # */
//FF{ 0x3400, 0xFC08, N|TYPE_D, "LA", }, /* Load Address NBR Note! FW instruction */
{ 0x3400, 0xFC00, N|TYPE_D, "LA", }, /* Load Address NBR Note! FW instruction */
{ 0x3800, 0xFC0F, H|TYPE_F, "ADR", }, /* Add Register to Register # */
{ 0x3801, 0xFC0F, H|TYPE_F, "ADRFW", }, /* Add Floating Point to Register # */
@ -873,7 +872,6 @@ int fprint_inst(FILE *of, uint32 val, int32 sw)
fputc(' ', of);
if (mode) {
/* base reg mode */
//UTX fprint_val(of, val&0xffff, 16, 16, PV_RZRO); /* output 16 bit offset */
fprint_val(of, val&0xffff, 16, 16, PV_LEFT); /* output 16 bit offset */
if (inst & 07) {
fputc('(', of);
@ -881,8 +879,6 @@ int fprint_inst(FILE *of, uint32 val, int32 sw)
fputc(('0'+(inst & 07)), of); /* output the base reg number */
fputc(')', of);
}
// if (inst & 0x70) {
// if ((inst & 0x70) && (tab->type != TYPE_D)) {
if (inst & 0x70) {
fputc(',', of);
// fputc('R', of);
@ -1029,8 +1025,8 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
rdx = 16; /* hex */
if (sw & SWMASK ('M')) { /* machine base mode? */
// sw &= ~ SWMASK('F'); /* Can't do F and M at same time */
// sw &= ~ SWMASK('W'); /* Can't do W and M at same time */
// sw &= ~ SWMASK('F'); /* Can't do F and M at same time */
// sw &= ~ SWMASK('W'); /* Can't do W and M at same time */
sw &= ~ SWMASK('B'); /* Can't do B and M at same time */
sw &= ~ SWMASK('C'); /* Can't do C and M at same time */
if (addr & 0x02)

6
SEL32/tests/diag.ini
View File

@ -187,6 +187,10 @@ set cpu idle
;bo dma0
;
; Go to simh on completion of script
expect "DOL>"^M
expect "DOL>"
; Boot from mag tape
bo mta0
det all
;rm temptape.tap
;rm output.tap
quit