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KA10: Fix KL10 ITS to work.
This commit is contained in:
Richard Cornwell
parent
5e2d18cfdd
commit
280432b0d1
@ -131,7 +131,6 @@ int uuo_cycle; /* Uuo cycle in progress */
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int SC; /* Shift count */
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int SCAD; /* Shift count extension */
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int FE; /* Exponent */
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uint32 max_dev; /* Max dev number */
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#if KA | PDP6
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t_addr Pl, Ph, Rl, Rh, Pflag; /* Protection registers */
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int push_ovf; /* Push stack overflow */
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@ -280,7 +279,6 @@ int watch_stop; /* Stop at memory watch point */
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int maoff = 0; /* Offset for traps */
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uint16 dev_irq[128]; /* Pending irq by device */
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uint8 dev_map[128]; /* Map device to irq slot */
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t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
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t_addr (*dev_irqv[128])(uint32 dev, t_addr addr);
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t_stat rtc_srv(UNIT * uptr);
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@ -980,6 +978,11 @@ int opflags[] = {
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#else
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#define QSLAVE 0
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#endif
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#if KS
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#define MAX_DEV 16
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#else
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#define MAX_DEV 128
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#endif
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#if KL
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struct _byte {
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@ -1078,7 +1081,7 @@ void set_interrupt(int dev, int lvl) {
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#if KS
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dev_irq[dev>>2] |= 0200 >> lvl;
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#else
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dev_irq[dev_map[dev>>2]] = 0200 >> lvl;
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dev_irq[dev>>2] = 0200 >> lvl;
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#endif
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pi_pending = 1;
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sim_debug(DEBUG_IRQ, &cpu_dev, "set irq %o %o %03o %03o %03o\n",
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@ -1090,9 +1093,9 @@ void set_interrupt(int dev, int lvl) {
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void set_interrupt_mpx(int dev, int lvl, int mpx) {
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lvl &= 07;
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if (lvl) {
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dev_irq[dev_map[dev>>2]] = 0200 >> lvl;
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dev_irq[dev>>2] = 0200 >> lvl;
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if (lvl == 1 && mpx != 0)
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dev_irq[dev_map[dev>>2]] |= mpx << 8;
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dev_irq[dev>>2] |= mpx << 8;
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pi_pending = 1;
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sim_debug(DEBUG_IRQ, &cpu_dev, "set mpx irq %o %o %o %03o %03o %03o\n",
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dev & 0774, lvl, mpx, PIE, PIR, PIH);
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@ -1104,7 +1107,7 @@ void set_interrupt_mpx(int dev, int lvl, int mpx) {
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* Clear the interrupt flag for a device
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*/
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void clr_interrupt(int dev) {
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dev_irq[dev_map[dev>>2]] = 0;
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dev_irq[dev>>2] = 0;
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if (dev > 4)
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sim_debug(DEBUG_IRQ, &cpu_dev, "clear irq %o\n", dev & 0774);
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}
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@ -1139,7 +1142,7 @@ int check_irq_level() {
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}
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/* Scan all devices */
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for(i = lvl = 0; i < (int)max_dev; i++)
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for(i = lvl = 0; i < MAX_DEV; i++)
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lvl |= dev_irq[i];
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if (lvl == 0)
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pi_pending = 0;
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@ -1149,7 +1152,7 @@ int check_irq_level() {
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if (mpx_enable && cpu_unit[0].flags & UNIT_MPX &&
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(pi_req & 0100) && (PIH & 0100) == 0) {
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pi_enc = 010;
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for(i = lvl = 0; i < (int)max_dev; i++) {
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for(i = lvl = 0; i < MAX_DEV; i++) {
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if (dev_irq[i] & 0100) {
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int l = dev_irq[i] >> 8;
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if (l != 0 && l < pi_enc)
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@ -2938,7 +2941,7 @@ int page_lookup(t_addr addr, int flag, t_addr *loc, int wr, int cur_context, int
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/*
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* Register access on KL 10
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*/
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#if 0
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#if 1
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uint64 get_reg(int reg) {
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return FM[fm_sel|(reg & 017)];
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}
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@ -2946,9 +2949,10 @@ uint64 get_reg(int reg) {
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void set_reg(int reg, uint64 value) {
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FM[fm_sel|(reg & 017)] = value;
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}
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#endif
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#else
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#define get_reg(reg) FM[fm_sel|((reg) & 017)]
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#define set_reg(reg, value) FM[fm_sel|((reg) & 017)] = (value)
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#endif
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int Mem_read(int flag, int cur_context, int fetch) {
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t_addr addr;
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@ -4625,20 +4629,20 @@ no_fetch:
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}
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#endif
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if ((!pi_cycle) & pi_pending
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#if KI | KL | KS
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& (!trap_flag)
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#endif
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) {
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pi_rq = check_irq_level();
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}
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/* Handle indirection repeat until no longer indirect */
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do {
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ind = TST_IND(MB) != 0;
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AR = MB;
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AB = MB & RMASK;
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ix = GET_XR(MB);
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if (ix) {
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if ((!pi_cycle) & pi_pending
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#if KI | KL | KS
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& (!trap_flag)
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#endif
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) {
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pi_rq = check_irq_level();
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}
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ind = TST_IND(MB) != 0;
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AR = MB;
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AB = MB & RMASK;
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ix = GET_XR(MB);
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if (ix) {
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#if KL | KS
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if (((xct_flag & 8) != 0 && !ptr_flg) ||
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((xct_flag & 2) != 0 && ptr_flg))
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@ -4745,15 +4749,16 @@ in_loop:
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ind = 0;
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}
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#endif
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/* Handle events during a indirect loop */
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AIO_CHECK_EVENT; /* queue async events */
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if (sim_interval <= 0) {
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if ((reason = sim_process_event()) != SCPE_OK) {
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return reason;
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}
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}
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}
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/* Handle events during a indirect loop */
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AIO_CHECK_EVENT; /* queue async events */
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if (--sim_interval <= 0) {
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if ((reason = sim_process_event()) != SCPE_OK) {
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return reason;
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}
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}
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#if 0
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if ((!pi_cycle) & pi_pending
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#if KI | KL | KS
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& (!trap_flag)
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@ -4761,6 +4766,7 @@ in_loop:
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) {
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pi_rq = check_irq_level();
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}
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#endif
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} while (ind & !pi_rq);
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/* If there is a interrupt handle it. */
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@ -4801,11 +4807,11 @@ st_pi:
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* Scan through the devices and allow KI devices to have first
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* hit at a given level.
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*/
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for (f = 0; f < 128; f++) {
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if (dev_irqv[f] != 0 && dev_irq[dev_map[f]] & pi_mask) {
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for (f = 0; f < MAX_DEV; f++) {
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if (dev_irqv[f] != 0 && dev_irq[f] & pi_mask) {
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AB = dev_irqv[f](f << 2, AB);
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sim_debug(DEBUG_IRQ, &cpu_dev, "vect irq %o %03o %06o\n",
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pi_enc, dev_irq[dev_map[f]], AB);
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pi_enc, dev_irq[f], AB);
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break;
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}
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}
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@ -5999,7 +6005,7 @@ dpnorm:
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#if KL | KS
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MQ = get_reg(AC + 1);
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#endif
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#if KL | KS
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#if KS
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IA = AB;
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AB = (AB + 1) & RMASK;
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modify = 1;
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@ -6054,7 +6060,7 @@ dpnorm:
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FLAGS |= TRP1;
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#endif
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}
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#if KL | KS
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#if KS
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IA = AB;
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modify = 1;
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AB = (AB + 1) & RMASK;
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@ -6628,12 +6634,10 @@ ldb_ptr:
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}
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#endif
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} else {
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#if KL
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#if KL | KS
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ptr_flg = 0;
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ld_exe:
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#endif
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BYF5 = 1;
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#if KA | KL | KI
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#else
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if ((IR & 06) == 6)
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modify = 1;
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#endif
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@ -11797,13 +11801,11 @@ sect = cur_sect = pc_sect = 0;
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#if BBN
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exec_map = 0;
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#endif
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for(i=0; i < 128; dev_irq[i++] = 0);
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#if KS
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int_cur = int_val = 0;
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max_dev = 16;
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#endif
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for(i=0; i < 128; dev_irq[i++] = 0);
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for(i=0; i < 128; dev_map[i++] = 0);
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sim_brk_types = SWMASK('E') | SWMASK('W') | SWMASK('R');
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sim_brk_dflt = SWMASK ('E');
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sim_clock_precalibrate_commands = pdp10_clock_precalibrate_commands;
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@ -11968,31 +11970,23 @@ t_bool build_dev_tab (void)
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for (i = 0; i < 128; i++) {
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dev_tab[i] = &null_dev;
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dev_irqv[i] = NULL;
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dev_map[i] = 0;
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}
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/* Set up basic devices. */
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dev_tab[0] = &dev_apr;
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dev_tab[1] = &dev_pi;
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max_dev = 2;
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#if KI | KL
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dev_tab[2] = &dev_pag;
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max_dev++;
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#if KL
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dev_tab[3] = &dev_cca;
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dev_tab[4] = &dev_tim;
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dev_irqv[4] = &tim_irq;
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dev_tab[5] = &dev_mtr;
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max_dev+=3;
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#endif
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#endif
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for (i = 0; i < max_dev; i++) {
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dev_map[i] = i;
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}
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#if BBN
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if (QBBN) {
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dev_tab[024>>2] = &dev_pag;
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dev_map[024>>2] = max_dev++;
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}
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#endif
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@ -12029,7 +12023,6 @@ t_bool build_dev_tab (void)
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#endif
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}
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dev_tab[(d >> 2)] = dibp->io;
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dev_map[(d >> 2)] = max_dev++;
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dev_irqv[(d >> 2)] = dibp->irq;
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rh[rh_idx].dev_num = d;
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rh[rh_idx].dev = dptr;
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@ -12056,7 +12049,6 @@ t_bool build_dev_tab (void)
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return TRUE;
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}
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dev_tab[(d >> 2) + j] = dibp->io; /* fill */
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dev_map[(d >> 2) + j] = max_dev++;
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dev_irqv[(d >> 2) + j] = dibp->irq;
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}
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}
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247
PDP10/kx10_rp.c
247
PDP10/kx10_rp.c
@ -319,28 +319,16 @@ UNIT rp_unit[] = {
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struct rh_if rp_rh[NUM_DEVS_RP] = {
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{ &rp_write, &rp_read, &rp_rst},
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#if (NUM_DEVS_RP > 1)
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{ &rp_write, &rp_read, &rp_rst},
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#if (NUM_DEVS_RP > 2)
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{ &rp_write, &rp_read, &rp_rst},
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#if (NUM_DEVS_RP > 3)
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{ &rp_write, &rp_read, &rp_rst}
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#endif
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#endif
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#endif
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};
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DIB rp_dib[] = {
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{RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[0]},
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#if (NUM_DEVS_RP > 1)
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{RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[1]},
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#if (NUM_DEVS_RP > 2)
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{RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[2]},
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#if (NUM_DEVS_RP > 3)
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{RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[3]}};
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#endif
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#endif
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#endif
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MTAB rp_mod[] = {
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@ -474,7 +462,6 @@ DEVICE rpd_dev = {
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#endif
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#endif
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#if 0
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DEVICE *rp_devs[] = {
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&rpa_dev,
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#if (NUM_DEVS_RP > 1)
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@ -487,7 +474,7 @@ DEVICE *rp_devs[] = {
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#endif
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#endif
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};
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#endif
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void
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rp_rst(DEVICE *dptr)
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@ -757,7 +744,7 @@ t_stat rp_svc (UNIT *uptr)
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int diff, da;
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int sts;
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dptr = uptr->dptr;
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dptr = rp_devs[ctlr];
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rhc = &rp_rh[ctlr];
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unit = uptr - dptr->units;
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if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
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@ -852,70 +839,70 @@ t_stat rp_svc (UNIT *uptr)
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goto rd_end;
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}
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if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect ||
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GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
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uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
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uptr->CMD &= ~CS1_GO;
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rh_finish_op(rhc, 0);
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sim_debug(DEBUG_DETAIL, dptr, "%s%o readx done\n", dptr->name, unit);
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return SCPE_OK;
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}
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sim_debug(DEBUG_DETAIL, dptr, "%s%o read (%d,%d,%d)\n", dptr->name, unit, cyl,
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GET_SF(uptr->DA), GET_SC(uptr->DA));
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da = GET_DA(uptr->DA, dtype);
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(void)disk_read(uptr, &rp_buf[ctlr][0], da, RP_NUMWD);
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uptr->hwmark = RP_NUMWD;
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uptr->DATAPTR = 0;
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sts = 1;
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/* On read headers, transfer 2 words to start */
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if (GET_FNC(uptr->CMD) == FNC_READH) {
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rhc->buf = (((uint64)cyl) << 18) |
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((uint64)((GET_SF(uptr->DA) << 8) | GET_SF(uptr->DA)));
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sim_debug(DEBUG_DATA, dptr, "%s%o read word h1 %012llo %09o %06o\n",
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dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr);
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if ((sts = rh_write(rhc)) == 0)
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goto rd_end;
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rhc->buf = ((uint64)((020 * ctlr) + (unit + 1)) << 18) | (uint64)(unit);
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sim_debug(DEBUG_DATA, dptr, "%s%o read word h2 %012llo %09o %06o\n",
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dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr);
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if ((sts = rh_write(rhc)) == 0)
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goto rd_end;
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}
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while (uptr->DATAPTR < RP_NUMWD && sts != 0) {
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rhc->buf = rp_buf[ctlr][uptr->DATAPTR++];
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sim_debug(DEBUG_DATA, dptr, "%s%o read word %d %012llo %09o %06o\n",
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dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr);
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sts = rh_write(rhc);
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}
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if (sts) {
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/* Increment to next sector. Set Last Sector */
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uptr->DATAPTR = 0;
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CLR_BUF(uptr);
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uptr->DA += 1 << DA_V_SC;
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if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect) {
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uptr->DA &= (DA_M_SF << DA_V_SF) | (DC_M_CY << DC_V_CY);
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uptr->DA += 1 << DA_V_SF;
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if (GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
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uptr->DA &= (DC_M_CY << DC_V_CY);
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uptr->DA += 1 << DC_V_CY;
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uptr->CMD |= DS_PIP;
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}
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if (BUF_EMPTY(uptr)) {
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if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect ||
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GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
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uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
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uptr->CMD &= ~CS1_GO;
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rh_finish_op(rhc, 0);
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sim_debug(DEBUG_DETAIL, dptr, "%s%o readx done\n", dptr->name, unit);
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return SCPE_OK;
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}
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if (rh_blkend(rhc))
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goto rd_end;
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sim_activate(uptr, 100);
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sim_debug(DEBUG_DETAIL, dptr, "%s%o read (%d,%d,%d)\n", dptr->name, unit, cyl,
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GET_SF(uptr->DA), GET_SC(uptr->DA));
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da = GET_DA(uptr->DA, dtype);
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(void)disk_read(uptr, &rp_buf[ctlr][0], da, RP_NUMWD);
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uptr->hwmark = RP_NUMWD;
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uptr->DATAPTR = 0;
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/* On read headers, transfer 2 words to start */
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if (GET_FNC(uptr->CMD) == FNC_READH) {
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rhc->buf = (((uint64)cyl) << 18) |
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((uint64)((GET_SF(uptr->DA) << 8) | GET_SF(uptr->DA)));
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sim_debug(DEBUG_DATA, dptr, "%s%o read word h1 %012llo %09o %06o\n",
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dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr);
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if (rh_write(rhc) == 0)
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goto rd_end;
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rhc->buf = ((uint64)((020 * ctlr) + (unit + 1)) << 18) | (uint64)(unit);
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sim_debug(DEBUG_DATA, dptr, "%s%o read word h2 %012llo %09o %06o\n",
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dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr);
|
||||
if (rh_write(rhc) == 0)
|
||||
goto rd_end;
|
||||
}
|
||||
}
|
||||
|
||||
rhc->buf = rp_buf[ctlr][uptr->DATAPTR++];
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o read word %d %012llo %09o %06o\n",
|
||||
dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr);
|
||||
if (rh_write(rhc)) {
|
||||
if (uptr->DATAPTR == RP_NUMWD) {
|
||||
/* Increment to next sector. Set Last Sector */
|
||||
uptr->DATAPTR = 0;
|
||||
CLR_BUF(uptr);
|
||||
uptr->DA += 1 << DA_V_SC;
|
||||
if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect) {
|
||||
uptr->DA &= (DA_M_SF << DA_V_SF) | (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DA_V_SF;
|
||||
if (GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
|
||||
uptr->DA &= (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DC_V_CY;
|
||||
uptr->CMD |= DS_PIP;
|
||||
}
|
||||
}
|
||||
if (rh_blkend(rhc))
|
||||
goto rd_end;
|
||||
}
|
||||
sim_activate(uptr, 10);
|
||||
} else {
|
||||
rd_end:
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o read done\n", dptr->name, unit);
|
||||
uptr->CMD |= DS_DRY;
|
||||
uptr->CMD &= ~CS1_GO;
|
||||
if (uptr->DATAPTR == RP_NUMWD)
|
||||
(void)rh_blkend(rhc);
|
||||
rh_finish_op(rhc, 0);
|
||||
return SCPE_OK;
|
||||
}
|
||||
rd_end:
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o read done\n", dptr->name, unit);
|
||||
uptr->CMD |= DS_DRY;
|
||||
uptr->CMD &= ~CS1_GO;
|
||||
if (sts == 0)
|
||||
(void)rh_blkend(rhc);
|
||||
rh_finish_op(rhc, 0);
|
||||
return SCPE_OK;
|
||||
break;
|
||||
|
||||
case FNC_WRITE: /* write */
|
||||
case FNC_WRITEH: /* write w/ headers */
|
||||
@ -924,68 +911,70 @@ rd_end:
|
||||
goto wr_end;
|
||||
}
|
||||
|
||||
if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect ||
|
||||
GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
|
||||
uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
|
||||
uptr->CMD &= ~CS1_GO;
|
||||
rh_finish_op(rhc, 0);
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o writex done\n", dptr->name, unit);
|
||||
return SCPE_OK;
|
||||
}
|
||||
sts = 1;
|
||||
/* On Write headers, transfer 2 words to start */
|
||||
if (GET_FNC(uptr->CMD) == FNC_WRITEH) {
|
||||
if ((sts = rh_read(rhc)) == 0)
|
||||
goto wr_end;
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word h1 %012llo %06o\n",
|
||||
dptr->name, unit, rhc->buf, rhc->wcr);
|
||||
if ((sts = rh_read(rhc)) == 0)
|
||||
goto wr_end;
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word h2 %012llo %06o\n",
|
||||
dptr->name, unit, rhc->buf, rhc->wcr);
|
||||
}
|
||||
uptr->DATAPTR = 0;
|
||||
uptr->hwmark = 0;
|
||||
rhc->buf = 0;
|
||||
while (uptr->DATAPTR < RP_NUMWD && (sts = rh_read(rhc)) != 0) {
|
||||
rp_buf[ctlr][uptr->DATAPTR++] = rhc->buf;
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word %d %012llo %06o %06o\n",
|
||||
dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr);
|
||||
}
|
||||
rp_buf[ctlr][uptr->DATAPTR++] = rhc->buf;
|
||||
while (uptr->DATAPTR < RP_NUMWD) {
|
||||
rp_buf[ctlr][uptr->DATAPTR++] = 0;
|
||||
}
|
||||
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o write (%d,%d,%d)\n", dptr->name,
|
||||
unit, cyl, GET_SF(uptr->DA), GET_SC(uptr->DA));
|
||||
da = GET_DA(uptr->DA, dtype);
|
||||
(void)disk_write(uptr, &rp_buf[ctlr][0], da, RP_NUMWD);
|
||||
uptr->DATAPTR = 0;
|
||||
CLR_BUF(uptr);
|
||||
uptr->DA += 1 << DA_V_SC;
|
||||
if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect) {
|
||||
uptr->DA &= (DA_M_SF << DA_V_SF) | (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DA_V_SF;
|
||||
if (GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
|
||||
uptr->DA &= (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DC_V_CY;
|
||||
uptr->CMD |= DS_PIP;
|
||||
if (BUF_EMPTY(uptr)) {
|
||||
if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect ||
|
||||
GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
|
||||
uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA;
|
||||
uptr->CMD &= ~CS1_GO;
|
||||
rh_finish_op(rhc, 0);
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o writex done\n", dptr->name, unit);
|
||||
return SCPE_OK;
|
||||
}
|
||||
/* On Write headers, transfer 2 words to start */
|
||||
if (GET_FNC(uptr->CMD) == FNC_WRITEH) {
|
||||
if (rh_read(rhc) == 0)
|
||||
goto wr_end;
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word h1 %012llo %06o\n",
|
||||
dptr->name, unit, rhc->buf, rhc->wcr);
|
||||
if (rh_read(rhc) == 0)
|
||||
goto wr_end;
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word h2 %012llo %06o\n",
|
||||
dptr->name, unit, rhc->buf, rhc->wcr);
|
||||
}
|
||||
uptr->DATAPTR = 0;
|
||||
uptr->hwmark = 0;
|
||||
}
|
||||
sts = rh_read(rhc);
|
||||
sim_debug(DEBUG_DATA, dptr, "%s%o write word %d %012llo %06o %06o\n",
|
||||
dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr);
|
||||
rp_buf[ctlr][uptr->DATAPTR++] = rhc->buf;
|
||||
if (sts == 0) {
|
||||
while (uptr->DATAPTR < RP_NUMWD)
|
||||
rp_buf[ctlr][uptr->DATAPTR++] = 0;
|
||||
}
|
||||
if (uptr->DATAPTR == RP_NUMWD) {
|
||||
sim_debug(DEBUG_DETAIL, dptr, "%s%o write (%d,%d,%d)\n", dptr->name,
|
||||
unit, cyl, GET_SF(uptr->DA), GET_SC(uptr->DA));
|
||||
da = GET_DA(uptr->DA, dtype);
|
||||
(void)disk_write(uptr, &rp_buf[ctlr][0], da, RP_NUMWD);
|
||||
uptr->DATAPTR = 0;
|
||||
CLR_BUF(uptr);
|
||||
if (sts) {
|
||||
uptr->DA += 1 << DA_V_SC;
|
||||
if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect) {
|
||||
uptr->DA &= (DA_M_SF << DA_V_SF) | (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DA_V_SF;
|
||||
if (GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) {
|
||||
uptr->DA &= (DC_M_CY << DC_V_CY);
|
||||
uptr->DA += 1 << DC_V_CY;
|
||||
uptr->CMD |= DS_PIP;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (rh_blkend(rhc))
|
||||
goto wr_end;
|
||||
}
|
||||
if (rh_blkend(rhc))
|
||||
goto wr_end;
|
||||
|
||||
if (sts) {
|
||||
sim_activate(uptr, 100);
|
||||
sim_activate(uptr, 10);
|
||||
} else {
|
||||
wr_end:
|
||||
sim_debug(DEBUG_DETAIL, dptr, "RP%o write done\n", unit);
|
||||
uptr->CMD |= DS_DRY;
|
||||
uptr->CMD &= ~CS1_GO;
|
||||
rh_finish_op(rhc, 0);
|
||||
return SCPE_OK;
|
||||
}
|
||||
return SCPE_OK;
|
||||
break;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
@ -1024,7 +1013,7 @@ rp_boot(int32 unit_num, DEVICE * rptr)
|
||||
UNIT *uptr = &rptr->units[unit_num];
|
||||
int ctlr = GET_CNTRL_RH(uptr->flags);
|
||||
struct rh_if *rhc = &rp_rh[ctlr];
|
||||
DEVICE *dptr = uptr->dptr;
|
||||
DEVICE *dptr = rp_devs[ctlr];
|
||||
uint32 addr;
|
||||
uint32 ptr = 0;
|
||||
int wc;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user