mirror of
https://github.com/rcornwell/sims.git
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KA10: More fixes to get ITS to work, added performance metering.
This commit is contained in:
Richard Cornwell
parent
efcf0c33e1
commit
38d6a0a58a
252
PDP10/kx10_cpu.c
252
PDP10/kx10_cpu.c
@ -183,6 +183,8 @@ int mtr_enable; /* Enable Timer */
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int mtr_flags; /* Flags for accounting */
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int tim_per; /* Timer period */
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int tim_val; /* Current timer value */
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int mem_cnt; /* Number of memory cycles */
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int rtc_tim; /* Time till next 60hz clock */
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uint32 brk_addr; /* Address break */
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int brk_flags; /* Break flags */
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int t20_page; /* Tops 20 paging selected */
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@ -1167,6 +1169,24 @@ t_stat null_dev(uint32 dev, uint64 *data) {
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#if KL
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static int timer_irq, timer_flg;
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void
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update_times(int tim)
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{
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uint64 temp;
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if (page_enable) {
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temp = (M[eb_ptr + 0511] & CMASK) + (tim << 12);
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if (temp & SMASK)
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M[eb_ptr + 0510] = (M[eb_ptr+0510] + 1) & FMASK;
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M[eb_ptr + 0511] = temp & CMASK;
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if (FLAGS & USER) {
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temp = (M[ub_ptr + 0506] & CMASK) + (tim << 12);
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if (temp & SMASK)
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M[ub_ptr + 0505] = (M[ub_ptr+0505] + 1) & FMASK;
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M[ub_ptr + 0506] = temp & CMASK;
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}
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}
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}
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/*
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* Page device for KL10.
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*/
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@ -1204,13 +1224,10 @@ t_stat dev_pag(uint32 dev, uint64 *data) {
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page &= ~7;
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/* Map the page */
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// if (uf || upmp) {
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for(i = 0; i < 8; i++)
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u_tlb[page+i] = 0;
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// } else {
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for(i = 0; i < 8; i++)
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e_tlb[page+i] = 0;
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// }
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for(i = 0; i < 8; i++)
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u_tlb[page+i] = 0;
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for(i = 0; i < 8; i++)
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e_tlb[page+i] = 0;
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/* If not user do exec mappping */
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if (/*!uf && !t20_page &&*/ (page & 0740) == 0340) {
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/* Pages 340-377 via UBT */
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@ -1219,29 +1236,36 @@ t_stat dev_pag(uint32 dev, uint64 *data) {
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for(i = 0; i < 8; i++)
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u_tlb[page+i] = 0;
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}
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break;
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}
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res = *data;
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if (res & SMASK) {
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fm_sel = (uint8)(res >> 23) & 0160;
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prev_ctx = (res >> 20) & 0160;
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}
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if (res & BIT1) {
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/* Load previous section */
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} else {
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res = *data;
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if (res & SMASK) {
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fm_sel = (uint8)(res >> 23) & 0160;
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prev_ctx = (res >> 20) & 0160;
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}
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if (res & BIT1) {
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/* Load previous section */
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#if KLB
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prev_sect = (res >> 18) & 077;
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prev_sect = (res >> 18) & 077;
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#endif
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}
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if (res & BIT2) {
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ub_ptr = (res & 017777) << 9;
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for (i = 0; i < 512; i++)
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u_tlb[i] = 0;
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for (;i < 546; i++)
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u_tlb[i] = 0;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev,
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}
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if ((res & RSIGN) == 0) {
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int t;
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double us = sim_activate_time_usecs (&cpu_unit[0]);
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t = rtc_tim - ((int)us);
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update_times(t);
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rtc_tim = ((int)us);
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}
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if (res & BIT2) {
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ub_ptr = (res & 017777) << 9;
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for (i = 0; i < 512; i++)
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u_tlb[i] = 0;
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for (;i < 546; i++)
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u_tlb[i] = 0;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev,
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"DATAO PAG %012llo ebr=%06o ubr=%06o\n",
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*data, eb_ptr, ub_ptr);
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}
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break;
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case DATAI:
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@ -1334,34 +1358,32 @@ t_stat dev_apr(uint32 dev, uint64 *data) {
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case DATAI:
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if (dev & 040) {
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/* APRID */
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AR = SMASK| (500LL << 18); /* MC level 500 */
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/* Bit 0 for TOPS-20 paging */
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/* Bit 1 for extended addressing */
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/* Bit 2 Exotic microcode */
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/* Bit 4 for ITS Style Paging */
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/* APRID */
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AR = SMASK| (500LL << 18); /* MC level 500 */
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/* Bit 0 for TOPS-20 paging */
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/* Bit 1 for extended addressing */
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/* Bit 2 Exotic microcode */
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/* Bit 4 for ITS Style Paging */
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#if KL_ITS
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if (QITS)
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AR |= 00020000000000LL;
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#endif
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/* Bit 18 50hz */
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/* Bit 19 Cache */
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/* Bit 20 Channel? */
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/* Bit 21 Extended KL10 */
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/* Bit 22 Master Osc */
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#if KLB
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if (QKLB)
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AR |= BIT1|040000;
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#endif
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AR |= (uint64)((apr_serial == -1) ? DEF_SERIAL : apr_serial);
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MB = AR;
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(void)Mem_write(0, 0);
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sim_debug(DEBUG_DATAIO, &cpu_dev, "APRID %012llo\n", MB);
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break;
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if (QITS)
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AR |= 00020000000000LL;
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#endif
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/* Bit 18 50hz */
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/* Bit 19 Cache */
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/* Bit 20 Channel? */
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/* Bit 21 Extended KL10 */
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/* Bit 22 Master Osc */
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#if KLB
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if (QKLB)
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AR |= BIT1|040000;
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#endif
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AR |= (uint64)((apr_serial == -1) ? DEF_SERIAL : apr_serial);
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sim_debug(DEBUG_DATAIO, &cpu_dev, "APRID BLKI %012llo\n", MB);
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} else {
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*data = ((uint64)brk_flags) << 23;
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*data |= (uint64)brk_addr;
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI APR %012llo\n", *data);
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}
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*data = ((uint64)brk_flags) << 23;
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*data |= (uint64)brk_addr;
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI APR %012llo\n", *data);
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break;
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}
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return SCPE_OK;
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@ -1399,6 +1421,7 @@ t_stat dev_mtr(uint32 dev, uint64 *data) {
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break;
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case DATAO:
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/* MUUO */
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if (dev & 040) {
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sim_debug(DEBUG_DATAIO, &cpu_dev, "BLKO MTR %012llo\n", *data);
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} else {
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@ -1408,12 +1431,34 @@ t_stat dev_mtr(uint32 dev, uint64 *data) {
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case DATAI:
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if (dev & 040) {
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/* RDMACT */
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/* Read memory accounting */
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if (page_enable) {
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res = (M[ub_ptr + 0507] & CMASK);
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BR = M[ub_ptr + 0506];
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} else {
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res = 0 << 12;
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BR = 0;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev, "BLKI MTR %012llo\n", *data);
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} else {
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/* RDEACT */
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/* Read executive accounting */
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int t;
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double us = sim_activate_time_usecs (&cpu_unit[0]);
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t = rtc_tim - ((int)us);
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update_times(t);
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rtc_tim = ((int)us);
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if (page_enable) {
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res = (M[ub_ptr + 0505] & CMASK);
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BR = M[ub_ptr + 0504];
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} else {
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res = t << 12;
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BR = 0;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI MTR %012llo\n", *data);
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}
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*data = res;
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break;
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}
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return SCPE_OK;
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@ -1463,7 +1508,8 @@ t_stat dev_tim(uint32 dev, uint64 *data) {
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case DATAO:
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if (dev & 040) {
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/* Write performance */
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/* WRPAE */
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/* Write performance enables */
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sim_debug(DEBUG_DATAIO, &cpu_dev, "BLKO TIM %012llo\n", *data);
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} else {
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAO TIM %012llo\n", *data);
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@ -1472,14 +1518,38 @@ t_stat dev_tim(uint32 dev, uint64 *data) {
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case DATAI:
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if (dev & 040) {
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/* Read perfomance */
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/* RDPERF */
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/* Read process execution time */
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int t;
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us = sim_activate_time_usecs (&cpu_unit[0]);
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t = rtc_tim - ((int)us);
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update_times(t);
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rtc_tim = ((int)us);
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if (page_enable) {
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res = (M[ub_ptr + 0505]);
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BR = M[ub_ptr + 0504];
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} else {
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res = 0 << 12;
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BR = t;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev, "BLKI TIM %012llo\n", *data);
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} else {
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/* RDTIME */
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*data = M[eb_ptr + 0510];
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BR = M[eb_ptr + 0511];
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int t;
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us = sim_activate_time_usecs (&cpu_unit[0]);
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t = rtc_tim - ((int)us);
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update_times(t);
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rtc_tim = ((int)us);
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if (page_enable) {
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res = (M[eb_ptr + 0511]);
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BR = M[eb_ptr + 0510];
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} else {
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res = t << 12;
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BR = 0;
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}
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI TIM %012llo\n", *data);
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}
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*data = res;
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return SCPE_OK;
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}
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/* If timer is on, figure out when it will go off */
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@ -1857,7 +1927,7 @@ load_tlb(int uf, int page, int upmp, int wr, int trap, int flag)
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((page & 0400) ? dbr3 : dbr4) ;
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pg = (page & 0377) >> 2; /* 2 1024 word page entries */
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data = M[dbr + pg];
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fprintf(stderr, "Load page %06o dbr%012llo pg%06o data=%012llo -> ", page, dbr, pg, data);
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//fprintf(stderr, "Load page %06o dbr%012llo pg%06o data=%012llo -> ", page, dbr, pg, data);
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if ((page & 02) == 0)
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data >>= 18;
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data &= RMASK;
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@ -1879,7 +1949,7 @@ fprintf(stderr, "Load page %06o dbr%012llo pg%06o data=%012llo -> ", page, dbr,
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e_tlb[(page & 0776)|1] = pg|1;
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data = e_tlb[page];
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}
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fprintf(stderr, " %06o %06o\n\r", pg, pg | 1);
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//fprintf(stderr, " %06o %06o\n\r", pg, pg | 1);
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} else
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#endif
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#define PG_PUB 0040000
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@ -2156,7 +2226,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch
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if (flag)
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uf = 0;
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else if (xct_flag != 0 && !uf && !fetch) {
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fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o w=%o", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg, wr);
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//fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o w=%o", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg, wr);
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if (((xct_flag & 8) != 0 && cur_context) ||
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((xct_flag & 4) != 0 && !cur_context && !BYF5 && !ptr_flg) ||
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((xct_flag & 2) != 0 && !cur_context && ptr_flg) ||
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@ -2164,7 +2234,7 @@ fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o w=%o", IR, P
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uf = (FLAGS & USERIO) != 0;
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pub = (FLAGS & PRV_PUB) != 0;
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}
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fprintf(stderr, "%o %o\n\r", uf, pub);
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//fprintf(stderr, "%o %o\n\r", uf, pub);
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}
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/* Handle KI paging odditiy */
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@ -2197,7 +2267,7 @@ fprintf(stderr, "%o %o\n\r", uf, pub);
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(!fetch || (M[*loc] & 00777740000000LL) != 0254040000000LL)) {
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/* Handle public violation */
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fault_data = ((uint64)addr) | 021LL << 30 | BIT8 |((uf)?SMASK:0);
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fprintf(stderr, "Public fault %012llo %06o\n\r", fault_data, FLAGS << 5);
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//fprintf(stderr, "Public fault %012llo %06o\n\r", fault_data, FLAGS << 5);
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page_fault = 1;
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return 0;
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}
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@ -2296,16 +2366,16 @@ int Mem_read(int flag, int cur_context, int fetch) {
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sim_interval--;
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if (AB < 020) {
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if (xct_flag != 0 && !fetch && (FLAGS & USER) == 0) {
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fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o rgr ", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg);
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//fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o rgr ", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg);
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if (((xct_flag & 8) != 0 && cur_context) ||
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((xct_flag & 4) != 0 && !cur_context && !BYF5 && !ptr_flg) ||
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((xct_flag & 2) != 0 && !cur_context && ptr_flg) ||
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((xct_flag & 1) != 0 && !cur_context && BYF5)) {
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MB = FM[prev_ctx|AB];
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fprintf(stderr, "prev \n\r");
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//fprintf(stderr, "prev \n\r");
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return 0;
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}
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fprintf(stderr, "\n\r");
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//fprintf(stderr, "\n\r");
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}
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MB = get_reg(AB);
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} else {
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@ -2328,16 +2398,16 @@ int Mem_write(int flag, int cur_context) {
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sim_interval--;
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if (AB < 020) {
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if (xct_flag != 0 && (FLAGS & USER) == 0) {
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fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o rgw ", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg);
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//fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o c=%o b=%o p=%o rgw ", IR, PC, addr, xct_flag, cur_context, BYF5, ptr_flg);
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if (((xct_flag & 8) != 0 && cur_context) ||
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((xct_flag & 4) != 0 && !cur_context && !BYF5 && !ptr_flg) ||
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((xct_flag & 2) != 0 && !cur_context && ptr_flg) ||
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((xct_flag & 1) != 0 && !cur_context && BYF5)) {
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fprintf(stderr, "prev \n\r");
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//fprintf(stderr, "prev \n\r");
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FM[prev_ctx|AB] = MB;
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return 0;
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}
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fprintf(stderr, "\n\r");
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//fprintf(stderr, "\n\r");
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}
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set_reg(AB, MB);
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} else {
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@ -3880,6 +3950,7 @@ no_fetch:
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/* Handle indirection repeat until no longer indirect */
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do {
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int ix;
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if ((!pi_cycle) & pi_pending
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#if KI | KL
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& (!trap_flag)
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@ -3887,16 +3958,19 @@ no_fetch:
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) {
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pi_rq = check_irq_level();
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}
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ind = (MB & 020000000) != 0;
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ind = TST_IND(MB) != 0;
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AR = MB;
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AB = MB & RMASK;
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if (MB & 017000000) {
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ix = GET_XR(MB);
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if (ix) {
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#if KL
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// if (xct_flag != 0)
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//fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o m=%012llo\n\r", IR, PC, AB, xct_flag, MB);
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if ((xct_flag & 8) != 0 && (FLAGS & USER) == 0)
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AR = MB = (AB + FM[prev_ctx|((MB >> 18) & 017)]) & FMASK;
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AR = MB = (AB + FM[prev_ctx|ix]) & FMASK;
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else
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#endif
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AR = MB = (AB + get_reg((MB >> 18) & 017)) & FMASK;
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AR = MB = (AB + get_reg(ix)) & FMASK;
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AB = MB & RMASK;
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}
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if (IR != 0254)
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@ -6621,12 +6695,10 @@ xjrstf:
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if (Mem_read(0, 0, 0))
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goto last;
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BR = MB >> 32; /* Move flags into position */
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fprintf(stderr, "Xjrst %012llo - ", MB);
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AB = (AB + 1) & RMASK;
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if (Mem_read(0, 0, 0))
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goto last;
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AR = MB; /* Get PC. */
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fprintf(stderr, " %012llo\n\r", MB);
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#if KLB
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if (QKLB)
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pc_sect = (MB >> 18) & 017;
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@ -7330,7 +7402,7 @@ skip_op:
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PC_CHANGE
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PC = (PC + 1) & RMASK;
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#if KI | KL
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} else if (pi_cycle) {
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} else if (trap_flag == 0 && pi_cycle) {
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pi_ov = pi_hold = 1;
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#endif
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}
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@ -7663,17 +7735,26 @@ fetch_opr:
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case 0: /* 00 BLKI */
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case 2: /* 10 BLKO */
|
||||
#if KL
|
||||
/* For KL10 special devices treat like DATAI/DATAO */
|
||||
if (d <= 05) {
|
||||
if (AC & 02) {
|
||||
// if (Mem_read(pi_cycle, 0, 0))
|
||||
// goto last;
|
||||
// AR = MB;
|
||||
if (d == 1 || d == 4) {
|
||||
if (Mem_read(pi_cycle, 0, 0))
|
||||
goto last;
|
||||
AR = MB;
|
||||
}
|
||||
dev_tab[d](040|DATAO|(d<<2), &AR);
|
||||
} else {
|
||||
dev_tab[d](040|DATAI|(d<<2), &AR);
|
||||
// MB = AR;
|
||||
// if (Mem_write(pi_cycle, 0))
|
||||
// goto last;
|
||||
MB = AR;
|
||||
if (Mem_write(pi_cycle, 0))
|
||||
goto last;
|
||||
if (d == 4 || d == 5) {
|
||||
AB = (AB + 1) & RMASK;
|
||||
MB = BR;
|
||||
if (Mem_write(pi_cycle, 0))
|
||||
goto last;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
@ -7704,7 +7785,7 @@ fetch_opr:
|
||||
if (Mem_write(pi_cycle, 0))
|
||||
goto last;
|
||||
#if KL
|
||||
if (d == 5) { /* DATAI TIM is two words */
|
||||
if (d == 4 || d == 5) { /* DATAI TIM, MTR is two words */
|
||||
AB = (AB + 1) & RMASK;
|
||||
MB = BR;
|
||||
if (Mem_write(pi_cycle, 0))
|
||||
@ -8746,14 +8827,23 @@ t_stat
|
||||
rtc_srv(UNIT * uptr)
|
||||
{
|
||||
int32 t;
|
||||
#if KL
|
||||
uint64 temp;
|
||||
#endif
|
||||
t = sim_rtcn_calb (rtc_tps, TMR_RTC);
|
||||
sim_activate_after(uptr, 1000000/rtc_tps);
|
||||
tmxr_poll = t/2;
|
||||
#if PDP6 | KA | KI
|
||||
clk_flg = 1;
|
||||
if (clk_en) {
|
||||
sim_debug(DEBUG_CONO, &cpu_dev, "CONO timmer\n");
|
||||
set_interrupt(4, clk_irq);
|
||||
}
|
||||
#endif
|
||||
#if KL
|
||||
update_times(rtc_tim);
|
||||
rtc_tim = (1000000/rtc_tps);
|
||||
#endif
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user