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IBM360: Fixes to fix errors uncovered by microcode testing.
This commit is contained in:
Richard Cornwell
parent
3866d240ef
commit
3bb3b76ff0
@ -290,7 +290,7 @@ extern int vma_lpsw(uint32 addr1);
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extern int vma_stssk(uint32 src1, uint32 addr1);
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extern int vma_stisk(uint8 reg1, uint32 addr1);
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extern int vma_stsvc(uint8 reg);
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extern int vma_lra(uint8 reg, uint32 addr1);
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extern int vma_lra(uint8 reg, uint32 addr1, uint8 *cc);
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extern int vma_stnsm(uint8 reg, uint32 addr1);
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extern int vma_stosm(uint8 reg, uint32 addr1);
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extern int vma_stctl(uint8 reg, uint32 addr1);
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@ -571,7 +571,7 @@ TransAddr(uint32 va, uint32 *pa)
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seg = (va >> seg_shift) & seg_mask; /* Segment number to word address */
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page = (va >> page_shift) & page_index;
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/* Check address against lenght of segment table */
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/* Check address against length of segment table */
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if (seg > seg_len) {
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if (Q370) {
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M[0x90 >> 2] = va;
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@ -1782,7 +1782,6 @@ set_cc3:
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src2 ^= FMASK;
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dest = src1 + src2 + 1;
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src1h = ((src1 & src2) | ((src1 ^ src2) & ~dest)) & MSIGN;
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src1h = (src1h != 0);
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cc = (dest != 0);
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if (src1h != 0)
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cc |= 2;
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@ -1794,7 +1793,6 @@ set_cc3:
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case OP_ALR:
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dest = src1 + src2;
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src1h = ((src1 & src2) | ((src1 ^ src2) & ~dest)) & MSIGN;
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src1h = (src1h != 0);
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cc = (dest != 0);
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if (src1h != 0)
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cc |= 2;
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@ -2108,7 +2106,7 @@ char_save:
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break;
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case OP_SRDL:
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if (reg & 1) {
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if (reg1 & 1) {
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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} else {
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@ -2133,7 +2131,7 @@ char_save:
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break;
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case OP_SLDL:
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if (reg & 1) {
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if (reg1 & 1) {
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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} else {
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@ -2158,7 +2156,7 @@ char_save:
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break;
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case OP_SLDA:
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if (reg & 1) {
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if (reg1 & 1) {
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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} else {
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@ -2206,7 +2204,7 @@ save_dbl:
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break;
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case OP_SRDA:
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if (reg & 1) {
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if (reg1 & 1) {
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storepsw(OPPSW, IRC_SPEC);
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goto supress;
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} else {
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@ -2426,8 +2424,12 @@ save_dbl:
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if ((cpu_unit[0].flags & FEAT_DAT) == 0) {
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storepsw(OPPSW, IRC_OPR);
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} else if (flags & PROBLEM) {
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/* RX in RS range */
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if (X2(reg) != 0)
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addr1 += regs[X2(reg)];
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/* Try to do quick LRA */
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if (QVMA && vma_lra(reg, addr1))
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if (QVMA && vma_lra(R1(reg), addr1, &cc))
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break;
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storepsw(OPPSW, IRC_PRIV);
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} else {
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@ -2497,7 +2499,7 @@ save_dbl:
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entry &= 0xffff;
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/* Check if entry valid */
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if (entry & pte_avail) {
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if (entry & (pte_avail|pte_mbz)) {
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cc = 2;
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regs[reg1] = addr2;
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per_mod |= 1 << reg1;
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@ -2819,6 +2821,7 @@ save_dbl:
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/* Check if too big */
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if (dest & MSIGN) {
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storepsw(OPPSW, IRC_FIXDIV);
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regs[reg1] = dest;
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goto supress;
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}
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/* Twos compliment if needed */
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@ -2998,23 +3001,31 @@ save_dbl:
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if (Q370) {
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int i, j;
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/* Fetch register */
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dest = regs[reg1];
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/* If no bits, just read byte and trap if needed */
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if (R2(reg) == 0) {
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if(ReadByte(addr1, &src1))
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goto supress;
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cc = 0;
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break;
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}
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/* Set flag to check first bit */
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fill = 0x80;
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digit = 0;
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/* Scan from Bit 12 to bit 15 */
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for (i = 0x8, j=24; i != 0; i >>= 1, j-=8) {
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/* If the bit is one, read in byte */
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if ((R2(reg) & i) != 0) {
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if(ReadByte(addr1, &src1))
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goto supress;
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addr1++;
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/* Make mask */
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src2 = 0xff << j;
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/* Put byte into place */
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dest = (dest & ~src2) | ((src1 & 0xff) << j);
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if (src1) {
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/* If byte not zero, compute new CC */
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if (src1 != 0) {
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if ((src1 & fill) != 0)
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digit = 1;
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else if (digit == 0)
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@ -3751,7 +3762,7 @@ save_dbl:
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if ((op & 0x1)) /* LN, LC */
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src2 ^= MSIGN;
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cc = 0;
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src1 = src2 & MMASK;
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src1 = src2 & (~MSIGN);
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if ((op & 0x10) == 0) {
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fpregs[reg1|1] = src2h;
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src1 |= src2h;
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@ -4504,7 +4515,7 @@ fpnorm:
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dest |= (e1 << 24) & EMASK;
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if (fill)
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dest |= MSIGN;
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if ((op & 0x10) == 0 || (op & 0xF) == 0xC)
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if ((op & 0x10) == 0)
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fpregs[reg1|1] = desth;
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fpregs[reg1] = dest;
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break;
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@ -4518,7 +4529,6 @@ fpnorm:
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e1 = (src1 & EMASK) >> 24;
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e2 = (src2 & EMASK) >> 24;
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fill = 0;
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fill = 0;
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if ((src1 & MSIGN) != (src2 & MSIGN))
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fill = 1;
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src1 &= MMASK;
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@ -5842,10 +5852,14 @@ dec_mul(int op, uint32 addr1, uint8 len1, uint32 addr2, uint8 len2)
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int mul;
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int len;
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if (len2 > 7 || len2 >= len1) {
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if (len2 == len1) {
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storepsw(OPPSW, IRC_SPEC);
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return;
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}
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if (len2 > 7 || len2 >= len1) {
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storepsw(OPPSW, IRC_DATA);
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return;
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}
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if (dec_load(b, addr2, (int)len2, &sb))
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return;
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if (dec_load(a, addr1, (int)len1, &sa))
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