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SEL32: Rewrite mapping and address translation software.

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This commit is contained in:
AZBevier 2019-12-18 20:56:01 -07:00
parent f660e8eb70
commit 4c012098ef
9 changed files with 1020 additions and 672 deletions
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3
SEL32/sel32_chan.c
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@ -470,7 +470,8 @@ loop:
#endif
#ifndef CON_BUG
#ifdef DO_DYNAMIC_DEBUG
if ((chp->chan_dev == 0x7efc) && ((chp->ccw_cmd & 0xff) == 0x03) && (chp->ccw_count == 0))
// if ((chp->chan_dev == 0x7efc) && ((chp->ccw_cmd & 0xff) == 0x03) && (chp->ccw_count == 0))
if ((chp->chan_dev == 0x0800) && ((chp->ccw_cmd & 0xff) == 0x00) && (chp->ccw_count == 0x24))
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
#endif

2
SEL32/sel32_com.c
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@ -263,7 +263,7 @@ DIB com_dib = {
0x7E00, /* uint16 chan_addr */ /* parent channel address */
0, /* uint32 chan_fifo_in */ /* fifo input index */
0, /* uint32 chan_fifo_out */ /* fifo output index */
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
REG com_reg[] = {

5
SEL32/sel32_con.c
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@ -138,7 +138,7 @@ DIB con_dib = {
0x7e00, /* uint16 chan_addr */ /* parent channel address */
0, /* uint32 chan_fifo_in */ /* fifo input index */
0, /* uint32 chan_fifo_out */ /* fifo output index */
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
DEVICE con_dev = {
@ -453,10 +453,7 @@ t_stat con_reset(DEVICE *dptr) {
/* Handle haltio transfers for console */
uint8 con_haltio(UNIT *uptr) {
uint16 chsa = GET_UADDR(uptr->u3);
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
int cmd = uptr->u3 & CON_MSK;
uint8 ch;
t_stat r;
sim_debug(DEBUG_EXP, &con_dev, "con_haltio enter chsa %04x cmd = %02x\n", chsa, cmd);

1623
SEL32/sel32_cpu.c
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File diff suppressed because it is too large Load Diff

51
SEL32/sel32_disk.c
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@ -213,6 +213,7 @@ struct disk_t
}
disk_type[] =
{
#ifdef NOTUSED_FOR_NOW
/* Class E Disc Devices */
{"FE004", 5888, 184, 256, 192, 23, 1, 1, 1, 0x80}, /* 4 M */
{"CE010", 12800, 200, 2, 96, 16, 1, 2, 400, 0x60}, /* 10 M */
@ -242,6 +243,16 @@ disk_type[] =
{"FM600", 80000, 2500, 40, 192, 20, 8, 1, 800, 0x40}, /* 600 M */
{"FM600", 1600, 50, 40, 192, 20, 1, 1, 2, 0x80}, /* 600 M */
{NULL, 0}
#else
/* Class F Disc Devices */
{"MH040", 20000, 625, 5, 192, 20, 2, 1, 400, 0x40}, /* 40 M */
{"MH080", 40000, 1250, 5, 192, 20, 2, 1, 800, 0x40}, /* 80 M */
{"MH300", 76000, 2375, 19, 192, 20, 4, 1, 800, 0x40}, /* 300 M */
{"MH600", 80000, 2500, 40, 192, 20, 8, 1, 800, 0x40}, /* 600 M */
/* For UTX */
{"9342", 40000, 1250, 5, 256, 16, 2, 1, 800, 0x40}, /*823 80 M */
{"9344", 76000, 2375, 19, 256, 16, 4, 1, 800, 0x40}, /*823 300 M */
#endif
};
#if 0
@ -316,15 +327,16 @@ MTAB disk_mod[] = {
};
UNIT dda_unit[] = {
/* SET_TYPE(9) DM300 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x800)}, /* 0 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x801)}, /* 1 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x802)}, /* 2 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x803)}, /* 3 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x804)}, /* 4 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x805)}, /* 5 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x806)}, /* 6 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0x807)}, /* 7 */
/* SET_TYPE(9) DM300 old */
/* SET_TYPE(2) DM300 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x800)}, /* 0 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x801)}, /* 1 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x802)}, /* 2 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x803)}, /* 3 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x804)}, /* 4 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x805)}, /* 5 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x806)}, /* 6 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0x807)}, /* 7 */
};
DIB dda_dib = {
@ -341,7 +353,7 @@ DIB dda_dib = {
0x0800, /* parent channel address */
0, /* fifo input index */
0, /* fifo output index */
0, /* interrupt status fifo for channel */
{0} /* interrupt status fifo for channel */
};
DEVICE dda_dev = {
@ -357,15 +369,16 @@ DEVICE dda_dev = {
CHANP ddb_chp[NUM_UNITS_DISK] = {0};
UNIT ddb_unit[] = {
/* SET_TYPE(9) DM300 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC00)}, /* 0 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC01)}, /* 1 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC02)}, /* 2 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC03)}, /* 3 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC04)}, /* 4 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC05)}, /* 5 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC06)}, /* 6 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(9), 0), 0, UNIT_ADDR(0xC07)}, /* 7 */
/* SET_TYPE(9) DM300 old */
/* SET_TYPE(2) DM300 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC00)}, /* 0 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC01)}, /* 1 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC02)}, /* 2 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC03)}, /* 3 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC04)}, /* 4 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC05)}, /* 5 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC06)}, /* 6 */
{UDATA(&disk_srv, UNIT_DISK|SET_TYPE(2), 0), 0, UNIT_ADDR(0xC07)}, /* 7 */
};

2
SEL32/sel32_iop.c
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@ -120,7 +120,7 @@ DIB iop_dib = {
0x7e00, /* uint16 chan_addr */ /* parent channel address */
0, /* uint32 chan_fifo_in */ /* fifo input index */
0, /* uint32 chan_fifo_out */ /* fifo output index */
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
DEVICE iop_dev = {

2
SEL32/sel32_lpr.c
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@ -183,7 +183,7 @@ DIB lpr_dib = {
0x7e00, /* uint16 chan_addr */ /* parent channel address */
0, /* uint32 chan_fifo_in */ /* fifo input index */
0, /* uint32 chan_fifo_out */ /* fifo output index */
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
DEVICE lpr_dev = {

2
SEL32/sel32_mt.c
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@ -376,7 +376,7 @@ DIB mta_dib = {
0x1000, /* parent channel address */
0, /* fifo input index */
0, /* fifo output index */
0, /* interrupt status fifo for channel */
{0} /* interrupt status fifo for channel */
};
DEVICE mta_dev = {

2
SEL32/sel32_scfi.c
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@ -331,7 +331,7 @@ DIB sda_dib = {
0x0400, /* uint16 chan_addr */ /* parent channel address */
0, /* uint32 chan_fifo_in */ /* fifo input index */
0, /* uint32 chan_fifo_out */ /* fifo output index */
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
DEVICE sda_dev = {