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https://github.com/rcornwell/sims.git
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SEL32: Correct lea * instruction and eom? instruction
This commit is contained in:
James C. Bevier
Richard Cornwell
parent
665b2beda2
commit
4eacef155a
@ -20,6 +20,9 @@
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Change History:
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12/12/2018 - handle F bit properly for LEA * instruction
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*/
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#include "sel32_defs.h"
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@ -159,12 +162,15 @@
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/* Wd 4 - Input/Output Command List Address (IOCL) for the Class F I/O CHannel */
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/* Wd 5 - 24 bit real address of the channel status word */
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/* CPU registers, map cache, spad, and other variables */
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//#define TRME /* set defined to enable instruction trace */
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/* instruction trace controls */
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//#define TRME /* set defined to enable instruction trace */
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#undef TRME
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int traceme = 0; /* dynamic trace function */
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int trstart = 8000000; /* count of when to start tracing */
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//int trstart = 37; /* count of when to start tracing */
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int traceme = 0; /* dynamic trace function */
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//int trstart = 0; /* count of when to start tracing */
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int trstart = 8000000; /* count of when to start tracing */
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//int trstart = 37; /* count of when to start tracing */
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/* CPU registers, map cache, spad, and other variables */
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int cpu_index; /* Current CPU running */
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uint32 PSD[2]; /* the PC for the instruction */
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#define PSD1 PSD[0] /* word 1 of PSD */
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@ -512,7 +518,7 @@ DEVICE cpu_dev = {
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#define R1 0x0040 /* Read destination register */
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#define RB 0x0080 /* Read base register into dest */
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#define SD 0x0100 /* Stores into destination register */
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#define SDD 0x0200 /* Stores double into destination */
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#define RNX 0x0200 /* Reads memory without sign extend */
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#define RM 0x0400 /* Reads memory */
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#define SM 0x0800 /* Stores memory */
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#define DBL 0x1000 /* Double word operation */
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@ -550,7 +556,7 @@ int nobase_mode[] = {
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/* 80 84 88 8C */
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/* LEAR ANM ORM EOM */
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SD|ADR, SCC|SD|RR|RM|ADR, SCC|SD|RR|RM|ADR, SCC|SD|RR|RM|ADR,
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SD|ADR, SCC|SD|RR|RNX|ADR, SCC|SD|RR|RNX|ADR, SCC|SD|RR|RNX|ADR,
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/* 90 94 98 9C */
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/* CAM CMM SBM ZBM */
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@ -574,7 +580,7 @@ int nobase_mode[] = {
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/* E0 E4 E8 EC */
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/* ADF MPF ARM BCT */
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RM|ADR, RM|ADR, SCC|SM|RR|RM|ADR, ADR,
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ADR, ADR, SCC|SM|RR|RM|ADR, ADR,
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/* F0 F4 F8 FC */
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/* BCF BI MISC IO */
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@ -612,7 +618,7 @@ int base_mode[] = {
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/* LEAR ANM ORM EOM */
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/* 80 84 88 8C */
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SD|ADR, SD|RM|ADR, SD|RM|ADR, SD|RM|ADR,
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SD|ADR, SD|RNX|ADR, SD|RNX|ADR, SD|RNX|ADR,
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/* CAM CMM SBM ZBM */
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/* 90 94 98 9C */
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@ -632,11 +638,11 @@ int base_mode[] = {
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/* D0 D4 D8 DC */
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/* LEA ST STM STFBR */
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SD|ADR, SM|ADR, SM|ADR, ADR,
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INV, SM|ADR, SM|ADR, ADR,
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/* E0 E4 E8 EC */
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/* ADF MPF ARM BCT */
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RM|ADR, RM|ADR, SM|RM|ADR, ADR,
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ADR, ADR, SM|RM|ADR, ADR,
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/* F0 F4 F8 FC */
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/* BCF BI MISC IO */
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@ -1173,6 +1179,9 @@ wait_loop:
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}
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sim_debug(DEBUG_EXP, &cpu_dev, "Normal int scan return icb %x irq_pend %x wait4int %x\n",
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int_icb, irq_pend, wait4int);
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if (traceme >= trstart) {
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fprintf(stderr, "Normal int scan return icb %x irq_pend %x wait4int %x\r\n", int_icb, irq_pend, wait4int);
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}
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/* take interrupt, store the PSD, fetch new PSD */
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bc = PSD2 & 0x3ffc; /* get copy of cpix */
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M[int_icb>>2] = PSD1&0xfffffffe; /* store PSD 1 */
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@ -1201,6 +1210,10 @@ wait_loop:
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sim_debug(DEBUG_INST, &cpu_dev,
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"Interrupt %x OPSD1 %.8x OPSD2 %.8x NPSD1 %.8x NPSD2 %.8x ICBA %x\n",
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il, M[int_icb>>2], M[(int_icb>>2)+1], PSD1, PSD2, int_icb);
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if (traceme >= trstart) {
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fprintf(stderr, "Interrupt %x OPSD1 %.8x OPSD2 %.8x NPSD1 %.8x NPSD2 %.8x ICBA %x\r\n",
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il, M[int_icb>>2], M[(int_icb>>2)+1], PSD1, PSD2, int_icb);
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}
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wait4int = 0; /* wait is over for int */
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skipinstr = 1; /* skip next interrupt test only once */
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}
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@ -1314,6 +1327,8 @@ exec:
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addr += BR[ix]; /* if not zero, add to base reg contents */
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FC = ((IR & F_BIT) ? 4 : 0); /* get F bit from original instruction */
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FC |= addr & 3; /* set new C bits to address from orig or regs */
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// if (OP == 0xe0 || OP == 0xe4)
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// FC &= 3; /* reset F bit for Float instr */
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break;
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case INV:
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TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
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@ -1357,7 +1372,7 @@ exec:
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/* wart alert! */
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/* the lea instruction requires special handling for indirection. */
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/* Bit 0,1 are set to 1 of result addr if indirect bit is zero in */
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/* Bits 0,1 are set to 1 in result addr if indirect bit is zero in */
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/* instruction. Bits 0 & 1 are set to the last word */
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/* or instruction in the chain bits 0 & 1 if indirect bit set */
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/* if IX == 00 => dest = IR */
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@ -1366,41 +1381,56 @@ exec:
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/* fall through */
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case WRD: /* Word addressing, no index */
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bc = 0xC0000000; /* set bits 0, 1 for instruction if not indirect */
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t = IR; /* get current IR */
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while (t & IND) { /* process indirection */
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bc = 0xC0000000; /* set bits 0, 1 for instruction if not indirect */
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t = IR; /* get current IR */
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while (t & IND) { /* process indirection */
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if ((TRAPME = Mem_read(addr, &temp))) /* get the word from memory */
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goto newpsd; /* memory read error or map fault */
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bc = temp & 0xC0000000; /* save new bits 0, 1 from indirect location */
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CC = (temp & 0x78000000); /* save CC's from the last indirect word */
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if (modes & EXTDBIT) { /* check if in extended mode */
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goto newpsd; /* memory read error or map fault */
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bc = temp & 0xC0000000; /* save new bits 0, 1 from indirect location */
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CC = (temp & 0x78000000); /* save CC's from the last indirect word */
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if (modes & EXTDBIT) { /* check if in extended mode */
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/* extended mode, so location has 24 bit addr, not X,I ADDR */
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addr = temp & MASK24; /* get 24 bit addr */
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addr = temp & MASK24; /* get 24 bit addr */
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/* if no C bits set, use original, else new */
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if ((IR & F_BIT) || (addr & 3))
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FC = ((IR & F_BIT) ? 0x4 : 0) | (addr & 3);
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t &= ~IND; /* turn off IND bit to stop while loop */
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else {
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addr |= (IR & F_BIT); /* copy F bit from instruction */
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addr |= (FC & 3); /* copy in last C bits */
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}
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t &= ~IND; /* turn off IND bit to stop while loop */
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} else {
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/* non-extended mode, process new X, I, ADDR fields */
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addr = temp & MASK19; /* get just the addr */
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ix = (temp >> 21) & 3; /* get the index reg from indirect word */
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addr = temp & MASK19; /* get just the addr */
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ix = (temp >> 21) & 3; /* get the index reg from indirect word */
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if (ix != 0)
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addr += (GPR[ix] & MASK19); /* add the register to the address */
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/* if no F or C bits set, use original, else new */
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if ((temp & F_BIT) || (addr & 3))
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FC = ((temp & F_BIT) ? 0x4 : 0) | (addr & 3);
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else {
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addr |= (IR & F_BIT); /* copy F bit from instruction */
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addr |= (FC & 3); /* copy in last C bits */
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}
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t = temp; /* go process next indirect location */
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}
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}
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if (OP == 0xD0) /* test for LEA op */
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addr |= bc; /* insert bits 0,1 values into address */
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dest = (t_uint64)addr; /* make into 64 bit variable */
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if ((OP & 0xFC) == 0xD0) { /* test for LEA op */
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addr |= bc; /* insert bits 0,1 values into address */
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#ifdef OLDWAY
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addr |= (IR & F_BIT); /* copy F bit from instruction */
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#else
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if (FC & 0x4)
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addr |= F_BIT; /* copy F bit from instruction */
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#endif
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}
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dest = (t_uint64)addr; /* make into 64 bit variable */
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break;
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case INV: /* Invalid instruction */
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if ((TRAPME = Mem_read(addr, &temp))) /* get the word from memory */
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goto newpsd; /* memory read error or map fault */
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TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
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goto newpsd; /* handle trap */
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case INV: /* Invalid instruction */
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if ((TRAPME = Mem_read(addr, &temp))) /* get the word from memory */
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goto newpsd; /* memory read error or map fault */
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TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
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goto newpsd; /* handle trap */
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break;
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}
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}
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@ -1446,6 +1476,42 @@ exec:
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}
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}
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/* Read memory operand without doing sign extend for EOMX/ANMX/ORMX */
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if (i_flags & RNX) {
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if ((TRAPME = Mem_read(addr, &temp))) { /* get the word from memory */
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goto newpsd; /* memory read error or map fault */
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}
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source = (t_uint64)temp; /* make into 64 bit value */
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switch(FC) {
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case 0: /* word address and no sign extend */
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source &= D32RMASK; /* just l/o 32 bits */
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break;
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case 1: /* left hw */
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source >>= 16; /* move left hw to right hw*/
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/* Fall through */
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case 3: /* right hw or right shifted left hw */
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source &= 0xffff; /* use just the right hw */
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break;
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case 2: /* double word address */
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if ((addr & 2) != 2) { /* must be double word adddress */
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TRAPME = ADDRSPEC_TRAP; /* bad address, error */
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goto newpsd; /* go execute the trap now */
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}
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if ((TRAPME = Mem_read(addr+4, &temp))) { /* get the 2nd word from memory */
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goto newpsd; /* memory read error or map fault */
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}
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source = (source << 32) | (t_uint64)temp; /* merge in the low order 32 bits */
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dbl = 1; /* double word instruction */
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break;
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case 4: /* byte mode, byte 0 */
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case 5: /* byte mode, byte 1 */
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case 6: /* byte mode, byte 2 */
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case 7: /* byte mode, byte 3 */
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source = (source >> (8*(7-FC))) & 0xff; /* right justify addressed byte */
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break;
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}
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}
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/* Read in if from register */
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if (i_flags & RR) {
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if (FC == 2 && (i_flags & HLF) == 0) /* double dest? */
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@ -1453,6 +1519,7 @@ exec:
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dest = (t_uint64)GPR[reg]; /* get the register content */
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if (dbl) { /* is it double regs */
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if (reg & 1) { /* check for odd reg load */
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//fprintf(stderr, "RR AD02 DBL WD opr %x FC %x addr = %x dest %lx\r\n", IR, FC, addr, dest);
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TRAPME = ADDRSPEC_TRAP; /* bad address, error */
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goto newpsd; /* go execute the trap now */
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}
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@ -2014,6 +2081,7 @@ tbr: /* handle basemode TBR too */
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/*TODO*/ case 0x30>>2: /* 0x30 */ /* CALM */
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fprintf(stderr, "ERROR - CALM called\r\n");
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fflush(stderr);
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goto inv; /* TODO */
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break;
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@ -2186,7 +2254,7 @@ tbr: /* handle basemode TBR too */
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source |= (t_uint64)GPR[sreg+1]; /* insert low order reg value */
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if ((opr & 0xF) == 0x9)
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dest = s_adfd(td, source, &CC); /* add */
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else
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else
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dest = s_sufd(td, source, &CC); /* subtract */
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PSD1 &= 0x87FFFFFE; /* clear the old CC's */
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PSD1 |= (CC & 0x78000000); /* update the CC's in the PSD */
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@ -2708,16 +2776,45 @@ src:
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dest = temp; /* put in dest to go out */
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break;
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case 0x84>>2: /* 0x84 SCC|SD|RR|RM|ADR - SD|RM|ADR */ /* ANMx */
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dest &= source;
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case 0x84>>2: /* 0x84 SCC|SD|RR|RNX|ADR - SD|RNX|ADR */ /* ANMx */
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// dest &= source;
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td = dest & source; /* DO ANMX */
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goto meoa;
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break;
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case 0x88>>2: /* 0x88 SCC|SD|RR|RM|ADR - SD|RM|ADR */ /* ORMx */
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dest |= source;
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case 0x88>>2: /* 0x88 SCC|SD|RR|RNX|ADR - SD|RNX|ADR */ /* ORMx */
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// dest |= source;
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td = dest | source; /* DO ORMX */
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goto meoa;
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break;
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case 0x8C>>2: /* 0x8C SCC|SD|RR|RM|ADR - SD|RM|ADR */ /* EOMx */
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dest ^= source;
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case 0x8C>>2: /* 0x8C SCC|SD|RR|RNX|ADR - SD|RNX|ADR */ /* EOMx */
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/* must special handle because we are getting bit difference */
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/* for word, halfword, & byte zero the upper 32 bits of dest */
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td = dest ^ source; /* DO EOMX */
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meoa:
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switch(FC) { /* adjust for hw or bytes */
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case 4: case 5: case 6: case 7: /* byte address */
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/* EOMB */
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td &= 0xff; /* mask out right most byte */
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dest &= 0xffffff00; /* make place for byte */
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break;
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case 1: /* left halfword addr */
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case 3: /* right halfword addr */
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/* EOMH */
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td &= RMASK; /* mask out right most 16 bits */
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dest &= LMASK; /* make place for halfword */
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break;
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case 0: /* 32 bit word */
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/* EOMW */
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td &= D32RMASK; /* mask out right most 32 bits */
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/* drop through */
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case 2: /* 64 bit double */
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/* EOMD */
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dest = 0; /* make place for 64 bits */
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break;
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}
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dest |= td; /* insert result into dest */
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break;
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case 0x90>>2: /* 0x90 SCC|RR|RM|ADR - RM|ADR */ /* CAMx */
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@ -2851,6 +2948,21 @@ src:
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goto inv; /* invalid instruction */
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}
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EXM_EXR = 4; /* set PC increment for EXM */
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#ifdef TRME /* set to 1 for traceme to work */
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/* no trap, so continue with next instruction */
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if (traceme >= trstart) {
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OPSD1 &= 0x87FFFFFE; /* clear the old CC's */
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OPSD1 |= PSD1 & 0x78000000; /* update the CC's in the PSD */
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if (modes & MAPMODE)
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fprintf(stderr, "M%.8x %.8x ", OPSD1, OIR);
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else
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fprintf(stderr, "U%.8x %.8x ", OPSD1, OIR);
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fprint_inst(stderr, OIR, 0); /* display instruction */
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fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
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fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
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fprintf(stderr, "\r\n");
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}
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#endif
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goto exec; /* go execute the instruction */
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case 0xAC>>2: /* 0xAC SCC|SD|RM|ADR - SD|RM|ADR */ /* Lx */
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@ -3127,6 +3239,21 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
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goto inv; /* invalid instruction */
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}
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EXM_EXR = 4; /* set PC increment for EXR */
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#ifdef TRME /* set to 1 for traceme to work */
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/* no trap, so continue with next instruction */
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if (traceme >= trstart) {
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OPSD1 &= 0x87FFFFFE; /* clear the old CC's */
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OPSD1 |= PSD1 & 0x78000000; /* update the CC's in the PSD */
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if (modes & MAPMODE)
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fprintf(stderr, "M%.8x %.8x ", OPSD1, OIR);
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else
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fprintf(stderr, "U%.8x %.8x ", OPSD1, OIR);
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fprint_inst(stderr, OIR, 0); /* display instruction */
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fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
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fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
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fprintf(stderr, "\r\n");
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}
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#endif
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goto exec;
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break;
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@ -3150,11 +3277,17 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
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TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
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goto newpsd; /* go execute the trap now */
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}
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temp = addr;
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temp2 = reg;
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bc = addr & 0x20; /* bit 26 initial value */
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while (reg < 8) {
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if (bc != (addr & 0x20)) { /* test for crossing file boundry */
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if (CPU_MODEL < MODEL_27) {
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TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
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//fprintf(stderr, "LF reg %x %x addr %x %x\r\n", temp2, reg, temp, addr);
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goto newpsd; /* go execute the trap now */
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}
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//fprintf(stderr, "LF reg %x %x addr %x %x\r\n", temp2, reg, temp, addr);
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}
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if (FC & 0x4) /* LFBR? */
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TRAPME = Mem_read(addr, &BR[reg]); /* read the base reg */
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@ -3168,10 +3301,14 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
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break;
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|
||||
case 0xD0>>2: /* 0xD0 SD|ADR - INV */ /* LEA none basemode only */
|
||||
dest = (t_uint64)(addr);
|
||||
break;
|
||||
dest = (t_uint64)(addr);
|
||||
//fprintf(stderr, "LEA AD02 opr %x FC %x addr = %x dest %lx\r\n", IR, FC, addr, dest);
|
||||
break;
|
||||
|
||||
case 0xD4>>2: /* 0xD4 SM|ADR - SM|ADR */ /* STx */
|
||||
//if (IR & IND) {
|
||||
//fprintf(stderr, "STX AD02 opr %x FC %x addr = %x dest %lx\r\n", IR, FC, addr, dest);
|
||||
//}
|
||||
break;
|
||||
|
||||
case 0xD8>>2: /* 0xD8 SM|ADR - SM|ADR */ /* STMx */
|
||||
@ -3179,46 +3316,62 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
|
||||
if (dbl) {
|
||||
/* we need to and both regs */
|
||||
t_uint64 nm = (((t_uint64)GPR[4]) << 32) | (((t_uint64)GPR[4]) & D32RMASK);
|
||||
dest &= nm; /* mask both regs with reg 4 contents */
|
||||
dest &= nm; /* mask both regs with reg 4 contents */
|
||||
} else {
|
||||
dest &= (((t_uint64)GPR[4]) & D32RMASK); /* mask with reg 4 contents */
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xDC>>2: /* 0xDC INV - */ /* INV nonbasemode (STFx basemode) */
|
||||
case 0xDC>>2: /* 0xDC INV - */ /* INV nonbasemode (STFx basemode) */
|
||||
/* DC00 STF */ /* DC08 STFBR */
|
||||
if ((FC & 0x4) && (CPU_MODEL <= MODEL_27)) {
|
||||
/* basemode undefined for 32/7x & 32/27 */ /* TODO check this */
|
||||
TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
|
||||
goto newpsd; /* handle trap */
|
||||
TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
|
||||
goto newpsd; /* handle trap */
|
||||
}
|
||||
/* For machines with Base mode 0xDC08 stores base registers */
|
||||
if ((FC & 3) != 0) { /* must be word address */
|
||||
TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
bc = addr & 0x20; /* bit 26 initial value */
|
||||
while (reg < 8) {
|
||||
if (bc != (addr & 0x20)) { /* test for crossing file boundry */
|
||||
TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
if (FC & 0x4) /* STFBR? */
|
||||
TRAPME = Mem_write(addr, &BR[reg]); /* store the base reg */
|
||||
else /* STF */
|
||||
TRAPME = Mem_write(addr, &GPR[reg]); /* store the GPR reg */
|
||||
if (TRAPME) /* TRAPME has error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
reg++; /* next reg to write */
|
||||
addr += 4; /* next addr */
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xE0>>2: /* 0xE0 RM|ADR - RM|ADR */ /* ADFx, SUFx */
|
||||
if ((FC & 3) != 0) { /* must be word address */
|
||||
TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
temp = addr;
|
||||
temp2 = reg;
|
||||
bc = addr & 0x20; /* bit 26 initial value */
|
||||
while (reg < 8) {
|
||||
if (bc != (addr & 0x20)) { /* test for crossing file boundry */
|
||||
if (CPU_MODEL < MODEL_27) {
|
||||
TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
|
||||
//fprintf(stderr, "STF reg %x %x addr %x %x\r\n", temp2, reg, temp, addr);
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
//fprintf(stderr, "STF reg %x %x addr %x %x\r\n", temp2, reg, temp, addr);
|
||||
}
|
||||
if (FC & 0x4) /* STFBR? */
|
||||
TRAPME = Mem_write(addr, &BR[reg]); /* store the base reg */
|
||||
else /* STF */
|
||||
TRAPME = Mem_write(addr, &GPR[reg]); /* store the GPR reg */
|
||||
if (TRAPME) /* TRAPME has error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
reg++; /* next reg to write */
|
||||
addr += 4; /* next addr */
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xE0>>2: /* 0xE0 ADR - ADR */ /* ADFx, SUFx */
|
||||
if ((TRAPME = Mem_read(addr, &temp))) { /* get the word from memory */
|
||||
goto newpsd; /* memory read error or map fault */
|
||||
}
|
||||
source = (t_uint64)temp; /* make into 64 bit value */
|
||||
if (FC & 2) { /* see if double word addr */
|
||||
if ((TRAPME = Mem_read(addr+4, &temp))) { /* get the 2nd word from memory */
|
||||
goto newpsd; /* memory read error or map fault */
|
||||
}
|
||||
source = (source << 32) | (t_uint64)temp; /* merge in the low order 32 bits */
|
||||
dbl = 1; /* double word instruction */
|
||||
} else {
|
||||
source |= (source & MSIGN) ? D32LMASK : 0;
|
||||
dbl = 0; /* not double wd */
|
||||
}
|
||||
PSD1 &= 0x87FFFFFE; /* clear the old CC's */
|
||||
CC = 0; /* clear the CC'ss */
|
||||
/* handle float or double add/sub instructions */
|
||||
@ -3279,10 +3432,20 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
|
||||
}
|
||||
break;
|
||||
|
||||
case 0xE4>>2: /* 0xE4 RM|ADR - RM|ADR */ /* MPFx, DVFx */
|
||||
if ((FC & 3) != 0) { /* must be word address */
|
||||
TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */
|
||||
goto newpsd; /* go execute the trap now */
|
||||
case 0xE4>>2: /* 0xE4 ADR - ADR */ /* MPFx, DVFx */
|
||||
if ((TRAPME = Mem_read(addr, &temp))) { /* get the word from memory */
|
||||
goto newpsd; /* memory read error or map fault */
|
||||
}
|
||||
source = (t_uint64)temp; /* make into 64 bit value */
|
||||
if (FC & 2) { /* see if double word addr */
|
||||
if ((TRAPME = Mem_read(addr+4, &temp))) { /* get the 2nd word from memory */
|
||||
goto newpsd; /* memory read error or map fault */
|
||||
}
|
||||
source = (source << 32) | (t_uint64)temp; /* merge in the low order 32 bits */
|
||||
dbl = 1; /* double word instruction */
|
||||
} else {
|
||||
source |= (source & MSIGN) ? D32LMASK : 0;
|
||||
dbl = 0; /* not double wd */
|
||||
}
|
||||
PSD1 &= 0x87FFFFFE; /* clear the old CC's */
|
||||
CC = 0; /* clear the CC'ss */
|
||||
@ -3291,7 +3454,7 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
|
||||
/* do MPFW or DIVW instructions */
|
||||
temp2 = GPR[reg]; /* dest - reg contents specified by Rd */
|
||||
addr = (uint32)(source & D32RMASK); /* get 32 bits from source memory */
|
||||
if ((opr & 0xf) == 0x8) { /* Was it MPFW? */
|
||||
if ((opr & 0xf) == 0x8) { /* Was it MPFW? */
|
||||
temp = s_mpfw(temp2, addr, &CC); /* do MPFW */
|
||||
} else {
|
||||
temp = s_dvfw(temp2, addr, &CC); /* do DVFW */
|
||||
@ -3362,11 +3525,11 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
|
||||
}
|
||||
if (t) { /* see if we are going to branch */
|
||||
/* we are taking the branch, set CC's if indirect, else leave'm */
|
||||
if (IR & IND) /* see if CCs from last indirect are wanted */
|
||||
PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */
|
||||
/* update the PSD with new address */
|
||||
PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */
|
||||
i_flags |= BT; /* we branched, so no PC update */
|
||||
if (IR & IND) /* see if CCs from last indirect are wanted */
|
||||
PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */
|
||||
}
|
||||
/* branch not taken, go do next instruction */
|
||||
break;
|
||||
@ -3487,11 +3650,33 @@ if (((temp2>>2) == 1) && ((IR&0xfff) == 0x75))
|
||||
/* map bit must be on to load maps */
|
||||
if (PSD2 & MAPBIT) {
|
||||
#ifdef TRME /* set to 1 for traceme to work */
|
||||
// FIXME DEBUG MACLIBR
|
||||
// if (n[0] == 'M' && n[1] == 'A' && n[2] == 'C' && n[3] == 'L')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG FILEMGR
|
||||
// if (n[0] == 'F' && n[1] == 'I' && n[2] == 'L' && n[3] == 'E')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG EDIT
|
||||
// if (n[0] == 'E' && n[1] == 'D' && n[2] == 'I' && n[3] == 'T')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG SYSGEN
|
||||
//if (n[0] == 'S' && n[1] == 'Y' && n[2] == 'S' && n[3] == 'G')
|
||||
// FIXME DEBUG LOG
|
||||
// traceme = trstart; /* start tracing */
|
||||
//if (n[0] == 'L' && n[1] == 'O' && n[2] == 'G')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG ASSEMBLER
|
||||
// if (n[0] == 'A' && n[1] == 'S' && n[2] == 'S')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG FORTRAN
|
||||
//if (n[0] == 'F' && n[1] == 'O' && n[2] == 'R' && n[3] == 'T')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG COMPRESS
|
||||
//if (n[0] == 'C' && n[1] == 'O' && n[2] == 'M' && n[3] == 'P')
|
||||
// traceme = trstart; /* start tracing */
|
||||
// FIXME DEBUG J.TSM
|
||||
if (n[0] == 'J' && n[1] == '.' && n[2] == 'T' && n[3] == 'S')
|
||||
traceme = trstart; /* start tracing */
|
||||
traceme++; /* start trace */
|
||||
//if (traceme >= trstart) {
|
||||
fprintf(stderr, "LPSDCM #%d LOAD MAPS PSD1 %x PSD2 %x SPAD PSD2 %x CPUSTATUS %x C.CURR %x LMN %s\r\n", traceme, PSD1, PSD2, SPAD[0xf5], CPUSTATUS, dqe, n);
|
||||
@ -3914,6 +4099,7 @@ mcheck:
|
||||
case 2: /* double word store */
|
||||
if ((addr & 2) != 2) {
|
||||
TRAPME = ADDRSPEC_TRAP; /* address not on dbl wd boundry, error */
|
||||
//fprintf(stderr, "SM AD02 DBL WD opr %x FC %x addr = %x dest %lx\r\n", opr, FC, addr, dest);
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
temp = (uint32)(dest & MASK32);/* get lo 32 bit */
|
||||
@ -3927,6 +4113,7 @@ mcheck:
|
||||
if ((addr & 3) != 0) {
|
||||
/* Address fault */
|
||||
TRAPME = ADDRSPEC_TRAP; /* address not on wd boundry, error */
|
||||
//fprintf(stderr, "SM AD02 WD opr %x FC %x addr = %x dest %x\r\n", opr, FC, addr, temp);
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
break;
|
||||
@ -3937,6 +4124,7 @@ mcheck:
|
||||
if ((addr & 1) != 1) {
|
||||
/* Address fault */
|
||||
TRAPME = ADDRSPEC_TRAP; /* address not on hw boundry, error */
|
||||
//fprintf(stderr, "SM AD02 LHWD opr %x FC %x addr = %x dest %x\r\n", opr, FC, addr, temp);
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
break;
|
||||
@ -3946,6 +4134,7 @@ mcheck:
|
||||
temp |= (uint32)(dest & RMASK); /* put into right most 16 bits */
|
||||
if ((addr & 3) != 3) {
|
||||
TRAPME = ADDRSPEC_TRAP; /* address not on hw boundry, error */
|
||||
//fprintf(stderr, "SM AD02 RHWD opr %x FC %x addr = %x dest %x\r\n", opr, FC, addr, temp);
|
||||
goto newpsd; /* go execute the trap now */
|
||||
}
|
||||
break;
|
||||
@ -3980,18 +4169,19 @@ mcheck:
|
||||
}
|
||||
|
||||
/* Update instruction pointer to next instruction */
|
||||
if (EXM_EXR != 0) { /* special handling for EXM, EXR, EXRR */
|
||||
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
|
||||
EXM_EXR = 0; /* reset PC increment for EXR */
|
||||
} else
|
||||
if ((i_flags & BT) == 0) { /* see if PSD was replaced on a branch instruction */
|
||||
/* branch not taken, so update the PC */
|
||||
if (EXM_EXR != 0) { /* special handling for EXM, EXR, EXRR */
|
||||
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
|
||||
EXM_EXR = 0; /* reset PC increment for EXR */
|
||||
} else
|
||||
if (i_flags & HLF) {
|
||||
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1);
|
||||
} else {
|
||||
PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1);
|
||||
}
|
||||
}
|
||||
} else
|
||||
EXM_EXR = 0; /* reset PC increment for EXR */
|
||||
|
||||
/* check if we had an arithmetic exception on the last instruction*/
|
||||
if (ovr && (modes & AEXPBIT)) {
|
||||
@ -4048,7 +4238,11 @@ newpsd:
|
||||
default:
|
||||
tta = tta + (TRAPME - 0x80); /* tta has mem addr of trap vector */
|
||||
tvl = M[tta>>2] & 0x7FFFC; /* get trap vector address from trap vector loc */
|
||||
//fprintf(stderr, "tvl %.8x, tta %.8x status %.8x\r\n", tvl, tta, CPUSTATUS);
|
||||
#ifdef TRME /* set to 1 for traceme to work */
|
||||
sim_debug(DEBUG_EXP, &cpu_dev, "TRAP PSD1 %x PSD2 %x CPUSTATUS %x\r\n", PSD1, PSD2, CPUSTATUS);
|
||||
fprintf(stderr, "Before TRAPS %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x\r\n", TRAPME, PSD1, PSD2, CPUSTATUS);
|
||||
fprintf(stderr, "tvl %.8x, tta %.8x status %.8x\r\n", tvl, tta, CPUSTATUS);
|
||||
#endif
|
||||
if (tvl == 0 || tvl == 0x7FFFC || (CPUSTATUS & 0x40) == 0) {
|
||||
/* vector is zero or software has not enabled traps yet */
|
||||
/* execute a trap halt */
|
||||
@ -4099,8 +4293,9 @@ fprintf(stderr, "[][][][][][][][][][][] HALT TRAP [][][][][][][][][][][][]\r\n")
|
||||
SPAD[0xf5] = PSD2; /* save the current PSD2 */
|
||||
#ifdef TRME /* set to 1 for traceme to work */
|
||||
//if (TRAPME == UNDEFINSTR_TRAP || TRAPME == MAPFAULT_TRAP) {
|
||||
if (TRAPME == MAPFAULT_TRAP) {
|
||||
sim_debug(DEBUG_EXP, &cpu_dev, "TRAP PSD1 %x PSD2 %x CPUSTATUS %x\n", PSD1, PSD2, CPUSTATUS);
|
||||
//if (TRAPME == MAPFAULT_TRAP) {
|
||||
if (TRAPME == ADDRSPEC_TRAP) {
|
||||
sim_debug(DEBUG_EXP, &cpu_dev, "TRAP PSD1 %x PSD2 %x CPUSTATUS %x\r\n", PSD1, PSD2, CPUSTATUS);
|
||||
fprintf(stderr, "TRAPS %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x\r\n", TRAPME, PSD1, PSD2, CPUSTATUS);
|
||||
goto dumpi;
|
||||
}
|
||||
@ -4127,11 +4322,13 @@ fprint_inst(stderr, OIR, 0); /* display instruction */
|
||||
fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
|
||||
fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
|
||||
fprintf(stderr, "\r\n");
|
||||
#if 0
|
||||
fprintf(stderr, "Current MAPC\r\n");
|
||||
for (ix=0; ix<16; ix++) {
|
||||
fprintf(stderr, "MAP %x MPC %x\r\n", ix/2, MAPC[ix]);
|
||||
}
|
||||
fflush(stderr);
|
||||
#endif
|
||||
//if (TRAPME == UNDEFINSTR_TRAP || TRAPME == MAPFAULT_TRAP)
|
||||
if (TRAPME == MAPFAULT_TRAP)
|
||||
return STOP_HALT; /* exit to simh for halt */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user