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KA10: Fixed handling of CCW complete flag to match documentations.

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This commit is contained in:
Richard Cornwell 2022-04-25 17:44:42 -04:00
parent 047beb0e3e
commit 56d5ca2823
8 changed files with 21 additions and 26 deletions
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5
PDP10/kx10_defs.h
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@ -346,11 +346,9 @@ extern DEBTAB crd_debug[];
#define API_MASK 0000000007
#define PI_ENABLE 0000000010 /* Clear DONE */
#define BUSY 0000000020 /* STOP */
#define CCW_COMP 0000000040 /* Write Final CCW */
/* RH10 / RH20 interrupt */
#define IADR_ATTN 0000000000040LL /* Interrupt on attention */
#define IARD_RAE 0000000000100LL /* Interrupt on register access error */
#define CCW_COMP_1 0000000040000LL /* Control word written. */
#if KI
#define DEF_SERIAL 514 /* Default DEC test machine */
@ -627,7 +625,6 @@ struct df10 {
uint32 devnum; /* Device number */
uint64 buf; /* Data buffer */
uint8 nxmerr; /* Bit to set for NXM */
uint8 ccw_comp; /* Have we written out CCW */
uint64 amask; /* Address mask */
uint64 wmask; /* Word mask */
int cshift; /* Shift amount */
@ -686,7 +683,7 @@ void df10_setup(struct df10 *df, uint32 addr);
int df10_fetch(struct df10 *df);
int df10_read(struct df10 *df);
int df10_write(struct df10 *df);
void df10_init(struct df10 *df, uint32 dev_num, uint8 nxmerr, uint8 ccw_comp);
void df10_init(struct df10 *df, uint32 dev_num, uint8 nxmerr);
#if PDP6_DEV
int dct_read(int u, t_uint64 *data, int c);
int dct_write(int u, t_uint64 *data, int c);

5
PDP10/kx10_df.c
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@ -35,7 +35,6 @@ df10_setirq(struct df10 *df) {
void
df10_writecw(struct df10 *df) {
uint64 wrd;
df->status |= 1 << df->ccw_comp;
if (df->wcr != 0)
df->cda++;
wrd = ((uint64)(df->ccw & df->wmask) << df->cshift) | ((uint64)(df->cda) & df->amask);
@ -58,7 +57,6 @@ df10_setup(struct df10 *df, uint32 addr) {
df->ccw = df->cia;
df->wcr = 0;
df->status |= BUSY;
df->status &= ~(1 << df->ccw_comp);
}
/* Fetch the next IO control word */
@ -161,12 +159,11 @@ df10_write(struct df10 *df) {
/* Initialize a DF10 to default values */
void
df10_init(struct df10 *df, uint32 dev_num, uint8 nxmerr, uint8 ccw_comp)
df10_init(struct df10 *df, uint32 dev_num, uint8 nxmerr)
{
df->status = 0;
df->devnum = dev_num; /* Set device number link */
df->nxmerr = nxmerr; /* Set bit in status for NXM */
df->ccw_comp = ccw_comp; /* Set bit number indicating CCW wanted */
#if KI_22BIT
if (cpu_unit[0].flags & UNIT_DF10C) {
df->amask = 00000017777777LL;

9
PDP10/kx10_dp.c
View File

@ -68,6 +68,7 @@
/* CONI/CONO Flags */
#define CCW_COMP 0000000000040LL
#define SUF_ERR 0000000000100LL
#define SEC_ERR 0000000000200LL
#define ILL_CMD 0000000000400LL
@ -295,7 +296,6 @@ REG dpa_reg[] = {
{ORDATA(DEVNUM, dp_df10[0].devnum, 9), REG_HRO},
{ORDATA(BUF, dp_df10[0].buf, 36), REG_HRO},
{ORDATA(NXM, dp_df10[0].nxmerr, 8), REG_HRO},
{ORDATA(COMP, dp_df10[0].ccw_comp, 8), REG_HRO},
{0}
};
@ -319,7 +319,6 @@ REG dpb_reg[] = {
{ORDATA(DEVNUM, dp_df10[1].devnum, 9), REG_HRO},
{ORDATA(BUF, dp_df10[1].buf, 36), REG_HRO},
{ORDATA(NXM, dp_df10[1].nxmerr, 8), REG_HRO},
{ORDATA(COMP, dp_df10[1].ccw_comp, 8), REG_HRO},
{0}
};
@ -343,7 +342,6 @@ REG dpc_reg[] = {
{ORDATA(DEVNUM, dp_df10[2].devnum, 9), REG_HRO},
{ORDATA(BUF, dp_df10[2].buf, 36), REG_HRO},
{ORDATA(NXM, dp_df10[2].nxmerr, 8), REG_HRO},
{ORDATA(COMP, dp_df10[2].ccw_comp, 8), REG_HRO},
{0}
};
@ -367,7 +365,6 @@ REG dpd_reg[] = {
{ORDATA(DEVNUM, dp_df10[3].devnum, 9), REG_HRO},
{ORDATA(BUF, dp_df10[3].buf, 36), REG_HRO},
{ORDATA(NXM, dp_df10[3].nxmerr, 8), REG_HRO},
{ORDATA(COMP, dp_df10[3].ccw_comp, 8), REG_HRO},
{0}
};
@ -443,7 +440,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) {
uptr->STATUS &= ~(CLRMSK2);
if (*data & CCW_COMP) {
df10_writecw(df10);
df10->status &= ~CCW_COMP;
df10->status |= CCW_COMP;
}
if (*data & PI_ENABLE) {
uptr->UFLAGS &= ~DONE;
@ -914,7 +911,7 @@ dp_reset(DEVICE * dptr)
uptr++;
}
for (ctlr = 0; ctlr < NUM_DEVS_DP; ctlr++) {
df10_init(&dp_df10[ctlr], dp_dib[ctlr].dev_num, 12, 5);
df10_init(&dp_df10[ctlr], dp_dib[ctlr].dev_num, 12);
}
return SCPE_OK;
}

12
PDP10/kx10_mt.c
View File

@ -222,7 +222,6 @@ REG mt_reg[] = {
{ORDATA(DEVNUM, mt_df10.devnum, 9), REG_HRO},
{ORDATA(BUF, mt_df10.buf, 36), REG_HRO},
{ORDATA(NXM, mt_df10.nxmerr, 8), REG_HRO},
{ORDATA(COMP, mt_df10.ccw_comp, 8), REG_HRO},
{0}
};
@ -405,8 +404,10 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
mt_hold_reg ^= mt_df10.buf;
}
if (dptr->flags & MTDF_TYPEB) {
if (*data & 04)
if (*data & 04) {
df10_writecw(&mt_df10);
mt_status |= WT_CW_DONE;
}
if (*data & 010)
mt_status &= ~(WT_CW_DONE);
}
@ -420,9 +421,10 @@ t_stat mt_devio(uint32 dev, uint64 *data) {
case DATAO|04:
/* Set Initial CCW */
if (dptr->flags & MTDF_TYPEB)
if (dptr->flags & MTDF_TYPEB) {
df10_setup(&mt_df10, (uint32) *data);
else
mt_status &= ~(WT_CW_DONE);
} else
mt_df10.buf ^= mt_hold_reg;
sim_debug(DEBUG_DATAIO, dptr, "MT DATAO %03o %012llo\n", dev, *data);
break;
@ -1035,7 +1037,7 @@ mt_reset(DEVICE * dptr)
uptr->CNTRL = 0;
sim_cancel(uptr);
}
df10_init(&mt_df10, mt_dib.dev_num, 24, 25);
df10_init(&mt_df10, mt_dib.dev_num, 24);
mt_pia = 0;
mt_status = 0;
mt_sel_unit = 0;

7
PDP10/kx10_rc.c
View File

@ -78,6 +78,7 @@
#define NXM_ERR 0000000000400LL /* Non existant memory */
#define ILL_WR 0000000000200LL /* Write to protected area */
#define OVRRUN 0000000000100LL /* Over run */
#define CCW_COMP 0000000000040LL /* Control word written */
#define RD10_DTYPE 0
#define RD10_WDS 32
@ -172,7 +173,6 @@ REG rca_reg[] = {
{ORDATA(DEVNUM, rc_df10[0].devnum, 9), REG_HRO},
{ORDATA(BUF, rc_df10[0].buf, 36), REG_HRO},
{ORDATA(NXM, rc_df10[0].nxmerr, 8), REG_HRO},
{ORDATA(COMP, rc_df10[0].ccw_comp, 8), REG_HRO},
{0}
};
@ -196,7 +196,6 @@ REG rcb_reg[] = {
{ORDATA(DEVNUM, rc_df10[1].devnum, 9), REG_HRO},
{ORDATA(BUF, rc_df10[1].buf, 36), REG_HRO},
{ORDATA(NXM, rc_df10[1].nxmerr, 8), REG_HRO},
{ORDATA(COMP, rc_df10[1].ccw_comp, 8), REG_HRO},
{0}
};
@ -270,6 +269,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
if ((df10->status & BUSY) != 0 && (*data & CCW_COMP) != 0) {
df10_writecw(df10);
df10->status |= CCW_COMP;
} else
df10->status &= ~CCW_COMP;
sim_debug(DEBUG_CONO, dptr, "HK %03o CONO %06o PC=%o %06o\n", dev,
@ -310,6 +310,7 @@ t_stat rc_devio(uint32 dev, uint64 *data) {
return SCPE_OK;
}
df10_setup(df10, (uint32)*data);
df10->status &= ~CCW_COMP;
tmp = (uint32)(*data >> 15) & ~07;
cyl = (tmp >> 10) & 0777;
if (((cyl & 017) > 9) || (((cyl >> 4) & 017) > 9)) {
@ -490,7 +491,7 @@ rc_reset(DEVICE * dptr)
}
for (ctlr = 0; ctlr < NUM_DEVS_RC; ctlr++) {
rc_ipr[ctlr] = 0;
df10_init(&rc_df10[ctlr], rc_dib[ctlr].dev_num, 8, 5);
df10_init(&rc_df10[ctlr], rc_dib[ctlr].dev_num, 8);
}
return SCPE_OK;
}

5
PDP10/kx10_rh.c
View File

@ -652,8 +652,10 @@ t_stat rh_devio(uint32 dev, uint64 *data) {
rhc->status &= ~(CXR_ILFC|CXR_SD_RAE);
if (*data & DRE_CLR)
rhc->status &= ~(CR_DRE);
if (*data & WRT_CW)
if (*data & WRT_CW) {
rh_writecw(rhc, 0);
rhc->status |= (CCW_COMP_1);
}
if (*data & PI_ENABLE)
rhc->status &= ~PI_ENABLE;
if (rhc->status & PI_ENABLE)
@ -914,7 +916,6 @@ void rh_writecw(struct rh_if *rhc, int nxm) {
#endif
if (nxm)
rhc->status |= CXR_NXM;
rhc->status |= CCW_COMP_1;
if (rhc->wcr != 0)
rhc->cda++;
wrd1 = ((uint64)(rhc->ccw & WMASK) << CSHIFT) | ((uint64)(rhc->cda) & AMASK);

2
PDP10/kx10_rp.c
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@ -1207,7 +1207,7 @@ if (len == 0)
#endif
#if !KS
rhc->reg = 040;
rhc->status |= CCW_COMP_1|PI_ENABLE;
rhc->status |= PI_ENABLE;
#endif
rhc->drive = uptr - dptr->units;
PC = word & RMASK;

2
PDP10/kx10_rs.c
View File

@ -650,7 +650,7 @@ rs_boot(int32 unit_num, DEVICE * rptr)
word = rs_buf[0][ptr++];
rhc->reg = 040;
rhc->drive = uptr - dptr->units;
rhc->status |= CCW_COMP_1|PI_ENABLE;
rhc->status |= PI_ENABLE;
PC = word & RMASK;
return SCPE_OK;