mirror of
https://github.com/rcornwell/sims.git
synced 2026-01-13 15:27:04 +00:00
KA10: Fixed bug with RH10 auto configure.
This commit is contained in:
parent
1268c3815c
commit
5af5310fed
@ -469,6 +469,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
|
||||
break;
|
||||
}
|
||||
df10 = &rp_df10[ctlr];
|
||||
df10->devnum = dev;
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
*data = df10->status & ~(IADR_ATTN|IARD_RAE);
|
||||
@ -659,7 +660,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
uptr->u3 |= DS_DRY;
|
||||
uptr->u3 &= ~(DS_ATA|CR_GO);
|
||||
rp_attn[ctlr] &= ~(1<<unit);
|
||||
clr_interrupt(rp_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0)
|
||||
df10_setirq(df10);
|
||||
break;
|
||||
@ -707,7 +708,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
rp_attn[ctlr] &= ~(1<<i);
|
||||
}
|
||||
}
|
||||
clr_interrupt(rp_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
if (((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) ||
|
||||
(df10->status & PI_ENABLE))
|
||||
df10_setirq(df10);
|
||||
|
||||
@ -315,6 +315,7 @@ t_stat rs_devio(uint32 dev, uint64 *data) {
|
||||
break;
|
||||
}
|
||||
df10 = &rs_df10[ctlr];
|
||||
df10->devnum = dev;
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
*data = df10->status & ~(IADR_ATTN|IARD_RAE);
|
||||
@ -499,7 +500,7 @@ rs_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
uptr->u3 |= DS_DRY;
|
||||
uptr->u3 &= ~(DS_ATA|CR_GO);
|
||||
rs_attn[ctlr] = 0;
|
||||
clr_interrupt(rs_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (rs_unit[(ctlr * 8) + i].u3 & DS_ATA)
|
||||
rs_attn[ctlr] = 1;
|
||||
@ -538,7 +539,7 @@ rs_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
if (rs_unit[(ctlr * 8) + i].u3 & DS_ATA)
|
||||
rs_attn[ctlr] = 1;
|
||||
}
|
||||
clr_interrupt(rs_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
if (((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) ||
|
||||
(df10->status & PI_ENABLE))
|
||||
df10_setirq(df10);
|
||||
|
||||
@ -300,6 +300,7 @@ t_stat tu_devio(uint32 dev, uint64 *data) {
|
||||
break;
|
||||
}
|
||||
df10 = &tu_df10[ctlr];
|
||||
df10->devnum = dev;
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
*data = df10->status & ~(IADR_ATTN|IARD_RAE);
|
||||
@ -498,7 +499,7 @@ tu_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
uptr->u3 &= ~(CS_ATA|CR_GO|CS_TM);
|
||||
uptr->u5 = 0;
|
||||
tu_attn[ctlr] = 0;
|
||||
clr_interrupt(tu_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (tu_unit[(ctlr * 8) + i].u3 & CS_ATA)
|
||||
tu_attn[ctlr] = 1;
|
||||
@ -533,7 +534,7 @@ tu_write(int ctlr, int unit, int reg, uint32 data) {
|
||||
if (tu_unit[(ctlr * 8) + i].u3 & CS_ATA)
|
||||
tu_attn[ctlr] = 1;
|
||||
}
|
||||
clr_interrupt(tu_dib[ctlr].dev_num);
|
||||
clr_interrupt(df10->devnum);
|
||||
if (((df10->status & IADR_ATTN) != 0 && tu_attn[ctlr] != 0) ||
|
||||
(df10->status & PI_ENABLE))
|
||||
df10_setirq(df10);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user