From 5b4f4c2be013ed59a1eb09a7dbee4ff57fa7c920 Mon Sep 17 00:00:00 2001 From: Richard Cornwell Date: Wed, 18 Oct 2017 23:44:04 -0400 Subject: [PATCH] I7000: Fixed Coverity errors. --- I7000/i7000_cdr.c | 2 ++ I7000/i7000_mt.c | 4 ++++ I7000/i7010_cpu.c | 2 +- I7000/i7090_lpr.c | 18 +++++++++++++----- 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/I7000/i7000_cdr.c b/I7000/i7000_cdr.c index f5da1c3..17063a9 100644 --- a/I7000/i7000_cdr.c +++ b/I7000/i7000_cdr.c @@ -204,6 +204,8 @@ cdr_srv(UNIT *uptr) { switch(sim_read_card(uptr)) { case SCPE_EOF: sim_debug(DEBUG_DETAIL, &cdr_dev, "%d: EOF\n", u); + /* Fall through */ + case SCPE_UNATT: chan_set_eof(chan); chan_set_attn(chan); diff --git a/I7000/i7000_mt.c b/I7000/i7000_mt.c index 600be79..a9f4244 100644 --- a/I7000/i7000_mt.c +++ b/I7000/i7000_mt.c @@ -988,6 +988,10 @@ t_stat mt_srv(UNIT * uptr) /* If no data was written, simulate a write gap */ if (uptr->u6 == 0) { r = sim_tape_wrgap(uptr, 35); + if (r != MTSE_OK) { + mt_error(uptr, chan, r, dptr); /* Record errors */ + return SCPE_OK; + } } #endif chan_set_attn(chan); diff --git a/I7000/i7010_cpu.c b/I7000/i7010_cpu.c index 106ac5e..ee4e5c0 100644 --- a/I7000/i7010_cpu.c +++ b/I7000/i7010_cpu.c @@ -3909,7 +3909,7 @@ cpu_show_hist(FILE * st, UNIT * uptr, int32 val, CONST void *desc) fputc(' ', st); for(i = 0; i< 15; i++) sim_eval[i] = h->inst[i]; - fprint_sym(st, pc, sim_eval, &cpu_unit, SWMASK((h->ic & HIST_1401)?'N':'M')); + (void)fprint_sym(st, pc, sim_eval, &cpu_unit, SWMASK((h->ic & HIST_1401)?'N':'M')); fputc('\n', st); /* end line */ } /* end else instruction */ } /* end for */ diff --git a/I7000/i7090_lpr.c b/I7000/i7090_lpr.c index 18d6f83..e666d60 100644 --- a/I7000/i7090_lpr.c +++ b/I7000/i7090_lpr.c @@ -437,7 +437,7 @@ t_stat lpr_srv(UNIT * uptr) /* Check if he write out last data */ if (uptr->u5 & URCSTA_READ) { - int wrow = pos; + int wrow = 0; t_uint64 wd = 0; int action = 0; @@ -469,19 +469,23 @@ t_stat lpr_srv(UNIT * uptr) case 14: case 15: /* Row 2 */ case 16: /* Row 1R */ + wrow = pos; break; case 17: /* Row 1L and start Echo */ + wrow = pos; action = 1; break; case 18: /* Echo 8-4 R */ wd = lpr_data[u].wbuff[2]; wd &= lpr_data[u].wbuff[10]; action = 2; + wrow = pos; break; case 19: /* Echo 8-4 L */ wd = lpr_data[u].wbuff[3]; wd &= lpr_data[u].wbuff[11]; action = 3; + wrow = pos; break; case 20: /* Row 10 R */ wrow = 18; @@ -495,11 +499,13 @@ t_stat lpr_srv(UNIT * uptr) wd = lpr_data[u].wbuff[12]; wd &= lpr_data[u].wbuff[2]; action = 2; + wrow = pos; break; case 23: wd = lpr_data[u].wbuff[13]; wd &= lpr_data[u].wbuff[3]; action = 3; + wrow = pos; break; case 24: /* Row 11 R */ wrow = 20; @@ -511,10 +517,12 @@ t_stat lpr_srv(UNIT * uptr) case 26: /* Echo 9 */ wd = lpr_data[u].wbuff[0]; action = 2; + wrow = pos; break; case 27: wd = lpr_data[u].wbuff[1]; action = 3; + wrow = pos; break; case 28: wrow = 22; @@ -551,14 +559,14 @@ t_stat lpr_srv(UNIT * uptr) if (action == 0 || action == 1) { /* If reading grab next word */ r = chan_read(chan, &lpr_data[u].wbuff[wrow], 0); - sim_debug(DEBUG_DATA, &lpr_dev, "print read row < %d %d %012llo eor=%d\n", pos, wrow, - lpr_data[u].wbuff[wrow], 0); + sim_debug(DEBUG_DATA, &lpr_dev, "print read row < %d %d %012llo eor=%d\n", + pos, wrow, lpr_data[u].wbuff[wrow], 0); if (action == 1) chan_clear(chan, DEV_WRITE); } else { /* action == 2 || action == 3 */ /* Place echo data in buffer */ - sim_debug(DEBUG_DATA, &lpr_dev, "print read row > %d %d %012llo eor=%d\n", pos, wrow, - wd, eor); + sim_debug(DEBUG_DATA, &lpr_dev, "print read row > %d %d %012llo eor=%d\n", + pos, wrow, wd, eor); r = chan_write(chan, &wd, 0); /* Change back to reading */ if (action == 3) {