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SEL32: More instructions.
This commit is contained in:
Richard Cornwell
parent
5decc40fa5
commit
66f4cc4c83
@ -1,6 +1,7 @@
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/* sel32_cpu.c: Sel 32 CPU simulator
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Copyright (c) 2017, Richard Cornwell
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Copyright (c) 2018, Richard Cornwell
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Copyright (c) 2018, James C. Bevier
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -15,9 +16,10 @@
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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RICHARD CORNWELL OR JAMES BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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@ -30,15 +32,6 @@
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#define UNIT_MSIZE (0x1F << UNIT_V_MSIZE)
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#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
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#define MODEL_55 0 /* 512K Mode Only */
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#define MODEL_75 1 /* Extended */
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#define MODEL_27 2 /* */
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#define MODEL_67 3 /* */
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#define MODEL_87 4 /* */
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#define MODEL_97 5 /* */
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#define MODEL_V6 6 /* V6 CPU */
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#define MODEL_V9 7 /* V9 CPU */
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#define TMR_RTC 1
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#define HIST_MIN 64
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@ -52,33 +45,20 @@ uint32 BR[8]; /* Base registers */
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uint32 PC; /* Program counter */
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uint8 CC: /* Condition code register */
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uint32 SPAD[256]; /* Scratch pad memory */
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#define CC1 0x40
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#define CC2 0x20
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#define CC3 0x10
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#define CC4 0x08
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#define AEXP 0x01 /* Arithmetic exception PSD 1 bit 7 */
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/* Held in CC */
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uint8 modes; /* Operating modes */
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#define PRIV 0x80 /* Privileged mode PSD 1 bit 0 */
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#define EXTD 0x04 /* Extended Addressing PSD 1 bit 5 */
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#define BASE 0x02 /* Base Mode PSD 1 bit 6 */
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#define MAP 0x40 /* Map mode, PSD 2 bit 0 */
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#define RET 0x20 /* Retain current map, PSD 2 bit 15 */
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uint8 irq_flags; /* Interrupt control flags PSD 2 bits 16&17 */
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uint16 cpix; /* Current Process index */
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uint16 bpix; /* Base process index */
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struct InstHistory
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{
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uint32 pc;
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uint32 inst;
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uint32 ea;
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uint64 dest;
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uint64 source;
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uint64 res;
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uint8 cc;
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uint32 pc; /* Program counter */
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uint32 inst; /* Instruction register */
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uint32 ea; /* Effective address */
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uint64 dest; /* Destination value */
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uint64 source; /* Source value */
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uint64 res; /* Result value */
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uint8 cc; /* Condition codes */
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};
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t_stat cpu_ex(t_value * vptr, t_addr addr, UNIT * uptr,
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@ -113,41 +93,25 @@ struct InstHistory *hst = NULL; /* History stack */
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UNIT cpu_unit =
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{ UDATA(rtc_srv, UNIT_BINK | MODEL(MODEL_27) | MEMAMOUNT(0),
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MAXMEMSIZE ), 120 };
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uint32 GPR[8]; /* General Purpose Registers */
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uint32 BR[8]; /* Base registers */
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uint32 PC; /* Program counter */
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uint8 CC: /* Condition code register */
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uint32 SPAD[256]; /* Scratch pad memory */
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uint8 modes; /* Operating modes */
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uint8 irq_flags; /* Interrupt control flags PSD 2 bits 16&17 */
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uint16 cpix; /* Current Process index */
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uint16 bpix; /* Base process index */
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uint32 tlb[2048]; /* Translation look asside buffer */
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REG cpu_reg[] = {
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{ORDATAD(IC, IC, 15, "Instruction Counter"), REG_FIT},
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{ORDATAD(AC, AC, 38, "Accumulator"), REG_FIT, 0},
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{ORDATAD(MQ, MQ, 36, "Multiplier Quotent"), REG_FIT, 0},
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{BRDATAD(XR, XR, 8, 15, 8, "Index registers"), REG_FIT},
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{ORDATAD(ID, ID, 36, "Indicator Register")},
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#ifdef EXTRA_SL
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{ORDATAD(SL, SL, 8, "Sense Lights"), REG_FIT},
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#else
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{ORDATAD(SL, SL, 4, "Sense Lights"), REG_FIT},
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#endif
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#ifdef EXTRA_SW
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{ORDATAD(SW, SW, 12, "Sense Switches"), REG_FIT},
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#else
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{ORDATAD(SW, SW, 6, "Sense Switches"), REG_FIT},
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#endif
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#endif
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{ORDATAD(KEYS, KEYS, 36, "Console Key Register"), REG_FIT},
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{ORDATAD(MTM, MTM, 1, "Multi Index registers"), REG_FIT},
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{ORDATAD(TM, TM, 1, "Trap mode"), REG_FIT},
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{ORDATAD(STM, STM, 1, "Select trap mode"), REG_FIT},
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{ORDATAD(CTM, CTM, 1, "Copy Trap Mode"), REG_FIT},
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{ORDATAD(FTM, FTM, 1, "Floating trap mode"), REG_FIT},
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{ORDATAD(NMODE, nmode, 1, "Storage null mode"), REG_FIT},
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{ORDATAD(ACOVF, acoflag, 1, "AC Overflow Flag"), REG_FIT},
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{ORDATAD(MQOVF, mqoflag, 1, "MQ Overflow Flag"), REG_FIT},
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{ORDATAD(IOC, iocheck, 1, "I/O Check flag"), REG_FIT},
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{ORDATAD(DVC, dcheck, 1, "Divide Check flag"), REG_FIT},
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{ORDATAD(RELOC, relocaddr, 14, "Relocation offset"), REG_FIT},
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{ORDATAD(BASE, baseaddr, 14, "Relocation base"), REG_FIT},
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{ORDATAD(LIMIT, limitaddr, 14, "Relocation limit"), REG_FIT},
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{ORDATAD(ENB, ioflags, 36, "I/O Trap Flags"), REG_FIT},
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{FLDATA(INST_BASE, bcore, 0), REG_FIT},
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{FLDATA(DATA_BASE, bcore, 1), REG_FIT},
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{HRDATAD(PC, PC, 24, "Program Counter Counter"), REG_FIT},
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{BRDATAD(GPR, GPR, 8, 32, 16, "General Purpose Registers"), REG_FIT, 0},
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{BRDATAD(BR, BR, 8, 32, 16, "Base Registers"), REG_FIT, 0},
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{HRDATAD(CC, CC, 4, "Condition codes"), REG_FIT},
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{BRDATAD(SPAD, SPAD, 256, 32, 16, "Scratch Pad Registers"), REG_FIT},
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{HRDATAD(CPIX, cpix, 16, "Current process index"), REG_FIT},
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{HRDATAD(BPIX, bpix, 16, "Base process index"), REG_FIT},
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{NULL}
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};
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@ -304,7 +268,35 @@ int base_mode[] = {
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ADR, RR|SR|WRD, ADR, IMM,
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};
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/* System 70 PTE:
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*
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* Bit 0 - NU
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* Bit 1 - Valid Entry
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* Bit 2 - Write Protect
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* Bit 3 - 15 Address.
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*
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* System 67 PTR:
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* Bit 0 - Valid Entry
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* Bit 1 - 0000-7ff Write Protected
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* Bit 2 - 0800-fff Write Protected
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* Bit 3 - 1000-7ff Write Protected
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* Bit 4 - 1800-fff Write Protected
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* Bit 5 - 15 Address.
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*
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* System V6&V9
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* Bit 0 - Valid Entry
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* Bit 1 - No Access
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* Bit 2 - Write protect
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* Bit 3 - Modified Block
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* Bit 4 - Access Block
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* Bit 5-15 Address.
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*/
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int page_lookup(uint32 addr, uint32 *loc, int wr) {
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int page = addr >> 12;
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if (tlb[page] != 0) {
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} else {
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}
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}
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int Mem_read(uint32 addr, uint32 *data) {
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@ -336,8 +328,10 @@ t_stat
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sim_instr(void)
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{
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t_stat reason;
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uint64 dest; /* Holds destination/source register */
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uint64 source; /* Holds source or memory data */
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uint64 d_dest; /* Holds double length destination/source register */
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uint32 dest; /* Holds destination/source register */
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uint64 d_source; /* Holds double length source or memory data */
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uint32 source; /* Holds source or memory data */
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uint32 addr; /* Holds address of last access */
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uint32 temp; /* General holding place for stuff */
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uint32 IR; /* Instruction register */
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@ -385,7 +379,7 @@ exec:
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op = (opr >> 26) & 03F;
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FC = (IR & F_BIT) ? 0x4 : 0;
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reg = (opr >> 23) & 0x7;
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dest = (uint64)IR;
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dest = IR;
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dbl = 0;
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ovr = 0;
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if (mode & BASE) {
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@ -464,7 +458,7 @@ exec:
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/* Fault */
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}
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addr = temp & 0xFF07FFFF;
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dest = (uint64)temp;
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dest = temp;
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ix = (temp >> 21) & 3;
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if (ix != 0)
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addr += GPR[ix];
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@ -499,7 +493,7 @@ exec:
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}
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if (Mem_read(addr + 4, &temp)) {
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}
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source |= ((uint64)temp) << 32;
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d_source = ((uint64)temp) << 32 | source;
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dbl = 1;
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break;
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case 4:
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@ -513,33 +507,33 @@ exec:
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/* Read in if from register */
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if (i_flags & RR) {
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dest = (uint64)GPR[reg];
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dest = GPR[reg];
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if (dbl) {
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if (reg & 1) {
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/* Spec fault */
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}
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dest |= ((uint64)GPR[reg|1]) << 32;
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d_dest = ((uint64)GPR[reg|1]) << 32 | dest;
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} else {
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dest |= (dest & FSIGN) ? 0xFFFFFFFF << 32: 0;
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d_dest |= ((dest & FSIGN) ? 0xFFFFFFFFLL << 32: 0) | dest;
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}
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}
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/* For Base mode */
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if (i_flags & RB) {
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dest = (uint64)BR[reg];
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dest = BR[reg];
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}
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/* For register instructions */
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if (i_flags & R1) {
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int r = (IR >> 20) & 07;
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source = (uint64)GPR[r];
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source = GPR[r];
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if (dbl) {
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if (r & 1) {
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/* Spec fault */
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}
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source |= ((uint64)GPR[r|1]) << 32;
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d_source = ((uint64)GPR[reg|1]) << 32 | source;
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} else {
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source |= (source & FSIGN) ? 0xFFFFFFFF << 32: 0;
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d_source |= ((source & FSIGN) ? 0xFFFFFFFFLL << 32: 0) | source;
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}
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}
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@ -638,17 +632,6 @@ exec:
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break;
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case 0x04: /* 0x10 */ /* CAR or (basemode SACZ ) */
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if (modes & BASE) {
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temp = GPR[reg];
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t = (IR >> 20) & 7;
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temp = temp - GPR[t];
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CC &= AEXP;
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else if (temp & FSIGN)
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CC |= CC3;
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else if (temp == 0)
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CC |= CC4;
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else
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CC |= CC2;
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} else {
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scaz:
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temp = GPR[reg];
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t = 0;
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@ -662,7 +645,18 @@ scaz:
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} else {
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CC |= CC4;
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}
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} else {
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GPR[(IR >> 20) & 7] = t;
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temp = GPR[reg];
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t = (IR >> 20) & 7;
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temp = temp - GPR[t];
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CC &= AEXP;
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else if (temp & FSIGN)
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CC |= CC3;
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else if (temp == 0)
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CC |= CC4;
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else
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CC |= CC2;
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}
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break;
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@ -1307,8 +1301,8 @@ scaz:
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if (reg & 1) {
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/* Spec fault */
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}
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dest = (uint64)temp | (temp & FSIGN) ? FMASK << 32: 0;
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source = (uint64)addr | (addr & FSIGN) ? FMASK << 32: 0;
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d_dest = (uint64)temp | (temp & FSIGN) ? FMASK << 32: 0;
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d_source = (uint64)addr | (addr & FSIGN) ? FMASK << 32: 0;
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GPR[reg] = (uint32)(dest & FMASK);
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GPR[reg|1] = (uint32)((dest >> 32) & FMASK);
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CC &= AEXP;
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@ -1324,24 +1318,24 @@ scaz:
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if (reg & 1) {
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/* Spec fault */
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}
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source = (uint64)addr | (addr & FSIGN) ? FMASK << 32: 0;
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if (source == 0) {
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d_source = (uint64)addr | (addr & FSIGN) ? FMASK << 32: 0;
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if (d_source == 0) {
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ovr = 1;
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break;
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}
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dest = (uint64)GPR[reg];
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dest |= ((uint64)GPR[reg|1]) << 32;
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t = (int64)dest % (int64)source;
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d_dest = (uint64)GPR[reg];
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d_dest |= ((uint64)GPR[reg|1]) << 32;
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t = (int64)d_dest % (int64)d_source;
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dbl = (t < 0);
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if ((t ^ (dest & MSIGN)) != 0) /* Fix sign if needed */
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if ((t ^ (d_dest & MSIGN)) != 0) /* Fix sign if needed */
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t = -t;
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dest = (int64)dest / (int64)source;
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if ((dest & LMASK) != 0 && (dest & LMASK) != LMASK)
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d_dest = (int64)d_dest / (int64)d_source;
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if ((d_dest & LMASK) != 0 && (d_dest & LMASK) != LMASK)
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ovr = 1;
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GPR[reg] = (uint32)t;
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GPR[reg|1] = (uint32)(dest & FMASK);
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GPR[reg|1] = (uint32)(d_dest & FMASK);
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CC &= AEXP;
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if (dest & MSIGN)
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if (d_dest & MSIGN)
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CC |= CC3;
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else if (dest == 0)
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CC |= CC4;
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@ -1503,9 +1497,12 @@ scaz:
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/* Store result to register */
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if (i_flags & SD) {
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if (dbl)
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GPR[reg|1] = (uint32)(dest>>32);
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GPR[reg] = (uint32)(dest & FMASK);
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if (dbl) {
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GPR[reg|1] = (uint32)(d_dest>>32);
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GPR[reg] = (uint32)(d_dest & FMASK);
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} else {
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GPR[reg] = dest;
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}
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}
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/* Store result to base register */
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@ -1513,7 +1510,7 @@ scaz:
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if (dbl) {
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/* Fault */
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}
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BR[reg] = (uint32)(dest & FMASK);
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BR[reg] = dest;
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}
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/* Store result to memory */
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@ -1,6 +1,7 @@
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/* sel32_defs.h: Gould Concept/32 (orignal SEL32) simulator definitions
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Copyright (c) 2017, Richard Cornwell
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Copyright (c) 2018, Richard Cornwell
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Copyright (c) 2018, James C. Bevier
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|
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@ -15,9 +16,10 @@
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
RICHARD CORNWELL OR JAMES BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
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|
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*/
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@ -255,5 +257,106 @@ typedef struct dib {
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extern DEBTAB dev_debug[];
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/* defines for all programs */
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#define RMASK 0x0000FFFF /* right hw 16 bit mask */
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#define LMASK 0xFFFF0000 /* left hw 16 bit mask */
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#define FMASK 0xFFFFFFFF /* 32 bit mask */
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#define DMASK 0xFFFFFFFFFFFFFFFFLL /* 64 bit all bits mask */
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#define D48LMASK 0xFFFFFFFFFFFF0000LL /* 64 bit left 48 bits mask */
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#define D32LMASK 0xFFFFFFFF00000000LL /* 64 bit left 32 bits mask */
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#define D32RMASK 0x00000000FFFFFFFFLL /* 64 bit right 32 bits mask */
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#define MSIGN 0x80000000 /* 32 bit minus sign */
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#define DMSIGN 0x8000000000000000LL /* 64 bit minus sign */
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#define FSIGN 0x80000000 /* 32 bit minus sign */
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/* sign extend 16 bit value to uint32 */
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#define SEXT16(x) (x&MSIGN?(uint32)(((uint32)x&RMASK)|LMASK):(uint32)x)
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/* sign extend 16 bit value to uint64 */
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#define DSEXT16(x) (x&MSIGN?(l_uint64)(((l_uint64)x&RMASK)|D48LMASK):(t_uint64)x)
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/* sign extend 32 bit value to uint64 */
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#define DSEXT32(x) (x&MSIGN?(l_uint64)(((l_uint64)x&D32RMASK)|D32LMASK):(t_uint64)x)
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#define UNIT_V_MODEL (UNIT_V_UF + 0)
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#define UNIT_MODEL (7 << UNIT_V_MODEL)
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#define MODEL(x) (x << UNIT_V_MODEL)
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#define UNIT_V_MSIZE (UNIT_V_MODEL + 3)
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#define UNIT_MSIZE (0x1F << UNIT_V_MSIZE)
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#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
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#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_MODEL) & 0x7) /* cpu model 0-7 */
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#define MODEL_55 0 /* 512K Mode Only */
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#define MODEL_75 1 /* Extended */
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#define MODEL_27 2 /* */
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#define MODEL_67 3 /* */
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||||
#define MODEL_87 4 /* */
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||||
#define MODEL_97 5 /* */
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||||
#define MODEL_V6 6 /* V6 CPU */
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||||
#define MODEL_V9 7 /* V9 CPU */
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||||
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||||
DEVICEC1 0x40 /* CC1 in CC */
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#define CC2 0x20 /* CC2 in CC */
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#define CC3 0x10 /* CC3 in CC */
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#define CC4 0x08 /* CC4 in CC */
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#define CC1BIT 0x40000000 /* CC1 in PSD1 */
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||||
#define CC2BIT 0x20000000 /* CC2 in PSD1 */
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||||
#define CC3BIT 0x10000000 /* CC3 in PSD1 */
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||||
#define CC4BIT 0x08000000 /* CC4 in PSD1 */
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||||
|
||||
/* PSD mode bits in 'modes' variable */
|
||||
#define PRIV 0x80 /* Privileged mode PSD 1 bit 0 */
|
||||
#define EXTD 0x04 /* Extended Addressing PSD 1 bit 5 */
|
||||
#define BASE 0x02 /* Base Mode PSD 1 bit 6 */
|
||||
#define AEXP 0x01 /* Arithmetic exception PSD 1 bit 7 */
|
||||
|
||||
#define MAP 0x40 /* Map mode, PSD 2 bit 0 */
|
||||
#define RET 0x20 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define BLKED 0x10 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define BLKRET 0x08 /* Set retain blocked mode, PSD 2 bit 16 */
|
||||
|
||||
/* PSD mode bits in PSD words 1&2 variable */
|
||||
#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
|
||||
#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
|
||||
#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
|
||||
#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
|
||||
|
||||
#define BLKEDBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define RETBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
|
||||
|
||||
/* Trap Table Address in memory is pointed to by SPAD 0xF0 */
|
||||
#define POWERFAIL_TRAP 0x80 /* Power fail trap */
|
||||
#define POWERON_TRAP 0x84 /* Power-On trap */
|
||||
#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
|
||||
#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
|
||||
#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
|
||||
#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
|
||||
#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
|
||||
#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
|
||||
#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
|
||||
#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
|
||||
#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
|
||||
#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
|
||||
#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
|
||||
#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
|
||||
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
|
||||
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
|
||||
|
||||
|
||||
/* Errors returned from various functions */
|
||||
#define ALLOK 0x0000 /* no error, all is OK */
|
||||
#define MAPFLT MAPFAULT_TRAP /* map fault error */
|
||||
#define NPMEM NONPRESMEM_TRAP /* non present memory */
|
||||
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
|
||||
|
||||
/* general instruction decode equates */
|
||||
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
|
||||
#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
|
||||
#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 20 & 31 */
|
||||
#define BIT0 0x80000000 /* general use for bit 0 testing */
|
||||
#define BIT1 0x40000000 /* general use for bit 1 testing */
|
||||
#define MASK16 0x0000FFFF /* 16 bit address mask */
|
||||
#define MASK19 0x0007FFFF /* 19 bit address mask */
|
||||
#define MASK20 0x000FFFFF /* 20 bit address mask */
|
||||
#define MASK24 0x00FFFFFF /* 24 bit address mask */
|
||||
#define MASK32 0xFFFFFFFF /* 32 bit address mask */
|
||||
|
||||
extern DEVICE cpu_dev;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user