From 710dafd70663f19f7676780767840a8b6522e536 Mon Sep 17 00:00:00 2001 From: Richard Cornwell Date: Sat, 28 May 2016 00:50:53 -0400 Subject: [PATCH] KA10: Added sim_debug and have working RH10/RP04 Fixed errors in sim_debug constants for DP driver. RH10 drive now works as RP04. --- PDP10/ka10_cpu.c | 13 ++- PDP10/ka10_defs.h | 1 + PDP10/ka10_dp.c | 2 +- PDP10/ka10_rp.c | 250 ++++++++++++++++++++++++++++++---------------- PDP10/ka10_sys.c | 6 +- 5 files changed, 178 insertions(+), 94 deletions(-) diff --git a/PDP10/ka10_cpu.c b/PDP10/ka10_cpu.c index b0733da..29ff1e1 100644 --- a/PDP10/ka10_cpu.c +++ b/PDP10/ka10_cpu.c @@ -243,11 +243,17 @@ MTAB cpu_mod[] = { { 0 } }; +/* Simulator debug controls */ +DEBTAB cpu_debug[] = { + {"IRQ", DEBUG_IRQ, "Debug IRQ requests"}, + {0, 0} +}; + DEVICE cpu_dev = { "CPU", &cpu_unit, cpu_reg, cpu_mod, 1, 8, 18, 1, 8, 36, &cpu_ex, &cpu_dep, &cpu_reset, - NULL, NULL, NULL, NULL, 0, 0, NULL, + NULL, NULL, NULL, NULL, DEV_DEBUG, 0, cpu_debug, NULL, NULL, &cpu_help, NULL, NULL, &cpu_description }; @@ -532,12 +538,13 @@ void set_interrupt(int dev, int lvl) { dev_irq[dev>>2] = 0200 >> lvl; pi_pending = 1; // if (dev != 4 && (dev & 0774) != 0120) -// fprintf(stderr, "set irq %o %o\n\r", dev & 0774, lvl); + sim_debug(DEBUG_IRQ, &cpu_dev, "set irq %o %o\n", dev & 0774, lvl); } } void clr_interrupt(int dev) { dev_irq[dev>>2] = 0; + sim_debug(DEBUG_IRQ, &cpu_dev, "clear irq %o\n", dev & 0774); } void check_apr_irq() { @@ -567,7 +574,7 @@ int check_irq_level() { if (lvl == 0) pi_pending = 0; PIR |= (lvl & PIE); - // fprintf(stderr, "PIR=%o PIE=%o\n\r", PIR, PIE); +// fprintf(stderr, "PIR=%o PIE=%o\n\r", PIR, PIE); /* Compute mask for pi_ok */ pi_t = (~PIR & ~PIH) >> 1; pi_ok = 0100 & (PIR & ~PIH); diff --git a/PDP10/ka10_defs.h b/PDP10/ka10_defs.h index b080e40..1ab67bc 100644 --- a/PDP10/ka10_defs.h +++ b/PDP10/ka10_defs.h @@ -105,6 +105,7 @@ #define DEBUG_CONI 0x0000010 /* Show CONI instructions */ #define DEBUG_CONO 0x0000020 /* Show CONO instructions */ #define DEBUG_DATAIO 0x0000040 /* Show DATAI/O instructions */ +#define DEBUG_IRQ 0x0000080 /* Show IRQ requests */ extern DEBTAB dev_debug[]; diff --git a/PDP10/ka10_dp.c b/PDP10/ka10_dp.c index ffb0da0..c79f046 100644 --- a/PDP10/ka10_dp.c +++ b/PDP10/ka10_dp.c @@ -377,7 +377,7 @@ t_stat dp_devio(uint32 dev, uint64 *data) { if (tmp) df10->status &= ~PI_ENABLE; } - sim_debug(DEBUG_CONI, dptr, "DP %03o CONO %06o %d PC=%o %06o\n", dev, + sim_debug(DEBUG_CONO, dptr, "DP %03o CONO %06o %d PC=%o %06o\n", dev, (uint32)*data, ctlr, PC, df10->status); return SCPE_OK; diff --git a/PDP10/ka10_rp.c b/PDP10/ka10_rp.c index 7708a83..d625def 100644 --- a/PDP10/ka10_rp.c +++ b/PDP10/ka10_rp.c @@ -58,15 +58,15 @@ #define CONTROL 007 -/* CONO Flags */ -#define IADR_ATTN 0000000000100 /* Interrupt on attention */ -#define IARD_RAE 0000000000200 /* Interrupt on register access error */ -#define DIB_CBOV 0000000000400 /* Control bus overrun */ -#define CXR_PS_FAIL 0000000001000 /* Power supply fail (not implemented) */ -#define CXR_ILC 0000000002000 /* Illegal function code */ -#define CR_DRE 0000000004000 /* Or Data and Control Timeout */ -#define DTC_OVER 0000000010000 /* DF10 did not supply word on time (not implemented) */ -#define CCW_COMP_1 0000000020000 /* Control word written. */ +/* CONI Flags */ +#define IADR_ATTN 0000000000040 /* Interrupt on attention */ +#define IARD_RAE 0000000000100 /* Interrupt on register access error */ +#define DIB_CBOV 0000000000200 /* Control bus overrun */ +#define CXR_PS_FAIL 0000000002000 /* Power supply fail (not implemented) */ +#define CXR_ILC 0000000004000 /* Illegal function code */ +#define CR_DRE 0000000010000 /* Or Data and Control Timeout */ +#define DTC_OVER 0000000020000 /* DF10 did not supply word on time (not implemented) */ +#define CCW_COMP_1 0000000040000 /* Control word written. */ #define CXR_CHAN_ER 0000000100000 /* Channel Error */ #define CXR_EXC 0000000200000 /* Error in drive transfer */ #define CXR_DBPE 0000000400000 /* Device Parity error (not implemented) */ @@ -82,7 +82,7 @@ #define CB_FULL 0200000000000 /* Set when channel buffer is full (not implemented) */ #define AR_FULL 0400000000000 /* Set when AR is full (not implemented) */ -/* CONI Flags */ +/* CONO Flags */ #define ATTN_EN 0000000000040 /* enable attention interrupt. */ #define REA_EN 0000000000100 /* enable register error interrupt */ #define CBOV_CLR 0000000000200 /* Clear CBOV */ @@ -144,7 +144,7 @@ #define DS_OFF 0000001 /* offset mode */ #define DS_VV 0000100 /* volume valid */ -#define DS_RDY 0000200 /* drive ready */ +#define DS_DRY 0000200 /* drive ready */ #define DS_DPR 0000400 /* drive present */ #define DS_PGM 0001000 /* programable NI */ #define DS_LST 0002000 /* last sector */ @@ -245,21 +245,21 @@ The RP07, despite its name, uses an RM-style controller. */ -#define RP04_DTYPE 1 +#define RP04_DTYPE 0 #define RP04_SECT 20 #define RP04_SURF 19 #define RP04_CYL 411 #define RP04_DEV 020020 #define RP04_SIZE (RP04_SECT * RP04_SURF * RP04_CYL * RP_NUMWD) -#define RP06_DTYPE 2 +#define RP06_DTYPE 1 #define RP06_SECT 20 #define RP06_SURF 19 #define RP06_CYL 815 #define RP06_DEV 020022 #define RP06_SIZE (RP06_SECT * RP06_SURF * RP06_CYL * RP_NUMWD) -#define RP07_DTYPE 3 +#define RP07_DTYPE 2 #define RP07_SECT 43 #define RP07_SURF 32 #define RP07_CYL 630 @@ -290,6 +290,7 @@ int rp_ivect[NUM_DEVS_RP]; int rp_imode[NUM_DEVS_RP]; int rp_drive[NUM_DEVS_RP]; int rp_rae[NUM_DEVS_RP]; +int rp_attn[NUM_DEVS_RP]; extern int readin_flag; t_stat rp_devio(uint32 dev, uint64 *data); @@ -457,7 +458,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) { DEVICE *dptr; struct df10 *df10; UNIT *uptr; - int drive; + int tmp; for (drive = 0; drive < NUM_DEVS_RP; drive++) { if (rp_dib[drive].dev_num == (dev & 0774)) { @@ -471,18 +472,22 @@ t_stat rp_devio(uint32 dev, uint64 *data) { df10 = &rp_df10[ctlr]; switch(dev & 3) { case CONI: - *data = df10->status; + *data = df10->status & ~(IADR_ATTN|IARD_RAE); + if (rp_attn[ctlr] != 0 && (df10->status & IADR_ATTN)) + *data |= IADR_ATTN; + if (rp_rae[ctlr] != 0 && (df10->status & IARD_RAE)) + *data |= IARD_RAE; #ifdef KI10 *data |= B22_FLAG; #endif - sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o\n", - dev, (uint32)*data, PC); + sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o %o\n", + dev, (uint32)*data, PC, rp_attn[ctlr]); return SCPE_OK; case CONO: clr_interrupt(dev); df10->status &= ~07LL; - df10->status |= *data & 07LL; + df10->status |= *data & (07LL|IADR_ATTN|IARD_RAE); /* Clear flags */ if (*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)) df10->status &= ~(*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)); @@ -494,7 +499,7 @@ t_stat rp_devio(uint32 dev, uint64 *data) { df10->status &= ~(CXR_ILFC|CXR_SD_RAE); if (*data & WRT_CW) df10_writecw(df10); - sim_debug(DEBUG_CONO, dptr, "RP %03o CONO %06o %d PC=%o %06o\n", + sim_debug(DEBUG_CONO, dptr, "RP %03o CONO %06o %d PC=%06o %06o\n", dev, (uint32)*data, ctlr, PC, df10->status); return SCPE_OK; @@ -517,38 +522,57 @@ t_stat rp_devio(uint32 dev, uint64 *data) { *data |= ((t_uint64)(rp_drive[ctlr])) << 18; } *data |= ((t_uint64)(rp_reg[ctlr])) << 30; - sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d PC=%o\n\r", - dev, *data, ctlr, PC); + sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d %d PC=%06o\n\r", + dev, *data, ctlr, rp_drive[ctlr], PC); return SCPE_OK; case DATAO: - sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATO %012llo, %d PC=%o\n\r", - dev, *data, ctlr, PC); - if (df10->status & BUSY) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } + sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATO %012llo, %d PC=%06o %06o\n\r", + dev, *data, ctlr, PC, df10->status); clr_interrupt(dev); df10->status &= ~(PI_ENABLE|CCW_COMP_1); rp_reg[ctlr] = ((int)(*data >> 30)) & 077; if (*data & LOAD_REG) { if (rp_reg[ctlr] == 040) { + if (df10->status & BUSY) { + df10->status |= CC_CHAN_ACT; + return SCPE_OK; + } + rp_drive[ctlr] = (int)(*data >> 18) & 07; + /* Check if access error */ + if (rp_rae[ctlr] & (1 << rp_drive[ctlr])) { + return SCPE_OK; + } + /* Start command */ df10_setup(df10, (uint32)(*data >> 6)); - rp_drive[ctlr] = (int)(*data >> 18) & 07; + df10->status |= BUSY; rp_write(ctlr, rp_drive[ctlr], 0, (uint32)(*data & 077)); + sim_debug(DEBUG_DATAIO, dptr, "RP %03o command %012llo, %d[%d] PC=%06o %06o\n\r", + dev, *data, ctlr, rp_drive[ctlr], PC, df10->status); } else if (rp_reg[ctlr] == 044) { /* Set KI10 Irq vector */ rp_ivect[ctlr] = (int)(*data & IRQ_VECT); rp_imode[ctlr] = (*data & IRQ_KI10) != 0; + } else if (rp_reg[ctlr] == 050) { + ; /* Diagnostic access to mass bus. */ } else if (rp_reg[ctlr] == 054) { /* clear flags */ rp_rae[ctlr] &= ~(*data & 0377); } else if ((rp_reg[ctlr] & 040) == 0) { + rp_drive[ctlr] = (int)(*data >> 18) & 07; + /* Check if access error */ + if (rp_rae[ctlr] & (1 << rp_drive[ctlr])) { + return SCPE_OK; + } rp_drive[ctlr] = (int)(*data >> 18) & 07; rp_write(ctlr, rp_drive[ctlr], rp_reg[ctlr] & 037, (int)(*data & 0777777)); } + } else { + if (rp_reg[ctlr] <= 040) { + rp_drive[ctlr] = (int)(*data >> 18) & 07; + } } return SCPE_OK; } @@ -558,23 +582,20 @@ t_stat rp_devio(uint32 dev, uint64 *data) { void rp_write(int ctlr, int unit, int reg, uint32 data) { UNIT *uptr = &rp_unit[(ctlr * 8) + unit]; - struct df10 *df10; - int i; + int i; + DEVICE *dptr = rp_devs[ctlr]; + switch(reg) { case 000: /* control */ - df10 = &rp_df10[ctlr]; - if (df10->status & BUSY) - return; - uptr->u3 &= ~(076|DS_VV); - uptr->u3 |= data & 076; - if ((uptr->flags & UNIT_ATT) && data & 01) { - uptr->u3 &= 0177777; - uptr->u3 |= DS_DPR|DS_MOL; - if (uptr->flags & UNIT_WLK) - uptr->u3 |= DS_WRL; + sim_debug(DEBUG_DETAIL, dptr, "RPA%o %d Status=%06o\n", unit, ctlr, uptr->u3); + if (uptr->flags & UNIT_WLK) + uptr->u3 |= DS_WRL; + if ((uptr->u3 & DS_DRY) && data & 01) { + uptr->u3 &= DS_ATA|DS_VV|DS_DPR|DS_MOL|DS_WRL; + uptr->u3 |= data & 076; switch (GET_FNC(data)) { case FNC_NOP: - uptr->u3 |= DS_RDY; + uptr->u3 |= DS_DRY; break; case FNC_PRESET: /* read-in preset */ uptr->u4 = 0; @@ -592,22 +613,27 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { case FNC_WRITEH: /* write w/ headers */ case FNC_READ: /* read */ case FNC_READH: /* read w/ headers */ - uptr->u3 |= DS_PIP; + uptr->u3 |= DS_PIP|CR_GO; + uptr->u6 = 0; break; case FNC_DCLR: /* drive clear */ - uptr->u3 |= DS_RDY; + uptr->u3 |= DS_DRY; + uptr->u3 &= ~(DS_ATA|CR_GO); + rp_attn[ctlr] &= ~(1<u3 |= DS_DRY; break; case FNC_PACK: /* pack acknowledge */ - uptr->u3 |= DS_VV|DS_RDY; + uptr->u3 |= DS_VV|DS_DRY; break; default: - uptr->u3 |= DS_RDY|DS_ERR; + uptr->u3 |= DS_DRY|DS_ERR; uptr->u3 |= (ER1_ILF << 16); } if (uptr->u3 & DS_PIP) sim_activate(uptr, 100); + sim_debug(DEBUG_DETAIL, dptr, "RPA%o AStatus=%06o\n", unit, uptr->u3); } return; case 001: /* status */ @@ -615,6 +641,8 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { case 002: /* error register 1 */ uptr->u3 &= 0177777; uptr->u3 |= data << 16; + if (data != 0) + uptr->u3 |= DS_ERR; break; case 003: /* maintenance */ break; @@ -622,6 +650,7 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { for (i = 0; i < 8; i++) { if (data & (1<u4 &= 0177777; uptr->u4 |= data << 16; break; - case 006: /* drive type */ - case 007: /* look ahead */ case 010: /* error register 2 */ - case 011: /* offset */ + if (data != 0) + uptr->u3 |= DS_ERR; uptr->u5 &= 0177777; uptr->u5 |= data << 16; + case 006: /* drive type */ + case 007: /* look ahead */ + case 011: /* offset */ break; case 012: /* desired cylinder */ uptr->u4 &= ~0177777; @@ -648,26 +679,28 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { break; default: uptr->u3 |= (ER1_ILR<<16)|DS_ERR; + rp_rae[ctlr] &= ~(1<u3 & 076; if (uptr->flags & UNIT_ATT) temp |= CS1_DVA; - if (df10->status & BUSY) + if (df10->status & BUSY || uptr->u3 & CR_GO) temp |= CS1_GO; break; case 001: /* status */ - temp = uptr->u3 & 0177701; + temp = uptr->u3 & 0177700; break; case 002: /* error register 1 */ temp = (uptr->u3 >> 16) & 0177777; @@ -704,6 +737,7 @@ rp_read(int ctlr, int unit, int reg) { break; default: uptr->u3 |= (ER1_ILR<<16); + rp_rae[ctlr] &= ~(1<flags); + int ctlr; + int unit; DEVICE *dptr; struct df10 *df; - int diff, unit, ctlr, da; int cyl = uptr->u4 & 01777; + int diff, da; t_stat err, r; - dptr = rp_devs[ctlr]; + /* Find dptr, and df10 */ + for (ctlr = 0; ctlr < NUM_DEVS_RP; ctlr++) { + dptr = rp_devs[ctlr]; + unit = uptr - dptr->units; + if (unit < 8) + break; + } + if (unit > 8) + return SCPE_OK; + df = &rp_df10[ctlr]; /* Check if seeking */ if (uptr->u3 & DS_PIP) { + sim_debug(DEBUG_DETAIL, dptr, "RPA%o seek %d %d\n", unit, cyl, uptr->u5); if (cyl > rp_drv_tab[dtype].cyl) { uptr->u3 &= ~DS_PIP; - uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_RDY|DS_ATA; + uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; } diff = cyl - (uptr->u5 & 01777); if (diff < 0) { @@ -756,10 +802,6 @@ t_stat rp_svc (UNIT *uptr) } } - dptr = find_dev_from_unit(uptr); - ctlr = ((DIB *)(dptr->ctxt)) - rp_dib; - df = &rp_df10[ctlr]; - unit = uptr - dptr->units; switch (GET_FNC(uptr->u3)) { case FNC_NOP: case FNC_DCLR: /* drive clear */ @@ -774,22 +816,26 @@ t_stat rp_svc (UNIT *uptr) case FNC_PRESET: /* read-in preset */ case FNC_RECAL: /* recalibrate */ case FNC_SEEK: /* seek */ - uptr->u3 |= DS_RDY|DS_ATA; - rp_rae[ctlr] |= 1<u3 |= DS_DRY|DS_ATA; + uptr->u3 &= ~CR_GO; df->status &= ~BUSY; if (df->status & IADR_ATTN) df10_setirq(df); + sim_debug(DEBUG_DETAIL, dptr, "RPA%o seekdone %d %o\n", unit, cyl, uptr->u3); break; case FNC_SEARCH: /* search */ if (GET_SC(uptr->u4) > rp_drv_tab[dtype].sect || GET_SF(uptr->u4) > rp_drv_tab[dtype].surf) uptr->u3 |= (ER1_IAE << 16)|DS_ERR; - uptr->u3 |= DS_RDY|DS_ATA; - rp_rae[ctlr] |= 1<u3 |= DS_DRY|DS_ATA; + uptr->u3 &= ~CR_GO; df->status &= ~BUSY; if (df->status & IADR_ATTN) df10_setirq(df); + sim_debug(DEBUG_DETAIL, dptr, "RPA%o searchdone %d %o\n", unit, cyl, uptr->u3); break; case FNC_READ: /* read */ @@ -800,12 +846,17 @@ t_stat rp_svc (UNIT *uptr) int wc; if (GET_SC(uptr->u4) > rp_drv_tab[dtype].sect || GET_SF(uptr->u4) > rp_drv_tab[dtype].surf) { - uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_RDY|DS_ATA; - rp_rae[ctlr] |= 1<u3 |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; + rp_attn[ctlr] |= 1<status &= ~BUSY; - df10_setirq(df); + uptr->u3 &= ~CR_GO; + sim_debug(DEBUG_DETAIL, dptr, "RPA%o readx done\n", unit); + if (df->status & IADR_ATTN) + df10_setirq(df); return SCPE_OK; } + sim_debug(DEBUG_DETAIL, dptr, "RPA%o read (%d,%d,%d)\n", unit, cyl, + GET_SC(uptr->u4), GET_SF(uptr->u4)); da = GET_DA(uptr->u4, dtype) * RP_NUMWD; sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); wc = sim_fread (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD, @@ -814,7 +865,9 @@ t_stat rp_svc (UNIT *uptr) rp_buf[ctlr][wc++] = 0; uptr->hwmark = RP_NUMWD; } + df->buf = rp_buf[ctlr][uptr->u6++]; + sim_debug(DEBUG_DATA, dptr, "RPA%o read word %d %012llo\n", unit, uptr->u6, df->buf); if (df10_write(df)) { if (uptr->u6 == uptr->hwmark) { /* Increment to next sector. Set Last Sector */ @@ -832,6 +885,13 @@ t_stat rp_svc (UNIT *uptr) } } sim_activate(uptr, 20); + } else { + sim_debug(DEBUG_DETAIL, dptr, "RPA%o read done\n", unit); + uptr->u3 |= DS_DRY; + uptr->u3 &= ~CR_GO; + df->status &= ~BUSY; + df10_setirq(df); + return SCPE_OK; } break; @@ -840,24 +900,30 @@ t_stat rp_svc (UNIT *uptr) if (uptr->u6 == 0) { if (GET_SC(uptr->u4) > rp_drv_tab[dtype].sect || GET_SF(uptr->u4) > rp_drv_tab[dtype].surf) { - uptr->u3 |= (ER1_IAE << 16)|DS_ERR|DS_RDY|DS_ATA; - rp_rae[ctlr] |= 1<u3 |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; + rp_attn[ctlr] |= 1<status &= ~BUSY; - df10_setirq(df); + uptr->u3 &= ~CR_GO; + sim_debug(DEBUG_DETAIL, dptr, "RPA%o writex done\n", unit); + if (df->status & IADR_ATTN) + df10_setirq(df); return SCPE_OK; } } - if (r = df10_read(df)) - rp_buf[ctlr][uptr->u6++] = df->buf; + r = df10_read(df); + rp_buf[ctlr][uptr->u6++] = df->buf; + sim_debug(DEBUG_DATA, dptr, "RPA%o write word %d %012llo\n", unit, uptr->u6, df->buf); if (r == 0 || uptr->u6 == RP_NUMWD) { while (uptr->u6 < RP_NUMWD) rp_buf[ctlr][uptr->u6++] = 0; + sim_debug(DEBUG_DETAIL, dptr, "RPA%o write (%d,%d,%d)\n", unit, cyl, + GET_SC(uptr->u4), GET_SF(uptr->u4)); da = GET_DA(uptr->u4, dtype) * RP_NUMWD; sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); sim_fwrite (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD, uptr->fileref); + uptr->u6 = 0; if (r) { - uptr->u6 = 0; uptr->u4 += 0x10000; /* Increment to next sector. Set Last Sector */ if (GET_SC(uptr->u4) > rp_drv_tab[dtype].sect) { @@ -872,8 +938,16 @@ t_stat rp_svc (UNIT *uptr) } } } - if (r) + if (r) { sim_activate(uptr, 20); + } else { + sim_debug(DEBUG_DETAIL, dptr, "RPA%o write done\n", unit); + uptr->u3 |= DS_DRY; + uptr->u3 &= ~CR_GO; + df->status &= ~BUSY; + df10_setirq(df); + return SCPE_OK; + } break; } return SCPE_OK; @@ -884,16 +958,13 @@ t_stat rp_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc) { int i; + if (uptr == NULL) return SCPE_IERR; - for (i = 0; rp_drv_tab[i].sect != 0; i++) { - if (GET_DTYPE(val) == rp_drv_tab[i].devtype) { - uptr->flags &= ~(UNIT_DTYPE); - uptr->flags |= val; - uptr->capac = rp_drv_tab[i].size; - return SCPE_OK; - } - } - return SCPE_IERR; + uptr->flags &= ~(UNIT_DTYPE); + uptr->flags |= val; + i = GET_DTYPE(val); + uptr->capac = rp_drv_tab[i].size; + return SCPE_OK; } @@ -903,8 +974,10 @@ rp_reset(DEVICE * rptr) int ctlr; for (ctlr = 0; ctlr < NUM_DEVS_RP; ctlr++) { rp_df10[ctlr].devnum = rp_dib[ctlr].dev_num; - rp_df10[ctlr].nxmerr = 18; - rp_df10[ctlr].ccw_comp = 13; + rp_df10[ctlr].nxmerr = 19; + rp_df10[ctlr].ccw_comp = 14; + rp_attn[ctlr] = 0; + rp_rae[ctlr] = 0; } return SCPE_OK; } @@ -953,6 +1026,9 @@ t_stat rp_attach (UNIT *uptr, CONST char *cptr) ctlr = dib->dev_num & 014; uptr->u4 = 0; uptr->u3 &= ~DS_VV; + uptr->u3 |= DS_DPR|DS_MOL|DS_DRY; + if (uptr->flags & UNIT_WLK) + uptr->u3 |= DS_WRL; rp_df10[ctlr].status |= PI_ENABLE; set_interrupt(dib->dev_num, rp_df10[ctlr].status & 7); return SCPE_OK; @@ -968,7 +1044,7 @@ t_stat rp_detach (UNIT *uptr) return SCPE_OK; if (sim_is_active (uptr)) /* unit active? */ sim_cancel (uptr); /* cancel operation */ - uptr->u3 &= ~DS_VV; + uptr->u3 &= ~(DS_VV|DS_WRL|DS_DPR|DS_DRY); return detach_unit (uptr); } diff --git a/PDP10/ka10_sys.c b/PDP10/ka10_sys.c index 0c60db3..ec85a17 100644 --- a/PDP10/ka10_sys.c +++ b/PDP10/ka10_sys.c @@ -138,9 +138,9 @@ DEBTAB dev_debug[] = { {"DATA", DEBUG_DATA, "Show data transfers"}, {"DETAIL", DEBUG_DETAIL, "Show details about device"}, {"EXP", DEBUG_EXP, "Show exception information"}, - {"CONI", DEBUG_EXP, "Show coni instructions"}, - {"CONO", DEBUG_EXP, "Show coni instructions"}, - {"DATAIO", DEBUG_EXP, "Show datai and datao instructions"}, + {"CONI", DEBUG_CONI, "Show coni instructions"}, + {"CONO", DEBUG_CONO, "Show coni instructions"}, + {"DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"}, {0, 0} };