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SEL32: Add track/sector label support for UDP/HSDP disks.

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SEL32: Add Linux network setup utility Setup.Net.
SEL32: Update disk image sim32disk to have track/sector labels.
SEL32: Update SEL32 documentation.
This commit is contained in:
AZBevier 2020-12-22 21:26:10 -07:00
parent 598749c579
commit 7be50aae66
18 changed files with 936 additions and 1385 deletions
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295
SEL32/sel32_chan.c
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@ -1,6 +1,6 @@
/* sel32_chan.c: SEL 32 Channel functions.
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -349,7 +349,7 @@ t_stat set_inch(UNIT *uptr, uint32 inch_addr) {
sim_debug(DEBUG_XIO, &cpu_dev,
"set_inch chan %04x inch addr %06x chp %p\n", chan, inch_addr, chp);
/* now go through all the sub addresses for the channel and set inch addr */
for (i=0; i<256; i++) {
for (i=0; i<SUB_CHANS; i++) {
chsa = chan | i; /* merge sa to real channel */
if (dib_unit[chsa] == dibp) /* if same dibp already done */
continue;
@ -650,7 +650,7 @@ loop:
return 1; /* error return */
}
#ifdef PROVIDE_FOR_DEVICE
#ifdef PROVIDE_FOR_EACH_DEVICE
/* validate the commands for the disk */
switch (chp->ccw_cmd) {
case DSK_WD: case DSK_RD: case DSK_INCH: case DSK_NOP: case DSK_ICH:
@ -882,23 +882,6 @@ int chan_read_byte(uint16 chsa, uint8 *data)
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte transferred %02x\n", byte);
chp->ccw_addr += 1; /* next byte address */
chp->ccw_count--; /* one char less to process */
#ifdef CAUSES_HALT_ON_LOAD
/* see if count is zero now */
if (chp->ccw_count == 0) { /* see if more data required */
if ((chp->ccw_flags & FLAG_DC) != 0) { /* see if Data Chain */
/* we have data chaining, process iocl */
if (load_ccw(chp, 1)) { /* process data chaining */
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_read_byte with DC error, cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chan);
return 1; /* return error */
}
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_read_byte with DC IOCD loaded, cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chan);
}
}
#endif
return 0; /* good return */
}
@ -913,28 +896,11 @@ int test_write_byte_end(uint16 chsa)
if (chp->ccw_count == 0) {
if ((chp->ccw_flags & FLAG_DC) == 0) { /* see if we have data chaining */
//1003 chp->chan_status |= STATUS_CEND; /* no, end of data */
//1003 chp->chan_byte = BUFF_CHNEND; /* thats all the data we want */
/*122320*/ chp->chan_byte = BUFF_CHNEND; /* thats all the data we want */
//sim_debug(DEBUG_EXP, &cpu_dev,
//"test_write_byte BUFF_CHNEND chp %p chan_byte %04x\n", chp, chp->chan_byte);
return 1; /* return done */
}
#ifdef OLD_WAY_112320
else {
/* we have data chaining, process iocl */
sim_debug(DEBUG_EXP, &cpu_dev,
"test_write_byte got DC, calling load_ccw chan %04x\n", chsa);
if (load_ccw(chp, 1)) { /* process data chaining */
sim_debug(DEBUG_EXP, &cpu_dev,
"test_write_byte with DC error, cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chsa);
return 1; /* return error */
}
sim_debug(DEBUG_EXP, &cpu_dev,
"test_write_byte with DC IOCD loaded cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chsa);
}
#endif
}
return 0; /* not done yet */
}
@ -1018,28 +984,6 @@ int chan_write_byte(uint16 chsa, uint8 *data)
chp->ccw_addr -= 1; /* no, use previous address */
else
chp->ccw_addr += 1; /* yes, use next address */
#ifdef CAUSES_HALT_ON_LOAD
/* see if count is zero now */
if (chp->ccw_count == 0) {
if ((chp->ccw_flags & FLAG_DC) == 0) { /* see if we have data chaining */
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_write_byte ZERO chan %04x ccw_count %04x addr %06x\n",
chan, chp->ccw_count, chp->ccw_addr);
/* we have data chaining, process iocl */
sim_debug(DEBUG_DETAIL, &cpu_dev,
"chan_write_byte got DC, calling load_ccw chan %04x\n", chan);
if (load_ccw(chp, 1)) { /* process data chaining */
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_write_byte with DC error, cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chan);
return 1; /* return error */
}
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_write_byte with DC IOCD loaded cnt %04x addr %06x chan %04x\n",
chp->ccw_count, chp->ccw_addr, chan);
}
}
#endif
return 0;
}
@ -1236,16 +1180,16 @@ void chan_end(uint16 chsa, uint16 flags) {
/* set status words in memory to first IOCD information */
sim_debug(DEBUG_XIO, &cpu_dev,
"$$ CHEND start IOCL processing chsa %04x iocla %06x\n",
chsa, iocla);
"$$ CHEND start IOCL processing from IOCLQ num %02x chsa %04x iocla %06x\n",
IOCLQ_Num(qp), chsa, iocla);
/* We are queueing the SIO */
/* Queue us to continue IOCL from cpu level & make busy */
chp->chan_byte = BUFF_NEXT; /* have main pick us up */
chp->chan_info = INFO_SIOCD; /* show first IOCD in channel prog */
sim_debug(DEBUG_EXP, &cpu_dev,
"chan_end BUFF_NEXT chas %04x from IOCLQ chp %p chan_byte %04x\n",
chsa, chp, chp->chan_byte);
"chan_end BUFF_NEXT chsa %04x from IOCLQ cnt %02x chp %p chan_byte %04x\n",
chsa, IOCLQ_Num(qp), chp, chp->chan_byte);
RDYQ_Put(chsa); /* queue us up */
sim_debug(DEBUG_XIO, &cpu_dev,
"$$$ CHEND SIO queued chsa %04x iocla %06x IOCD1 %08x IOCD2 %08x\n",
@ -1253,8 +1197,7 @@ void chan_end(uint16 chsa, uint16 flags) {
#ifndef TRY_UTX_DELAY
if (waitqcnt == 0)
// waitqcnt = 25; /* tell cpu to wait 20 instructions before int */
waitqcnt = 20; /* tell cpu to wait 20 instructions before int */
waitqcnt = 25; /* tell cpu to wait 20 instructions before int */
#endif
}
}
@ -1378,15 +1321,6 @@ nothere:
inta = ((~spadent)>>16)&0x7f; /* get channel interrupt level */
chp->chan_int = inta; /* make sure it is set in channel */
#ifdef NOT_NEEDED
if (uptr->flags & UNIT_ATTABLE) {
sim_debug(DEBUG_EXP, &cpu_dev,
"checkxio rchsa %04x flags UNIT_ATTABLE %1x UNIT_ATT %1x UNIT_DIS %1x\n",
rchsa, (uptr->flags & UNIT_ATTABLE)?1:0, (uptr->flags & UNIT_ATT)?1:0,
(uptr->flags & UNIT_DIS)?1:0);
}
#endif
/* check for the device being defined and attached in simh */
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) {
sim_debug(DEBUG_EXP, &cpu_dev,
@ -1457,9 +1391,11 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
"startxio entry inta %02x lchan %04x spadent %08x rchsa %04x\n",
inta, lchan, spadent, chsa);
dibp = dib_unit[chsa & 0x7f00]; /* get the device information pointer */
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
// uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
/* FIXME */
/* chp will be NULL for odd disk address */
// chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa&0x7f00); /* get unit 0 unit pointer */
if (uptr != NULL) {
dptr = get_dev(uptr); /* get device address */
@ -1475,7 +1411,7 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
incha = RMW(chan_icb+20); /* post inch addr in ICB+5w */
sim_debug(DEBUG_XIO, &cpu_dev,
"startxio debug itva %04x icba %04x iocla %06x incha %06x IOCD1 %08x IOCD2 %08x\n",
"startxio itva %03x icba %04x iocla %06x incha %06x IOCD1 %08x IOCD2 %08x\n",
itva, chan_icb, iocla, incha, RMW(iocla), RMW(iocla+4));
#endif
/* check if we have a valid unit */
@ -1546,16 +1482,6 @@ missing:
chp, chsa, chp->ccw_flags, tstat, tcnt);
return SCPE_OK; /* just busy CC3&CC4 */
}
#ifdef NOTHERE
else {
/* everyone else just gets a busy return */
*status = CC4BIT|CC3BIT; /* busy, so CC3&CC4 */
sim_debug(DEBUG_XIO, &cpu_dev,
"startxio done BUSY chp %p chsa %04x ccw_flags %04x stat %04x cnt %04x\n",
chp, chsa, chp->ccw_flags, tstat, tcnt);
}
return SCPE_OK; /* just busy CC3&CC4 */
#endif
}
// chan_icb = find_int_icb(chsa); /* Interrupt level context block address */
@ -1593,6 +1519,7 @@ missing:
if (dibp->pre_io != NULL) { /* NULL if no startio function */
DEVICE *dptr = get_dev(uptr); /* get device ptr */
int unit = uptr-dptr->units; /* get unit number */
/* call the device controller to get prestart_io status */
tempa = dibp->pre_io(uptr, chan); /* get status from device */
/* SCPE_OK if unit not busy and IOCLQ is not full */
@ -1622,8 +1549,8 @@ missing:
return SCPE_OK; /* just busy or something, CC3|CC4 */
}
sim_debug(DEBUG_XIO, &cpu_dev,
"startxio IOCLQ call sucessful chan %04x unit %02x\n",
chan, unit);
"startxio IOCLQ_Put call sucessful count %02x chan %04x unit %02x\n",
IOCLQ_Num(&dibp->ioclq_ptr[unit]), chan, unit);
*status = CC1BIT; /* CCs = 1, SIO accepted & queued, no echo status */
return SCPE_OK; /* CC1 all OK */
}
@ -1691,7 +1618,6 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
DIB *dibp; /* device information pointer */
UNIT *uptr; /* pointer to unit in channel */
uint32 chan_icb; /* Interrupt level context block address */
// uint32 iocla; /* I/O channel IOCL address int ICB */
CHANP *chp; /* Channel prog pointers */
uint32 inta, incha, itva;
uint16 lchan = get_chan(lchsa); /* get the logical channel number */
@ -1710,9 +1636,11 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
dibp = dib_chan[rchan]; /* get the DIB pointer */
chp = find_chanp_ptr(rchan << 8); /* find the device chanp pointer */
#ifndef TRY_UTX_DELAY
if (waitqcnt != 0)
#ifndef TRY_UTX_DELAY_121420
if (waitqcnt != 0) {
waitqcnt = 0; /* tell cpu ok to int */
/*add*/ irq_pend = 1; /* flag to test for int condition */
}
#endif
if (dibp == 0 || chp == 0) { /* if no dib or channel ptr, CC3 return */
*status = CC3BIT; /* not found, so CC3 */
@ -1730,50 +1658,19 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
return SCPE_OK; /* Not found, CC3 */
}
#ifdef NOT_HERE
/* check for a Command or data chain operation in progress */
if ((chp->chan_byte & BUFF_BUSY) && chp->chan_byte != BUFF_POST) {
sim_debug(DEBUG_EXP, &cpu_dev,
"TIO busy return CC3&CC4 chsa %04x chp %p cmd %02x flags %04x byte %02x\n",
chsa, chp, chp->ccw_cmd, chp->ccw_flags, chp->chan_byte);
*status = CC4BIT|CC3BIT; /* busy, so CC3&CC4 */
return SCPE_OK; /* just busy CC3&CC4 */
}
#endif
/* the XIO opcode processing software has already checked for F class */
inta = ((~spadent)>>16)&0x7f; /* get channel interrupt level */
chp->chan_int = inta; /* make sure it is set in channel */
itva = SPAD[0xf1] + (inta<<2); /* int vector address */
chan_icb = RMW(itva); /* Interrupt context block addr */
// inta = find_int_lev(chsa); /* Interrupt Level for channel */
// chan_icb = find_int_icb(chsa); /* Interrupt level context block address */
sim_debug(DEBUG_XIO, &cpu_dev,
"TIO int spad %08x icb %06x inta %04x rchan %04x\n",
SPAD[inta+0x80], chan_icb, inta, rchan);
// iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */
incha = chp->chan_inch_addr; /* get inch address */
#ifdef NOT_HERE
sim_debug(DEBUG_XIO, &cpu_dev,
"TIO test1 chsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x IOCLA %06x\n",
chsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4), iocla);
sim_debug(DEBUG_XIO, &cpu_dev,
"TIO test2 chsa %04x ICB incha %08x SW1 %08x SW2 %08x\n",
chsa, incha, RMW(incha), RMW(incha+4));
#endif
// chan = chan << 8; /* make zero unit channel */
/* see if any status ready to post */
if (FIFO_Num(rchsa)) {
#ifdef NOT_HERE
/* find actual device with the channel program */
uint32 tempa = dibp->chan_fifo[dibp->chan_fifo_out]; /* get SW1 of FIFO entry */
chsa = (chan) | (tempa >> 24); /* find device address for requesting chan prog */
chp = find_chanp_ptr(chsa); /* find the chanp pointer for channel */
#endif
sim_debug(DEBUG_IRQ, &cpu_dev,
"TIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n",
rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte);
@ -1791,12 +1688,7 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
sim_debug(DEBUG_XIO, &cpu_dev,
"TIO END status stored incha %06x rchsa %04x sw1 %08x sw2 %08x\n",
incha, rchsa, RMW(incha), RMW(incha+4));
#ifndef FIX_SPARE_INT_IN_DPDIAG
if (FIFO_Num(rchsa) == 0)
INTS[inta] &= ~INTS_REQ; /* clear any level request if no status */
#else
INTS[inta] &= ~INTS_REQ; /* clear any level request if no status */
#endif
*status = CC2BIT; /* status stored from SIO, so CC2 */
return SCPE_OK; /* No CC's all OK */
} else {
@ -1823,7 +1715,7 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
}
/* Stop XIO */
t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
DIB *dibp; /* device information pointer */
UNIT *uptr; /* pointer to unit in channel */
uint32 chan_icb; /* Interrupt level context block address */
@ -1871,8 +1763,8 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
"STPIO busy test rchsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]);
// sim_debug(DEBUG_CMD, &cpu_dev, "$$$ STPIO %04x %02x %04x\n",
// chsa, chp->ccw_cmd, chp->ccw_flags);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ STPIO %04x %02x %04x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags);
if ((chp->chan_byte & BUFF_BUSY) == 0) {
/* the channel is not busy, so return OK */
@ -1912,7 +1804,7 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
/* change status from BUFF_POST to BUFF_DONE */
/*082420*/ if (chp->chan_byte == BUFF_POST) {
/*082420*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
sim_debug(DEBUG_EXP, &cpu_dev, "STPIO BUFF_DONE1 chp %p chan_byte %04x\n", chp, chp->chan_byte);
//sim_debug(DEBUG_EXP, &cpu_dev, "STPIO BUFF_DONE1 chp %p chan_byte %04x\n", chp, chp->chan_byte);
}
return SCPE_OK; /* CC2 & all OK */
}
@ -1938,12 +1830,16 @@ sim_debug(DEBUG_EXP, &cpu_dev, "STPIO BUFF_DONE1 chp %p chan_byte %04x\n", chp,
}
/* device does not have stop_io entry, so stop the I/O */
/* check for a Command or data chain operation in progresss */
/* set the return to CC3BIT & CC4BIT causes infinite loop in MPX1X */
/* restore code to old CC1BIT return 12/21/2020 */
*status = CC1BIT; /* request accepted, no status, so CC1 */
// *status = CC4BIT; /*1204*/ /* device is busy, so CC4 */
// *status = CC3BIT|CC4BIT; /*1204*/ /* device is busy, so CC3 & CC4 */
/* reset the DC or CC bits to force completion after current IOCD */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
sim_debug(DEBUG_CMD, &cpu_dev,
"STPIO busy return CC1 %08x rchsa %04x status %08x flags %04x\n",
CC1BIT, rchsa, *status, chp->ccw_flags);
"STPIO busy return CC1 %08x rchsa %04x status %08x cmd %02x flags %04x\n",
CC1BIT, rchsa, *status, chp->ccw_cmd, chp->ccw_flags);
return SCPE_OK; /* go wait CC1 */
}
@ -2000,7 +1896,7 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
SPAD[inta+0x80] &= ~SINT_ACT; /* clear in spad too */
/* now go through all the sa for the channel and stop any IOCLs */
for (i=0; i<256; i++) {
for (i=0; i<SUB_CHANS; i++) {
rchsa = rchan | i; /* merge sa to real channel */
dibp = dib_unit[rchsa]; /* get the DIB pointer */
if (dibp == 0)
@ -2073,27 +1969,8 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
// incha = RMW(chan_icb+20); /* post inch addr in ICB+5w */
sim_debug(DEBUG_XIO, &cpu_dev,
"$$ HIO busy test rchsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4));
if ((chp->chan_byte & BUFF_BUSY) == 0) {
/* the channel is not busy, so return OK */
*status = CC1BIT; /* request accepted, no status, so CC1 */
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ HIO END1 rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags, *status);
chp->chan_byte = BUFF_DONE; /* we are done */
sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
chp->chan_status = (STATUS_DEND|STATUS_CEND);
store_csw(chp); /* store the status */
/* change chan_byte to BUFF_POST */
chp->chan_byte = BUFF_POST; /* show done with data */
sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_POST chp %p chan_byte %04x\n", chp, chp->chan_byte);
chp->chan_status = 0; /* no status anymore */
chp->ccw_cmd = 0; /* no command anymore */
irq_pend = 1; /* flag to test for int condition */
return SCPE_OK; /* CC1 & all OK */
}
"$$ HIO busy test byte %02x rchsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x\n",
chp->chan_byte, rchsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4));
/* the channel is busy, so process */
/* see if we have a haltio device entry */
@ -2133,6 +2010,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_POST chp %p chan_byte %04x\n", chp,
chp->ccw_count = 0; /* zero the count */
/* The diags want the interrupt for the disk */
*status = CC1BIT; /* request accepted, no status, so CC1 */
//BAD *status = CC4BIT; /* request accepted, no status, so CC1 */
//BAD *status = 0; /* request accepted, no status, so CC1 */
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ HIO END2 ECHO rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
@ -2148,8 +2026,44 @@ sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_POST chp %p chan_byte %04x\n", chp,
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ HIO END3 rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags, *status);
#ifndef GIVE_INT_ON_NOT_BUSY_121420
chp->chan_byte = BUFF_DONE; /* we are done */
sim_debug(DEBUG_EXP, &cpu_dev,
"haltxio BUFF_DONE2 chp %p chan_byte %04x\n", chp, chp->chan_byte);
chp->chan_status = (STATUS_DEND|STATUS_CEND);
store_csw(chp); /* store the status */
/* change chan_byte to BUFF_POST */
chp->chan_byte = BUFF_POST; /* show done with data */
chp->chan_status = 0; /* no status anymore */
chp->ccw_cmd = 0; /* no command anymore */
irq_pend = 1; /* flag to test for int condition */
#endif
return SCPE_OK; /* No CC's all OK */
}
/* device does not have a HIO entry, so terminate the I/O */
if ((chp->chan_byte & BUFF_BUSY) == 0) {
/* the channel is not busy, so return OK */
*status = CC1BIT; /* request accepted, no status, so CC1 */
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ HIO END1 not busy return rchsa %04x cmd %02x ccw_flags %04x status %04x\n",
rchsa, chp->ccw_cmd, chp->ccw_flags, *status);
#ifndef JUNK
chp->chan_byte = BUFF_DONE; /* we are done */
sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
//1204 chp->chan_status = (STATUS_DEND|STATUS_CEND);
/*1204*/chp->chan_status = (STATUS_DEND|STATUS_CEND|STATUS_EXPT);
store_csw(chp); /* store the status */
/* change chan_byte to BUFF_POST */
chp->chan_byte = BUFF_POST; /* show done with data */
//sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_POST chp %p chan_byte %04x\n", chp, chp->chan_byte);
chp->chan_status = 0; /* no status anymore */
chp->ccw_cmd = 0; /* no command anymore */
irq_pend = 1; /* flag to test for int condition */
#endif
return SCPE_OK; /* CC1 & all OK */
}
/* device does not have a HIO entry, so terminate the I/O */
/* a haltxio entry should be provided for a device so busy can be cleared */
/* check for a Command or data chain operation in progresss */
@ -2159,7 +2073,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_POST chp %p chan_byte %04x\n", chp,
/* reset the DC or CC bits to force completion */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
chp->chan_byte = BUFF_BUSY; /* wait for post_csw to be done */
sim_debug(DEBUG_EXP, &cpu_dev, "HIO BUFF_DONE3 chp %p chan_byte %04x\n", chp, chp->chan_byte);
//sim_debug(DEBUG_EXP, &cpu_dev, "HIO BUFF_DONE3 chp %p chan_byte %04x\n", chp, chp->chan_byte);
// chp->ccw_count = 0; /* zero the count */
sim_cancel(uptr); /* cancel timer service */
chp->chan_status &= ~STATUS_BUSY; /* remove BUSY status bit */
@ -2178,7 +2092,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "HIO BUFF_DONE3 chp %p chan_byte %04x\n", chp, ch
/* change status from BUFF_POST to BUFF_DONE */
/*082420*/ if (chp->chan_byte == BUFF_POST) {
/*082420*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
sim_debug(DEBUG_EXP, &cpu_dev, "HIO BUFF_DONE4 chp %p chan_byte %04x\n", chp, chp->chan_byte);
//sim_debug(DEBUG_EXP, &cpu_dev, "HIO BUFF_DONE4 chp %p chan_byte %04x\n", chp, chp->chan_byte);
}
return SCPE_OK; /* CC2 & all OK */
}
@ -2238,10 +2152,13 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u *
return SCPE_OK; /* CC4 all OK */
}
/* If this is console, debuger wants CC3 & CC4 = 0 */
/* If this is console, debugger wants CC3 & CC4 = 0 */
if (rchan == 0x7e) {
/* returning No CC's causes MPX1X to loop forever */
/* so restore returning CC1 */
*status = 0; /* return no CC's */
// *status = CC1BIT; /* return no CC's */
// *status = CC3BIT|CC4BIT; /* busy */
} else {
/* diags want unsupported transaction for disk */
*status = CC2BIT|CC4BIT; /* unsupported transaction */
@ -2252,7 +2169,7 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u *
}
/* reset controller XIO */
t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
DIB *dibp;
UNIT *uptr;
uint32 spadent;
@ -2260,6 +2177,7 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
CHANP *chp;
int lev, i;
uint32 chan = get_chan(lchsa);
DEVICE *dptr; /* get device ptr */
/* get the device entry for the logical channel in SPAD */
spadent = SPAD[chan]; /* get spad device entry for logical channel */
@ -2279,40 +2197,45 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
dptr = get_dev(uptr); /* get device ptr */
lev = find_int_lev(chan); /* get our int level */
INTS[lev] &= ~INTS_ACT; /* clear level active */
SPAD[lev+0x80] &= ~SINT_ACT; /* clear spad too */
INTS[lev] &= ~INTS_REQ; /* clear level request */
/* now go through all the sa for the channel and stop any IOCLs */
for (i=0; i<256; i++) {
for (i=0; i<SUB_CHANS; i++) {
int j;
IOCLQ *qp; /* IOCLQ pointer */
int unit; /* get the UNIT number */
chsa = chan | i; /* merge sa to real channel */
dibp = dib_unit[chsa]; /* get the DIB pointer */
if (dibp == 0) {
continue; /* not used */
}
/* reset the FIFO pointers */
dibp->chan_fifo_in = 0; /* set no FIFO entries */
dibp->chan_fifo_out = 0; /* set no FIFO entries */
// qp = &dibp->ioclq_ptr[0]; /* IOCLQ pointer */
if ((dibp->ioclq_ptr != NULL) && (qp != NULL)) {
for (j=0; j<dibp->numunits; j++) {
qp = &dibp->ioclq_ptr[j]; /* IOCLQ pointer */
qp->ioclq_in = 0; /* clear any entries */
qp->ioclq_out = 0; /* clear any entries */
}
}
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
if (chp == 0) {
continue; /* not used */
}
/* reset the FIFO pointers */
dibp->chan_fifo_in = 0; /* set no FIFO entries */
dibp->chan_fifo_out = 0; /* set no FIFO entries */
uptr = chp->unitptr; /* get the unit ptr */
unit = uptr - dptr->units; /* get the UNIT number */
qp = &dibp->ioclq_ptr[unit]; /* IOCLQ pointer */
if (qp != NULL) {
qp->ioclq_in = 0; /* clear any entries */
qp->ioclq_out = 0; /* clear any entries */
}
/* see if we have a rsctl device entry */
if (dibp->rsctl_io != NULL) { /* NULL if no haltio function */
/* call the device controller to process rsctl */
j = dibp->rsctl_io(uptr); /* get status from device */
sim_debug(DEBUG_CMD, &cpu_dev,
"rsctl_io returned %02x chsa %04x\n", j, chan);
}
chp->chan_status = 0; /* clear the channel status */
chp->chan_byte = BUFF_EMPTY; /* no data yet */
@ -2324,8 +2247,12 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
chp->ccw_cmd = 0; /* read command */
}
sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio return CC1 chan %04x lev %04x\n", chan, lev);
// *status = CC1BIT; /* request accepted, no status, so CC1 TRY THIS */
*status = 0; /* request accepted, no status, return 0 */
/* returning 0 for status breaks ethernet controller */
if ((dptr != NULL) &&
(DEV_TYPE(dptr) == DEV_ETHER)) { /* see if this is ethernet */
*status = CC1BIT; /* request accepted, no status, so CC1 */
} else
*status = 0; /* request accepted, no status, return 0 */
return SCPE_OK; /* All OK */
}
@ -2383,7 +2310,7 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr) {
chan, chp->chan_status);
chp->ccw_flags = 0; /* clear the command flags */
chp->chan_byte = BUFF_DONE; /* done with errors */
sim_debug(DEBUG_EXP, &cpu_dev, "chan_boot BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
//sim_debug(DEBUG_EXP, &cpu_dev, "chan_boot BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
loading = 0; /* show we are done loading from the boot device */
return SCPE_IOERR; /* return error */
}
@ -2515,6 +2442,10 @@ uint32 scan_chan(uint32 *ilev) {
/* see if we are able to look for ints */
if (irq_pend == 0) /* pending int? */
return 0; /* no, done */
#ifndef TRY_121420_NOGOOD
if (CPUSTATUS & BIT24) /* interrupts blocked? */
return 0; /* yes, done */
#endif
/* ints not blocked, so look for highest requesting interrupt */
for (i=0; i<112; i++) {
@ -2560,12 +2491,12 @@ uint32 scan_chan(uint32 *ilev) {
if (CPUSTATUS & BIT24) { /* interrupts blocked? */
#endif
if (waitqcnt) /* interrupts blocked? */
// sim_debug(DEBUG_DETAIL, &cpu_dev,
sim_debug(DEBUG_IRQ, &cpu_dev,
sim_debug(DEBUG_DETAIL, &cpu_dev,
// sim_debug(DEBUG_IRQ, &cpu_dev,
"scan_chan waitqcnt %02x\n", waitqcnt);
if (CPUSTATUS & BIT24) /* interrupts blocked? */
// sim_debug(DEBUG_DETAIL, &cpu_dev,
sim_debug(DEBUG_IRQ, &cpu_dev,
sim_debug(DEBUG_DETAIL, &cpu_dev,
// sim_debug(DEBUG_IRQ, &cpu_dev,
"scan_chan INTS blocked!\n");
goto tryme; /* needed for MPX */
}
@ -2643,7 +2574,7 @@ uint32 scan_chan(uint32 *ilev) {
/* so leave the channel status alone */
/*082420*/ if (chp->chan_byte == BUFF_POST) {
/*082420*/ chp->chan_byte = BUFF_DONE; /* show done & not busy */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chanx BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
//sim_debug(DEBUG_EXP, &cpu_dev, "scan_chanx BUFF_DONE chp %p chan_byte %04x\n", chp, chp->chan_byte);
}
} else {
sim_debug(DEBUG_IRQ, &cpu_dev,
@ -2866,7 +2797,7 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
/* change all the unit addresses with the new channel, but keep sub address */
/* Clear out existing entries for all units on this device */
tuptr = dptr->units; /* get pointer to units defined for this device */
fprintf(stderr, "Set dev new addr %s chan %04X units %02X\r\n", cptr, chan, dibp->numunits);
// fprintf(stderr, "Set dev new addr %s chan %04X units %02X\r\n", cptr, chan, dibp->numunits);
/* loop through all units for this device */
for (i = 0; i < dibp->numunits; i++) {
@ -2878,8 +2809,8 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
tuptr->u3 |= UNIT_ADDR(chsa); /* set new chsa for this unit */
dib_unit[chan&0x7f00] = dibp; /* set the channel dib address */
dib_unit[chsa] = dibp; /* save the dib address for new chsa */
fprintf(stderr, "Set old chsa %04X to new addr %04X new chsa %04X\r\n",
ochsa, GET_UADDR(tuptr->u3), chsa);
// fprintf(stderr, "Set old chsa %04X to new addr %04X new chsa %04X\r\n",
// ochsa, GET_UADDR(tuptr->u3), chsa);
tuptr++; /* next unit pointer */
}
return SCPE_OK;

12
SEL32/sel32_clk.c
View File

@ -1,7 +1,7 @@
/* sel32_clk.c: SEL 32 Class F IOP processor RTOM functions.
Copyright (c) 2018-2020, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -28,7 +28,6 @@
when the count reaches zero, The clock continues down counting
until read/reset by the programmer. The rate can be external or
38.4 microseconds per count.
*/
#include "sel32_defs.h"
@ -104,15 +103,9 @@ DEVICE rtc_dev = {
sets an interrupt that invokes the clock counter.
*/
#ifdef DO_TIME
uint32 lastms = 0;
uint32 grtime = 0;
#endif
/* service clock signal from simulator */
t_stat rtc_srv (UNIT *uptr)
{
// int32 temp;
#ifdef STOP_CLOCK_INTS_FOR_DEXP_TEST_DEBUGGING
/* stop clock interrupts for dexp debugging */
rtc_pie = 0;
@ -367,7 +360,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
switch (cmd) {
case 0x20: /* stop timer */
/* stop the timer and save the curr value for later */
// fprintf(stderr, "clk 0x20 kill value %08x (%08d)\r\n", cnt, cnt);
temp = itm_load; /* use last loaded value */
sim_debug(DEBUG_CMD, &itm_dev, "Intv 0x%2x kill value %08x (%08d) itm_load %08x\n",
cmd, cnt, cnt, temp);

2
SEL32/sel32_com.c
View File

@ -1,6 +1,6 @@
/* sel32_com.c: SEL 32 8-Line IOP communications controller
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a

30
SEL32/sel32_con.c
View File

@ -1,6 +1,6 @@
/* sel32_con.c: SEL 32 Class F IOP processor console.
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -214,36 +214,12 @@ uint16 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD |= (cmd & CON_MSK); /* save command */
if (unit == 0)
sim_cancel(uptr); /* stop input poll */
// sim_activate(uptr, 400); /* start us off */
sim_activate(uptr, 400); /* start us off */
// sim_activate(uptr,1000); /* start us off */
sim_activate(uptr, 500); /* start us off */
// sim_activate(uptr, 500); /* start us off */
return SCPE_OK; /* no status change */
break;
#ifdef NONO
case CON_CON: /* 0x1f */ /* Connect, return Data Set ready */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd %02xN\n", chan, cmd);
uptr->SNS |= (SNS_DSR|SNS_DCD); /* Data set ready, Data Carrier detected */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case CON_DIS: /* 0x23 */ /* Disconnect has do nothing */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd %02x DIS\n", chan, cmd);
uptr->SNS &= ~(SNS_DSR|SNS_DCD); /* Data set not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case CON_SNS: /* 0x04 */ /* Sense */
sim_debug(DEBUG_CMD, &con_dev,
"con_startcmd %04x: Cmd Sense %02x\n", chan, uptr->SNS);
/* value 4 is Data Set Ready */
/* value 5 is Data carrier detected n/u */
ch = uptr->SNS; /* status */
chan_write_byte(GET_UADDR(uptr->CMD), &ch); /* write status */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
#endif
default: /* invalid command */
break;
}

228
SEL32/sel32_cpu.c
View File

@ -1,6 +1,6 @@
/* sel32_cpu.c: Sel 32 CPU simulator
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -26,70 +26,6 @@
#define DO_DYNAMIC_DEBUG
/* 32/7x PSW/PSD Mode Trap/Interrupt Priorities */
/* Relative Logical Int Vect TCW IOCD Description */
/* Priority Priority Location Addr Addr */
/* 0 0F4 Power Fail Safe Trap */
/* 1 0FC System Override Trap (Not Used) */
/* 2 0E8* Memory Parity Trap */
/* 3 190 Nonpresent Memory Trap */
/* 4 194 Undefined Instruction Trap */
/* 5 198 Privilege Violation Trap */
/* 6 180 Supervisor Call Trap (SVC) */
/* 7 184 Machine Check Trap */
/* 8 188 System Check Trap */
/* 9 18C Map Fault Trap */
/* A Not Used */
/* B Not Used */
/* C Not Used */
/* D Not Used */
/* E 0E4 Block Mode Timeout Trap */
/* F 1A4* Arithmetic Exception Trap */
/* 10 00 0F0 Power Fail Safe Interrupt */
/* 11 01 0F8 System Override Interrupt */
/* 12 12 0E8* Memory Parity Trap */
/* 13 13 0EC Attention Interrupt */
/* 14 14 140 100 700 I/O Channel 0 interrupt */
/* 15 15 144 104 708 I/O Channel 1 interrupt */
/* 16 16 148 108 710 I/O Channel 2 interrupt */
/* 17 17 14C 10C 718 I/O Channel 3 interrupt */
/* 18 18 150 110 720 I/O Channel 4 interrupt */
/* 19 19 154 114 728 I/O Channel 5 interrupt */
/* 1A 1A 158 118 730 I/O Channel 6 interrupt */
/* 1B 1B 15C 11C 738 I/O Channel 7 interrupt */
/* 1C 1C 160 120 740 I/O Channel 8 interrupt */
/* 1D 1D 164 124 748 I/O Channel 9 interrupt */
/* 1E 1E 168 128 750 I/O Channel A interrupt */
/* 1F 1F 16C 12C 758 I/O Channel B interrupt */
/* 20 20 170 130 760 I/O Channel C interrupt */
/* 21 21 174 134 768 I/O Channel D interrupt */
/* 22 22 178 138 770 I/O Channel E interrupt */
/* 23 23 17C 13C 778 I/O Channel F interrupt */
/* 24 24 190* Nonpresent Memory Trap */
/* 25 25 194* Undefined Instruction Trap */
/* 26 26 198* Privlege Violation Trap */
/* 27 27 19C Call Monitor Interrupt */
/* 28 28 1A0 Real-Time Clock Interrupt */
/* 29 29 1A4* Arithmetic Exception Interrupt */
/* 2A 2A 1A8 External/Software Interrupt */
/* 2B 2B 1AC External/Software Interrupt */
/* 2C 2C 1B0 External/Software Interrupt */
/* 2D 2D 1B4 External/Software Interrupt */
/* 2E 2E 1B8 External/Software Interrupt */
/* 2F 2F 1BC External/Software Interrupt */
/* 30 30 1C0 External/Software Interrupt */
/* 31 31 1C4 External/Software Interrupt */
/* THRU THRU THRU THRU */
/* 77 77 2DC External/Software Interrupt */
/* 78 2E0 End of IPU Processing Trap (CPU) */
/* 79 2E4 Start IPU Processing Trap (IPU) */
/* 7A 2E8 Supervisor Call Trap (IPU) */
/* 7B 2EC Error Trap (IPU) */
/* 7C 2F0 Call Monitor Trap (IPU) */
/* 7D 7D 2F4 Stop IPU Processing Trap (IPU) */
/* 7E 7E 2F8 External/Software Interrupt */
/* 7F 7F 2FC External/Software Interrupt */
/* Concept 32 PSD Mode Trap/Interrupt Priorities */
/* Relative|Logical |Int Vect|TCW |IOCD|Description */
/* Priority|Priority|Location|Addr|Addr */
@ -227,13 +163,13 @@ uint8 waitqcnt = 0; /* # instructions before start */
struct InstHistory
{
uint32 opsd1; /* original PSD1 */
uint32 opsd2; /* original PSD2 */
uint32 npsd1; /* new PSD1 after instruction */
uint32 npsd2; /* new PSD2 after instruction */
uint32 oir; /* the instruction itself */
uint32 modes; /* current cpu mode bits */
uint32 reg[16]; /* regs/bregs for operation */
uint32 opsd1; /* original PSD1 */
uint32 opsd2; /* original PSD2 */
uint32 npsd1; /* new PSD1 after instruction */
uint32 npsd2; /* new PSD2 after instruction */
uint32 oir; /* the instruction itself */
uint32 modes; /* current cpu mode bits */
uint32 reg[16]; /* regs/bregs for operation */
};
/* forward definitions */
@ -292,9 +228,9 @@ extern uint32 s_normfw(uint32 mem, uint32 *cc);
extern t_uint64 s_normfd(t_uint64 mem, uint32 *cc);
/* History information */
int32 hst_p = 0; /* History pointer */
int32 hst_lnt = 0; /* History length */
struct InstHistory *hst = NULL; /* History stack */
int32 hst_p = 0; /* History pointer */
int32 hst_lnt = 0; /* History length */
struct InstHistory *hst = NULL; /* History stack */
/* CPU data structures
@ -1966,8 +1902,11 @@ wait_loop:
}
#ifndef TRY_UTX_DELAY
if (waitqcnt > 0)
if (waitqcnt > 0) {
waitqcnt--; /* wait b4 ints */
/*121420*/ if (waitqcnt == 0)
/*121420*/ irq_pend = 1; /* start scanning interrupts again */
}
#endif
/* we are booting the system, so see if boot channel prog is completed */
@ -2013,18 +1952,7 @@ wait_loop:
sim_debug(DEBUG_XIO, &cpu_dev,
"CPU RDYQ entry loading for chsa %04x processed\n", chsa);
}
#ifdef XXXXX
goto wait_loop; /* continue waiting for boot */
#endif
}
#ifdef XXXXX
/* see if in wait instruction */
if (wait4int) { /* keep waiting */
/* tell simh we will be waiting */
//0905 sim_idle(TMR_RTC, 1); /* wait for clock tick */
sim_idle(TMR_RTC, 1); /* wait for clock tick */
}
#endif
goto wait_loop; /* continue waiting */
}
@ -2085,10 +2013,6 @@ wait_loop:
irq_auto, il, INTS[il], il+0x80, SPAD[il+0x80]);
}
irq_auto = il; /* show processing in blocked mode */
#ifdef LEAVE_AUTO_INT_ACT_051020
INTS[il] &= ~INTS_ACT; /* deactivate specified int level */
SPAD[il+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
#endif
sim_debug(DEBUG_IRQ, &cpu_dev,
"<|>Auto-reset interrupt INTS[%02x] %08x SPAD[%02x] %08x simi %02x\n",
il, INTS[il], il+0x80, SPAD[il+0x80], sim_interval);
@ -2100,10 +2024,6 @@ wait_loop:
CPUSTATUS &= ~BIT24; /* no, reset blk state in cpu status bit 24 */
MODES &= ~BLKMODE; /* reset blocked mode */
}
#ifndef DO_DYNAMIC_DEBUG
/* start debugging */
cpu_dev.dctrl |= DEBUG_INST;
#endif
} else {
/* handle retain blocking state */
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
@ -2158,7 +2078,6 @@ wait_loop:
"scan_chan CPU RDYQ entry for chsa %04x processed w/error byte %04x\n",
chsa, chp->chan_byte);
}
// goto wait_loop; /*1119*/ /* continue waiting */
}
}
#else
@ -2189,7 +2108,6 @@ wait_loop:
/* see if in wait instruction */
if (wait4int) { /* keep waiting */
/* tell simh we will be waiting */
//0905 sim_idle(TMR_RTC, 1); /* wait for clock tick */
sim_idle(TMR_RTC, 1); /* wait for clock tick */
irq_pend = 1; /* start scanning interrupts again */
goto wait_loop; /* continue waiting */
@ -2249,19 +2167,12 @@ skipi:
IR <<= 16; /* put instruction in left hw */
if ((CPU_MODEL <= MODEL_27) || (CPU_MODEL == MODEL_87) ||
(CPU_MODEL == MODEL_97) || (CPU_MODEL == MODEL_V9)) {
#ifdef NOTNOW
if (skipinstr)
sim_debug(DEBUG_IRQ, &cpu_dev,
"1Rt HW instruction skipinstr %1x is set PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
skipinstr, PSD1, PSD2, CPUSTATUS);
#endif
drop_nop = 0; /* not dropping nop for these machines */
goto exec; /* machine does not drop nop instructions */
}
/* We have 67 or V6 and have a rt hw instruction */
if (IR == 0x00020000) { /* is this a NOP from rt hw? */
PSD1 = (PSD1 + 2) | (((PSD1 & 2) >> 1) & 1); /* skip this instruction */
// fprintf(stderr, "RIGHT HW skip NOP instr %x skip nop at %x\n", IR, PSD1);
if (skipinstr)
sim_debug(DEBUG_IRQ, &cpu_dev,
"2Rt HW instruction skipinstr %1x is set PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
@ -2287,7 +2198,6 @@ skipi:
if ((IR & 0xffff) == 0x0002) { /* see if rt hw is a nop */
/* treat this as a fw instruction */
drop_nop = 1; /* we need to skip nop next time */
// fprintf(stderr, "LEFT HW skip NOP instr %x skip nop at %x\r\n", IR, PSD1);
}
}
}
@ -2304,14 +2214,6 @@ exec:
sim_debug(DEBUG_DETAIL, &cpu_dev, "-----Instr @ PC %08x PSD1 %08x PSD2 %08x IR %08x\n",
PC, PSD1, PSD2, IR);
#ifdef OLDPLACE
/* check for breakpoint request */
if (sim_brk_summ && sim_brk_test(PC, SWMASK('E'))) {
reason = STOP_IBKPT;
break;
}
#endif
/* Update history for this instruction */
if (hst_lnt) {
hst_p += 1; /* next history location */
@ -2685,7 +2587,6 @@ exec:
}
fprintf(stdout, "[][][][][][][][][][] HALT [][][][][][][][][][]\r\n");
/*TEST DIAG*/ reason = STOP_HALT; /* do halt for now */
///*TEST DIAG*/ return STOP_HALT; /* exit to simh for halt */
break;
case 0x1: /* WAIT */
if ((MODES & PRIVBIT) == 0) { /* must be privileged to wait */
@ -2713,7 +2614,6 @@ exec:
}
wait4int = 1; /* show we are waiting for interrupt */
/* tell simh we will be waiting */
//0905 sim_idle(TMR_RTC, 1); /* wait for clock tick */
sim_idle(TMR_RTC, 0); /* wait for next pending device event */
/*719*/ irq_pend = 1; /* start scanning interrupts again */
i_flags |= BT; /* keep PC from being incremented while waiting */
@ -2773,11 +2673,6 @@ exec:
TRAPSTATUS |= BIT19; /* set bit 19 of trap status */
goto newpsd; /* Privlege violation trap */
}
#ifdef FOR_DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev,
"bei int was %01x at PSD1 %08x PSD2 %08x\n",
CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
#endif
CPUSTATUS |= BIT24; /* into status word bit 24 too */
PSD2 &= ~(SETBBIT|RETBBIT); /* clear bit 48 & 49 */
MODES &= ~(BLKMODE|RETMODE);/* reset blocked & retain mode bits */
@ -2796,11 +2691,6 @@ CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
TRAPSTATUS |= BIT19; /* set bit 19 of trap status */
goto newpsd; /* Privlege violation trap */
}
#ifdef FOR_DEBUG
sim_debug(DEBUG_IRQ, &cpu_dev,
"uei int was %01x at PSD1 %08x PSD2 %08x\n",
CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
#endif
if (CPUSTATUS & BIT24) { /* see if old mode is blocked */
irq_pend = 1; /* start scanning interrupts again */
if (irq_auto) {
@ -2811,10 +2701,6 @@ CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
irq_auto, PSD1, PSD2);
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
/*103020*/ skipinstr = 1; /* skip interrupt test */
#ifndef DO_DYNAMIC_DEBUG
/* stop debugging */
cpu_dev.dctrl &= ~DEBUG_INST;
#endif
}
}
CPUSTATUS &= ~BIT24; /* clear status word bit 24 */
@ -2830,8 +2716,6 @@ CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
break;
case 0x9: /* RDSTS */
GPR[reg] = CPUSTATUS; /* get CPU status word */
//sim_debug(DEBUG_CMD, &cpu_dev,
//"RDSTS CPUSTATUS %08x SPAD[0xf9] %08x\n", CPUSTATUS, SPAD[0xf9]);
break;
case 0xA: /* SIPU */ /* ignore for now */
sim_debug(DEBUG_CMD, &cpu_dev,
@ -3093,13 +2977,11 @@ CPUSTATUS&0x80 ? 1 : 0, PSD1, PSD2);
break;
case 0x08: /* 0x0408 INV (Diag Illegal instruction) */
#ifndef NO_HACK
/* HACK HACK HACK for DIAGS */
if (CPU_MODEL <= MODEL_27) { /* DIAG error for 32/27 only */
if ((PSD1 & 2) == 0) /* if lf hw instruction */
i_flags |= HLF; /* if nop in rt hw, bump pc a word */
}
#endif
/* drop through */
default: /* INV */ /* everything else is invalid instruction */
TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
@ -3825,8 +3707,6 @@ tbr: /* handle basemode TBR too *
t = (GPR[reg] >> 16) & 0xff; /* get SPAD address from Rd (6-8) */
temp2 = SPAD[t]; /* get old SPAD data */
SPAD[t] = GPR[sreg]; /* store Rs into SPAD */
//sim_debug(DEBUG_CMD, &cpu_dev,
//"At TRSC with spad[%02x] %08x old %08x\n", t, SPAD[t], temp2);
break;
case 0xF: /* TSCR */ /* Transfer scratchpad to register */
@ -3840,8 +3720,6 @@ tbr: /* handle basemode TBR too *
}
t = (GPR[sreg] >> 16) & 0xff; /* get SPAD address from Rs (9-11) */
temp = SPAD[t]; /* get SPAD data into Rd (6-8) */
//sim_debug(DEBUG_CMD, &cpu_dev,
//"At TSCR with spad[%02x] %08x\n", t, SPAD[t]);
break;
}
GPR[reg] = temp; /* save the temp value to Rd reg */
@ -3915,10 +3793,6 @@ skipit:
irq_auto, PSD1);
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
/*103020*/ skipinstr = 1; /* skip interrupt test */
#ifndef DO_DYNAMIC_DEBUG
/* stop debugging */
cpu_dev.dctrl &= ~DEBUG_INST;
#endif
}
}
} else {
@ -5190,13 +5064,6 @@ meoa: /* merge point for eor, and, or */
"\n\tR0=%.8x R1=%.8x R2=%.8x R3=%.8x", GPR[0], GPR[1], GPR[2], GPR[3]);
sim_debug(DEBUG_INST, &cpu_dev,
" R4=%.8x R5=%.8x R6=%.8x R7=%.8x\n", GPR[4], GPR[5], GPR[6], GPR[7]);
#ifdef NOTNOW
if (skipinstr)
sim_debug(DEBUG_IRQ, &cpu_dev,
"EXM skipinstr %x reset irq_pend %x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
skipinstr, irq_pend, PSD1, PSD2, CPUSTATUS);
#endif
/*DIAG*/ //1106 skipinstr = 0; /* only test this once */
goto exec; /* go execute the instruction */
break;
@ -5542,10 +5409,6 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
irq_auto, temp2, PSD1);
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
/*103020*/ skipinstr = 1; /* skip interrupt test */
#ifndef DO_DYNAMIC_DEBUG
/* stop debugging */
cpu_dev.dctrl &= ~DEBUG_INST;
#endif
}
}
} else {
@ -5614,13 +5477,6 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
"\n\tR0=%.8x R1=%.8x R2=%.8x R3=%.8x", GPR[0], GPR[1], GPR[2], GPR[3]);
sim_debug(DEBUG_INST, &cpu_dev,
" R4=%.8x R5=%.8x R6=%.8x R7=%.8x\n", GPR[4], GPR[5], GPR[6], GPR[7]);
#ifdef NOTNOW
if (skipinstr)
sim_debug(DEBUG_IRQ, &cpu_dev,
"EXR skipinstr %x reset irq_pend %x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
skipinstr, irq_pend, PSD1, PSD2, CPUSTATUS);
#endif
/*DIAG*/ //1106 skipinstr = 0; /* only test this once */
goto exec; /* go execute the instruction */
break;
@ -6176,10 +6032,6 @@ temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS);
irq_auto, PSD1, PSD2);
/*AIR*/ irq_auto = 0; /* show done processing in blocked mode */
/*103020*/ skipinstr = 1; /* skip interrupt test */
#ifndef DO_DYNAMIC_DEBUG
/* stop debugging */
cpu_dev.dctrl &= ~DEBUG_INST;
#endif
}
}
} else {
@ -6662,14 +6514,14 @@ mcheck:
case 0x02: /* Start I/O SIO */
// chsa = temp2 & 0x7fff; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO SIO b4 call PSD1 %08x rchsa %04x lchsa %04x BLK %1x\n",
"SIO b4 call PSD1 %08x rchsa %04x lchsa %04x BLK %1x\n",
PSD1, rchsa, lchsa, CPUSTATUS&0x80?1:0);
// PSD1, lchan, lchsa, CPUSTATUS&0x80?1:0);
if ((TRAPME = startxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO SIO ret PSD1 %08x chan %04x chsa %04x status %08x BLK %1x\n",
"SIO ret PSD1 %08x chan %04x chsa %04x status %08x BLK %1x\n",
PSD1, rchsa, lchsa, rstatus, CPUSTATUS&0x80?1:0);
break;
@ -6677,28 +6529,26 @@ mcheck:
// lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = testxio(lchsa, &rstatus))) {
sim_debug(DEBUG_TRAP, &cpu_dev,
"XIO TIO ret PSD1 %x rchsa %x lchsa %x status %x BLK %1x\n",
"TIO ret PSD1 %x rchsa %x lchsa %x status %x BLK %1x\n",
PSD1, rchsa, lchsa, rstatus, CPUSTATUS&0x80?1:0);
goto newpsd; /* error returned, trap cpu */
}
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO TIO ret PSD1 %08x lchsa %04x stat %08x spad %08x INTS[%02x] %08x BLK %1x\n",
"TIO ret PSD1 %08x lchsa %04x stat %08x spad %08x INTS[%02x] %08x BLK %1x\n",
PSD1, lchsa, rstatus, t, ix, INTS[ix], CPUSTATUS&0x80?1:0);
break;
case 0x04: /* Stop I/O STPIO */
// lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = stopxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev, "XIO STPIO ret rchsa %04x lchsa %04x status %08x\n",
sim_debug(DEBUG_XIO, &cpu_dev, "STPIO ret rchsa %04x lchsa %04x status %08x\n",
rchsa, lchsa, rstatus);
break;
/* TODO Finish XIO */
case 0x05: /* Reset channel RSCHNL */
// lchsa = (lchan << 8) | suba; /* logical address */
/* TODO Maybe we need to disable int too???? */
if ((TRAPME = rschnlxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
@ -6707,43 +6557,39 @@ mcheck:
INTS[ix] &= ~INTS_ACT; /* deactivate specified int level */
SPAD[ix+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev, "XIO RSCHNL ret rchsa %04x lchsa %04x status %08x\n",
sim_debug(DEBUG_XIO, &cpu_dev, "RSCHNL rschnlxio ret rchsa %04x lchsa %04x status %08x\n",
rchsa, lchsa, rstatus);
break;
case 0x06: /* Halt I/O HIO */
// lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = haltxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev,
"HIO HALTXIO ret rchsa %04x lchsa %04x status %08x\n",
"HIO haltxio ret rchsa %04x lchsa %04x status %08x\n",
rchsa, lchsa, rstatus);
break;
case 0x07: /* Grab controller GRIO n/u */
lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = grabxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev, "XIO GRIO ret rchsa %04x lchsa %04x status %08x\n",
sim_debug(DEBUG_XIO, &cpu_dev, "GRIO ret rchsa %04x lchsa %04x status %08x\n",
rchsa, lchsa, rstatus);
break;
case 0x08: /* Reset controller RSCTL */
// lchsa = (lchan << 8) | suba; /* logical address */
if ((TRAPME = rsctlxio(lchsa, &rstatus)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev, "XIO RSCTL ret rchsa %04x lchsa %04x status %08x\n",
sim_debug(DEBUG_XIO, &cpu_dev, "RSCTL ret rchsa %04x lchsa %04x status %08x\n",
rchsa, lchsa, rstatus);
break;
case 0x0C: /* Enable channel interrupt ECI */
/* disable int only */
// lchsa = (lchan << 8) | suba; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO ECI chsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
"ECI chsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
rchsa, lchsa, t, ix, INTS[ix]);
if ((TRAPME = checkxio(lchsa, &rstatus)))
@ -6766,9 +6612,8 @@ mcheck:
case 0x0D: /* Disable channel interrupt DCI */
/* disable int, leave req */
// lchsa = (lchan << 8) | suba; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO DCI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
"DCI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
rchsa, lchsa, t, ix, INTS[ix]);
if ((TRAPME = checkxio(lchsa, &rstatus)))
@ -6783,16 +6628,13 @@ mcheck:
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] &= ~INTS_ENAB; /* disable specified int level */
SPAD[ix+0x80] &= ~SINT_ENAB; /* disable in SPAD too */
/* MFP doc says req is dropped, 67 cpu says no */
// TRYING 032920 */ INTS[ix] &= ~INTS_REQ; /* clears any requests also */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
break;
case 0x0E: /* Activate channel interrupt ACI */
/* Set int active, clear request */
// lchsa = (lchan << 8) | suba; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO ACI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
"ACI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
rchsa, lchsa, t, ix, INTS[ix]);
if ((TRAPME = checkxio(lchsa, &rstatus)))
@ -6804,17 +6646,14 @@ mcheck:
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] |= INTS_ACT; /* activate specified int level */
SPAD[ix+0x80] |= SINT_ACT; /* enable in SPAD too */
/*917*/ /* tech manual says to remove any request */
//BAD/*1030*/ INTS[ix] &= ~INTS_REQ; /* clears any requests also */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
break;
case 0x0F: /* Deactivate channel interrupt DACI */
/* Clear active and leave any request */
/* Note, instruction following DACI is not interruptable */
// lchsa = (lchan << 8) | suba; /* logical address */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO DACI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
"DACI rchsa %04x lchsa %04x spad %08x INTS[%02x] %08x\n",
rchsa, lchsa, t, ix, INTS[ix]);
if ((TRAPME = checkxio(rchsa, &rstatus)))
@ -6830,12 +6669,8 @@ mcheck:
skipinstr = 1; /* skip interrupt test */
PSD1 = ((PSD1 & 0x87fffffe) | (rstatus & 0x78000000)); /* insert status */
sim_debug(DEBUG_XIO, &cpu_dev,
"XIO DACI ret lchsa %04x status %08x spad %08x INTS[%02x] %08x BLK %1x\n",
"DACI ret lchsa %04x status %08x spad %08x INTS[%02x] %08x BLK %1x\n",
lchsa, rstatus, t, ix, INTS[ix], CPUSTATUS&0x80?1:0);
#ifndef DO_DYNAMIC_DEBUG
/* stop debugging */
cpu_dev.dctrl &= ~DEBUG_INST;
#endif
break;
} /* end of XIO switch */
break;
@ -7323,11 +7158,6 @@ t_stat cpu_reset(DEVICE *dptr)
GPR[i] = BOOTR[i]; /* set boot register values */
BR[i] = 0; /* clear the registers */
}
#ifdef NOTNOW
/* TEMP for UTX boot messages */
if (GPR[7] != 0)
GPR[7] = 0x40; /* set RE_VERBOSE bit for UTX tape boot */
#endif
/* set console switch settings */
M[0x780>>2] = CSW; /* set console switch settings */

239
SEL32/sel32_defs.h
View File

@ -1,7 +1,7 @@
/* sel32_defs.h: SEL-32 Concept/32 simulator definitions
Copyright (c) 2018-2020, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -196,8 +196,8 @@ extern DEVICE ec_dev;
/* Memory */
#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size in 32bit words */
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size in 32bit words */
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
/* channel program data for a chan/sub-address */
@ -219,12 +219,12 @@ typedef struct chp {
} CHANP;
/* Device information block */
#define FIFO_SIZE 256 /* fifo to hold 128 double words of status */
#define FIFO_SIZE 256 /* fifo to hold 128 double words of status */
extern int32 FIFO_Put(uint16 chsa, uint32 entry);
extern int32 FIFO_Get(uint16 chsa, uint32 *old);
extern int32 FIFO_Num(uint16 chsa);
#define IOCLQ_SIZE 32 /* fifo to hold 32 iocl cmds */
#define IOCLQ_SIZE 32 /* fifo to hold 32 iocl cmds */
typedef struct ioclq {
uint32 ioclq_fifo[IOCLQ_SIZE];
@ -242,11 +242,11 @@ typedef struct dib {
/* Start a channel command SIO */
uint16 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
/* Halt I/O HIO */
uint16 (*halt_io)(UNIT *uptr); /* Halt I/O */
uint16 (*halt_io)(UNIT *uptr); /* Halt I/O */
/* Test I/O STOPIO */
uint16 (*stop_io)(UNIT *uptr); /* Stop I/O */
uint16 (*stop_io)(UNIT *uptr); /* Stop I/O */
/* Test I/O TESTIO */
uint16 (*test_io)(UNIT *uptr); /* Test I/O */
uint16 (*test_io)(UNIT *uptr); /* Test I/O */
/* Reset Controller RSCTL */
uint16 (*rsctl_io)(UNIT *uptr); /* Reset Controller */
/* Reset Controller RSCHNL */
@ -255,22 +255,22 @@ typedef struct dib {
uint16 (*iocl_io)(CHANP *chp, int32 tic_ok); /* IOCL processing */
/* Controller init */
void (*dev_ini)(UNIT *, t_bool); /* init function */
UNIT *units; /* Pointer to units structure */
CHANP *chan_prg; /* Pointer to channel program */
IOCLQ *ioclq_ptr; /* pointer to array of IOCLQ entries */
uint8 numunits; /* number of units */
uint8 mask; /* device mask */
uint16 chan_addr; /* parent channel address */
uint32 chan_fifo_in; /* fifo input index */
uint32 chan_fifo_out; /* fifo output index */
UNIT *units; /* Pointer to units structure */
CHANP *chan_prg; /* Pointer to channel program */
IOCLQ *ioclq_ptr; /* pointer to array of IOCLQ entries */
uint8 numunits; /* number of units */
uint8 mask; /* device mask */
uint16 chan_addr; /* parent channel address */
uint32 chan_fifo_in; /* fifo input index */
uint32 chan_fifo_out; /* fifo output index */
uint32 chan_fifo[FIFO_SIZE]; /* interrupt status fifo for each channel */
} DIB;
extern DIB *dib_unit[MAX_DEV]; /* Pointer to Device info block */
extern DIB *dib_chan[MAX_CHAN]; /* Pointer to channel mux dib */
extern DIB *dib_unit[MAX_DEV]; /* Pointer to Device info block */
extern DIB *dib_chan[MAX_CHAN]; /* Pointer to channel mux dib */
#define DEV_CHAN (1 << DEV_V_UF) /* Device is channel mux if set */
#define DEV_V_UF2 (DEV_V_UF+1) /* current usage */
#define DEV_CHAN (1 << DEV_V_UF) /* Device is channel mux if set */
#define DEV_V_UF2 (DEV_V_UF+1) /* current usage */
#ifdef NOT_USED_NOW
//#define DEV_V_ADDR DEV_V_UF /* Pointer to device address (16) */
@ -339,16 +339,16 @@ extern DEBTAB dev_debug[];
#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_MODEL) & 0x7) /* cpu model 0-7 */
#define MODEL_55 0 /* 512K Mode Only */
#define MODEL_75 1 /* Extended */
#define MODEL_27 2 /* */
#define MODEL_67 3 /* */
#define MODEL_87 4 /* */
#define MODEL_97 5 /* */
#define MODEL_V6 6 /* V6 CPU */
#define MODEL_V9 7 /* V9 CPU */
#define MODEL_55 0 /* 512K Mode Only */
#define MODEL_75 1 /* Extended */
#define MODEL_27 2 /* */
#define MODEL_67 3 /* */
#define MODEL_87 4 /* */
#define MODEL_97 5 /* */
#define MODEL_V6 6 /* V6 CPU */
#define MODEL_V9 7 /* V9 CPU */
#define TMR_RTC 1 /* RTC will not work if set to 0!! */
#define TMR_RTC 1 /* RTC will not work if set to 0!! */
//#define TMR_RTC 0
#define HIST_MIN 64
@ -356,95 +356,95 @@ extern DEBTAB dev_debug[];
#define HIST_PC 0x80000000
/* CC defs Held in CC */
#define CC1BIT 0x40000000 /* CC1 in PSD1 */
#define CC2BIT 0x20000000 /* CC2 in PSD1 */
#define CC3BIT 0x10000000 /* CC3 in PSD1 */
#define CC4BIT 0x08000000 /* CC4 in PSD1 */
#define CC1BIT 0x40000000 /* CC1 in PSD1 */
#define CC2BIT 0x20000000 /* CC2 in PSD1 */
#define CC3BIT 0x10000000 /* CC3 in PSD1 */
#define CC4BIT 0x08000000 /* CC4 in PSD1 */
#define MAPMODE 0x40 /* Map mode, PSD 2 bit 0 */
#define RETMODE 0x20 /* Retain current maps, PSD 2 bit 15 */
#define BLKMODE 0x10 /* Set blocked mode, PSD 2 bit 17 */
#define RETBLKM 0x08 /* Set retain blocked mode, PSD 2 bit 16 */
#define MAPMODE 0x40 /* Map mode, PSD 2 bit 0 */
#define RETMODE 0x20 /* Retain current maps, PSD 2 bit 15 */
#define BLKMODE 0x10 /* Set blocked mode, PSD 2 bit 17 */
#define RETBLKM 0x08 /* Set retain blocked mode, PSD 2 bit 16 */
/* PSD mode bits in PSD words 1&2 variable */
#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
#define SETBBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
#define RETBBIT 0x00008000 /* Retain current blocking state, PSD 2 bit 16 */
#define RETMBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
#define SETBBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
#define RETBBIT 0x00008000 /* Retain current blocking state, PSD 2 bit 16 */
#define RETMBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
/* Trap Table Address in memory is pointed to by SPAD 0xF0 */
#define POWERFAIL_TRAP 0x80 /* Power fail trap */
#define POWERON_TRAP 0x84 /* Power-On trap */
#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
#define CACHEERR_TRAP 0xC0 /* Cache Error Trap (V9 Only) */
#define DEMANDPG_TRAP 0xC4 /* Demand Page Fault Trap (V6&V9 Only) */
#define POWERFAIL_TRAP 0x80 /* Power fail trap */
#define POWERON_TRAP 0x84 /* Power-On trap */
#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
#define CACHEERR_TRAP 0xC0 /* Cache Error Trap (V9 Only) */
#define DEMANDPG_TRAP 0xC4 /* Demand Page Fault Trap (V6&V9 Only) */
/* Errors returned from various functions */
#define ALLOK 0x0000 /* no error, all is OK */
#define MAPFLT MAPFAULT_TRAP /* map fault error */
#define NPMEM NONPRESMEM_TRAP /* non present memory */
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
#define DMDPG DEMANDPG_TRAP /* Demand Page Fault Trap (V6&V9 Only) */
#define ALLOK 0x0000 /* no error, all is OK */
#define MAPFLT MAPFAULT_TRAP /* map fault error */
#define NPMEM NONPRESMEM_TRAP /* non present memory */
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
#define DMDPG DEMANDPG_TRAP /* Demand Page Fault Trap (V6&V9 Only) */
/* general instruction decode equates */
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 20 & 31 */
#define BIT0 0x80000000 /* general use for bit 0 testing */
#define BIT1 0x40000000 /* general use for bit 1 testing */
#define BIT2 0x20000000 /* general use for bit 2 testing */
#define BIT3 0x10000000 /* general use for bit 3 testing */
#define BIT4 0x08000000 /* general use for bit 4 testing */
#define BIT5 0x04000000 /* general use for bit 5 testing */
#define BIT6 0x02000000 /* general use for bit 6 testing */
#define BIT7 0x01000000 /* general use for bit 7 testing */
#define BIT8 0x00800000 /* general use for bit 8 testing */
#define BIT9 0x00400000 /* general use for bit 9 testing */
#define BIT10 0x00200000 /* general use for bit 10 testing */
#define BIT11 0x00100000 /* general use for bit 11 testing */
#define BIT12 0x00080000 /* general use for bit 12 testing */
#define BIT13 0x00040000 /* general use for bit 13 testing */
#define BIT14 0x00020000 /* general use for bit 14 testing */
#define BIT15 0x00010000 /* general use for bit 15 testing */
#define BIT16 0x00008000 /* general use for bit 16 testing */
#define BIT17 0x00004000 /* general use for bit 17 testing */
#define BIT18 0x00002000 /* general use for bit 18 testing */
#define BIT19 0x00001000 /* general use for bit 19 testing */
#define BIT20 0x00000800 /* general use for bit 20 testing */
#define BIT21 0x00000400 /* general use for bit 21 testing */
#define BIT22 0x00000200 /* general use for bit 22 testing */
#define BIT23 0x00000100 /* general use for bit 23 testing */
#define BIT24 0x00000080 /* general use for bit 24 testing */
#define BIT25 0x00000040 /* general use for bit 25 testing */
#define BIT26 0x00000020 /* general use for bit 26 testing */
#define BIT27 0x00000010 /* general use for bit 27 testing */
#define BIT28 0x00000008 /* general use for bit 28 testing */
#define BIT29 0x00000004 /* general use for bit 29 testing */
#define BIT30 0x00000002 /* general use for bit 30 testing */
#define BIT31 0x00000001 /* general use for bit 31 testing */
#define MASK16 0x0000FFFF /* 16 bit address mask */
#define MASK19 0x0007FFFF /* 19 bit address mask */
#define MASK20 0x000FFFFF /* 20 bit address mask */
#define MASK24 0x00FFFFFF /* 24 bit address mask */
#define MASK32 0xFFFFFFFF /* 32 bit address mask */
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 20 & 31 */
#define BIT0 0x80000000 /* general use for bit 0 testing */
#define BIT1 0x40000000 /* general use for bit 1 testing */
#define BIT2 0x20000000 /* general use for bit 2 testing */
#define BIT3 0x10000000 /* general use for bit 3 testing */
#define BIT4 0x08000000 /* general use for bit 4 testing */
#define BIT5 0x04000000 /* general use for bit 5 testing */
#define BIT6 0x02000000 /* general use for bit 6 testing */
#define BIT7 0x01000000 /* general use for bit 7 testing */
#define BIT8 0x00800000 /* general use for bit 8 testing */
#define BIT9 0x00400000 /* general use for bit 9 testing */
#define BIT10 0x00200000 /* general use for bit 10 testing */
#define BIT11 0x00100000 /* general use for bit 11 testing */
#define BIT12 0x00080000 /* general use for bit 12 testing */
#define BIT13 0x00040000 /* general use for bit 13 testing */
#define BIT14 0x00020000 /* general use for bit 14 testing */
#define BIT15 0x00010000 /* general use for bit 15 testing */
#define BIT16 0x00008000 /* general use for bit 16 testing */
#define BIT17 0x00004000 /* general use for bit 17 testing */
#define BIT18 0x00002000 /* general use for bit 18 testing */
#define BIT19 0x00001000 /* general use for bit 19 testing */
#define BIT20 0x00000800 /* general use for bit 20 testing */
#define BIT21 0x00000400 /* general use for bit 21 testing */
#define BIT22 0x00000200 /* general use for bit 22 testing */
#define BIT23 0x00000100 /* general use for bit 23 testing */
#define BIT24 0x00000080 /* general use for bit 24 testing */
#define BIT25 0x00000040 /* general use for bit 25 testing */
#define BIT26 0x00000020 /* general use for bit 26 testing */
#define BIT27 0x00000010 /* general use for bit 27 testing */
#define BIT28 0x00000008 /* general use for bit 28 testing */
#define BIT29 0x00000004 /* general use for bit 29 testing */
#define BIT30 0x00000002 /* general use for bit 30 testing */
#define BIT31 0x00000001 /* general use for bit 31 testing */
#define MASK16 0x0000FFFF /* 16 bit address mask */
#define MASK19 0x0007FFFF /* 19 bit address mask */
#define MASK20 0x000FFFFF /* 20 bit address mask */
#define MASK24 0x00FFFFFF /* 24 bit address mask */
#define MASK32 0xFFFFFFFF /* 32 bit address mask */
/* SPAD int entry equates, entries accessed by interrupt level number */
#define SINT_RAML 0x80000000 /* ram loaded (n/u) */
@ -472,11 +472,10 @@ extern DEBTAB dev_debug[];
/* The RMW and WMW macros are used to read/write memory words */
/* RMW(addr) or WMW(addr, data) where addr is a byte alligned word address */
//#define RMB(a) ((M[(a)>>2]>>(8*(7-(a&3))))&0xff) /* read memory addressed byte */
#define RMB(a) ((M[(a)>>2]>>(8*(3-(a&3))))&0xff) /* read memory addressed byte */
#define RMB(a) ((M[(a)>>2]>>(8*(3-(a&3))))&0xff) /* read memory addressed byte */
#define RMH(a) ((a)&2?(M[(a)>>2]&RMASK):(M[(a)>>2]>>16)&RMASK) /* read memory addressed halfword */
#define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */
#define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */
#define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */
#define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */
/* write halfword to memory address */
#define WMH(a,d) ((a)&2?(M[(a)>>2]=(M[(a)>>2]&LMASK)|((d)&RMASK)):(M[(a)>>2]=(M[(a)>>2]&RMASK)|((d)<<16)))
/* write byte to memory */
@ -503,18 +502,18 @@ extern t_stat chan_boot(uint16 addr, DEVICE *dptr);
extern int test_write_byte_end(uint16 chsa);
extern DEVICE *get_dev(UNIT *uptr);
extern t_stat set_inch(UNIT *uptr, uint32 inch_addr); /* set channel inch address */
extern CHANP *find_chanp_ptr(uint16 chsa); /* find chanp pointer */
extern CHANP *find_chanp_ptr(uint16 chsa); /* find chanp pointer */
extern uint32 M[]; /* our memory */
extern uint32 SPAD[]; /* cpu SPAD memory */
extern uint32 M[]; /* our memory */
extern uint32 SPAD[]; /* cpu SPAD memory */
extern uint32 attention_trap;
extern uint32 RDYQ[]; /* ready queue */
extern uint32 RDYQIN; /* input index */
extern uint32 RDYQOUT; /* output index */
extern uint32 RDYQ[]; /* ready queue */
extern uint32 RDYQIN; /* input index */
extern uint32 RDYQOUT; /* output index */
#define RDYQ_SIZE 128
extern int32 RDYQ_Put(uint32 entry);
extern int32 RDYQ_Get(uint32 *old);
extern int32 RDYQ_Num(void);
#define get_chan(chsa) ((chsa>>8)&0x7f) /* get channel number from ch/sa */
#define get_chan(chsa) ((chsa>>8)&0x7f) /* get channel number from ch/sa */

446
SEL32/sel32_disk.c
View File

@ -1,6 +1,6 @@
/* sel32_disk.c: SEL-32 2311/2314 Disk Processor II
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -129,7 +129,7 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
12 short ldef2; defect #2 sec and byte position
14 short ldef3; defect #3 sec and byte position
* for track 0 write UMAP which is DMAP - 2 * SPT
* write sector number of cyl-4, hds-4, sec 0 value in 16-19
* write sector number of cyl-4, hds-3, sec 0 value in 16-19
* otherwise write current values
16 short ladef1; defect #1 abs position
18 short ladef2; defect #2 abs position
@ -176,8 +176,8 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option
10 short ldef1; defect #1 sec and byte position
12 short ldef2; defect #2 sec and byte position
14 short ldef3; defect #3 sec and byte position
* for track 0 write UMAP which is DMAP - 2 * SPT
* write sector number of cyl-4, hds-4, sec 0 value in 16-19
* for sec 1 UTX prep will write UMAP, which is DMAP - 1 * SPT
* write sector number of cyl-4, hds-3, sec 0 value in 16-19
* otherwise write zeros
16 short lspar3; n/u = 0
18 short lspar4; n/u = 0
@ -409,6 +409,22 @@ extern uint32 PSD[]; /* PSD */
/* channel program information */
CHANP dda_chp[NUM_UNITS_DISK] = {0};
#define TRK_CACHE 10
/* track label queue */
struct _trk_data
{
int32 age;
uint32 track;
uint8 label[30];
};
struct _trk_label
{
struct _trk_data tkl[TRK_CACHE];
};
static struct _trk_label tkl_label[NUM_UNITS_DISK] = {0};
MTAB disk_mod[] = {
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "TYPE", "TYPE",
&disk_set_type, &disk_get_type, NULL, "Type of disk"},
@ -563,11 +579,12 @@ uint32 disksec2star(uint32 daddr, int type)
/* read alternate track label and return new STAR */
uint32 get_dmatrk(UNIT *uptr, uint32 star, uint8 buf[])
{
uint32 nstar, tstart;
uint32 nstar, tstart, offset;
uint32 sec=0, trk=0, cyl=0;
int type = GET_TYPE(uptr->flags);
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
int len, i;
int unit = (uptr - dptr->units); /* get the UNIT number */
int len, i, cn, found = -1;
/* zero the Track Label Buffer */
for (i = 0; i < 30; i++)
@ -588,23 +605,39 @@ uint32 get_dmatrk(UNIT *uptr, uint32 star, uint8 buf[])
cyl, cyl, trk, tstart);
/* calc offset in file to track label */
tstart = CAPB(type) + (tstart * 30);
offset = CAPB(type) + (tstart * 30);
/* file offset in bytes */
sim_debug(DEBUG_EXP, dptr, "get_dmatrk RTL SEEK on seek to %06x\n", tstart);
/* seek to the location where we will r/w track label */
if ((sim_fseek(uptr->fileref, tstart, SEEK_SET)) != 0) { /* do seek */
sim_debug(DEBUG_EXP, dptr, "get_dmatrk RTL, Error on seek to %04x\n", tstart);
return 0;
/* see if track label is in cache */
for (cn=0; cn<TRK_CACHE; cn++) {
if (offset == tkl_label[unit].tkl[cn].track) {
/* we found it, copy data to buf */
for (i=0; i<30; i++)
buf[i] = tkl_label[unit].tkl[cn].label[i];
found = cn;
tkl_label[unit].tkl[cn].age++;
sim_debug(DEBUG_EXP, dptr, "get_dpatrk found in Cache to %06x\n", offset);
break;
}
}
/* read in a track label from disk */
if ((len=sim_fread(buf, 1, 30, uptr->fileref)) != 30) {
sim_debug(DEBUG_CMD, dptr,
"get_dmatrk Error %08x on read %04x of diskfile cyl %04x hds %02x sec 00\n",
len, 30, cyl, trk);
return 0;
/* see if found in cache */
if (found == -1) {
/* file offset in bytes */
sim_debug(DEBUG_EXP, dptr, "get_dpatrk RTL SEEK on seek to %06x\n", offset);
/* seek to the location where we will r/w track label */
if ((sim_fseek(uptr->fileref, offset, SEEK_SET)) != 0) { /* do seek */
sim_debug(DEBUG_EXP, dptr, "get_dpatrk RTL, Error on seek to %04x\n", offset);
return 0;
}
/* read in a track label from disk */
if ((len=sim_fread(buf, 1, 30, uptr->fileref)) != 30) {
sim_debug(DEBUG_CMD, dptr,
"get_dpatrk Error %08x on read %04x of diskfile cyl %04x hds %02x sec 00\n",
len, 30, cyl, trk);
return 0;
}
}
/* now write track label data to log */
@ -622,11 +655,32 @@ uint32 get_dmatrk(UNIT *uptr, uint32 star, uint8 buf[])
/* get the alternate track address */
cyl = (buf[22] << 8) | buf[23]; /* get the cylinder */
trk = buf[24]; /* get the track */
//bad sec = 0; /* sec is zero */
//bad sec = 0; /* sec is zero */
nstar = CHS2STAR(cyl, trk, sec);
sim_debug(DEBUG_DETAIL, dptr,
"Track %08x is defective, new track %08x\n", tstart, nstar);
}
/* see if we had it in our cache */
if (found == -1) {
/* not in our cache, save the new track label */
int32 na = 0;
for (cn=0; cn<TRK_CACHE; cn++) {
/* see if in use yet */
if (tkl_label[unit].tkl[cn].age == 0) {
na = cn; /* use this one */
break;
}
if (tkl_label[unit].tkl[cn].age > na)
continue; /* older */
/* this is less used, so replace it */
na = cn;
}
/* use na entry */
for (i=0; i<30; i++)
tkl_label[unit].tkl[na].label[i] = buf[i];
tkl_label[unit].tkl[na].age = 1;
tkl_label[unit].tkl[cn].track = offset;
}
return nstar; /* return track address */
}
@ -684,14 +738,6 @@ loop:
return 1; /* return error */
}
#ifdef WHATISTHIS
/* Check if we have status modifier set */
if (chp->chan_status & STATUS_MOD) {
chp->chan_caw += 8; /* move to next IOCD */
chp->chan_status &= ~STATUS_MOD; /* turn off status modifier flag */
}
#endif
/* Read in first CCW */
if (readfull(chp, chp->chan_caw, &word1) != 0) { /* read word1 from memory */
chp->chan_status |= STATUS_PCHK; /* memory read error, program check */
@ -933,14 +979,12 @@ uint16 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->SNS &= ~SNS_CMDREJ; /* not rejected yet */
uptr->CMD |= DSK_INCH2; /* use 0xF0 for inch, just need int */
//J sim_activate(uptr, 20); /* start things off */
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 50); /* start things off */
// sim_activate(uptr, 40); /* start things off */
sim_activate(uptr, 30); /* start things off */
#else
// sim_activate(uptr, 250); /* start things off */
sim_activate(uptr, 500); /* start things off */
sim_activate(uptr, 250); /* start things off */
// sim_activate(uptr, 500); /* start things off */
#endif
return SCPE_OK; /* good to go */
break;
@ -978,11 +1022,13 @@ uint16 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
sim_debug(DEBUG_CMD, dptr,
"disk_startcmd starting disk cmd %02x chsa %04x\n",
cmd, chsa);
//J sim_activate(uptr, 20); /* start things off */
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 50); /* start things off */
// sim_activate(uptr, 40); /* start things off */
sim_activate(uptr, 30); /* start things off */
/* when value was 30, UTX would get a spontainous interrupt */
/* when starting cron */
/* changed to 25 from 30 121420 */
//121420sim_activate(uptr, 30); /* start things off */
sim_activate(uptr, 25); /* start things off */
#else
// sim_activate(uptr, 250); /* start things off */
sim_activate(uptr, 500); /* start things off */
@ -1022,8 +1068,10 @@ uint16 disk_haltio(UNIT *uptr) {
uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */
sim_cancel(uptr); /* clear the input timer */
sim_debug(DEBUG_CMD, dptr,
"disk_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */
"disk_haltio HIO I/O stop chsa %04x cmd = %02x CHS %08x STAR %08x\n",
chsa, cmd, uptr->CHS, uptr->STAR);
//1204 chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* force end */
return SCPE_IOERR;
}
uptr->CMD &= LMASK; /* make non-busy */
@ -1424,8 +1472,6 @@ iha_error:
unit, ch);
chan_write_byte(chsa, &ch);
// ch = 0x30; /* drive on cylinder and ready for now */
// uptr->SNS2 &= ~uptr->SNS2; /* clean out old status */
uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */
ch = uptr->SNS2 & 0xff; /* drive on cylinder and ready for now */
sim_debug(DEBUG_DETAIL, dptr, "disk_srv dsr unit=%02x 2 %02x\n",
@ -1433,7 +1479,6 @@ iha_error:
chan_write_byte(chsa, &ch);
}
uptr->SNS &= 0xff000000; /* reset status */
//28 uptr->SNS2 = (SNS_UNR|SNS_ONC); /* reset status to on cyl & ready */
uptr->SNS2 = 0; /* reset status */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
@ -1461,15 +1506,13 @@ iha_error:
sim_debug(DEBUG_CMD, dptr, "disk_srv seek over on cylinder unit=%02x %04x %04x\n",
unit, uptr->STAR >> 16, uptr->CHS >> 16);
uptr->CHS = uptr->STAR; /* we are there */
//J sim_activate(uptr, 10);
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 15);
// sim_activate(uptr, 25); /* start things off */
// sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 15); /* start things off */
#else
// sim_activate(uptr, 150); /* start things off */
sim_activate(uptr, 300); /* start things off */
sim_activate(uptr, 150); /* start things off */
// sim_activate(uptr, 300); /* start things off */
#endif
break;
}
@ -1491,7 +1534,6 @@ iha_error:
sim_debug(DEBUG_CMD, dptr,
"disk_srv SEEK bad count unit %02x count %04x\n", unit, len);
uptr->CMD &= LMASK; /* remove old status bits & cmd */
//?? uptr->SNS2 |= SNS_SKER;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK|STATUS_LENGTH);
break;
}
@ -1615,7 +1657,6 @@ iha_error:
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 20); /* start us off */
// sim_activate(uptr, 25); /* start things off */
// sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 15); /* start things off */
#else
// sim_activate(uptr, 200+diff); /* start us off */
@ -1977,9 +2018,7 @@ iha_error:
sim_debug(DEBUG_CMD, dptr,
"DISK sector read complete, %x bytes to go from diskfile %04x/%02x/%02x\n",
chp->ccw_count, STAR2CYL(uptr->CHS), ((uptr->CHS) >> 8)&0xff, (uptr->CHS&0xff));
//J sim_activate(uptr, 10); /* wait to read next sector */
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 15); /* wait to read next sector */
// sim_activate(uptr, 25); /* start things off */
// sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 15); /* start things off */
@ -2190,9 +2229,7 @@ iha_error:
break;
}
//J sim_activate(uptr, 10); /* keep writing */
#ifdef FAST_FOR_UTX
// sim_activate(uptr, 15); /* keep writing */
// sim_activate(uptr, 25); /* start things off */
// sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 15); /* start things off */
@ -2407,7 +2444,7 @@ iha_error:
/* command done */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr, "disk_srv cmd RSL done chsa %04x count %04x completed\n",
sim_debug(DEBUG_CMD, dptr, "disk_srv cmd WSL done chsa %04x count %04x completed\n",
chsa, chp->ccw_count);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
break;
@ -2484,12 +2521,6 @@ iha_error:
}
sim_debug(DEBUG_DETAIL, dptr, "\n");
#ifdef NONO
/* leave STAR "unnormalized" for diags */
if (uptr->CHS != 0) /* only incr address if not trk 0 */
uptr->CHS += 0x10; /* bump to next track */
#endif
/* command done */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr, "disk_srv cmd RTL done chsa %04x count %04x completed\n",
@ -2504,16 +2535,6 @@ iha_error:
sim_debug(DEBUG_EXP, dptr, "disk_srv WTL start cnt %04x CHS %08x\n",
chp->ccw_count, uptr->CHS);
#ifdef NONO
/* see if user trying to write other than 30 bytes */
if (chp->ccw_count != 30 && chp->ccw_count != 34) { /* see if wrong byte count */
// uptr->SNS |= SNS_DEFTRK; /* disk formating error */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK);
break;
}
#endif
/* get file offset in sectors */
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
/* convert sector number back to chs value to sync disk for diags */
@ -2535,12 +2556,6 @@ iha_error:
/* file offset in bytes */
sim_debug(DEBUG_EXP, dptr, "disk_srv WTL SEEK on seek to %06x\n", tstart);
/* get alternate track info */
tempt = get_dmatrk(uptr, uptr->CHS, lbuf);
uptr->SNS &= ~SNS_DEFTRK; /* remove any defective track flag */
/* file offset in bytes to std or alt track */
//// tstart = STAR2SEC(tempt, SPT(type), SPC(type)) * SSB(type);
/* seek to the location where we will write track label */
if ((sim_fseek(uptr->fileref, tstart, SEEK_SET)) != 0) { /* do seek */
sim_debug(DEBUG_EXP, dptr, "disk_srv WTL, Error on seek to %04x\n", tstart);
@ -2587,6 +2602,18 @@ iha_error:
break;
}
/* clear cache entry for this track */
/* see if track label is in cache */
for (i=0; i<TRK_CACHE; i++) {
if (tstart == tkl_label[unit].tkl[i].track) {
/* we found it, clear the entry */
tkl_label[unit].tkl[i].age = 0;
tkl_label[unit].tkl[i].track = 0;
sim_debug(DEBUG_EXP, dptr, "WTL clearing Cache to %06x\n", tstart);
break;
}
}
uptr->CHS = mema; /* restore address */
uptr->CMD &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr,
@ -2628,11 +2655,30 @@ void disk_ini(UNIT *uptr, t_bool f)
t_stat disk_reset(DEVICE *dptr)
{
/* add reset code here */
int cn, unit;
for(unit=0; unit < NUM_UNITS_DISK; unit++) {
for (cn=0; cn<TRK_CACHE; cn++) {
tkl_label[unit].tkl[cn].track = 0;
tkl_label[unit].tkl[cn].age = 0;
}
}
/* add more reset code here */
return SCPE_OK;
}
/* add track and sector labels to disk */
/* The dmap pointer is placed by the vendor or diag into the */
/* track zero label in word 3 of the 30 byte label. */
/* The disk address in track 0 label is the last sector of the disk. */
/* The vendor reserves the last cylinder, SEL diags reserve the next */
/* two, so the last track of the user area is CYL-4/HDS-1/0 */
/* The vender places the flaw information in the track and is the VDT */
/* The previous track has the media defect table and is the MDT. */
/* It is at MDT = VDT-SPT or CYL-4/HDS-2/0 */
/* The media defect table is pointed to by track 0 label in word 3 */
/* The next lower track contains the UTX media map (UMAP) and is pointed */
/* to by word 3 of sector label 1 and is placed there by the UTX prep program */
/* Add track and sector labels to disk */
int disk_label(UNIT *uptr) {
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
@ -2645,13 +2691,16 @@ int disk_label(UNIT *uptr) {
uint32 CHS; /* cyl, hds, sec format */
uint8 label[34]; /* track/sector label */
int32 i, j;
/* get sector address of vendor defect table VDT */
/* put data = 0xf0000000 0xf4000000 */
int32 vaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-1) * SPT(type);
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
/* 0x9a000000 + (cyl-1), 0xf4000000 */
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* get sector address of utx flaw map sec 1 pointer */
/* use this address for sec 1 label pointer */
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-4) * SPT(type);
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-3) * SPT(type);
/* write 30 byte track labels for all tracks on disk */
/* tot_tracks entries will be created starting at end of disk */
@ -2663,7 +2712,7 @@ int disk_label(UNIT *uptr) {
return 1;
}
/* write track labels */
for (i=0; i<tot_tracks; i++) {
for (i=0; i<(int)tot_tracks; i++) {
/* zero the Track Label Buffer */
for (j = 0; j < 30; j++)
@ -2712,14 +2761,19 @@ int disk_label(UNIT *uptr) {
label[15] = (daddr) & 0xff;
}
/* is this is removed, utx is unable to create newfs */
/* get preposterous size 0 error message */
#ifndef XXXX_121720
/* maybe not needed, but left anyway */
/* uaddr has umap value for track zero label */
if (CHS == 0) { /* only write dmap address in trk 0 */
if (CHS == 0) { /* only write dmap address in trk 0 */
/* output last sector address of disk */
label[16] = (uaddr >> 24) & 0xff; /* lumapp DMAP pointer */
label[17] = (uaddr >> 16) & 0xff;
label[18] = (uaddr >> 8) & 0xff;
label[19] = (uaddr) & 0xff;
}
#endif
/* the tech doc shows the cyl/trk/sec data is in the first 4 bytes */
/* of the track label, BUT it is really in the configuration data */
@ -2740,7 +2794,7 @@ int disk_label(UNIT *uptr) {
/* write 30 byte sector labels for all sectors on disk */
/* tot_sector entries will be created starting at end of disk */
/* plus the track label area size. seek first sector after end */
/* plus the track label area size. Seek first sector after end */
/* of disk track label area */
if ((sim_fseek(uptr->fileref, CAPB(type)+TRK(type)*30, SEEK_SET)) != 0) {
sim_debug(DEBUG_CMD, dptr,
@ -2755,7 +2809,7 @@ int disk_label(UNIT *uptr) {
/* convert sector number to CHS value for label */
/* write sector labels */
for (i=0; i<tot_sectors; i++) {
for (i=0; i<(int)tot_sectors; i++) {
CHS = disksec2star(i, type); /* get current CHS value */
@ -2779,23 +2833,36 @@ int disk_label(UNIT *uptr) {
"disk_format WSL star %02x %02x %02x %02x\n",
label[0], label[1], label[2], label[3]);
label[12] = 0;
label[13] = 0;
label[14] = 0;
label[15] = 0;
/* write vaddr to sector label for dmap */
if (i == daddr) { /* get track address in sectors */
/* output last sector address of disk */
label[12] = (vaddr >> 24) & 0xff; /* Vaddr pointer */
label[13] = (vaddr >> 16) & 0xff;
label[14] = (vaddr >> 8) & 0xff;
label[15] = (vaddr) & 0xff;
sim_debug(DEBUG_DETAIL, dptr,
"hsdp_format WSL vaddr@daddr %08x -> %08x\n", vaddr, daddr);
}
/* if this is written, UTX will not be able to do a newfs */
/* gets preposterous size 0 error */
#ifdef TRYING_121720
/* uaddr has umap value for sector one label */
if (CHS == 1) { /* only write dmap address in trk 0 */
/* output last sector address of disk */
label[16] = (uaddr >> 24) & 0xff; /* lumapp UMAP pointer */
label[17] = (uaddr >> 16) & 0xff;
label[18] = (uaddr >> 8) & 0xff;
label[19] = (uaddr) & 0xff;
label[12] = (uaddr >> 24) & 0xff; /* lumapp UMAP pointer */
label[13] = (uaddr >> 16) & 0xff;
label[14] = (uaddr >> 8) & 0xff;
label[15] = (uaddr) & 0xff;
sim_debug(DEBUG_DETAIL, dptr,
"disk_format WSL uaddr star %02x %02x %02x %02x\n",
label[16], label[17], label[18], label[19]);
} else {
label[16] = 0;
label[17] = 0;
label[18] = 0;
label[19] = 0;
}
label[12], label[13], label[14], label[15]);
}
#endif
/* the tech doc shows the cyl/trk/sec data is in the first 4 bytes */
/* of the track label, BUT it is really in the configuration data */
@ -2841,38 +2908,20 @@ int disk_format(UNIT *uptr) {
/* last sector address of disk (cyl * hds * spt) - 1 */
uint32 laddr = CAP(type) - 1; /* last sector of disk */
/* last track address of disk (cyl * hds * spt) - spt */
uint32 ltaddr = CAP(type)-SPT(type); /* last track of disk */
/* get sector address of vendor defect table VDT */
/* put data = 0xf0000000 0xf4000000 */
int32 vaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-1) * SPT(type);
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
/* 0x9a000000 + (cyl-1), 0xf4000000 */
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* get sector address of utx flaw data (1 track long) */
/* set trace data to zero */
int32 faddr = (CYL(type)-4) * SPC(type) + (HDS(type)-3) * SPT(type);
/* get sector address of utx flaw map sec 1 pointer */
/* use this address for sec 1 label pointer */
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-4) * SPT(type);
int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-3) * SPT(type);
// int32 uaddr = (CYL(type)-4) * SPC(type) + (HDS(type)-4) * SPT(type);
/* last user block available */
int32 luaddr = (CYL(type)-4) * SPC(type);
/* make up a UMAP with the partiton data for 9346 disk */
uint32 umap[256] =
{
/* try to makeup a utx dmap */
0x4e554d50,(cap-1),luaddr-1,0,0,0,0,0xe10,
0,0x5320,0,0x4e60,0x46,luaddr,0,0xd360,
0x88,0x186b0,0x13a,0xd100,0x283,0,0,0,
0,0x22c2813e,0,0x06020000,0xf4,0,0x431b1c,0,
};
/* vendor flaw map in vaddr */
uint32 vmap[2] = {0xf0000004, 0xf4000000};
@ -2881,10 +2930,6 @@ int disk_format(UNIT *uptr) {
uint32 dmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | (cap-1), 0xf4000000};
/* utx flaw map */
uint32 fmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
0x9a000000 | ltaddr, 0xf4000000};
/* see if user wants to initialize the disk */
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
return 1;
@ -2892,8 +2937,7 @@ int disk_format(UNIT *uptr) {
/* VDT 249264 (819/18/0) 0x3cdb0 for 9346 - 823/19/16 vaddr */
/* MDT 249248 (819/17/0) 0x3cda0 for 9346 - 823/19/16 daddr */
/* DMAP 249232 (819/16/0) 0x3cd90 for 9346 - 823/19/16 faddr */
/* UMAP 249216 (819/15/0) 0x3cd80 for 9346 - 823/19/16 uaddr */
/* UMAP 249216 (819/16/0) 0x3cd80 for 9346 - 823/19/16 uaddr */
/* seek to sector 0 */
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
@ -2906,11 +2950,6 @@ int disk_format(UNIT *uptr) {
detach_unit(uptr);
return SCPE_ARG;
}
/* put dummy data in first word of disk */
buff[0] = 'Z';
buff[1] = 'E';
buff[2] = 'R';
buff[3] = 'O';
sim_debug(DEBUG_CMD, dptr,
"Creating disk file of trk size %04x bytes, capacity %d\n",
tsize*ssize, cap*ssize);
@ -2924,12 +2963,6 @@ int disk_format(UNIT *uptr) {
buff = 0;
return 1;
}
if (cyl == 0) {
buff[0] = 0;
buff[1] = 0;
buff[2] = 0;
buff[3] = 0;
}
if ((cyl % 100) == 0)
fputc('.', stderr);
}
@ -2947,14 +2980,6 @@ int disk_format(UNIT *uptr) {
dmap[i] = (((dmap[i] & 0xff) << 24) | ((dmap[i] & 0xff00) << 8) |
((dmap[i] & 0xff0000) >> 8) | ((dmap[i] >> 24) & 0xff));
}
for (i=0; i<4; i++) {
fmap[i] = (((fmap[i] & 0xff) << 24) | ((fmap[i] & 0xff00) << 8) |
((fmap[i] & 0xff0000) >> 8) | ((fmap[i] >> 24) & 0xff));
}
for (i=0; i<256; i++) {
umap[i] = (((umap[i] & 0xff) << 24) | ((umap[i] & 0xff00) << 8) |
((umap[i] & 0xff0000) >> 8) | ((umap[i] >> 24) & 0xff));
}
/* now seek to end of disk and write the dmap data */
/* setup dmap pointed to by track label 0 wd[3] = (cyl-4) * spt + (spt - 1) */
@ -3001,41 +3026,11 @@ int disk_format(UNIT *uptr) {
return 1;
}
/* write dummy DMAP to faddr */
if ((sim_fseek(uptr->fileref, faddr*ssize, SEEK_SET)) != 0) { /* seek DMAP */
sim_debug(DEBUG_CMD, dptr,
"Error on media flaw map seek to sect %06x offset %06x\n",
faddr, faddr*ssize);
return 1;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
"Error writing flaw map to sect %06x offset %06x\n",
faddr, faddr*ssize);
return 1;
}
/* write UTX umap to uaddr */
if ((sim_fseek(uptr->fileref, uaddr*ssize, SEEK_SET)) != 0) { /* seek UMAP */
sim_debug(DEBUG_CMD, dptr,
"Error on umap seek to sect %06x offset %06x\n",
uaddr, uaddr*ssize);
return 1;
}
if ((sim_fwrite((char *)&umap, sizeof(uint32), 256, uptr->fileref)) != 256) {
sim_debug(DEBUG_CMD, dptr,
"Error writing UMAP to sect %06x offset %06x\n",
uaddr, uaddr*ssize);
return 1;
}
printf("Disk %s has %x (%d) cyl, %x (%d) hds, %x (%d) sec\r\n",
disk_type[type].name, CYL(type), CYL(type), HDS(type), HDS(type),
SPT(type), SPT(type));
printf("writing to vmap sec %x (%d) bytes %x (%d)\r\n",
vaddr, vaddr, (vaddr)*ssize, (vaddr)*ssize);
printf("writing to flaw map sec %x (%d) bytes %x (%d)\r\n",
faddr, faddr, (faddr)*ssize, (faddr)*ssize);
printf("writing dmap to %x %d %x %d dmap to %x %d %x %d\r\n",
cap-1, cap-1, (cap-1)*ssize, (cap-1)*ssize,
daddr, daddr, daddr*ssize, daddr*ssize);
@ -3071,7 +3066,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
uint32 laddr = CAP(type) - 1; /* last sector of disk */
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
/* 0x9a000000 + (cyl-1), 0xf4000000 */
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* defect map */
uint32 dmap[4] = {0xf0000000 | (CAP(type)-1), 0x8a000000 | daddr,
@ -3094,7 +3089,7 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
uptr->capac = CAP(type); /* disk capacity in sectors */
ssize = SSB(type); /* get sector size in bytes */
for (i=0; i<ssize; i++)
for (i=0; i<(int)ssize; i++)
buff[i] = 0; /* zero the buffer */
sim_debug(DEBUG_CMD, dptr,
@ -3106,24 +3101,23 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
disk_type[type].name, disk_type[type].cyl, disk_type[type].nhds,
disk_type[type].spt, ssize, uptr->capac); /* disk capacity */
#ifndef FIXUP_MPX1X_DISK
/* seek to end of disk */
if ((sim_fseek(uptr->fileref, 0, SEEK_END)) != 0) {
sim_debug(DEBUG_CMD, dptr, "SCFI Disk attach SEEK end failed\n");
sim_debug(DEBUG_CMD, dptr, "UDP Disk attach SEEK end failed\n");
printf("Disk attach SEEK end failed\r\n");
goto fmt; /* not setup, go format */
}
s = ftell(uptr->fileref); /* get current file position */
if (s == 0) {
sim_debug(DEBUG_CMD, dptr, "SCFI Disk attach ftell failed s=%06d\n", s);
sim_debug(DEBUG_CMD, dptr, "UDP Disk attach ftell failed s=%06d\n", s);
printf("Disk attach ftell failed s=%06d\r\n", s);
goto fmt; /* not setup, go format */
}
sim_debug(DEBUG_CMD, dptr, "SCFI Disk attach ftell value s=%06d b=%06d CAP %06d\n", s/ssize, s, CAP(type));
printf("Disk attach ftell value s=%06d b=%06d CAP %06d\r\n", s/ssize, s, CAP(type));
// sim_debug(DEBUG_CMD, dptr, "UDP Disk attach ftell value s=%06d b=%06d CAP %06d\n", s/ssize, s, CAP(type));
// printf("Disk attach ftell value s=%06d b=%06d CAP %06d\r\n", s/ssize, s, CAP(type));
if ((s/ssize) < (CAP(type))) { /* full sized disk? */
if (((int)s/(int)ssize) < ((int)CAP(type))) { /* full sized disk? */
j = (CAP(type) - (s/ssize)); /* get # sectors to write */
sim_debug(DEBUG_CMD, dptr,
"Disk attach for MPX 1.X needs %04d more sectors added to disk\n", j);
@ -3144,82 +3138,56 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
printf("Disk attach MPX 1.X file extended & sized secs %06d bytes %06d\r\n", s/ssize, s);
}
#ifndef FIXUP_MPX1X_DISK
/* seek last sector of disk */
if ((sim_fseek(uptr->fileref, (CAP(type)-1)*ssize, SEEK_SET)) != 0) {
sim_debug(DEBUG_CMD, dptr, "Disk attach SEEK last sector failed\n");
printf( "Disk attach SEEK last sector failed\r\n");
sim_debug(DEBUG_CMD, dptr, "UDP Disk attach SEEK last sector failed\n");
printf("UDP Disk attach SEEK last sector failed\r\n");
goto fmt;
}
/* see if there is disk size-1 in last sector of disk, if not add it */
if ((r = sim_fread(buff, sizeof(uint8), ssize, uptr->fileref) != ssize)) {
sim_debug(DEBUG_CMD, dptr, "Disk format fread error = %04d\n", r);
printf( "Disk format fread error = %04d\r\n", r);
sim_debug(DEBUG_CMD, dptr, "UDP Disk format fread error = %04d\n", r);
printf("UDP Disk format fread error = %04d\r\n", r);
add_size:
if (ssize == 768) {
/* assume we have MPX 1x, and go on */
// goto dompx1x;
/* write dmap data to last sector on disk for mpx 1.x */
if ((sim_fseek(uptr->fileref, laddr*ssize, SEEK_SET)) != 0) { /* seek last sector */
sim_debug(DEBUG_CMD, dptr,
/* write dmap data to last sector on disk for mpx 1.x */
if ((sim_fseek(uptr->fileref, laddr*ssize, SEEK_SET)) != 0) { /* seek last sector */
sim_debug(DEBUG_CMD, dptr,
"Disk Error on last sector seek to sect %06d offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf(
"Disk Error on last sector seek to sect %06d offset %06d bytes\r\n",
printf("Disk Error on last sector seek to sect %06d offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
goto fmt;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
goto fmt;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
"Disk Error writing DMAP to sect %06x offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf(
"Disk Error writing DMAP to sect %06x offset %06d bytes\r\n",
printf("Disk Error writing DMAP to sect %06x offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
goto fmt;
}
/* seek last sector of disk */
if ((sim_fseek(uptr->fileref, (CAP(type))*ssize, SEEK_SET)) != 0) {
sim_debug(DEBUG_CMD, dptr, "Disk attach SEEK last sector failed\n");
printf( "Disk attach SEEK last sector failed\r\n");
goto fmt;
}
s = ftell(uptr->fileref); /* get current file position */
sim_debug(DEBUG_CMD, dptr,
"Disk attach MPX file extended & sized secs %06d bytes %06d\n", s/ssize, s);
printf("Disk attach MPX file extended & sized secs %06d bytes %06d\r\n", s/ssize, s);
goto ldone;
} else {
/* error if UTX */
detach_unit(uptr); /* if error, abort */
return SCPE_FMT; /* error */
goto fmt;
}
/* seek last sector of disk */
if ((sim_fseek(uptr->fileref, (CAP(type))*ssize, SEEK_SET)) != 0) {
sim_debug(DEBUG_CMD, dptr, "Disk attach SEEK last sector failed\n");
printf( "Disk attach SEEK last sector failed\r\n");
goto fmt;
}
s = ftell(uptr->fileref); /* get current file position */
sim_debug(DEBUG_CMD, dptr,
"UDP Disk attach MPX file extended & sized secs %06d bytes %06d\n", s/ssize, s);
printf("UDP Disk attach MPX file extended & sized secs %06d bytes %06d\r\n", s/ssize, s);
goto ldone;
} else {
/* if not disk size, go add it in for MPX, error if UTX */
if ((buff[0] | buff[1] | buff[2] | buff[3]) == 0) {
sim_debug(DEBUG_CMD, dptr,
"Disk format0 buf0 %02x buf1 %02x buf2 %02x buf3 %02x\n",
"UDP Disk format0 buf0 %02x buf1 %02x buf2 %02x buf3 %02x\n",
buff[0], buff[1], buff[2], buff[3]);
goto add_size;
}
}
#endif
#endif
#ifdef JUNK
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
detach_unit(uptr); /* if no space, error */
return SCPE_UNATT; /* error */
}
/* see if there is any data on sector zero of disk, if not format it */
if ((r = sim_fread(buff, sizeof(uint8), ssize, uptr->fileref) != ssize)) {
sim_debug(DEBUG_CMD, dptr, "Disk format fread ret = %04x\n", r);
goto fmt;
}
#endif
info = (buff[0]<<24) | (buff[1]<<16) | (buff[2]<<8) | buff[3];
good = 0xf0000000 | (CAP(type)-1);
@ -3273,19 +3241,17 @@ ldone:
uptr->CHS = 0; /* set CHS to cyl/hd/sec = 0 */
sim_debug(DEBUG_CMD, dptr,
"Disk Attach %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\n",
"UDP %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\n",
disk_type[type].name, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
printf(
"Disk Attach %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\r\n",
printf("UDP Attach %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\r\n",
disk_type[type].name, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
sim_debug(DEBUG_CMD, dptr,
"File %s attached to %s with labels\n",
"UDP File %s attached to %s with labels\n",
file, disk_type[type].name);
printf(
"File %s attached to %s with labels\r\n",
printf("UDP File %s attached to %s with labels\r\n",
file, disk_type[type].name);
/* check for valid configured disk */
@ -3293,9 +3259,9 @@ ldone:
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (chp == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nDISK device %s not configured on system, aborting\n",
"ERROR===ERROR\nUDP device %s not configured on system, aborting\n",
dptr->name);
printf("ERROR===ERROR\nDISK device %s not configured on system, aborting\r\n",
printf("ERROR===ERROR\nUDP device %s not configured on system, aborting\r\n",
dptr->name);
detach_unit(uptr); /* detach if error */
return SCPE_UNATT; /* error */

14
SEL32/sel32_ec.c
View File

@ -361,14 +361,6 @@ loop:
return 1; /* return error */
}
#ifdef WHATISTHIS
/* Check if we have status modifier set */
if (chp->chan_status & STATUS_MOD) {
chp->chan_caw += 8; /* move to next IOCD */
chp->chan_status &= ~STATUS_MOD; /* turn off status modifier flag */
}
#endif
/* Read in first CCW */
if (readfull(chp, chp->chan_caw, &word1) != 0) { /* read word1 from memory */
chp->chan_status |= STATUS_PCHK; /* memory read error, program check */
@ -457,7 +449,6 @@ loop:
"ec_iocl tic cmd bad address chan %02x tic caw %06x IOCD wd 1 %08x\n",
chan, chp->chan_caw, word1);
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
// chp->chan_caw = word1; /* get new IOCD address */
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
// uptr->SNS |= SNS_INAD; /* invalid address status */
@ -470,7 +461,6 @@ loop:
chan, chp->chan_caw, word1);
goto loop; /* restart the IOCD processing */
}
// chp->chan_caw = word1; /* get new IOCD address */
chp->chan_caw = word1 & MASK24; /* get new IOCD address */
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
uptr->SNS |= SNS_CMDREJ; /* cmd rejected status */
@ -1013,7 +1003,7 @@ uint16 ec_haltio(UNIT *uptr) {
chp->ccw_count = 0; /* zero the count */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC);/* stop any chaining */
uptr->CMD &= LMASK; /* make non-busy */
uptr->SNS = SNS_RCV_RDY; /* status is online & ready */
//12 uptr->SNS = SNS_RCV_RDY; /* status is online & ready */
sim_cancel(uptr); /* clear the input timer */
sim_debug(DEBUG_CMD, dptr,
"ec_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd);
@ -1021,7 +1011,7 @@ uint16 ec_haltio(UNIT *uptr) {
return SCPE_IOERR;
}
uptr->CMD &= LMASK; /* make non-busy */
uptr->SNS = SNS_RCV_RDY; /* status is online & ready */
//12uptr->SNS = SNS_RCV_RDY; /* status is online & ready */
sim_debug(DEBUG_CMD, dptr,
"ec_haltio HIO I/O not busy chsa %04x cmd = %02x\n", chsa, cmd);
return SCPE_OK; /* not busy */

2
SEL32/sel32_fltpt.c
View File

@ -1,6 +1,6 @@
/* sel32_fltpt.c: SEL 32 floating point instructions processing.
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a

912
SEL32/sel32_hsdp.c
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File diff suppressed because it is too large Load Diff

2
SEL32/sel32_iop.c
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@ -1,6 +1,6 @@
/* sel32_iop.c: SEL-32 Model 8000/8001/8002 IOP processor controller
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),

7
SEL32/sel32_lpr.c
View File

@ -1,6 +1,6 @@
/* sel32_lpr.c: SEL 32 Line Printer
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -136,9 +136,9 @@ LPFCTBL EQU $
struct _lpr_data
{
uint8 lbuff[160]; /* Output line buffer */
}
};
lpr_data[NUM_DEVS_LPR];
struct _lpr_data lpr_data[NUM_DEVS_LPR];
uint16 lpr_startcmd(UNIT *, uint16, uint8);
void lpr_ini(UNIT *, t_bool);
@ -465,7 +465,6 @@ t_stat lpr_attach(UNIT *uptr, CONST char *file)
/* check for valid configured lpr */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
//??if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (chp == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nLPR device %s not configured on system, aborting\n",

35
SEL32/sel32_mfp.c
View File

@ -1,6 +1,6 @@
/* sel32_mfp.c: SEL-32 Model 8002 MFP processor controller
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -237,16 +237,6 @@ t_stat mfp_srv(UNIT *uptr)
uint8 ch;
/* Word 0 */ /* board mod 4324724 = 0x0041fd74 */
#ifdef USE_OLD_UTX
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 0 */
ch = 0x41;
chan_write_byte(chsa, &ch); /* write byte 1 */
ch = 0xfd;
chan_write_byte(chsa, &ch); /* write byte 2 */
ch = 0x74;
chan_write_byte(chsa, &ch); /* write byte 3 */
#else
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 0 */
ch = 0x00;
@ -255,19 +245,8 @@ t_stat mfp_srv(UNIT *uptr)
chan_write_byte(chsa, &ch); /* write byte 2 */
ch = 0x02;
chan_write_byte(chsa, &ch); /* write byte 3 */
#endif
/* Word 1 */ /* firmware 4407519 = 0x004340df */
#ifdef USE_OLD_UTX
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 4 */
ch = 0x43;
chan_write_byte(chsa, &ch); /* write byte 5 */
ch = 0x40;
chan_write_byte(chsa, &ch); /* write byte 6 */
ch = 0xdf;
chan_write_byte(chsa, &ch); /* write byte 7 */
#else
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 4 */
ch = 0x00;
@ -276,19 +255,8 @@ t_stat mfp_srv(UNIT *uptr)
chan_write_byte(chsa, &ch); /* write byte 6 */
ch = 0x02;
chan_write_byte(chsa, &ch); /* write byte 7 */
#endif
/* Word 2 */ /* firmware rev 4259588 = 0x0040ff04 */
#ifdef USE_OLD_UTX
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 8 */
ch = 0x40;
chan_write_byte(chsa, &ch); /* write byte 9 */
ch = 0xff;
chan_write_byte(chsa, &ch); /* write byte 10 */
ch = 0x04;
chan_write_byte(chsa, &ch); /* write byte 11 */
#else
ch = 0x00;
chan_write_byte(chsa, &ch); /* write byte 8 */
ch = 0x00;
@ -297,7 +265,6 @@ t_stat mfp_srv(UNIT *uptr)
chan_write_byte(chsa, &ch); /* write byte 10 */
ch = 0x14;
chan_write_byte(chsa, &ch); /* write byte 11 */
#endif
uptr->u3 &= LMASK; /* nothing left, command complete */
sim_debug(DEBUG_CMD, &mfp_dev, "mfp_srv SID chan %02x: chnend|devend\n", chsa);

3
SEL32/sel32_mt.c
View File

@ -1,6 +1,6 @@
/* sel32_mt.c: SEL-32 8051 Buffered Tape Processor
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
@ -1139,7 +1139,6 @@ t_stat mt_attach(UNIT *uptr, CONST char *file)
/* check for valid configured tape */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */
//??if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (dibp->chan_prg == NULL)) {
if ((dib_unit[chsa] == NULL) || (dibp == NULL) || (chp == NULL)) {
sim_debug(DEBUG_CMD, dptr,
"ERROR===ERROR\nMT device %s not configured on system, aborting\n",

83
SEL32/sel32_scfi.c
View File

@ -570,7 +570,6 @@ loop:
return 1; /* error return */
}
#ifndef NOT_FOR_EVERYONE
/* DC can only be used with a read/write cmd */
if (chp->ccw_flags & FLAG_DC) {
if ((chp->ccw_cmd != DSK_RD) && (chp->ccw_cmd != DSK_WD)) {
@ -581,7 +580,6 @@ loop:
return 1; /* error return */
}
}
#endif
chp->chan_byte = BUFF_BUSY; /* busy & no bytes transferred yet */
@ -1502,6 +1500,16 @@ int scfi_format(UNIT *uptr) {
uint32 cap = CAP(type); /* disk capacity in sectors */
uint32 cylv = cyl; /* number of cylinders */
uint8 *buff;
int32 i;
/* last sector address of disk (cyl * hds * spt) - 1 */
uint32 laddr = CAP(type) - 1; /* last sector of disk */
/* make up dummy defect map */
// uint32 dmap[4] = {0xf0000000 | (cap-1), 0x8a000000 | daddr,
uint32 dmap[4] = {0xf0000000 | (cap-1), 0x8a000000,
0x9a000000 | (cap-1), 0xf4000000};
/* see if user wants to initialize the disk */
if (!get_yn("Initialize disk? [Y] ", TRUE)) {
@ -1519,11 +1527,6 @@ int scfi_format(UNIT *uptr) {
detach_unit(uptr);
return SCPE_ARG;
}
/* put dummy data in first word of disk */
buff[0] = 'Z';
buff[1] = 'E';
buff[2] = 'R';
buff[3] = 'O';
sim_debug(DEBUG_CMD, dptr,
"Creating disk file of trk size %04x bytes, capacity %d\n",
tsize*ssize, cap*ssize);
@ -1537,12 +1540,6 @@ int scfi_format(UNIT *uptr) {
buff = 0;
return 1;
}
if (cyl == 0) {
buff[0] = 0;
buff[1] = 0;
buff[2] = 0;
buff[3] = 0;
}
if ((cyl % 100) == 0)
fputc('.', stderr);
}
@ -1551,7 +1548,32 @@ int scfi_format(UNIT *uptr) {
free(buff); /* free cylinder buffer */
buff = 0;
/* byte swap the buffer for dmap */
for (i=0; i<4; i++) {
dmap[i] = (((dmap[i] & 0xff) << 24) | ((dmap[i] & 0xff00) << 8) |
((dmap[i] & 0xff0000) >> 8) | ((dmap[i] >> 24) & 0xff));
}
/* now seek to end of disk and write the dmap data to last sector */
/* write dmap data to last sector on disk */
if ((sim_fseek(uptr->fileref, laddr*ssize, SEEK_SET)) != 0) { /* seek last sector */
sim_debug(DEBUG_CMD, dptr,
"Error on last sector seek to sect %06x offset %06x\n",
cap-1, (cap-1)*ssize);
return 1;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
"Error writing DMAP to sect %06x offset %06x\n",
cap-1, (cap-1)*ssize);
return 1;
}
printf("Disk %s has %x (%d) cyl, %x (%d) hds, %x (%d) sec\r\n",
scfi_type[type].name, CYL(type), CYL(type), HDS(type), HDS(type),
SPT(type), SPT(type));
/* seek home again */
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
fprintf (stderr, "Error on seek to 0\r\n");
return 1;
@ -1577,10 +1599,11 @@ t_stat scfi_attach(UNIT *uptr, CONST char *file)
uint32 laddr = CAP(type) - 1; /* last sector of disk */
/* get sector address of utx diag map (DMAP) track 0 pointer */
/* put data = 0xf0000000 + (cyl-1), 0x8a000000 + daddr, */
/* 0x9a000000 + (cyl-1), 0xf4000008 */
int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* 0x9a000000 + (cyl-1), 0xf4000000 */
// int32 daddr = (CYL(type)-4) * SPC(type) + (HDS(type)-2) * SPT(type);
/* defect map */
uint32 dmap[4] = {0xf0000000 | (CAP(type)-1), 0x8a000000 | daddr,
// uint32 dmap[4] = {0xf0000000 | (CAP(type)-1), 0x8a000000 | daddr,
uint32 dmap[4] = {0xf0000000 | (CAP(type)-1), 0x8a000000,
0x9a000000 | (CAP(type)-1), 0xf4000000};
for (i=0; i<4; i++) { /* byte swap data for last sector */
@ -1600,7 +1623,7 @@ t_stat scfi_attach(UNIT *uptr, CONST char *file)
uptr->capac = CAP(type); /* disk capacity in sectors */
ssize = SSB(type); /* get sector size in bytes */
for (i=0; i<ssize; i++)
for (i=0; i<(int)ssize; i++)
buff[i] = 0; /* zero the buffer */
sim_debug(DEBUG_CMD, dptr,
@ -1628,7 +1651,7 @@ t_stat scfi_attach(UNIT *uptr, CONST char *file)
sim_debug(DEBUG_CMD, dptr, "SCFI Disk attach ftell value s=%06d b=%06d CAP %06d\n", s/ssize, s, CAP(type));
printf("SCFI Disk attach ftell value s=%06d b=%06d CAP %06d\r\n", s/ssize, s, CAP(type));
if ((s/ssize) < (CAP(type))) { /* full sized disk? */
if (((int)s/(int)ssize) < ((int)CAP(type))) { /* full sized disk? */
j = (CAP(type) - (s/ssize)); /* get # sectors to write */
sim_debug(DEBUG_CMD, dptr,
"SCFI Disk attach for MPX 1.X needs %04d more sectors added to disk\n", j);
@ -1666,20 +1689,18 @@ add_size:
/* write dmap data to last sector on disk for mpx 1.x */
if ((sim_fseek(uptr->fileref, laddr*ssize, SEEK_SET)) != 0) { /* seek last sector */
sim_debug(DEBUG_CMD, dptr,
"SCFI Error on last sector seek to sect %06d offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf(
"SCFI Error on last sector seek to sect %06d offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
"SCFI Error on last sector seek to sect %06d offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf("SCFI Error on last sector seek to sect %06d offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
goto fmt;
}
if ((sim_fwrite((char *)&dmap, sizeof(uint32), 4, uptr->fileref)) != 4) {
sim_debug(DEBUG_CMD, dptr,
"SCFI Error writing DMAP to sect %06x offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf(
"SCFI Error writing DMAP to sect %06x offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
"SCFI Error writing DMAP to sect %06x offset %06d bytes\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
printf("SCFI Error writing DMAP to sect %06x offset %06d bytes\r\n",
(CAP(type)-1), (CAP(type)-1)*ssize);
goto fmt;
}
@ -1744,6 +1765,12 @@ ldone:
scfi_type[type].name, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
sim_debug(DEBUG_CMD, dptr,
"SCFI File %s attached to %s is ready\n",
file, scfi_type[type].name);
printf("SCFI File %s attached to %s is ready\r\n",
file, scfi_type[type].name);
/* check for valid configured disk */
/* must have valid DIB and Channel Program pointer */
dibp = (DIB *)dptr->ctxt; /* get the DIB pointer */

2
SEL32/sel32_scsi.c
View File

@ -1,6 +1,6 @@
/* sel32_scsi.c: SEL-32 MFP SCSI Disk controller
Copyright (c) 2018-2020, James C. Bevier
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a

9
SEL32/sel32_sys.c
View File

@ -1,7 +1,7 @@
/* sel32_sys.c: SEL-32 Gould Concept/32 (orignal SEL-32) Simulator system interface.
Copyright (c) 2018-2020, James C. Bevier
Portions provided by Richard Cornwell and other SIMH contributers
Copyright (c) 2018-2021, James C. Bevier
Portions provided by Richard Cornwell, Geert Rolf and other SIMH contributers
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -19,7 +19,6 @@
JAMES C. BEVIER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sel32_defs.h"
@ -49,7 +48,6 @@ architecture specific formats
fprint_sym print symbolic output
fparse_sym parse symbolic input
*/
char sim_name[] = "SEL-32"; /* our simulator name */
@ -821,7 +819,6 @@ int fprint_inst(FILE *of, uint32 val, int32 sw)
int mode = 0; /* assume non base mode instructions */
t_opcode *tab;
// printf("inst %x sw %x\r\n", val, sw);
if ((PSD[0] & 0x02000000) || (sw & SWMASK('M'))) /* bit 6 is base mode */
mode = 1;
/* loop through the instruction table for an opcode match and get the type */
@ -1066,7 +1063,6 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
}
if (addr & 0x02)
num <<= 16; /* use rt hw */
//printf("call pr_sym addr %x inst %x sw %x num %x\r\n", addr, tmp, sw, num);
l = fprint_inst(of, num, sw); /* go print the instruction */
if (((addr & 2) == 0) && (l == 2)) { /* did we execute a left halfword instruction */
fprintf(of, "; ");
@ -1078,7 +1074,6 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
num = 0;
for (i = 0; i < l && i < 4; i++)
num |= (uint32)val[i] << ((l-i-1) * 8); /* collect 8-32 bit data value to print */
//printf("call pr_val addr %x inst %x sw %x num %x\r\n", addr, tmp, sw, num);
fprint_val(of, num, rdx, l*8, PV_RZRO); /* print it in requested radix */
}
return -(l-1); /* will be negative if we did anything */

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doc/sel32_doc.doc
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