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KA10: Updates to fix KS tapes and ITS support.

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This commit is contained in:
Richard Cornwell 2021-07-11 22:17:30 -04:00
parent 202d3580b1
commit 8de55eea5c
5 changed files with 50 additions and 50 deletions
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6
PDP10/ks10_cty.c
View File

@ -84,8 +84,8 @@ MTAB cty_mod[] = {
};
UNIT cty_unit[] = {
{ UDATA (&ctyo_svc, TT_MODE_7B, 0), 1000},
{ UDATA (&ctyi_svc, TT_MODE_7B|UNIT_DIS, 0), 2000 },
{ UDATA (&ctyo_svc, TT_MODE_7B, 0), 4000},
{ UDATA (&ctyi_svc, TT_MODE_7B|UNIT_DIS, 0), 3000 },
{ UDATA (&ctyrtc_srv, UNIT_IDLE|UNIT_DIS, 0), 1000 }
};
@ -117,7 +117,7 @@ t_stat ctyi_svc (UNIT *uptr)
uint64 buffer;
int32 ch;
sim_clock_coschedule (uptr, tmxr_poll);
sim_clock_coschedule (uptr, tmxr_poll * 2);
if (Mem_read_word(CTY_IN, &buffer, 0))
return SCPE_OK;

64
PDP10/kx10_cpu.c
View File

@ -8829,7 +8829,7 @@ jrstf:
/* On KA or KI the AC is stored before Memory */
MQ = BR; /* Save original stack in case fault on write */
BR = SOB(BR);
AR = BR & FMASK;
AR = BR & FMASK;
set_reg(AC, AR);
#endif
@ -8915,7 +8915,7 @@ jrstf:
AR = BR & FMASK;
set_reg(AC, AR);
break;
}
}
}
#endif
if ((BR & C1) == 0) {
@ -8932,7 +8932,7 @@ jrstf:
break;
case 0264: /* JSR */
AR &= RMASK;
AR &= RMASK;
#if KL
if (QKLB && t20_page && pc_sect != 0)
MB = ((uint64)pc_sect << 18) + (PC + !pi_cycle);
@ -9020,8 +9020,8 @@ jrstf:
break;
case 0266: /* JSA */ /* FBR|SCE */
AR = ((AR & RMASK) << 18) | ((PC + 1) & RMASK);
MB = BR;
AR = ((AR & RMASK) << 18) | ((PC + 1) & RMASK);
MB = BR;
set_reg(AC, AR);
#if !PDP6
if (uuo_cycle | pi_cycle) {
@ -9479,7 +9479,7 @@ skip_op:
if (Mem_write(0, 0)) {
goto last;
}
AR = MB;
AR = MB;
break;
case 0417: /* SETMB */ /* SAC|FCE */
@ -10911,7 +10911,13 @@ skip_op:
goto last;
AR = MB;
break;
#if 0
/* 70154 */
case 011:
case 013:
if (QITS)
break;
#endif
default:
goto muuo;
}
@ -11000,60 +11006,60 @@ skip_op:
case 010: /* WRSPB */ /* ITS LDBR1 */
#if KS_ITS
if (QITS) {
dbr1 = AR;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", dbr3);
dbr1 = AB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR1 %012llo\n", dbr1);
break;
}
#endif
if (Mem_read(0, 0, 0, 0))
goto last;
spt = MB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", spt);
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPB %012llo\n", spt);
break;
/* 70244 */
case 011: /* WRCSB */ /* ITS LDBR2 */
#if KS_ITS
if (QITS) {
dbr2 = AR;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", dbr3);
dbr2 = AB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR2 %012llo\n", dbr2);
break;
}
#endif
if (Mem_read(0, 0, 0, 0))
goto last;
cst = MB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", cst);
sim_debug(DEBUG_CONI, &cpu_dev, "WRCSB %012llo\n", cst);
break;
/* 70250 */
case 012: /* WRPUR */ /* ITS LDBR3 */
#if KS_ITS
if (QITS) {
dbr3 = AR;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", dbr3);
dbr3 = AB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR3 %012llo\n", dbr3);
break;
}
#endif
if (Mem_read(0, 0, 0, 0))
goto last;
cst_dat = MB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", cst_dat);
sim_debug(DEBUG_CONI, &cpu_dev, "WRPUR %012llo\n", cst_dat);
break;
/* 70254 */
case 013: /* WRCSTM */ /* ITS LDBR4 */
#if KS_ITS
if (QITS) {
dbr4 = AR;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", dbr4);
dbr4 = AB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRDBR4 %012llo\n", dbr4);
break;
}
#endif
if (Mem_read(0, 0, 0, 0))
goto last;
cst_msk = MB;
sim_debug(DEBUG_CONI, &cpu_dev, "WRSPD %012llo\n", cst_msk);
sim_debug(DEBUG_CONI, &cpu_dev, "WRCSTM %012llo\n", cst_msk);
break;
/* 70264 */
@ -11130,13 +11136,13 @@ skip_op:
io_fault:
fault_data = (020LL << 30) | BIT8 | BIT10;
fault_data |= (uint64)((020 & IR) << 18);
fault_data |= AB | (ctl << 18);
fault_data |= AB | (ctl << 18);
page_fault = 1;
goto last;
}
if ((BR & MB) == 0)
PC = (PC + 1) & RMASK;
AR = MB;
AR = MB;
break;
case 011: /* TION, ITS RDIOQ */
@ -11150,7 +11156,7 @@ io_fault:
goto io_fault;
if ((BR & MB) != 0)
PC = (PC + 1) & RMASK;
AR = MB;
AR = MB;
break;
case 012: /* RDIO */
@ -11221,11 +11227,11 @@ its_wr:
#endif
if (uba_read(AB, ctl, &MB, BYTE))
goto io_fault;
if (AB & 1)
BR >>= 8;
if (AB & 1)
BR >>= 8;
if ((BR & MB) == 0)
PC = (PC + 1) & RMASK;
AR = MB;
AR = MB;
break;
case 021: /* TIONB */
@ -11237,8 +11243,8 @@ its_wr:
#endif
if (uba_read(AB, ctl, &MB, BYTE))
goto io_fault;
if (AB & 1)
BR >>= 8;
if (AB & 1)
BR >>= 8;
if ((BR & MB) != 0)
PC = (PC + 1) & RMASK;
break;
@ -11255,8 +11261,8 @@ its_rdb:
#endif
if (uba_read(AB, ctl, &AR, BYTE))
goto io_fault;
if (AB & 1)
AR >>= 8;
if (AB & 1)
AR >>= 8;
set_reg(AC, AR);
break;

12
PDP10/kx10_rh.c
View File

@ -193,7 +193,6 @@ int rh_map[] = { 0, /* 776700 */
#if KS
int
uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
int i;
int r = 0;
struct pdp_dib *dibp = (DIB *) dptr->ctxt;
struct rh_if *rhc;
@ -223,7 +222,7 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
if (addr & 1)
data = data | (temp & 0377);
else
data = (temp & 0177600) | data;
data = (temp & 0177400) | data;
}
switch(addr) {
@ -253,7 +252,7 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
if (addr & 1)
data = data | (rhc->wcr & 0377);
else
data = (rhc->wcr & 0177600) | data;
data = (rhc->wcr & 0177400) | data;
}
rhc->wcr = data;
break;
@ -262,7 +261,7 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
if (addr & 1)
data = data | (rhc->cda & 0377);
else
data = (rhc->cda & 0177600) | data;
data = (rhc->cda & 0177400) | data;
}
rhc->cda = (rhc->cda & 0600000) | (data & 0177776);
break;
@ -315,7 +314,6 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) {
int
uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access) {
int i;
int r = 1;
struct pdp_dib *dibp = (DIB *) dptr->ctxt;
struct rh_if *rhc;
@ -1045,7 +1043,7 @@ int rh_read(struct rh_if *rhc) {
rhc->status &= ~BUSY;
return 0;
}
if ((rhc->cs2 & CS2_UAI) == 0)
// if ((rhc->cs2 & CS2_UAI) == 0)
rhc->cda += 4;
rhc->wcr = (rhc->wcr + 2) & 0177777;
if (rhc->wcr == 0) {
@ -1110,7 +1108,7 @@ int rh_write(struct rh_if *rhc) {
rhc->status &= ~BUSY;
return 0;
}
if ((rhc->cs2 & CS2_UAI) == 0)
// if ((rhc->cs2 & CS2_UAI) == 0)
rhc->cda += 4;
rhc->wcr = (rhc->wcr + 2) & 0177777;
if (rhc->wcr == 0) {

4
PDP10/kx10_rp.c
View File

@ -1099,8 +1099,10 @@ rp_boot(int32 unit_num, DEVICE * rptr)
DEVICE *dptr = uptr->dptr;
uint32 addr;
uint32 ptr = 0;
int wc;
uint64 word;
#if !KS
int wc;
#endif
#if KS
int da;

14
PDP10/kx10_tu.c
View File

@ -800,14 +800,6 @@ t_stat tu_srv(UNIT * uptr)
case FNC_SPACEB:
sim_debug(DEBUG_DETAIL, dptr, "%s%o space %06o %o\n", dptr->name, unit, regs[TUDC], GET_FNC(uptr->CMD));
uptr->STATUS &= ~DS_PIP;
#if 0
if (regs[TUDC] == 0) {
regs[TUER1] |= ER1_NEF;
uptr->STATUS |= DS_ATA;
tu_error(uptr, MTSE_OK);
return SCPE_OK;
}
#endif
/* Always skip at least one record */
if (GET_FNC(uptr->CMD) == FNC_SPACEF)
r = sim_tape_sprecf(uptr, &reclen);
@ -912,13 +904,15 @@ tu_boot(int32 unit_num, DEVICE * dptr)
return r;
uptr->DATAPTR = 0;
uptr->hwmark = reclen;
wc = reclen;
addr = 01000;
while ((uint32)uptr->DATAPTR < uptr->hwmark) {
while (uptr->DATAPTR < wc) {
tu_read_word(uptr);
M[addr] = tu_boot_buffer;
addr ++;
}
regs[TUTC] |= unit_num;
M[036] = rhc->dib->uba_addr | (rhc->dib->uba_ctl << 18);
M[037] = 0;
M[040] = regs[TUTC];
@ -955,8 +949,8 @@ tu_boot(int32 unit_num, DEVICE * dptr)
M[addr] = tu_boot_buffer;
PC = tu_boot_buffer & RMASK;
#endif
regs[TUTC] |= unit_num;
#endif
return SCPE_OK;
}