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SEL32: Change channel programming support code.

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SEL32: Correct trap status bits for 32/97 & V9 diags.
SEL32: Allow I/O processing while CPU interrupts are blocked.
SEL32: Rewrite testxio and haltxio processing logic.
SEL32: Rewrite CPU interrupt processing logic.
SEL32: Correct known Coverity errors.
This commit is contained in:
AZBevier 2020-03-30 20:27:27 -07:00
parent 71c6453f69
commit 96f762e2f0
11 changed files with 1486 additions and 1288 deletions
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1362
SEL32/sel32_chan.c
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File diff suppressed because it is too large Load Diff

18
SEL32/sel32_clk.c
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@ -35,6 +35,8 @@
#if NUM_DEVS_RTOM > 0
#define UNIT_CLK UNIT_ATTABLE|UNIT_IDLE|UNIT_DISABLE
void rtc_setup (uint32 ss, uint32 level);
t_stat rtc_srv (UNIT *uptr);
t_stat rtc_reset (DEVICE *dptr);
@ -51,6 +53,8 @@ extern uint32 M[]; /* system memory */
int32 rtc_pie = 0; /* rtc pulse ie */
int32 rtc_tps = 60; /* rtc ticks/sec */
int32 rtc_lvl = 0x18; /* rtc interrupt level */
time_t lastcresult = 0; /* last clock int time for rtc */
time_t lastiresult = 0; /* last clock int time for tim */
/* Clock data structures
@ -62,6 +66,7 @@ int32 rtc_lvl = 0x18; /* rtc interrupt level */
/* clock is attached all the time */
/* default to 60 HZ RTC */
UNIT rtc_unit = { UDATA (&rtc_srv, UNIT_IDLE, 0), 16666, UNIT_ADDR(0x7F06)};
//UNIT rtc_unit = { UDATA (&rtc_srv, UNIT_CLK, 0), 16666, UNIT_ADDR(0x7F06)};
REG rtc_reg[] = {
{ FLDATA (PIE, rtc_pie, 0) },
@ -106,11 +111,14 @@ t_stat rtc_srv (UNIT *uptr)
if (rtc_pie) { /* set pulse intr */
time_t result = time(NULL);
// fprintf(stderr, "Clock int time %08x\r\n", (uint32)result);
sim_debug(DEBUG_CMD, &rtc_dev, "RT Clock int time %08x\n", (uint32)result);
sim_debug(DEBUG_CMD, &rtc_dev, "RT Clock int time %08x diff from last %08x\n",
(uint32)result, (uint32)(result-lastcresult));
// lastcresult = result; /* save last clock time */
if (((INTS[rtc_lvl] & INTS_ENAB) || /* make sure enabled */
(SPAD[rtc_lvl+0x80] & SINT_ENAB)) && /* in spad too */
(((INTS[rtc_lvl] & INTS_ACT) == 0) || /* and not active */
((SPAD[rtc_lvl+0x80] & SINT_ACT) == 0))) { /* in spad too */
//DIAGHELP INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
irq_pend = 1; /* make sure we scan for int */
}
@ -142,12 +150,13 @@ void rtc_setup(uint32 ss, uint32 level)
INTS[level] &= ~INTS_ENAB; /* make sure disabled */
SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
// INTS[level] &= ~INTS_REQ; /* make sure request not requesting */
// INTS[level] &= ~INTS_ACT; /* make sure request not active */
// SPAD[level+0x80] &= ~SINT_ACT; /* in spad too */
INTS[level] &= ~INTS_ACT; /* make sure request not active */
SPAD[level+0x80] &= ~SINT_ACT; /* in spad too */
sim_debug(DEBUG_CMD, &rtc_dev,
"RT Clock setup disable int %02x rtc_pie %01x ss %01x\n",
rtc_lvl, rtc_pie, ss);
}
lastcresult = time(NULL); /* save start time */
rtc_pie = ss; /* set new state */
}
@ -374,12 +383,13 @@ void itm_setup(uint32 ss, uint32 level)
INTS[level] &= ~INTS_ENAB; /* make sure disabled */
SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
// INTS[level] &= ~INTS_REQ; /* make sure request not requesting */
// INTS[level] &= ~INTS_ACT; /* make sure request not active */
INTS[level] &= ~INTS_ACT; /* make sure request not active */
SPAD[level+0x80] &= ~SINT_ACT; /* in spad too */
sim_debug(DEBUG_CMD, &itm_dev,
"Intv Timer setup disable int %02x value %08x itm_pie %01x ss %01x\n",
itm_lvl, itm_cnt, itm_pie, ss);
}
lastiresult = time(NULL); /* save start time */
itm_pie = ss; /* set new state */
}

118
SEL32/sel32_con.c
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@ -193,7 +193,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD |= CON_INCH2; /* save INCH command as 0xf0 */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -203,7 +204,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD |= (cmd & CON_MSK); /* save command */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -219,7 +221,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->u4 = 0; /* no I/O yet */
con_data[unit].incnt = 0; /* clear any input data */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0;
break;
@ -229,7 +232,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->CMD |= (cmd & CON_MSK); /* save command */
// uptr->u4 = 0; /* no I/O yet */
// con_data[unit].incnt = 0; /* clear any input data */
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
@ -238,7 +242,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->CMD &= LMASK; /* leave only chsa */
uptr->CMD |= (cmd & CON_MSK); /* save command */
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 40); /* start us off */
return 0; /* no status change */
break;
#endif
@ -278,6 +283,10 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
}
#ifdef DO_DYNAMIC_DEBUG
static uint32 last2 = 0;
#endif
/* Handle output transfers for console */
t_stat con_srvo(UNIT *uptr) {
uint16 chsa = GET_UADDR(uptr->CMD);
@ -286,7 +295,7 @@ t_stat con_srvo(UNIT *uptr) {
CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uint8 ch, cp;
sim_debug(DEBUG_DETAIL, &con_dev, "con_srvo enter chsa %04x cmd = %02x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvo enter chsa %04x cmd = %02x\n", chsa, cmd);
/* if input tried from output device, error */
if ((cmd == CON_RD) || (cmd == CON_ECHO) || (cmd == 0xC0)) { /* check for output */
@ -348,12 +357,20 @@ t_stat con_srvo(UNIT *uptr) {
sim_debug(DEBUG_CMD, &con_dev,
"con_srvo write %01x: putch 0x%02x %c\n", unit, ch, cp);
sim_putchar(ch); /* output next char to device */
#ifdef DO_DYNAMIC_DEBUG
last2 = ((last2 << 8) & 0xffff) | cp; /* get last 2 chars */
if (last2 == 0x503e) { /* check for DXP> */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
con_dev.dctrl |= (DEBUG_CMD | DEBUG_EXP | DEBUG_DETAIL);
}
#endif
//OLD sim_putchar(cp); /* output next char to device */
#else
sim_putchar(ch); /* output next char to device */
//WAS sim_putchar(cp); /* output next char to device */
#endif
sim_activate(uptr, 20); /* keep going */
//@ sim_activate(uptr, 20); /* keep going */
sim_activate(uptr, 30); /* start us off */
}
}
return SCPE_OK;
@ -368,7 +385,7 @@ t_stat con_srvi(UNIT *uptr) {
uint8 ch;
t_stat r;
sim_debug(DEBUG_DETAIL, &con_dev,
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi enter chsa %04x cmd %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count);
/* if output tried to input device, error */
@ -446,8 +463,14 @@ t_stat con_srvi(UNIT *uptr) {
// if (uptr->u4 == con_data[unit].incnt) { /* read completed */
con_data[unit].incnt = 0; /* buffer is empty */
cmd = 0; /* no cmd either */
#ifdef DO_DYNAMIC_DEBUG
if (chp->ccw_addr == 0x18d3) {
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
con_dev.dctrl |= (DEBUG_CMD | DEBUG_EXP | DEBUG_DETAIL);
}
#endif
sim_debug(DEBUG_CMD, &con_dev,
"con_srvi write nothing to mem unit %02x: u4 %02x ccw_count %02x\n",
"con_srvi nothing to write to mem unit %02x: u4 %02x ccw_count %02x\n",
unit, uptr->u4, chp->ccw_count);
uptr->u4 = 0; /* no I/O yet */
uptr->CMD &= LMASK; /* nothing left, command complete */
@ -577,8 +600,10 @@ t_stat con_srvi(UNIT *uptr) {
//WAS2 return sim_activate (uptr, 100);
//WAS3 return sim_activate (uptr, 50);
//LAST return sim_activate (uptr, 200);
return sim_activate (uptr, 40);
//TRY return sim_activate (uptr, 500);
//@ return sim_activate (uptr, 40);
return sim_activate(uptr, 80); /* keep going */
// return sim_activate(uptr, 200); /* keep going */
// return sim_activate (uptr, 5000);
return tmxr_clock_coschedule_tmr (uptr, TMR_RTC, 1); /* come back soon */
}
@ -591,69 +616,30 @@ t_stat con_reset(DEVICE *dptr) {
uint8 con_haltio(UNIT *uptr) {
uint16 chsa = GET_UADDR(uptr->CMD);
int cmd = uptr->CMD & CON_MSK;
int unit = (uptr - con_unit); /* unit # 0 is read, 1 is write */
uint8 ch = 0x20; /* dummy space char for outstanding input */
// int unit = (uptr - con_unit); /* unit # 0 is read, 1 is write */
CHANP *chp = find_chanp_ptr(chsa); /* find the chanp pointer */
// int len = chp->ccw_count; /* command byte count */
sim_debug(DEBUG_EXP, &con_dev, "con_haltio enter chsa %04x cmd = %02x\n", chsa, cmd);
#ifdef DO_DYNAMIC_DEBUG
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
con_dev.dctrl |= (DEBUG_CMD | DEBUG_EXP | DEBUG_DETAIL);
#endif
/* terminate any input command */
if ((uptr->CMD & CON_MSK) != 0) { /* is unit busy */
if ((uptr->CMD & CON_MSK) != 0) { /* is unit busy */
sim_debug(DEBUG_CMD, &con_dev,
"con_haltio HIO chsa %04x cmd = %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count);
if (unit == 0) {
// new code 2/28/2020
if (test_write_byte_end(chsa)) { /* see if read request complete */
chan_write_byte(chsa, &ch); /* write fake byte to memory */
con_data[unit].incnt = 0; /* buffer empty */
uptr->CMD &= LMASK; /* nothing left, command complete */
// chp->ccw_count = 0; /* zero command count */
sim_debug(DEBUG_CMD, &con_dev,
"con_haltio HIO I/O stop chsa %04x cmd %02x ccw_count %02x\n",
chsa, cmd, chp->ccw_count);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
// return SCPE_OK; /* not busy anymore */
return SCPE_IOERR;
}
#ifdef NOT_NOW
else
if (chan_write_byte(chsa, &ch)) { /* write fake byte to memory */
con_data[unit].incnt = 0; /* buffer is empty */
sim_debug(DEBUG_CMD, &con_dev,
"con_haltio write nothing to mem unit %02x: u4 %02x ccw_count %02x\n",
unit, uptr->u4, chp->ccw_count);
uptr->u4 = 0; /* no I/O yet */
uptr->CMD &= LMASK; /* nothing left, command complete */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
//WAS return SCPE_IOERR;
}
#endif
} else {
if (chp->ccw_count > 0) {
if (chan_read_byte(chsa, &ch)) { /* get byte from memory */
uptr->CMD &= LMASK; /* nothing left, command complete */
sim_debug(DEBUG_CMD, &con_dev,
"con_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
// return SCPE_OK; /* not busy anymore */
return SCPE_IOERR;
}
}
}
uptr->CMD &= LMASK; /* make non-busy */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
return SCPE_OK; /* not busy */
//no work chan_end(chsa, SNS_CHNEND|SNS_UNITCHK); /* write terminated */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK); /* write terminated */
// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* done bit 15 */ /* bad status */
// return SCPE_IOERR;
// stop any I/O and post status and return error status */
chp->chan_byte = BUFF_EMPTY; /* there is no data to read/store */
chp->ccw_flags = 0; /* stop any chaining */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* force error */
uptr->CMD &= LMASK; /* make non-busy */
uptr->u4 = 0; /* no I/O yet */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_debug(DEBUG_CMD, &con_dev,
"con_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd);
return SCPE_IOERR;
}
return SCPE_OK; /* not busy */
uptr->u4 = 0; /* no I/O yet */
uptr->CMD &= LMASK; /* make non-busy */
uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */
return SCPE_OK; /* not busy */
}
#endif

795
SEL32/sel32_cpu.c
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File diff suppressed because it is too large Load Diff

37
SEL32/sel32_defs.h
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@ -80,6 +80,9 @@
#define STATUS_DEND 0x0004 /* Device end */
#define STATUS_CHECK 0x0002 /* Unit check */
#define STATUS_EXPT 0x0001 /* Unit exception */
#define STATUS_ERROR 0x3f03 /* bad errors */
//#define STATUS_ERROR (STATUS_LENGTH|STATUS_PCHK|STATUS_CDATA|STATUS_CCNTL|
// STATUS_INTER|STATUS_CHAIN|STATUS_CHECK|STATUS_EXPT)
/* Class F channel bits */
/* bit 32 - 37 of IOCD word 2 (0-5) */
@ -94,6 +97,8 @@
#define BUFF_DIRTY 0x8 /* Buffer is dirty flag */
#define BUFF_NEWCMD 0x10 /* Channel ready for new command */
#define BUFF_CHNEND 0x20 /* Channel end */
#define BUFF_DONE 0x40 /* Channel program done */
#define BUFF_NEXT 0x80 /* Continue Channel with next IOCB */
#define MAX_CHAN 128 /* max channels that can be defined */
#define SUB_CHANS 256 /* max sub channels that can be defined */
@ -110,17 +115,15 @@
#define NUM_UNITS_CON 2 /* 2 console input & output */
#define NUM_DEVS_MT 1 /* 1 mag tape controllers */
#define NUM_UNITS_MT 4 /* 4 of 8 devices */
#define FOR_UTX
#ifdef FOR_UTX
#define NUM_DEVS_HSDP 1 /* 1 HSPD disk drive controller */
#define NUM_DEVS_HSDP 1 /* 1 hspd disk drive controller */
#define NUM_UNITS_HSDP 2 /* 2 disk drive devices */
//#else
#define NUM_DEVS_DISK 1 /* 1 DP02 disk drive controller */
#define NUM_DEVS_DISK 1 /* 1 dp02 disk drive controller */
#define NUM_UNITS_DISK 2 /* 2 disk drive devices */
//#define NUM_UNITS_DISK 4 /* 4 disk drive devices */
#endif
#define NUM_DEVS_SCFI 1 /* 1 scfi (SCSI) disk drive units */
#define NUM_UNITS_SCFI 1 /* 1 of 4 disk drive devices */
#define NUM_DEVS_SCSI 1 /* 1 scsi (MFP SCSI) disk drive units */
#define NUM_UNITS_SCSI 1 /* 1 of 4 disk drive devices */
#define NUM_DEVS_RTOM 1 /* 1 IOP RTOM channel */
#define NUM_UNITS_RTOM 1 /* 1 IOP RTOM device (clock & interval timer) */
#define NUM_DEVS_LPR 1 /* 1 IOP Line printer */
@ -192,6 +195,7 @@ typedef struct chp {
uint16 chan_dev; /* Device on channel */
uint8 ccw_cmd; /* Channel command and flags */
uint8 chan_byte; /* Current byte, dirty/full */
uint8 chan_int; /* channel interrupt level */
} CHANP;
/* Device information block */
@ -394,15 +398,15 @@ extern DEBTAB dev_debug[];
#define SINT_EWCS 0x40000000 /* Enabled channel WCS executed (XIO) */
#define SINT_ACT 0x20000000 /* Interrupt active when set (copy is in INTS */
#define SINT_ENAB 0x10000000 /* Interrupt enabled when set (copy is in INTS */
#define SINT_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy in INTS) */
#define SINT_EXTL 0x00800000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy in INTS) */
/* INTS int entry equates, entries accessed by interrupt level number */
#define INTS_NU1 0x80000000 /* Not used */
#define INTS_NU2 0x40000000 /* Not used */
#define INTS_ACT 0x20000000 /* Interrupt active when set (copy is of SPAD */
#define INTS_ENAB 0x10000000 /* Interrupt enabled when set (copy is of SPAD */
#define INTS_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy of SPAD) */
#define INTS_REQ 0x04000000 /* Interrupt is requesting */
#define INTS_EXTL 0x00800000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy of SPAD) */
#define INTS_REQ 0x40000000 /* Interrupt is requesting (use bit 1) */
/* ReadAddr memory access requested */
#define MEM_RD 0x0 /* read memory */
@ -417,12 +421,12 @@ extern DEBTAB dev_debug[];
/* RMW(addr) or WMW(addr, data) where addr is a byte alligned word address */
#define RMB(a) ((M[(a)>>2]>>(8*(7-(a&3))))&0xff) /* read memory addressed byte */
#define RMH(a) ((a)&2?(M[(a)>>2]&RMASK):(M[(a)>>2]>>16)&RMASK) /* read memory addressed halfword */
#define RMW(a) (M[(a)>>2]) /* read memory addressed word */
#define WMW(a,d) (M[(a)>>2]=d) /* write memory addressed word */
#define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */
#define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */
/* write halfword to memory address */
#define WMH(a,d) ((a)&2?(M[(a)>>2]=(M[(a)>>2]&LMASK)|((d)&RMASK)):(M[(a)>>2]=(M[(a)>>2]&RMASK)|((d)<<16)))
/* write byte to memory */
#define WMB(a,d) (M[(a)>>2]=(M[(a)>>2]&(~(0xff<<(8*(7-(a&3)))))|((d&0xff)<<(8*(7-(a&3))))))
#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(7-(a&3))))))|((d&0xff)<<(8*(7-(a&3))))))
/* map register access macros */
/* The RMR and WMR macros are used to read/write the MAPC cache registers */
@ -432,7 +436,7 @@ extern DEBTAB dev_debug[];
/* write halfword map register to MAP cache address */
#define WMR(a,d) ((a)&2?(MAPC[(a)>>2]=(MAPC[(a)>>2]&LMASK)|((d)&RMASK)):(MAPC[(a)>>2]=(MAPC[(a)>>2]&RMASK)|((d)<<16)))
/* Definitions for common used functions */
/* Definitions for commonly used functions */
extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_dev_addr(FILE * st, UNIT *uptr, int32 v, CONST void *desc);
extern void chan_end(uint16 chan, uint16 flags);
@ -449,4 +453,11 @@ extern CHANP *find_chanp_ptr(uint16 chsa); /* find chanp pointer *
extern uint32 M[]; /* our memory */
extern uint32 SPAD[]; /* cpu SPAD memory */
extern uint32 attention_trap;
extern uint32 RDYQ[]; /* ready queue */
extern uint32 RDYQIN; /* input index */
extern uint32 RDYQOUT; /* output index */
#define RDYQ_SIZE 128
extern int32 RDYQ_Put(uint32 entry);
extern int32 RDYQ_Get(uint32 *old);
extern int32 RDYQ_Num(void);

259
SEL32/sel32_disk.c
View File

@ -272,12 +272,12 @@ disk_type[] =
{"MH300", 19, 192, 20, 800, 823, 0x40}, /* 3 823 300M 8127 */
{"MH600", 40, 192, 20, 800, 843, 0x40}, /* 4 843 600M 8155 */
/* For UTX */
{"9342", 5, 256, 16, 819, 823, 0x40}, /* 5 823 80M XXXX */
{"9342", 5, 256, 16, 819, 823, 0x40}, /* 5 823 80M XXXX */
{"8148", 10, 256, 16, 819, 823, 0x40}, /* 6 823 160M 8148 */
{"9346", 19, 256, 16, 819, 823, 0x40}, /* 7 823 300M */
{"8858", 24, 256, 16, 707, 711, 0x40}, /* 8 711 340M */
{"8887", 10, 256, 35, 819, 823, 0x40}, /* 9 823 340M */
{"8155", 40, 256, 16, 839, 843, 0x40}, /* 10 843 675M */
{"9346", 19, 256, 16, 819, 823, 0x40}, /* 7 823 300M */
{"8858", 24, 256, 16, 707, 711, 0x40}, /* 8 711 340M */
{"8887", 10, 256, 35, 819, 823, 0x40}, /* 9 823 340M */
{"8155", 40, 256, 16, 839, 843, 0x40}, /* 10 843 675M */
{NULL, 0}
};
@ -424,12 +424,12 @@ uint8 disk_preio(UNIT *uptr, uint16 chan)
uint16 chsa = GET_UADDR(uptr->CMDu3);
int unit = (uptr - dptr->units);
sim_debug(DEBUG_CMD, dptr, "disk_preio CMD %08x unit %02x\n", uptr->CMDu3, unit);
if ((uptr->CMDu3 & 0xff00) != 0) { /* just return if busy */
sim_debug(DEBUG_DETAIL, dptr, "disk_preio CMD %08x unit %02x\n", uptr->CMDu3, unit);
if ((uptr->CMDu3 & 0xff00) != 0) { /* just return if busy */
return SNS_BSY;
}
sim_debug(DEBUG_CMD, dptr, "disk_preio unit %02x chsa %04x OK\n", unit, chsa);
sim_debug(DEBUG_DETAIL, dptr, "disk_preio unit %02x chsa %04x OK\n", unit, chsa);
return 0; /* good to go */
}
@ -450,10 +450,10 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
}
if ((uptr->CMDu3 & DSK_CMDMSK) != 0) {
uptr->CMDu3 |= DSK_BUSY; /* Flag we are busy */
uptr->CMDu3 |= DSK_BUSY; /* Flag we are busy */
return SNS_BSY;
}
if ((uptr->CMDu3 & 0xff00) != 0) { /* if any status info, we are busy */
if ((uptr->CMDu3 & 0xff00) != 0) { /* if any status info, we are busy */
return SNS_BSY;
}
sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD continue unit=%02x cmd %02x\n", unit, cmd);
@ -466,8 +466,9 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
"disk_startcmd starting INCH %06x cmd, chsa %04x MemBuf %06x cnt %04x\n",
uptr->u4, chsa, chp->ccw_addr, chp->ccw_count);
uptr->CMDu3 |= DSK_INCH2; /* use 0xf0 for inch, just need int */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= DSK_INCH2; /* use 0xf0 for inch, just need int */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
@ -477,46 +478,53 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case DSK_RD: /* Read command 0x02 */
case DSK_LMR: /* read mode register 0x15 */
uptr->CMDu3 |= cmd; /* save cmd */
uptr->CMDu3 |= cmd; /* save cmd */
sim_debug(DEBUG_CMD, dptr,
"disk_startcmd starting disk seek r/w cmd %02x chsa %04x\n",
cmd, chsa);
sim_activate(uptr, 20); /* start things off */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_NOP: /* NOP 0x03 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_SNS: /* Sense 0x04 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
break;
case DSK_WSL: /* WSL 0x31 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_RSL: /* RSL 0x32 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_WTL: /* WTL 0x51 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
case DSK_RTL: /* RTL 0x52 */
uptr->CMDu3 |= cmd; /* save cmd */
sim_activate(uptr, 20); /* start things off */
uptr->CMDu3 |= cmd; /* save cmd */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return 0;
break;
}
@ -524,9 +532,10 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
sim_debug(DEBUG_CMD, dptr,
"disk_startcmd done with disk_startcmd %02x chsa %04x SNS %08x\n",
cmd, chsa, uptr->SNS);
if (uptr->SNS & 0xff) /* any other cmd is error */
if (uptr->SNS & 0xff) /* any other cmd is error */
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK;
sim_activate(uptr, 20); /* start things off */
//@ sim_activate(uptr, 20); /* start things off */
sim_activate(uptr, 40); /* start things off */
return SNS_CHNEND|SNS_DEVEND;
}
@ -592,7 +601,7 @@ t_stat disk_srv(UNIT *uptr)
if (len != 36) {
/* we have invalid count, error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
@ -607,7 +616,7 @@ t_stat disk_srv(UNIT *uptr)
for (i=0; i < 36; i++) {
if (chan_read_byte(chsa, &buf[i])) {
/* we have error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
@ -632,13 +641,13 @@ t_stat disk_srv(UNIT *uptr)
#ifdef NOTYET
if ((i == SCPE_MEM) || (i == SCPE_ARG)) { /* any error */
/* we have error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
#endif
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr,
"disk_srv cmd INCH chsa %04x addr %06x count %04x completed\n",
chsa, mema, chp->ccw_count);
@ -651,7 +660,7 @@ t_stat disk_srv(UNIT *uptr)
break;
case DSK_WSL: /* WSL 0x31 make into NOP */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr,
"disk_srv cmd WSL chsa %04x count %04x completed\n",
chsa, chp->ccw_count);
@ -662,7 +671,7 @@ t_stat disk_srv(UNIT *uptr)
for (i = 0; i < len; i++) {
if (chan_read_byte(chsa, &buf[i])) {
/* we have write error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
//XXX goto goout;
return SCPE_OK;
@ -703,7 +712,7 @@ t_stat disk_srv(UNIT *uptr)
break;
case DSK_NOP: /* NOP 0x03 */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr,
"disk_srv cmd NOP chsa %04x count %04x completed\n",
chsa, chp->ccw_count);
@ -734,7 +743,7 @@ t_stat disk_srv(UNIT *uptr)
chan_write_byte(chsa, &ch);
/* bytes 4 - mode reg, byte 0 of SNS */
ch = (uptr->SNS >> 24) & 0xff; /* return the sense data */
ch = (uptr->SNS >> 24) & 0xff; /* return the sense data */
sim_debug(DEBUG_DETAIL, dptr, "disk_srv sense unit=%02x 1 %02x\n",
unit, ch);
chan_write_byte(chsa, &ch);
@ -784,7 +793,7 @@ t_stat disk_srv(UNIT *uptr)
unit, ch);
chan_write_byte(chsa, &ch);
}
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
break;
@ -796,12 +805,11 @@ t_stat disk_srv(UNIT *uptr)
/* we are on cylinder, seek is done */
sim_debug(DEBUG_CMD, dptr, "disk_srv seek on cylinder unit=%02x %04x %04x\n",
unit, uptr->STAR >> 16, uptr->CHS >> 16);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
/* we have already seeked to the required sector */
/* we do not need to seek again, so move on */
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
return SCPE_OK;
//XXX sim_activate(uptr, 20);
break;
} else {
/* we have wasted enough time, we are there */
@ -817,7 +825,8 @@ t_stat disk_srv(UNIT *uptr)
}
#endif
uptr->CHS = uptr->STAR; /* we are there */
sim_activate(uptr, 10);
//@ sim_activate(uptr, 10);
sim_activate(uptr, 20);
break;
}
}
@ -884,7 +893,7 @@ t_stat disk_srv(UNIT *uptr)
"disk_srv seek ERROR cyl %04x trk %02x sec %02x unit=%02x\n",
cyl, trk, buf[3], unit);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK; /* set error status */
/* we have an error, tell user */
@ -915,17 +924,18 @@ t_stat disk_srv(UNIT *uptr)
/* if not, do a delay to slow things down */
if (STAR2CYL(uptr->STAR) != STAR2CYL(uptr->CHS)) {
/* Do a fake seek to kill time */
uptr->CMDu3 |= DSK_SEEKING; /* show we are seeking */
uptr->CMDu3 |= DSK_SEEKING; /* show we are seeking */
sim_debug(DEBUG_EXP, dptr,
"disk_srv seeking unit=%02x to cyl %04x trk %02x sec %02x\n",
unit, cyl, trk, buf[3]);
sim_activate(uptr, 20); /* start us off */
//@ sim_activate(uptr, 20); /* start us off */
sim_activate(uptr, 30); /* start us off */
} else {
/* we are on cylinder/track/sector, so go on */
sim_debug(DEBUG_DETAIL, dptr,
"disk_srv done seeking to %04x cyl %04x trk %02x sec %02x\n",
tstart, cyl, trk, buf[3]);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
}
return SCPE_OK;
@ -936,14 +946,14 @@ t_stat disk_srv(UNIT *uptr)
/* Do a seek to 0 */
uptr->STAR = 0; /* set STAR to 0, 0, 0 */
uptr->CHS = 0; /* set current CHS to 0, 0, 0 */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 |= DSK_SCK; /* show as seek command */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 |= DSK_SCK; /* show as seek command */
tstart = 0; /* byte offset is 0 */
#ifdef NOT_NEEDED
/* Read in 1 dummy character for length to inhibit SLI posting */
if (chan_read_byte(chsa, &buf[0])) {
/* we have error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
@ -954,13 +964,13 @@ t_stat disk_srv(UNIT *uptr)
/* just seek to the location where we will r/w data */
if ((sim_fseek(uptr->fileref, tstart, SEEK_SET)) != 0) { /* do seek */
sim_debug(DEBUG_EXP, dptr, "disk_srv Error on seek to %04x\n", tstart);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
return SCPE_OK;
}
/* we are on cylinder/track/sector zero, so go on */
sim_debug(DEBUG_DETAIL, dptr, "disk_srv done seek trk 0\n");
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_DEVEND|SNS_CHNEND);
return SCPE_OK;
#else
@ -975,28 +985,28 @@ t_stat disk_srv(UNIT *uptr)
/* Read in 1 character of mode data */
if (chan_read_byte(chsa, &buf[0])) {
/* we have error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->SNS |= SNS_CMDREJ|SNS_EQUCHK;
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
sim_debug(DEBUG_CMD, dptr, "Load Mode Reg unit=%02x old %x new %x\n",
unit, (uptr->SNS)&0xff, buf[0]);
uptr->CMDu3 &= LMASK; /* remove old cmd */
uptr->CMDu3 &= LMASK; /* remove old cmd */
uptr->SNS &= MASK24; /* clear old mode data */
uptr->SNS |= (buf[0] << 24); /* save mode value */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
break;
case DSK_RD: /* Read Data */
if ((uptr->CMDu3 & DSK_READING) == 0) { /* see if we are reading data */
uptr->CMDu3 |= DSK_READING; /* read from disk starting */
if ((uptr->CMDu3 & DSK_READING) == 0) { /* see if we are reading data */
uptr->CMDu3 |= DSK_READING; /* read from disk starting */
sim_debug(DEBUG_CMD, dptr,
"DISK READ starting CMD %08x chsa %04x buffer %06x count %04x\n",
uptr->CMDu3, chsa, chp->ccw_addr, chp->ccw_count);
}
if (uptr->CMDu3 & DSK_READING) { /* see if we are reading data */
if (uptr->CMDu3 & DSK_READING) { /* see if we are reading data */
cyl = STAR2CYL(uptr->CHS); /* get current cyl */
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
@ -1013,7 +1023,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"Error %08x on read %04x of diskfile cyl %04x hds %02x sec %02x\n",
len, ssize, cyl, trk, sec);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
@ -1029,7 +1039,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_DATA, dptr,
"DISK Read %04x bytes leaving %04x from diskfile /%04x/%02x/%02x\n",
i, chp->ccw_count, cyl, trk, sec);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND);
return SCPE_OK;
//XXX goto rddone;
@ -1061,9 +1071,10 @@ t_stat disk_srv(UNIT *uptr)
// if (tstart >= CAPB(type)) {
if (tstart >= (uint32)CAP(type)) {
/* EOM reached, abort */
sim_debug(DEBUG_CMD, dptr, "DISK Read reached EOM for read from disk @ /%04x/%02x/%02x\n",
sim_debug(DEBUG_CMD, dptr,
"DISK Read reached EOM for read from disk @ /%04x/%02x/%02x\n",
STAR2CYL(uptr->CHS), (uptr->CHS >> 8)&0xff, (uptr->CHS&0xff));
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CHS = 0; /* reset cylinder position */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
@ -1072,23 +1083,34 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_DATA, dptr,
"DISK sector read complete, %x bytes to go from diskfile /%04x/%02x/%02x\n",
chp->ccw_count, STAR2CYL(uptr->CHS), ((uptr->CHS) >> 8)&0xff, (uptr->CHS&0xff));
sim_activate(uptr, 10); /* wait to read next sector */
//@ sim_activate(uptr, 10); /* wait to read next sector */
sim_activate(uptr, 30); /* wait to read next sector */
break;
//XXXrddone:
//XXX uptr->CMDu3 &= ~(0xffff); /* remove old status bits & cmd */
//XXX uptr->CMDu3 &= ~(0xffff); /* remove old status bits & cmd */
}
break;
case DSK_WD: /* Write Data */
if ((uptr->CMDu3 & DSK_WRITING) == 0) { /* see if we are writing data */
uptr->CMDu3 |= DSK_WRITING; /* write to disk starting */
sim_debug(DEBUG_CMD, dptr,
"DISK WRITE starting unit=%02x CMD %02x\n", unit, uptr->CMDu3);
}
if (uptr->CMDu3 & DSK_WRITING) { /* see if we are writing data */
if ((uptr->CMDu3 & DSK_WRITING) == 0) { /* see if we are writing data */
cyl = STAR2CYL(uptr->CHS); /* get current cyl */
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
uptr->CMDu3 |= DSK_WRITING; /* write to disk starting */
sim_debug(DEBUG_CMD, dptr,
"DISK WRITE starting unit=%02x CMD %02x write %4x from %06x to %03x/%02x/%02x\n",
unit, uptr->CMDu3, chp->ccw_count, chp->ccw_addr, cyl, trk, sec);
}
if (uptr->CMDu3 & DSK_WRITING) { /* see if we are writing data */
cyl = STAR2CYL(uptr->CHS); /* get current cyl */
trk = (uptr->CHS >> 8) & 0xff; /* get trk/head */
sec = uptr->CHS & 0xff; /* get sec */
#ifdef DO_DYNAMIC_DEBUG
if (cyl == 10 && trk == 3 && sec == 0 &&
chp->ccw_count == 0x2000 && chp->ccw_addr == 0x1e7a40)
/* start debugging at test 46 of cn.mmm diag */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
#endif
/* get sector offset */
// tstart = STAR2SEC(uptr->STAR, SPT(type), SPC(type));
tstart = STAR2SEC(uptr->CHS, SPT(type), SPC(type));
@ -1096,10 +1118,10 @@ t_stat disk_srv(UNIT *uptr)
/* process the next sector of data */
len = 0; /* used here as a flag for short read */
for (i=0; i<ssize; i++) {
if (chan_read_byte(chsa, &ch)) { /* get a byte from memory */
if (chan_read_byte(chsa, &ch)) {/* get a byte from memory */
/* if error on reading 1st byte, we are done writing */
if (i == 0) {
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr,
"DISK Wrote %04x bytes to diskfile cyl %04x hds %02x sec %02x\n",
ssize, cyl, trk, sec);
@ -1118,7 +1140,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"Error %08x on write %04x bytes to diskfile cyl %04x hds %02x sec %02x\n",
i, ssize, cyl, trk, sec);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
@ -1126,7 +1148,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_DATA, dptr,
"DISK WroteB %04x bytes to diskfile cyl %04x hds %02x sec %02x\n",
ssize, cyl, trk, sec);
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
break;
}
@ -1145,15 +1167,14 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, dptr,
"DISK Write reached EOM for write to disk @ /%04x/%02x/%02x\n",
STAR2CYL(uptr->CHS), (uptr->CHS >> 8)&0xff, (uptr->CHS&0xff));
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CHS = 0; /* reset cylinder position */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
sim_activate(uptr, 10); /* keep writing */
//@ sim_activate(uptr, 10); /* keep writing */
sim_activate(uptr, 30); /* keep writing */
break;
//XXXwrdone:
//XXX uptr->CMDu3 &= ~(0xffff); /* remove old status bits & cmd */
}
break;
@ -1232,7 +1253,7 @@ t_stat disk_srv(UNIT *uptr)
for (i = 0; i < 30; i++) {
if (chan_write_byte(chsa, &buf[i])) {
/* we have write error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
@ -1243,7 +1264,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_DETAIL, dptr, "\n");
/* command done */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr, "hsdp_srv cmd RSL done chsa %04x count %04x completed\n",
chsa, chp->ccw_count);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
@ -1349,7 +1370,7 @@ t_stat disk_srv(UNIT *uptr)
for (i = 0; i < 30; i++) {
if (chan_write_byte(chsa, &buf[i])) {
/* we have write error, bail out */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
@ -1360,7 +1381,7 @@ t_stat disk_srv(UNIT *uptr)
sim_debug(DEBUG_DETAIL, dptr, "\n");
/* command done */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
sim_debug(DEBUG_CMD, dptr, "disk_srv cmd RTL done chsa %04x count %04x completed\n",
chsa, chp->ccw_count);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */
@ -1369,7 +1390,7 @@ t_stat disk_srv(UNIT *uptr)
default:
sim_debug(DEBUG_CMD, dptr, "invalid command %02x unit %02x\n", cmd, unit);
uptr->SNS |= SNS_CMDREJ;
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK);
break;
}
@ -1406,20 +1427,20 @@ t_stat disk_reset(DEVICE *dptr)
int disk_format(UNIT *uptr) {
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
uint32 ssize = disk_type[type].ssiz * 4; /* disk sector size in bytes */
uint32 tsize = disk_type[type].spt; /* get track size in sectors */
uint32 csize = disk_type[type].nhds * tsize; /* get cylinder size in sectors */
uint32 cyl = disk_type[type].cyl; /* get # cylinders */
uint32 cap = disk_type[type].cyl * csize; /* disk capacity in sectors */
uint32 cylv = cyl; /* number of cylinders */
uint32 ssize = disk_type[type].ssiz * 4; /* disk sector size in bytes */
uint32 tsize = disk_type[type].spt; /* get track size in sectors */
uint32 csize = disk_type[type].nhds * tsize; /* get cylinder size in sectors */
uint32 cyl = disk_type[type].cyl; /* get # cylinders */
uint32 cap = disk_type[type].cyl * csize; /* disk capacity in sectors */
uint32 cylv = cyl; /* number of cylinders */
uint8 *buff;
int i;
/* last sector address of disk (cyl * hds * spt) - 1 */
uint32 laddr = CAP(type) - 1; /* last sector of disk */
uint32 laddr = CAP(type) - 1; /* last sector of disk */
/* last track address of disk (cyl * hds * spt) - spt */
uint32 ltaddr = CAP(type)-SPT(type); /* last sector of disk */
uint32 ltaddr = CAP(type)-SPT(type); /* last sector of disk */
/* get sector address of vendor defect table VDT */
/* put data = 0xf0000000 0xf4000000 */
@ -1455,7 +1476,7 @@ int disk_format(UNIT *uptr) {
0,0x22c2813e,0,0x06020000,0xf4,0,0x431b1c,0,
};
#ifdef USEFORMPX
#ifdef USE_FOR_MPX
{
/* some values created by j.vfmt */
// 0xf003d14f,0x8a03cda0,0x9a03cdbf,0x8903cdc0,
@ -1530,7 +1551,7 @@ int disk_format(UNIT *uptr) {
if ((sim_fwrite(buff, 1, csize*ssize, uptr->fileref)) != csize*ssize) {
sim_debug(DEBUG_CMD, dptr,
"Error on write to diskfile cyl %04x\n", cyl);
free(buff); /* free cylinder buffer */
free(buff); /* free cylinder buffer */
buff = 0;
return 1;
}
@ -1545,7 +1566,7 @@ int disk_format(UNIT *uptr) {
}
fputc('\r', stderr);
fputc('\n', stderr);
free(buff); /* free cylinder buffer */
free(buff); /* free cylinder buffer */
buff = 0;
/* byte swap the buffers for dmap and umap */
@ -1664,29 +1685,29 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
int type = GET_TYPE(uptr->flags);
DEVICE *dptr = get_dev(uptr);
t_stat r;
uint32 ssize; /* sector size in bytes */
uint32 ssize; /* sector size in bytes */
uint8 buff[1024];
/* see if valid disk entry */
if (disk_type[type].name == 0) { /* does the assigned disk have a name */
detach_unit(uptr); /* no, reject */
return SCPE_FMT; /* error */
if (disk_type[type].name == 0) { /* does the assigned disk have a name */
detach_unit(uptr); /* no, reject */
return SCPE_FMT; /* error */
}
/* have simulator attach the file to the unit */
if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r;
uptr->capac = CAP(type); /* disk capacity in sectors */
ssize = SSB(type); /* get sector size in bytes */
uptr->capac = CAP(type); /* disk capacity in sectors */
ssize = SSB(type); /* get sector size in bytes */
sim_debug(DEBUG_CMD, dptr, "Disk %s cyl %d hds %d sec %d ssiz %d capacity %d\n",
disk_type[type].name, disk_type[type].cyl, disk_type[type].nhds,
disk_type[type].spt, ssize, uptr->capac); /* disk capacity */
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
detach_unit(uptr); /* if no space, error */
return SCPE_FMT; /* error */
detach_unit(uptr); /* if no space, error */
return SCPE_FMT; /* error */
}
/* see if there is any data on sector zero of disk, if not format it */
@ -1702,19 +1723,19 @@ t_stat disk_attach(UNIT *uptr, CONST char *file)
fmt:
/* format the drive */
if (disk_format(uptr)) {
detach_unit(uptr); /* if no space, error */
return SCPE_FMT; /* error */
detach_unit(uptr); /* if no space, error */
return SCPE_FMT; /* error */
}
}
/* there is data on sector 0, so already formatted */
if ((sim_fseek(uptr->fileref, 0, SEEK_SET)) != 0) { /* seek home */
detach_unit(uptr); /* detach if error */
return SCPE_FMT; /* error */
detach_unit(uptr); /* detach if error */
return SCPE_FMT; /* error */
}
/* start out at sector 0 */
uptr->CHS = 0; /* set CHS to cyl/hd/sec = 0 */
uptr->CHS = 0; /* set CHS to cyl/hd/sec = 0 */
sim_debug(DEBUG_CMD, dptr,
"Attach %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\n",
@ -1730,27 +1751,27 @@ fmt:
/* detach a disk device */
t_stat disk_detach(UNIT *uptr) {
uptr->SNS = 0; /* clear sense data */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
return detach_unit(uptr); /* tell simh we are done with disk */
uptr->SNS = 0; /* clear sense data */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
return detach_unit(uptr); /* tell simh we are done with disk */
}
/* boot from the specified disk unit */
t_stat disk_boot(int32 unit_num, DEVICE *dptr) {
UNIT *uptr = &dptr->units[unit_num]; /* find disk unit number */
UNIT *uptr = &dptr->units[unit_num]; /* find disk unit number */
sim_debug(DEBUG_CMD, dptr, "Disk Boot dev/unit %x\n", GET_UADDR(uptr->CMDu3));
if ((uptr->flags & UNIT_ATT) == 0) {
sim_debug(DEBUG_EXP, &mta_dev, "Disk Boot attach error dev/unit %04x\n",
GET_UADDR(uptr->CMDu3));
return SCPE_UNATT; /* attached? */
return SCPE_UNATT; /* attached? */
}
SPAD[0xf4] = GET_UADDR(uptr->CMDu3); /* put boot device chan/sa into spad */
SPAD[0xf8] = 0xF000; /* show as F class device */
SPAD[0xf4] = GET_UADDR(uptr->CMDu3); /* put boot device chan/sa into spad */
SPAD[0xf8] = 0xF000; /* show as F class device */
/* now boot the disk */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
uptr->CMDu3 &= LMASK; /* remove old status bits & cmd */
return chan_boot(GET_UADDR(uptr->CMDu3), dptr); /* boot the ch/sa */
}
@ -1760,18 +1781,18 @@ t_stat disk_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
int i;
if (cptr == NULL) /* any disk name input? */
return SCPE_ARG; /* arg error */
if (uptr == NULL) /* valid unit? */
return SCPE_IERR; /* no, error */
if (uptr->flags & UNIT_ATT) /* is unit attached? */
return SCPE_ALATT; /* no, error */
if (cptr == NULL) /* any disk name input? */
return SCPE_ARG; /* arg error */
if (uptr == NULL) /* valid unit? */
return SCPE_IERR; /* no, error */
if (uptr->flags & UNIT_ATT) /* is unit attached? */
return SCPE_ALATT; /* no, error */
/* now loop through the units and find named disk */
for (i = 0; disk_type[i].name != 0; i++) {
if (strcmp(disk_type[i].name, cptr) == 0) {
uptr->flags &= ~UNIT_TYPE; /* clear the old UNIT type */
uptr->flags |= SET_TYPE(i); /* set the new type */
uptr->flags &= ~UNIT_TYPE; /* clear the old UNIT type */
uptr->flags |= SET_TYPE(i); /* set the new type */
/* set capacity of disk in sectors */
uptr->capac = CAP(i);
return SCPE_OK;

14
SEL32/sel32_iop.c
View File

@ -93,7 +93,7 @@ MTAB iop_mod[] = {
};
UNIT iop_unit[] = {
{UDATA(&iop_srv, UNIT_IDLE, 0), 0, UNIT_ADDR(0x7E00)}, /* Channel controller */
{UDATA(&iop_srv, UNIT_IDLE|UNIT_DISABLE, 0), 0, UNIT_ADDR(0x7E00)}, /* Channel controller */
};
//DIB iop_dib = {NULL, iop_startcmd, NULL, NULL, NULL, iop_ini, iop_unit, iop_chp, NUM_UNITS_IOP, 0xff, 0x7e00,0,0,0};
@ -163,7 +163,8 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
// set_inch(uptr, iop_chp[0].ccw_addr); /* new address */
uptr->u3 |= IOP_INCH2; /* save INCH command as 0xf0 */
sim_activate(uptr, 20); /* go on */
//@ sim_activate(uptr, 20); /* go on */
sim_activate(uptr, 40); /* go on */
return 0; /* no status change */
break;
@ -172,7 +173,8 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save NOP command */
sim_activate(uptr, 20); /* TRY 07-13-19 */
//@ sim_activate(uptr, 20); /* TRY 07-13-19 */
sim_activate(uptr, 40); /* TRY 07-13-19 */
return 0; /* no status change */
break;
@ -182,8 +184,10 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
chan, cmd, uptr->u5);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save command */
sim_activate(uptr, 20); /* force interrupt */
return 0; /* no status change */
//@ sim_activate(uptr, 20); /* force interrupt */
/*UTX*/ sim_activate(uptr, 40); /* force interrupt */
//UTX return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* not a valid cmd */
/*UTX*/ return 0; /* no status change */
break;
}

14
SEL32/sel32_mfp.c
View File

@ -94,7 +94,7 @@ MTAB mfp_mod[] = {
};
UNIT mfp_unit[] = {
{UDATA(&mfp_srv, UNIT_IDLE, 0), 0, UNIT_ADDR(0x7600)}, /* Channel controller */
{UDATA(&mfp_srv, UNIT_IDLE|UNIT_DISABLE, 0), 0, UNIT_ADDR(0x7600)}, /* Channel controller */
};
//DIB mfp_dib = {NULL, mfp_startcmd, NULL, NULL, NULL, mfp_ini, mfp_unit, mfp_chp, NUM_UNITS_MFP, 0xff, 0x7e00,0,0,0};
@ -164,7 +164,8 @@ uint8 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
// set_inch(uptr, mfp_chp[0].ccw_addr); /* new address */
uptr->u3 |= MFP_INCH2; /* save INCH command as 0xf0 */
sim_activate(uptr, 20); /* go on */
//@ sim_activate(uptr, 20); /* go on */
sim_activate(uptr, 40); /* go on */
return 0; /* no status change */
break;
@ -173,7 +174,8 @@ uint8 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & MFP_MSK); /* save NOP command */
sim_activate(uptr, 20); /* TRY 07-13-19 */
//@ sim_activate(uptr, 20); /* TRY 07-13-19 */
sim_activate(uptr, 40); /* TRY 07-13-19 */
return 0; /* no status change */
break;
@ -183,8 +185,10 @@ uint8 mfp_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
chan, cmd, uptr->u5);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & MFP_MSK); /* save command */
sim_activate(uptr, 20); /* force interrupt */
return 0; /* no status change */
//@ sim_activate(uptr, 20); /* force interrupt */
//@ sim_activate(uptr, 40); /* force interrupt */
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* not a valid command */
//WAS return 0; /* no status change */
break;
}

120
SEL32/sel32_mt.c
View File

@ -400,7 +400,15 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
/* UTX_needs_interrupt on NOP or INCH */
/* fall through */
case 0x01: /* Write command */
if (cmd == 0x01)
sim_debug(DEBUG_EXP, &mta_dev,
"mt_startcmd WRITE chan %04x addr %06x cnt %04x\n",
chan, chp->ccw_addr, chp->ccw_count);
case 0x02: /* Read command */
if (cmd == 0x02)
sim_debug(DEBUG_EXP, &mta_dev,
"mt_startcmd READ chan %04x addr %06x cnt %04x\n",
chan, chp->ccw_addr, chp->ccw_count);
case 0x0C: /* Read backward */
if (cmd != 0x03) /* if this is a nop do not zero status */
uptr->SNS = (uptr->SNS & 0x0000ff00); /* clear all but byte 2 */
@ -414,15 +422,13 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
uptr->SNS |= (SNS_EOT); /* tape at EOM */
/* Fall through */
case 0x4: /* Sense */
#ifndef FIX_DIAG
case 0x04: /* Sense */
case 0x80: /* Unknown diag cmd with byte cnt of 0x0c */
#ifdef DO_DYNAMIC_DEBUG
if ((cmd & 0xff) == 0x80) {
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ);
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP | DEBUG_IRQ | DEBUG_TRAP);
}
#endif
#endif
uptr->CMD &= ~(MT_CMDMSK); /* clear out last cmd */
uptr->CMD |= cmd & MT_CMDMSK; /* insert new cmd */
@ -431,7 +437,8 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
mt_busy[GET_DEV_BUF(dptr->flags)] = 1; /* show we are busy */
sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd sense %08x return 0 chan %04x cmd %02x\n",
uptr->SNS, chan, cmd);
sim_activate(uptr, 100); /* Start unit off */
//@ sim_activate(uptr, 100); /* Start unit off */
sim_activate(uptr, 150); /* Start unit off */
return 0;
default: /* invalid command */
@ -558,7 +565,7 @@ t_stat mt_srv(UNIT *uptr)
}
/* just dump data */
}
#ifdef CHANGE_FOR_UTX_TEST
#ifdef CHANGE_FOR_UTX_BTP_TEST
/* a BTP uses a 41 word INCH memory buffer */
// for (i=0; i<41; i++) {
for (i=0; i<9; i++) {
@ -577,7 +584,7 @@ t_stat mt_srv(UNIT *uptr)
/* call set_inch() to setup inch buffer */
i = set_inch(uptr, mema); /* new address */
#ifndef NOTYET
#ifdef NOTYET
if ((i == SCPE_MEM) || (i == SCPE_ARG)) { /* any error */
/* we have error, bail out */
uptr->CMD &= ~(0xffff); /* remove old status bits & cmd */
@ -614,13 +621,15 @@ t_stat mt_srv(UNIT *uptr)
ch = (uptr->SNS >> 0) & 0xff; /* get sense byte 3 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 3 %02x\n", unit, ch);
chan_write_byte(addr, &ch); /* write byte 3 */
#ifdef TRYTHIS
#ifndef NO_HARDWARE_STATUS_FOR_DIAGS
/* write zero extra status */
for (ch=4; ch < 0xc; ch++) {
uint8 zc = 0;
chan_write_byte(addr, &zc); /* write zero byte */
sim_debug(DEBUG_CMD, &mta_dev,
"sense unit %02x byte %1x %02x\n", unit, ch, zc);
}
#else
#else /* FOR UTX */
/* write status 2 more times */
ch = (uptr->SNS >> 24) & 0xff; /* get sense byte 0 status */
sim_debug(DEBUG_CMD, &mta_dev, "sense unit %02x byte 0 %02x\n", unit, ch);
@ -684,12 +693,13 @@ t_stat mt_srv(UNIT *uptr)
break;
case MT_READ: /* 0x02 */ /* read a record from the device */
sim_debug(DEBUG_DATA, &mta_dev, "mt_srv cmd 2 READ unit=%02x\n", unit);
sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv cmd 2 READ unit=%02x\n", unit);
if (uptr->CMD & MT_READDONE) { /* is the read complete */
uptr->SNS &= ~(SNS_LOAD|SNS_EOT); /* reset BOT & EOT */
if (sim_tape_eot(uptr)) { /* see if at EOM */
uptr->SNS |= SNS_EOT; /* set EOT status */
}
uptr->CMD &= ~(MT_CMDMSK|MT_READDONE); /* clear all but readdone & cmd */
uptr->CMD &= ~MT_CMDMSK; /* clear the cmd */
mt_busy[bufnum] &= ~1; /* not busy anymore */
@ -718,14 +728,17 @@ t_stat mt_srv(UNIT *uptr)
/* Send character over to channel */
if (chan_write_byte(addr, &ch)) {
sim_debug(DEBUG_CMD, &mta_dev, "Read unit %02x EOR cnt %04x\n", unit, uptr->POS);
sim_debug(DEBUG_CMD, &mta_dev,
"Read unit %02x EOR cnt %04x hwm %04x\n", unit, uptr->POS, uptr->hwmark);
/* If not read whole record, skip till end */
if ((uint32)uptr->POS < uptr->hwmark) {
/* Send dummy character to force SLI */
chan_write_byte(addr, &ch); /* write the byte */
sim_debug(DEBUG_CMD, &mta_dev, "Read unit %02x send dump SLI\n", unit);
//@ sim_activate(uptr, (uptr->hwmark-uptr->POS) * 10); /* wait again */
sim_activate(uptr, (uptr->hwmark-uptr->POS) * 10); /* wait again */
uptr->CMD |= MT_READDONE; /* read is done */
//NEW uptr->POS -= 1; /* uncount dummy char */
break;
}
sim_debug(DEBUG_CMD, &mta_dev,
@ -735,9 +748,9 @@ t_stat mt_srv(UNIT *uptr)
mt_busy[bufnum] &= ~1; /* set not busy */
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* return end status */
} else {
sim_debug(DEBUG_DATA, &mta_dev,
sim_debug(DEBUG_DETAIL, &mta_dev,
"Read data @2 unit %02x cnt %04x ch %02x hwm %04x\n", unit, uptr->POS, ch,
uptr->hwmark);
uptr->hwmark);
if ((uint32)uptr->POS >= uptr->hwmark) { /* In IRG */
/* Handle end of data record */
sim_debug(DEBUG_CMD, &mta_dev,
@ -749,10 +762,12 @@ t_stat mt_srv(UNIT *uptr)
chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* return end status */
#else
uptr->CMD |= MT_READDONE; /* read is done */
sim_activate(uptr, 20); /* wait again */
//@ sim_activate(uptr, 20); /* wait again */
sim_activate(uptr, 40); /* wait again */
#endif
} else
sim_activate(uptr, 20); /* wait again */
//@ sim_activate(uptr, 20); /* wait again */
sim_activate(uptr, 40); /* wait again */
}
break;
@ -777,7 +792,8 @@ t_stat mt_srv(UNIT *uptr)
sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x ch %02x\n",
unit, uptr->POS, ch);
uptr->hwmark = uptr->POS; /* set high water mark */
sim_activate(uptr, 20); /* wait time */
//@ sim_activate(uptr, 20); /* wait time */
sim_activate(uptr, 40); /* wait again */
}
break;
@ -805,11 +821,12 @@ t_stat mt_srv(UNIT *uptr)
}
} else {
mt_buffer[bufnum][uptr->POS++] = ch;
sim_debug(DEBUG_DATA, &mta_dev, "Write data unit=%02x %04x %02x\n",
sim_debug(DEBUG_DETAIL, &mta_dev, "Write data unit=%02x %04x %02x\n",
unit, uptr->POS, ch);
uptr->hwmark = uptr->POS;
}
sim_activate(uptr, 20);
//@ sim_activate(uptr, 20);
sim_activate(uptr, 40);
break;
case MT_RDBK: /* 0x0C */ /* Read Backwards */
@ -843,24 +860,26 @@ t_stat mt_srv(UNIT *uptr)
if (chan_write_byte(addr, &ch)) {
sim_debug(DEBUG_CMD, &mta_dev, "Read unit=%02x EOR cnt %04x\n",
unit, uptr->POS);
/* If not read whole record, skip till end */
if (uptr->POS >= 0) {
sim_activate(uptr, (uptr->POS) * 20);
uptr->CMD |= MT_READDONE;
return SCPE_OK;
}
uptr->CMD &= ~MT_CMDMSK;
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
/* If not read whole record, skip till end */
if (uptr->POS >= 0) {
//@ sim_activate(uptr, (uptr->POS) * 20);
sim_activate(uptr, (uptr->POS) * 20);
uptr->CMD |= MT_READDONE;
return SCPE_OK;
}
uptr->CMD &= ~MT_CMDMSK;
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
} else {
sim_debug(DEBUG_DATA, &mta_dev, "Read data unit=%02x %04x %02x\n",
sim_debug(DEBUG_DETAIL, &mta_dev, "Read data unit=%02x %04x %02x\n",
unit, uptr->POS, ch);
if (uptr->POS == 0) { /* In IRG */
uptr->CMD &= ~MT_CMDMSK;
mt_busy[bufnum] &= ~1;
chan_end(addr, SNS_CHNEND|SNS_DEVEND);
} else
sim_activate(uptr, 20);
//@ sim_activate(uptr, 20);
sim_activate(uptr, 40);
}
break;
@ -896,7 +915,8 @@ t_stat mt_srv(UNIT *uptr)
return SCPE_OK;
}
uptr->POS++;
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
break;
case 1:
uptr->POS++;
@ -907,10 +927,12 @@ t_stat mt_srv(UNIT *uptr)
if (r == MTSE_TMK) {
uptr->POS++;
sim_debug(DEBUG_CMD, &mta_dev, "MARK\n");
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "Backspace reclen %04x\n", reclen);
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
}
break;
case 2:
@ -945,12 +967,15 @@ t_stat mt_srv(UNIT *uptr)
if (r == MTSE_TMK) {
uptr->POS++;
sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n");
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else if (r == MTSE_BOT) {
uptr->POS+= 2;
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else {
sim_activate(uptr, 20);
//@ sim_activate(uptr, 20);
sim_activate(uptr, 80);
}
break;
case 2: /* File Mark */
@ -971,7 +996,8 @@ t_stat mt_srv(UNIT *uptr)
case 0:
sim_debug(DEBUG_CMD, &mta_dev, "Skip rec entry unit=%02x ", unit);
uptr->POS++;
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
break;
case 1:
uptr->POS++;
@ -981,14 +1007,17 @@ t_stat mt_srv(UNIT *uptr)
uptr->POS = 3;
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
sim_debug(DEBUG_CMD, &mta_dev, "FSR MARK\n");
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else if (r == MTSE_EOM) {
uptr->POS = 4;
uptr->SNS |= SNS_EOT; /* set EOT status */
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "FSR skipped %04x byte record\n",
reclen);
//@ sim_activate(uptr, 10 + (10 * reclen));
sim_activate(uptr, 10 + (10 * reclen));
}
break;
@ -1019,7 +1048,8 @@ t_stat mt_srv(UNIT *uptr)
case 0:
sim_debug(DEBUG_CMD, &mta_dev, "Skip file entry sense %08x unit %02x\n", uptr->SNS, unit);
uptr->POS++;
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
break;
case 1:
sim_debug(DEBUG_CMD, &mta_dev, "Skip file unit=%02x\n", unit);
@ -1028,15 +1058,18 @@ t_stat mt_srv(UNIT *uptr)
uptr->POS++;
uptr->SNS |= SNS_FMRKDT; /* file mark detected */
sim_debug(DEBUG_CMD, &mta_dev, "FSF EOF MARK sense %08x\n", uptr->SNS);
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else if (r == MTSE_EOM) {
uptr->SNS |= SNS_EOT; /* set EOT status */
sim_debug(DEBUG_CMD, &mta_dev, "FSF EOT sense %08x\n", uptr->SNS);
uptr->POS+= 2;
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
} else {
sim_debug(DEBUG_CMD, &mta_dev, "FSF skipped %04x byte record\n", reclen);
sim_activate(uptr, 50);
//@ sim_activate(uptr, 50);
sim_activate(uptr, 80);
}
break;
case 2:
@ -1068,7 +1101,8 @@ t_stat mt_srv(UNIT *uptr)
chan_end(addr, SNS_DEVEND|SNS_UNITEXP);
} else {
uptr->POS ++;
sim_activate(uptr, 500);
//@ sim_activate(uptr, 500);
sim_activate(uptr, 200);
}
break;
case 1:

34
SEL32/sel32_scsi.c
View File

@ -244,7 +244,7 @@ t_stat scsi_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *c
const char *scsi_description (DEVICE *dptr);
/* channel program information */
CHANP sda_chp[NUM_UNITS_SCSI] = {0};
CHANP sca_chp[NUM_UNITS_SCSI] = {0};
MTAB scsi_mod[] = {
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "TYPE", "TYPE",
@ -254,7 +254,7 @@ MTAB scsi_mod[] = {
{0}
};
UNIT sda_unit[] = {
UNIT sca_unit[] = {
/* SET_TYPE(2) SG120 */
{UDATA(&scsi_srv, UNIT_SCSI|SET_TYPE(2), 0), 0, UNIT_ADDR(0x400)}, /* 0 */
{UDATA(&scsi_srv, UNIT_SCSI|SET_TYPE(2), 0), 0, UNIT_ADDR(0x410)}, /* 1 */
@ -266,17 +266,17 @@ UNIT sda_unit[] = {
{UDATA(&scsi_srv, UNIT_SCSI|SET_TYPE(2), 0), 0, UNIT_ADDR(0x470)}, /* 7 */
};
//DIB sda_dib = {scsi_preio, scsi_startcmd, NULL, NULL, NULL, scsi_ini, sda_unit, sda_chp, NUM_UNITS_SCSI, 0x0f, 0x0400, 0, 0, 0};
//DIB sca_dib = {scsi_preio, scsi_startcmd, NULL, NULL, NULL, scsi_ini, sca_unit, sca_chp, NUM_UNITS_SCSI, 0x0f, 0x0400, 0, 0, 0};
DIB sda_dib = {
DIB sca_dib = {
scsi_preio, /* uint8 (*pre_io)(UNIT *uptr, uint16 chan)*/ /* Pre Start I/O */
scsi_startcmd, /* uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd)*/ /* Start a command */
NULL, /* uint8 (*halt_io)(UNIT *uptr) */ /* Stop I/O */
NULL, /* uint8 (*test_io)(UNIT *uptr) */ /* Test I/O */
NULL, /* uint8 (*post_io)(UNIT *uptr) */ /* Post I/O */
scsi_ini, /* void (*dev_ini)(UNIT *, t_bool) */ /* init function */
sda_unit, /* UNIT* units */ /* Pointer to units structure */
sda_chp, /* CHANP* chan_prg */ /* Pointer to chan_prg structure */
sca_unit, /* UNIT* units */ /* Pointer to units structure */
sca_chp, /* CHANP* chan_prg */ /* Pointer to chan_prg structure */
NUM_UNITS_SCSI, /* uint8 numunits */ /* number of units defined */
0xF0, /* uint8 mask */ /* 16 devices - device mask */
0x0400, /* uint16 chan_addr */ /* parent channel address */
@ -285,12 +285,12 @@ DIB sda_dib = {
{0} /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
};
DEVICE sda_dev = {
"SDA", sda_unit, NULL, scsi_mod,
DEVICE sca_dev = {
"SCA", sca_unit, NULL, scsi_mod,
NUM_UNITS_SCSI, 16, 24, 4, 16, 32,
NULL, NULL, &scsi_reset, &scsi_boot, &scsi_attach, &scsi_detach,
/* ctxt is the DIB pointer */
&sda_dib, DEV_DISABLE|DEV_DEBUG|DEV_DIS, 0, dev_debug,
&sca_dib, DEV_DISABLE|DEV_DEBUG|DEV_DIS, 0, dev_debug,
NULL, NULL, &scsi_help, NULL, NULL, &scsi_description
};
@ -330,7 +330,7 @@ DIB sdb_dib = {
};
DEVICE sdb_dev = {
"SDB", sdb_unit, NULL, scsi_mod,
"SCB", sdb_unit, NULL, scsi_mod,
NUM_UNITS_SCSI, 16, 24, 4, 16, 32,
NULL, NULL, &scsi_reset, &scsi_boot, &scsi_attach, &scsi_detach,
/* ctxt is the DIB pointer */
@ -458,7 +458,7 @@ t_stat scsi_srv(UNIT *uptr)
uint8 buf2[1024];
uint8 buf[1024];
sim_debug(DEBUG_DETAIL, &sda_dev,
sim_debug(DEBUG_DETAIL, &sca_dev,
"scsi_srv entry unit %02x CMD %08x chsa %04x count %04x %x/%x/%x \n",
unit, uptr->CMD, chsa, chp->ccw_count,
STAR2CYL(uptr->CHS), (uptr->CHS >> 8)&0xff, (uptr->CHS&0xff));
@ -917,7 +917,7 @@ void scsi_ini(UNIT *uptr, t_bool f)
/* total sectors on disk */
uptr->capac = CAP(i); /* disk size in sectors */
sim_debug(DEBUG_EXP, &sda_dev, "SDA init device %s on unit SDA%.1x cap %x\n",
sim_debug(DEBUG_EXP, &sca_dev, "SCA init device %s on unit SCA%.1x cap %x\n",
dptr->name, GET_UADDR(uptr->CMD), uptr->CMD);
}
@ -1022,12 +1022,12 @@ t_stat scsi_attach(UNIT *uptr, CONST char *file) {
/* read in the 1st sector of the 'disk' */
if ((r = sim_fread(&buff[0], sizeof(uint8), ssize, uptr->fileref) != ssize)) {
sim_debug(DEBUG_CMD, &sda_dev, "Disk format fread ret = %04x\n", r);
sim_debug(DEBUG_CMD, &sca_dev, "Disk format fread ret = %04x\n", r);
goto fmt;
}
if ((buff[0] | buff[1] | buff[2] | buff[3]) == 0) {
sim_debug(DEBUG_CMD, &sda_dev,
sim_debug(DEBUG_CMD, &sca_dev,
"Disk format buf0 %02x buf1 %02x buf2 %02x buf3 %02x\n",
buff[0], buff[1], buff[2], buff[3]);
fmt:
@ -1045,12 +1045,12 @@ fmt:
uptr->CHS = 0; /* set CHS to cyl/hd/sec = 0 */
sim_debug(DEBUG_CMD, &sda_dev,
sim_debug(DEBUG_CMD, &sca_dev,
"Attach %s cyl %d hds %d spt %d spc %d cap sec %d cap bytes %d\n",
scsi_type[type].name, CYL(type), HDS(type), SPT(type), SPC(type),
CAP(type), CAPB(type));
sim_debug(DEBUG_CMD, &sda_dev, "File %s attached to %s\r\n",
sim_debug(DEBUG_CMD, &sca_dev, "File %s attached to %s\r\n",
file, scsi_type[type].name);
set_devattn(addr, SNS_DEVEND);
@ -1068,7 +1068,7 @@ t_stat scsi_detach(UNIT *uptr) {
t_stat scsi_boot(int32 unit_num, DEVICE *dptr) {
UNIT *uptr = &dptr->units[unit_num]; /* find disk unit number */
sim_debug(DEBUG_CMD, &sda_dev, "SCSI Disk Boot dev/unit %04x\n", GET_UADDR(uptr->CMD));
sim_debug(DEBUG_CMD, &sca_dev, "SCSI Disk Boot dev/unit %04x\n", GET_UADDR(uptr->CMD));
SPAD[0xf4] = GET_UADDR(uptr->CMD); /* put boot device chan/sa into spad */
SPAD[0xf8] = 0xF000; /* show as F class device */
if ((uptr->flags & UNIT_ATT) == 0)

3
SEL32/sel32_sys.c
View File

@ -662,7 +662,8 @@ t_opcode optab[] = {
{ 0x2C0E, 0xFC0F, H|TYPE_F, "TRSC", }, /* Transfer Register to Scratchpad # * */
{ 0x2C0F, 0xFC0F, H|TYPE_F, "TSCR", }, /* Transfer Scratchpad to Register # * */
{ 0x3000, 0xFC0F, X|H|TYPE_F, "CALM", }, /* Call Monitor 32/55 # */
{ 0x3400, 0xFC08, N|TYPE_D, "LA", }, /* Load Address NBR Note! FW instruction */
//FF{ 0x3400, 0xFC08, N|TYPE_D, "LA", }, /* Load Address NBR Note! FW instruction */
{ 0x3400, 0xFC00, N|TYPE_D, "LA", }, /* Load Address NBR Note! FW instruction */
{ 0x3800, 0xFC0F, H|TYPE_F, "ADR", }, /* Add Register to Register # */
{ 0x3801, 0xFC0F, H|TYPE_F, "ADRFW", }, /* Add Floating Point to Register # */
{ 0x3802, 0xFC0F, B|H|TYPE_F, "MPR", }, /* Multiply Register BR # */