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I7000: Fixes to allow IBM 704 Fortran II to work.

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This commit is contained in:
Richard Cornwell 2018-05-21 14:55:38 -04:00
parent db232ee122
commit 987f7c912a
6 changed files with 22 additions and 19 deletions
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2
I7000/i7000_chan.c
View File

@ -481,7 +481,7 @@ void
chan_clear_status(int chan)
{
chan_flags[chan] &=
~(CHS_ATTN | CHS_EOT | CHS_BOT | DEV_REOR | DEV_WEOR);
~(CHS_ATTN | CHS_EOT | CHS_BOT | CHS_EOF | DEV_REOR | DEV_WEOR);
}
void

11
I7000/i7000_mt.c
View File

@ -510,7 +510,7 @@ uint32 mt_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
return SCPE_IOERR;
}
uptr->u5 |= MT_WEF;
#if I7010
#if I7010
chan_set_sel(chan, 1);
chan_clear_status(chan);
mt_chan[chan] = MTC_BSY | MTC_SEL | unit;
@ -743,7 +743,7 @@ t_stat mt_srv(UNIT * uptr)
/* Channel has disconnected, abort current read. */
if ((mt_chan[chan] & 037) == (MTC_SEL | unit) &&
chan_stat(chan, DEV_DISCO)) {
chan_test(chan, DEV_DISCO)) {
uptr->u5 &= ~MT_CMDMSK;
reclen = uptr->hwmark;
if (cmd == MT_WRS || cmd == MT_WRSB) {
@ -811,7 +811,7 @@ t_stat mt_srv(UNIT * uptr)
#else
chan_clear(chan, DEV_SEL|STA_TWAIT);
#endif
mt_chan[chan] = 0;
mt_chan[chan] = 0;
sim_debug(DEBUG_DETAIL, dptr, "Skip unit=%d\n", unit);
/* Allow time for tape to be restarted, before stop */
sim_activate(uptr, us_to_ticks(500));
@ -879,6 +879,7 @@ t_stat mt_srv(UNIT * uptr)
chan_set_error(chan);
}
#else
chan_set(chan, DEV_REOR);
chan_set_attn(chan);
#endif
}
@ -891,7 +892,7 @@ t_stat mt_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, dptr, "%s Block %d chars\n",
(cmd == MT_RDS) ? "BCD" : "Binary", reclen);
#ifdef I7010
if (mode && mt_buffer[bufnum][0] == 017)
if (mode && mt_buffer[bufnum][0] == 017)
chan_set_eof(chan);
#endif
@ -944,7 +945,7 @@ t_stat mt_srv(UNIT * uptr)
sim_activate(uptr, (uptr->hwmark-uptr->u6) * T1_us);
uptr->u3 += (uptr->hwmark - uptr->u6);
uptr->u6 = uptr->hwmark; /* Force read next record */
}
}
sim_activate(uptr, T1_us);
break;

10
I7000/i7090_chan.c
View File

@ -344,10 +344,6 @@ chan_proc()
cmask = 0x0100 << chan;
switch (CHAN_G_TYPE(chan_unit[chan].flags)) {
case CHAN_PIO:
if (chan_flags[chan] & CHS_ATTN) {
chan_flags[chan] &=
~(CHS_ATTN | STA_START | STA_ACTIVE | STA_WAIT);
}
if ((chan_flags[chan] & (DEV_REOR|DEV_SEL|DEV_FULL)) ==
(DEV_SEL|DEV_REOR)) {
sim_debug(DEBUG_DETAIL, &chan_dev, "chan got EOR\n");
@ -1266,8 +1262,10 @@ chan_cmd(uint16 dev, uint16 dcmd)
if ((chan_flags[chan] & (DEV_FULL|DEV_WRITE)) == (DEV_FULL|DEV_WRITE))
return SCPE_BUSY;
/* Yes, disconnect device and tell it to write a EOR */
chan_flags[chan] |= DEV_DISCO | DEV_WEOR;
return SCPE_BUSY;
if ((chan_flags[chan] & (DEV_WRITE)) == (DEV_WRITE) ||
(chan_flags[chan] & (DEV_FULL)) == (DEV_FULL))
chan_flags[chan] |= DEV_DISCO | DEV_WEOR;
return SCPE_BUSY;
}
/* Unit is busy doing something, wait */
if (chan_flags[chan] & (DEV_SEL | DEV_DISCO | STA_TWAIT | STA_WAIT))

14
I7000/i7090_cpu.c
View File

@ -187,7 +187,7 @@
#define HIST_INT 2 /* interrupt cycle */
#define HIST_TRP 3 /* trap cycle */
#define HIST_MIN 64
#define HIST_MAX 10000
#define HIST_MAX 1000000
#define HIST_NOEA 0x40000000
#define HIST_PC 0x10000
@ -299,8 +299,13 @@ extern uint32 drum_addr;
*/
UNIT cpu_unit =
#ifdef I7090
{ UDATA(rtc_srv, UNIT_BINK | MODEL(CPU_7090) | MEMAMOUNT(4),
MAXMEMSIZE/2 ), 120 };
#else
{ UDATA(rtc_srv, UNIT_BINK | MODEL(CPU_704) | MEMAMOUNT(4),
MAXMEMSIZE/2 ), 120 };
#endif
REG cpu_reg[] = {
{ORDATAD(IC, IC, 15, "Instruction Counter"), REG_FIT},
@ -734,7 +739,7 @@ sim_instr(void)
/* Set cycle time for delays */
switch(CPU_MODEL) {
case CPU_704:
case CPU_704: cycle_time = 50; break; /* Needed to allow SAP to work */
case CPU_709: cycle_time = 120; break; /* 83,333 cycles per second */
default:
case CPU_7090: cycle_time = 22; break; /* 454,545 cycles per second */
@ -808,7 +813,7 @@ sim_instr(void)
/* Check if we need to take any traps */
#ifdef I7090 /* I704 did not have interrupts */
if (itrap && ihold == 0 && iowait == 0 && ioflags != 0) {
if (CPU_MODEL != CPU_704 && itrap && ihold == 0 && iowait == 0 && ioflags != 0) {
t_uint64 mask = 00000001000001LL;
MA = 012;
@ -3246,10 +3251,9 @@ prottrap:
case OP_LDA:
if (chan_select(0)) {
extern DEVICE drm_dev;
drum_addr = (uint32)(MQ = SR);
drum_addr = (uint32)(SR);
sim_debug(DEBUG_DETAIL, &drm_dev,
"set address %06o\n", drum_addr);
MQ <<= 1;
chan_clear(0, DEV_FULL); /* In case we read something
before we got here */
} else

2
I7000/i7090_drum.c
View File

@ -109,7 +109,7 @@ uint32 drm_cmd(UNIT * uptr, uint16 cmd, uint16 dev)
/* Choose which part to use */
uptr->u5 |= u << DRMSTA_UNITSHIFT;
drum_addr = 0; /* Set drum address */
chan_clear(chan, CHS_ATTN); /* Clear attentions */
chan_clear_status(chan);
/* Make sure drum is spinning */
sim_activate(uptr, us_to_ticks(100));
return SCPE_OK;

2
I7000/i7090_sys.c
View File

@ -110,7 +110,7 @@ DEVICE *sim_devices[] = {
/* Device addressing words */
#ifdef NUM_DEVS_DR
DIB drm_dib = { CH_TYP_PIO, 1, 0301, 0740, &drm_cmd, &drm_ini };
DIB drm_dib = { CH_TYP_PIO, 1, 0301, 0760, &drm_cmd, &drm_ini };
#endif
#ifdef NUM_DEVS_CDP
DIB cdp_dib = { CH_TYP_PIO|CH_TYP_76XX, 1, 0341, 0777, &cdp_cmd, &cdp_ini };