diff --git a/SEL32/sel32_chan.c b/SEL32/sel32_chan.c index d4f4ac9..7fcdc1c 100644 --- a/SEL32/sel32_chan.c +++ b/SEL32/sel32_chan.c @@ -246,13 +246,15 @@ t_stat set_inch(UNIT *uptr, uint32 inch_addr) { CHANP *pchp = 0; /* for channel prog ptr */ sim_debug(DEBUG_XIO, &cpu_dev, - "set_inch chan %04x inch addr %06x\n", chan, inch_addr); + "set_inch chan %04x inch addr %06x dibp %p\n", chan, inch_addr, dibp); /* must be valid DIB pointer */ if (dibp == NULL) return SCPE_MEM; /* return memory error */ pchp = dibp->chan_prg; /* get parent channel prog ptr */ + sim_debug(DEBUG_XIO, &cpu_dev, + "set_inch chan %04x inch addr %06x pchp %p\n", chan, inch_addr, pchp); /* must be valid channel pointer */ if (pchp == NULL) return SCPE_MEM; /* return memory error */ @@ -268,6 +270,8 @@ t_stat set_inch(UNIT *uptr, uint32 inch_addr) { chp++; /* next unit channel */ } + sim_debug(DEBUG_XIO, &cpu_dev, + "set_inch chan %04x inch addr %06x chp %p\n", chan, inch_addr, chp); /* now go through all the sub addresses for the channel and set inch addr */ for (i=0; i<256; i++) { chsa = chan | i; /* merge sa to real channel */ @@ -562,7 +566,7 @@ loop: chp->chan_caw += 8; /* point to to next IOCD */ chp->ccw_count = word2 & 0xffff; /* get 16 bit byte count from IOCD WD 2*/ chp->chan_byte = BUFF_BUSY; /* busy & no bytes transferred yet */ -sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); chp->ccw_flags = (word2 >> 16) & 0xffff; /* get flags from bits 0-7 of WD 2 of IOCD */ if (chp->ccw_flags & FLAG_PCI) { /* do we have prog controlled int? */ chp->chan_status |= STATUS_PCI; /* set PCI flag in status */ @@ -754,7 +758,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte BUFF_CHNEND chp %p chan_byte %04 if (chp->ccw_flags & FLAG_SKIP) { chp->ccw_count--; /* decrement skip count */ chp->chan_byte = BUFF_BUSY; /* busy, but no data */ -sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "chan_write_byte1 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); if ((chp->ccw_cmd & 0xff) == CMD_RDBWD) chp->ccw_addr--; /* backward */ else @@ -821,7 +825,7 @@ void chan_end(uint16 chsa, uint16 flags) { chsa, flags, chp->chan_status, chp->ccw_cmd); chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */ -sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); chp->chan_status |= STATUS_CEND; /* set channel end */ chp->chan_status |= ((uint16)flags); /* add in the callers flags */ @@ -864,7 +868,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_end BUFF_BUSY chp %p chan_byte %04x\n", chp /* test for device or controller end */ if (chp->chan_status & (STATUS_DEND|STATUS_CEND)) { chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */ -sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); while ((chp->ccw_flags & FLAG_DC)) { /* handle data chaining */ if (load_ccw(chp, 1)) /* continue channel program */ break; /* error */ @@ -874,7 +878,7 @@ sim_debug(DEBUG_EXP, &cpu_dev, "chan_end2 BUFF_BUSY chp %p chan_byte %04x\n", ch } } chp->chan_byte = BUFF_BUSY; /* we are empty & still busy now */ -sim_debug(DEBUG_EXP, &cpu_dev, "chan_end3 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "chan_end3 BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); sim_debug(DEBUG_XIO, &cpu_dev, "chan_end FIFO #%1x IOCL done chsa %04x ccw_flags %04x status %04x\n", FIFO_Num(chsa), chsa, chp->ccw_flags, chp->chan_status); @@ -1063,6 +1067,10 @@ nothere: return SCPE_OK; /* not found, CC3 */ } + sim_debug(DEBUG_EXP, &cpu_dev, + "checkxio chsa %04x flags UNIT_ATTABLE %1x UNIT_ATT %1x\n", + chsa, (uptr->flags & UNIT_ATTABLE)?1:0, (uptr->flags & UNIT_ATT)?1:0); +#ifndef TEST_ETHERNET /* check for the device being defined and attached in simh */ if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { sim_debug(DEBUG_EXP, &cpu_dev, @@ -1070,6 +1078,7 @@ nothere: *status = CC3BIT; /* not attached, so error CC3 */ return SCPE_OK; /* not found, CC3 */ } +#endif inta = find_int_lev(chsa&0x7f00); /* Interrupt Level for channel */ chan_icb = find_int_icb(chsa&0x7f00); /* Interrupt level context block address */ @@ -1196,8 +1205,8 @@ t_stat startxio(uint16 chsa, uint32 *status) { incha = chp->chan_inch_addr; /* get inch address */ sim_debug(DEBUG_XIO, &cpu_dev, - "startxio do normal chsa %04x iocla %06x IOCD1 %08x IOCD2 %08x\n", - chsa, iocla, RMW(iocla), RMW(iocla+4)); + "startxio do normal chsa %04x iocla %06x incha %06x IOCD1 %08x IOCD2 %08x\n", + chsa, iocla, incha, RMW(iocla), RMW(iocla+4)); iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */ // incha = chp->chan_inch_addr; /* get inch address */ @@ -1309,7 +1318,7 @@ t_stat testxio(uint16 chsa, uint32 *status) { /* test XIO */ chsa, chp->ccw_cmd, chp->ccw_flags, RMW(iocla), RMW(iocla+4), iocla); sim_debug(DEBUG_XIO, &cpu_dev, - "testxio test2 chsa %04x ICBincha %08x SW1 %08x SW2 %08x\n", + "testxio test2 chsa %04x ICB incha %08x SW1 %08x SW2 %08x\n", chsa, incha, RMW(incha), RMW(incha+4)); /* the channel is not busy, see if any status to post */ @@ -1547,7 +1556,7 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ chp->chan_status &= ~STATUS_PCI; /* remove PCI status bit */ chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */ chp->chan_byte = BUFF_BUSY; /* wait for post_csw to be done */ -sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); +//sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_BUSY chp %p chan_byte %04x\n", chp, chp->chan_byte); chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* show I/O complete */ /* post the channel status */ @@ -1626,7 +1635,9 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */ /* reset the FIFO pointers */ dibp->chan_fifo_in = 0; dibp->chan_fifo_out = 0; +#ifdef NOT4CONTROLLER chp->chan_inch_addr = 0; /* remove inch status buffer address */ +#endif lev = find_int_lev(chan); /* get our int level */ INTS[lev] &= ~INTS_ACT; /* clear level active */ SPAD[lev+0x80] &= ~SINT_ACT; /* clear spad too */ @@ -1887,7 +1898,9 @@ sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan BUFF_DONE chp %p chan_byte %04x\n", ch /* cannot make anyone active if ints are blocked */ if (CPUSTATUS & 0x80) { /* interrupts blocked? */ - sim_debug(DEBUG_IRQ, &cpu_dev, "scan_chan INTS blocked!\n"); + sim_debug(DEBUG_DETAIL, &cpu_dev, +// sim_debug(DEBUG_IRQ, &cpu_dev, + "scan_chan INTS blocked!\n"); goto tryme; /* needed for MPX */ //718 return 0; /* yes, done */ } @@ -1902,8 +1915,8 @@ sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan BUFF_DONE chp %p chan_byte %04x\n", ch if (SPAD[i+0x80] == 0xefffffff) /* not initialize? */ continue; /* skip this one */ if ((INTS[i]&INTS_ACT) || (SPAD[i+0x80]&SINT_ACT)) { /* look for level active */ -// sim_debug(DEBUG_DETAIL, &cpu_dev, - sim_debug(DEBUG_IRQ, &cpu_dev, + sim_debug(DEBUG_DETAIL, &cpu_dev, +// sim_debug(DEBUG_IRQ, &cpu_dev, "scan_chan INTS ACT irq %02x SPAD %08x INTS %08x\n", i, SPAD[i+0x80], INTS[i]); return 0; /* this level active, so stop looking */ @@ -2153,28 +2166,36 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) { int i; /* temp */ int chsa; /* dev addr */ +// fprintf(stderr, "Set dev entry DEVICE ptr %s\r\n", cptr); if (cptr == NULL) /* is there a UNIT name specified */ return SCPE_ARG; /* no, arg error */ if (uptr == NULL) /* is there a UNIT pointer */ return SCPE_IERR; /* no, arg error */ dptr = get_dev(uptr); /* find the device from unit pointer */ - if (dptr == NULL) /* device not found, so error */ + if (dptr == NULL) { /* device not found, so error */ + fprintf(stderr, "Set dev no DEVICE ptr %s\r\n", cptr); return SCPE_IERR; /* error */ + } dibp = (DIB *)dptr->ctxt; /* get dib pointer from device struct */ - if (dibp == NULL) /* we need a DIB */ + if (dibp == NULL) { /* we need a DIB */ + fprintf(stderr, "Set dev no DIB ptr %s\r\n", GET_UADDR(tuptr->u3), chsa); return SCPE_IERR; /* no DIB, so error */ + } +// fprintf(stderr, "Set dev new addr %s\r\n", cptr); chan = get_uint(cptr, 16, 0xffff, &r); /* get new device address */ if (r != SCPE_OK) /* need good number */ return r; /* number error, return error */ chan &= 0x7f00; /* clean channel address */ dibp->chan_addr = chan; /* set new parent channel addr */ +// fprintf(stderr, "Set dev new addr %s chan %02x\r\n", cptr, chan); /* change all the unit addresses with the new channel, but keep sub address */ /* Clear out existing entries for all units on this device */ tuptr = dptr->units; /* get pointer to units defined for this device */ +// fprintf(stderr, "Set dev new addr %s chan %02x units %02x\r\n", cptr, chan, dibp->numunits); /* loop through all units for this device */ for (i = 0; i < dibp->numunits; i++) { diff --git a/SEL32/sel32_cpu.c b/SEL32/sel32_cpu.c index 63efd7e..70fafab 100644 --- a/SEL32/sel32_cpu.c +++ b/SEL32/sel32_cpu.c @@ -2101,6 +2101,14 @@ wait_loop: goto skipi; /* skip int test */ } } + /* see if in wait instruction */ + if (wait4int) { /* keep waiting */ + /* tell simh we will be waiting */ +// sim_idle(TMR_RTC, 1); /* wait for clock tick */ + sim_idle(0, 1); /* wait for clock tick */ +/*722*/ irq_pend = 1; /* start scanning interrupts again */ + goto wait_loop; /* continue waiting */ + } /* Check for external interrupt here */ /* see if we have an attention request from console */ @@ -5389,6 +5397,14 @@ doovr2: PSD2 = (M[(t>>2)+3] & ~0x3ff8) | bc; /* get new PSD 2 w/old cpix */ M[(t>>2)+4] = IR&0xFFF; /* store call number */ +#ifdef DO_DYNAMIC_DEBUG + if ((temp2 == 0) && ((IR&0xFFF) == 0xa11)) + /* start debugging */ + cpu_dev.dctrl |= (DEBUG_INST | DEBUG_TRAP | DEBUG_EXP | DEBUG_IRQ); +#endif +sim_debug(DEBUG_IRQ, &cpu_dev, +"SVC #%02x call #%03x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n", +temp2, IR&0xFFF, PSD1, PSD2, CPUSTATUS); /* set the mode bits and CCs from the new PSD */ CC = PSD1 & 0x78000000; /* extract bits 1-4 from PSD1 */ modes = PSD1 & 0x87000000; /* extract bits 0, 5, 6, 7 from PSD 1 */ @@ -5978,6 +5994,7 @@ doovr2: TRAPSTATUS |= BIT18; /* set bit 18 of trap status */ goto newpsd; /* memory read error or map fault */ } +//bad /* 723 */ temp &= ~0x02000000; /* reset base reg bit 6 */ bc = CPUSTATUS; /* save the CPU STATUS */ TPSD[0] = PSD1; /* save the PSD for the instruction */ TPSD[1] = PSD2; diff --git a/SEL32/sel32_disk.c b/SEL32/sel32_disk.c index 334c3a0..6b8fe82 100644 --- a/SEL32/sel32_disk.c +++ b/SEL32/sel32_disk.c @@ -600,7 +600,7 @@ t_stat disk_srv(UNIT *uptr) | (buf[i-1]<<8) | (buf[i]); } } - /* now call set_inch() function to write and test inch bybber addresses */ + /* now call set_inch() function to write and test inch buffer addresses */ i = set_inch(uptr, mema); /* new address */ #ifdef NOTYET if ((i == SCPE_MEM) || (i == SCPE_ARG)) { /* any error */ diff --git a/SEL32/sel32_mt.c b/SEL32/sel32_mt.c index 423abde..8648c0a 100644 --- a/SEL32/sel32_mt.c +++ b/SEL32/sel32_mt.c @@ -74,7 +74,7 @@ #define MT_MDEN_6250 0x02 /* =0 Use mode from bit one for NRZI/PE */ #define MT_MDEN_6250 0x02 /* =1 6250 BPI GCR mode 9 track only */ #define MT_MDEN_SCATGR 0x01 /* =1 HSTP scatter/gather mode */ -#define MT_MDEN_MSK 0xc0 /* Density mask */ +#define MT_MDEN_MSK 0x42 /* Density mask */ #define MT_CTL_MSK 0x38 /* Mask for control flags */ #define MT_CTL_NOP 0x00 /* Nop control mode */ @@ -510,6 +510,8 @@ t_stat mt_srv(UNIT *uptr) { uint16 addr = GET_UADDR(uptr->CMD); DEVICE *dptr = get_dev(uptr); +// DIB *dibp = (DIB *)dptr->ctxt; /* get DIB address */ +// CHANP *chp = (CHANP *)dibp->chan_prg; /* get pointer to channel program */ int unit = (uptr - dptr->units); int cmd = uptr->CMD & MT_CMDMSK; int bufnum = GET_DEV_BUF(dptr->flags); @@ -662,7 +664,12 @@ t_stat mt_srv(UNIT *uptr) uptr->SNS &= ~(SNS_LOAD|SNS_EOT); /* reset BOT & EOT */ uptr->POS = 0; /* reset buffer position */ uptr->hwmark = reclen; /* set buffer chars read in */ - sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen); +// sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen); + sim_debug(DEBUG_CMD, &mta_dev, "mt_srv READ fill buffer complete count %04x\n", reclen); + sim_debug(DEBUG_CMD, &mta_dev, + "mt_srv READ MemBuf %06x cnt %04x %02x%02x%02x%02x\n", + chp->ccw_addr, chp->ccw_count, + mt_buffer[0][0], mt_buffer[0][1], mt_buffer[0][2], mt_buffer[0][3]); } /* get a char from the buffer */ ch = mt_buffer[bufnum][uptr->POS++]; @@ -710,7 +717,7 @@ t_stat mt_srv(UNIT *uptr) reclen = uptr->hwmark; /* set record length */ ch = mt_buffer[bufnum][0]; /* get the first byte read */ sim_debug(DEBUG_CMD, &mta_dev, - "Write mode data done unit %02x chars %04x char %02x\n", unit, reclen, ch); + "Write mode data done unit %02x chars %02x mode %02x\n", unit, reclen, ch); /* put mode bits into byte 2 of SNS */ uptr->SNS = (uptr->SNS & 0xffff00ff) | (ch << 8); uptr->POS = 0; /* no bytes anymore */ @@ -720,7 +727,7 @@ t_stat mt_srv(UNIT *uptr) } } else { mt_buffer[bufnum][uptr->POS++] = ch; /* save the character read in */ - sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x ch %02x\n", + sim_debug(DEBUG_CMD, &mta_dev, "Write mode data in unit %02x POS %04x mode %02x\n", unit, uptr->POS, ch); uptr->hwmark = uptr->POS; /* set high water mark */ sim_activate(uptr, 40); /* wait time */ @@ -849,10 +856,14 @@ t_stat mt_srv(UNIT *uptr) sim_debug(DEBUG_CMD, &mta_dev, "Backspace rec unit %02x POS %04x\n", unit, uptr->POS); r = sim_tape_sprecr(uptr, &reclen); - /* We don't set EOF on BSR */ - if (r == MTSE_TMK) { + /* SEL requires Unit Except & EOF on EOF */ + if (r == MTSE_TMK) { /* test for EOF */ uptr->POS++; - sim_debug(DEBUG_CMD, &mta_dev, "MARK\n"); + sim_debug(DEBUG_CMD, &mta_dev, "BSR MARK\n"); + sim_activate(uptr, 50); + /* SEL requires Unit Except & BOT on BOT */ + } else if (r == MTSE_BOT) { + uptr->POS+= 2; sim_activate(uptr, 50); } else { sim_debug(DEBUG_CMD, &mta_dev, "Backspace reclen %04x\n", reclen); @@ -864,9 +875,16 @@ t_stat mt_srv(UNIT *uptr) mt_busy[bufnum] &= ~1; chan_end(addr, SNS_CHNEND|SNS_DEVEND); break; - case 3: + case 3: /* EOF */ uptr->CMD &= ~(MT_CMDMSK); mt_busy[bufnum] &= ~1; + uptr->SNS |= SNS_FMRKDT; /* file mark detected */ + chan_end(addr, SNS_DEVEND|SNS_UNITEXP); + break; + case 4: /* BOT */ + uptr->CMD &= ~(MT_CMDMSK); + mt_busy[bufnum] &= ~1; + uptr->SNS |= SNS_LOAD; /* set BOT detected */ chan_end(addr, SNS_DEVEND|SNS_UNITEXP); break; } @@ -887,10 +905,11 @@ t_stat mt_srv(UNIT *uptr) break; case 1: sim_debug(DEBUG_CMD, &mta_dev, "Backspace file unit=%02x\n", unit); + uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */ r = sim_tape_sprecr(uptr, &reclen); if (r == MTSE_TMK) { uptr->POS++; - sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n"); + sim_debug(DEBUG_DETAIL, &mta_dev, "BSF MARK\n"); sim_activate(uptr, 50); } else if (r == MTSE_BOT) { uptr->POS+= 2; @@ -901,12 +920,14 @@ t_stat mt_srv(UNIT *uptr) break; case 2: /* File Mark */ uptr->CMD &= ~(MT_CMDMSK); + uptr->SNS |= SNS_FMRKDT; /* file mark detected */ mt_busy[bufnum] &= ~1; chan_end(addr, SNS_DEVEND); break; case 3: /* BOT */ uptr->CMD &= ~(MT_CMDMSK); mt_busy[bufnum] &= ~1; + uptr->SNS |= SNS_LOAD; /* set BOT */ chan_end(addr, SNS_DEVEND); break; } @@ -922,6 +943,7 @@ t_stat mt_srv(UNIT *uptr) case 1: uptr->POS++; sim_debug(DEBUG_CMD, &mta_dev, "Skip rec unit=%02x ", unit); + uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */ r = sim_tape_sprecf(uptr, &reclen); if (r == MTSE_TMK) { uptr->POS = 3; @@ -931,6 +953,7 @@ t_stat mt_srv(UNIT *uptr) } else if (r == MTSE_EOM) { uptr->POS = 4; uptr->SNS |= SNS_EOT; /* set EOT status */ + sim_debug(DEBUG_CMD, &mta_dev, "FSR EOT\n"); sim_activate(uptr, 50); } else { sim_debug(DEBUG_CMD, &mta_dev, "FSR skipped %04x byte record\n", @@ -947,13 +970,13 @@ t_stat mt_srv(UNIT *uptr) case 3: uptr->CMD &= ~(MT_CMDMSK); mt_busy[bufnum] &= ~1; - sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOF\n"); + sim_debug(DEBUG_CMD, &mta_dev, "Skip record now at EOF\n"); chan_end(addr, SNS_DEVEND|SNS_UNITEXP); break; case 4: uptr->CMD &= ~(MT_CMDMSK); mt_busy[bufnum] &= ~1; - sim_debug(DEBUG_CMD, &mta_dev, "Skip record at EOT\n"); + sim_debug(DEBUG_CMD, &mta_dev, "Skip record now at EOT\n"); chan_end(addr, SNS_DEVEND|SNS_UNITEXP); break; } @@ -969,6 +992,7 @@ t_stat mt_srv(UNIT *uptr) break; case 1: sim_debug(DEBUG_CMD, &mta_dev, "Skip file unit=%02x\n", unit); + uptr->SNS &= ~(SNS_LOAD|SNS_EOT|SNS_FMRKDT); /* reset BOT, EOT, EOF */ r = sim_tape_sprecf(uptr, &reclen); if (r == MTSE_TMK) { uptr->POS++; @@ -988,14 +1012,12 @@ t_stat mt_srv(UNIT *uptr) case 2: uptr->CMD &= ~(MT_CMDMSK); mt_busy[bufnum] &= ~1; - uptr->SNS &= ~SNS_LOAD; /* reset BOT */ sim_debug(DEBUG_CMD, &mta_dev, "Skip file done sense %08x unit %02x\n", uptr->SNS, unit); chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */ break; case 3: uptr->CMD &= ~(MT_CMDMSK); - uptr->SNS &= ~SNS_LOAD; /* reset BOT */ uptr->SNS |= SNS_EOT; /* set EOT status */ mt_busy[bufnum] &= ~1; sim_debug(DEBUG_CMD, &mta_dev, diff --git a/SEL32/taptools/mkvmtape.c b/SEL32/taptools/mkvmtape.c index 98df6ad..5e5df83 100644 --- a/SEL32/taptools/mkvmtape.c +++ b/SEL32/taptools/mkvmtape.c @@ -33,14 +33,14 @@ /* memory access macros */ /* The RMW and WMW macros are used to read/write memory words */ /* RMW(addr) or WMW(addr, data) where addr is a byte alligned word address */ -#define RMB(a) ((M[(a)>>2]>>(8*(7-(a&3))))&0xff) /* read memory addressed byte */ +#define RMB(a) ((M[(a)>>2]>>(8*(3-(a&3))))&0xff) /* read memory addressed byte */ #define RMH(a) ((a)&2?(M[(a)>>2]&RMASK):(M[(a)>>2]>>16)&RMASK) /* read memory addressed halfword */ #define RMW(a) (M[((a)&MASK24)>>2]) /* read memory addressed word */ #define WMW(a,d) (M[((a)&MASK24)>>2]=d) /* write memory addressed word */ /* write halfword to memory address */ #define WMH(a,d) ((a)&2?(M[(a)>>2]=(M[(a)>>2]&LMASK)|((d)&RMASK)):(M[(a)>>2]=(M[(a)>>2]&RMASK)|((d)<<16))) /* write byte to memory */ -#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(7-(a&3))))))|((d&0xff)<<(8*(7-(a&3)))))) +#define WMB(a,d) (M[(a)>>2]=(((M[(a)>>2])&(~(0xff<<(8*(3-(a&3))))))|((d&0xff)<<(8*(3-(a&3)))))) #define BLKSIZE 768 /* MPX file sector size */ u_int32_t dir[32]; /* directory name */ @@ -258,7 +258,7 @@ char *argv[]; break; case 'A': case 'a': - if (option & DOBOOT) { /* error if boor specified with append command */ + if (option & DOBOOT) { /* error if boot specified with append command */ fprintf(stderr, "Error: -a cannot be specified with -b option\n"); goto error1; /* we are done here */ } @@ -424,7 +424,7 @@ getout: if (option & DOBOOT) { int32_t w2, n1, n2, nw, hc, blks; fnp = bootp; /* get file name pointer */ -#ifdef USE_FILENAME +#ifndef USE_FILENAME memset((char *)data, 0, 0x800); /* zero data storage */ if ((fp = fopen(bootp, "r")) == NULL) { fprintf(stderr, "error: can't open boot file %s\n", bootp); @@ -442,7 +442,8 @@ printf("bootfile %s is %x (%d) bytes\n", bootp, word, word); w2 = fread((char *)data, 1, word, fp); /* read the boot file */ #else /* go cut the boot code from the volmgr load module */ - w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d144); +// w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d144); + w2 = readboot("volmgr", (char *)data, 0x1c9a0, 0x1d140); #endif /* we have data to write */ hc = (w2 + 1) & ~1; /* make byte count even */