From 60e649de5acb39f248d3b36dd1f0240992e13e9f Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:15:48 -0700 Subject: [PATCH 01/10] SEL32: Change support of INCH command to always generate interrupt. SEL32: Remove unused debug code. --- SEL32/sel32_chan.c | 173 ++++++++++++++++++--------------------------- 1 file changed, 70 insertions(+), 103 deletions(-) diff --git a/SEL32/sel32_chan.c b/SEL32/sel32_chan.c index c35ee82..c733650 100644 --- a/SEL32/sel32_chan.c +++ b/SEL32/sel32_chan.c @@ -20,6 +20,11 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + Change History: + 07/01/2019 - make data address mask 24 bit + 07/02/2019 - make chan mask 0x7f for 128 channels max + 07/18/2019 - change INCH command processing for UTX + */ /* Handle Class E and F channel I/O operations */ @@ -179,11 +184,11 @@ uint32 find_int_lev(uint16 chsa) /* F class only uses chan entry */ if (((val >> 8 ) & 0x7f) == chan) { /* channel matches, now get interrupt level number */ - level = ((val >> 16) & 0x7f); /* 1's comp of int level */ - level = 127 - level; /* get positive number level */ + level = ((val >> 16) & 0x7f); /* 1's comp of int level */ + level = 127 - level; /* get positive number level */ sim_debug(DEBUG_EXP, &cpu_dev, "find_int_lev F SPAD %x chan %x chsa %x level %x\n", val, chan, chsa, level); - return(level); /* return the level*/ + return(level); /* return the level*/ } } /* look for E class or class 3 device */ @@ -192,33 +197,33 @@ uint32 find_int_lev(uint16 chsa) /* E class uses chan and device address */ if ((val & 0x7f00) == (chsa & 0x7f00)) { /* check chan/subaddress */ /* channel/subaddress matches, now get interrupt level number */ - level = ((val >> 16) & 0x7f); /* 1's comp of int level */ - level = 127 - level; /* get positive number level */ + level = ((val >> 16) & 0x7f); /* 1's comp of int level */ + level = 127 - level; /* get positive number level */ sim_debug(DEBUG_EXP, &cpu_dev, "find_int_lev E SPAD %x chan %x chsa %x level %x\n", val, chan, chsa, level); - return(level); /* return the level*/ + return(level); /* return the level*/ } } } /* not a real device, so check interrupt entries for match */ /* scan the entries for our channel/subaddress */ for (i=0; i<112; i++) { - val = SPAD[i+0x80]; /* get spade entry */ + val = SPAD[i+0x80]; /* get spade entry */ if (val == 0 || val == 0xffffffff) - continue; /* not valid entry */ + continue; /* not valid entry */ /* look for class 3 device or non device entries */ if (((val & 0x0f800000) == 0x00800000) || /* clock or external interrupt */ ((val & 0x0f800000) == 0x03800000)) { /* class 3 (interval timer) */ /* E class or non I/O uses chan and device address */ if ((val & 0x7f00) == (chsa & 0x7f00)) { /* check chan/sub address */ /* channel/subaddress matches, now get interrupt level number */ - level = ((val >> 16) & 0x7f); /* 1's comp of int level */ - level = 127 - level; /* get positive number level */ - return(level); /* return the level*/ + level = ((val >> 16) & 0x7f); /* 1's comp of int level */ + level = 127 - level; /* get positive number level */ + return(level); /* return the level*/ } } } - return 0; /* not found */ + return 0; /* not found */ } /* Find interrupt context block address for given device (ch/sa) */ @@ -349,7 +354,7 @@ int writebuff(CHANP *chp) return 1; } addr &= MASK24; - sim_debug(DEBUG_EXP, &cpu_dev, "writebuff WRITE addr %x status %x\n", addr, MEMSIZE, chp->chan_status); + sim_debug(DEBUG_EXP, &cpu_dev, "writebuff WRITE addr %x MEMSIZE %x status %x\n", addr, MEMSIZE, chp->chan_status); M[addr>>2] = chp->chan_buf; return 0; } @@ -387,6 +392,7 @@ loop: sim_debug(DEBUG_CMD, &cpu_dev, "load_ccw read ccw chan %02x caw %06x IOCD wd 1 %08x\n", chan, chp->chan_caw, word); + /* TIC can't follow TIC or be first in command chain */ if (((word >> 24) & 0xf) == CMD_TIC) { if (tic_ok) { @@ -404,17 +410,12 @@ loop: /* Check if not chaining data */ if ((chp->ccw_flags & FLAG_DC) == 0) { chp->ccw_cmd = (word >> 24) & 0xff; /* not DC, so set command from IOCD wd 1 */ - sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw No DC, flags %x cmd %x\n", - chp->ccw_flags, chp->ccw_cmd); + sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw No DC, flags %x cmd %x\n", chp->ccw_flags, chp->ccw_cmd); docmd = 1; /* show we have a command */ } /* Set up for this command */ -#ifndef HASK_HACK + /* make a 24 bit address */ chp->ccw_addr = word & MASK24; /* set the data address */ -#else - /* make a 20 bit address */ - chp->ccw_addr = word & 0xfffff; /* set the data address */ -#endif readfull(chp, chp->chan_caw, &word); /* get IOCD WD 2 */ sim_debug(DEBUG_CMD, &cpu_dev, "load_ccw read ccw chan %02x caw %06x IOCD wd 2 %08x\n", @@ -430,9 +431,9 @@ loop: sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw read docmd %x irq_flag %x count %x chan %x ccw_flags %x\n", docmd, irq_pend, chp->ccw_count, chan, chp->ccw_flags); + /* LPR sends CC cmd only without data addr/count */ +#ifdef HACK_FOR_LPR /* Check invalid count */ - /* HACK HACK - LPR sends CC cmd only without data addr/count */ -#ifdef NONO if ((chp->ccw_count == 0) && (chp->ccw_addr != 0)) { /* see if byte count is zero */ chp->chan_status |= STATUS_PCHK; /* program check if it is */ irq_pend = 1; /* status pending int */ @@ -475,16 +476,29 @@ loop: return 1; /* error return */ } +#ifndef TRY_THIS + /* INCH cmd will return here too, get INCH buffer addr from uptr->u4 */ + /* see if this is an initialize channel cmd */ + if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 != 0)) { +/// if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 >= 0)) { + chp->chan_inch_addr = uptr->u4; /* save INCH buffer address */ + sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH %x saved chan %0x\n", + chp->chan_inch_addr, chan); + } +#endif + /* see if command completed */ if (chp->chan_status & (STATUS_DEND|STATUS_CEND)) { +#ifdef TRY_THIS /* INCH cmd will return here too, get INCH buffer addr from uptr->u4 */ /* see if this is an initialize channel cmd */ -// if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 != 0)) { - if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 >= 0)) { + if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 != 0)) { +/// if ((chp->ccw_cmd & 0xFF) == 0 && (uptr->us9 >= 0)) { chp->chan_inch_addr = uptr->u4; /* save INCH buffer address */ sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH %x saved chan %0x\n", chp->chan_inch_addr, chan); } +#endif chp->chan_status |= STATUS_CEND; /* set channel end status */ chp->chan_byte = BUFF_NEWCMD; /* ready for new cmd */ chp->ccw_cmd = 0; /* stop IOCD processing */ @@ -493,8 +507,8 @@ loop: chan, chp->chan_status, chp->ccw_count); } } - sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw return, chan %0x status %.8x count %x\n", - chan, chp->chan_status, chp->ccw_count); + sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw return, chan %0x status %.8x count %x irq %x\n", + chan, chp->chan_status, chp->ccw_count, irq_pend); return 0; /* good return */ } @@ -694,7 +708,7 @@ void chan_end(uint16 chsa, uint16 flags) { sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %x ccw_flags %x count %x status %x\n", chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status); #ifdef HACK_HACK /* hack - rewind had byte count of 1, so triggered this error when it is not */ - /* remove until I firgure out what is required */ + /* remove until I figure out what is required */ /* FIXME */ /* test for incorrect transfer length */ if (chp->ccw_count != 0 && ((chp->ccw_flags & FLAG_SLI) == 0)) { @@ -748,7 +762,7 @@ void store_csw(CHANP *chp) if ((FIFO_Put(chsa, stwd1) == -1) || (FIFO_Put(chsa, stwd2) == -1)) { fprintf(stderr, "FIFO Overflow ERROR on chsa %x\r\n", chsa); } -//fprintf(stderr, "store_csw on chsa %x sw1 %x sw2 %x\r\n", chsa, stwd1, stwd2); + sim_debug(DEBUG_CMD, &cpu_dev, "store_csw on chsa %x sw1 %x sw2 %x\r\n", chsa, stwd1, stwd2); chp->chan_status = 0; /* no status anymore */ irq_pend = 1; /* wakeup controller */ } @@ -788,14 +802,13 @@ t_stat startxio(uint16 lchsa, uint32 *status) { /* get the device entry for the logical channel in SPAD */ spadent = SPAD[lchan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ dibp = dev_unit[chsa & 0x7f00]; /* get the device information pointer */ chp = find_chanp_ptr(chsa); /* find the chanp pointer */ uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */ - sim_debug(DEBUG_CMD, &cpu_dev, "startxio 1 chsa %x chan %x\n", chsa, chan); + sim_debug(DEBUG_CMD, &cpu_dev, "startxio 1 chsa %x chan %x loc 0 %x\n", chsa, chan, M[0]); if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */ *status = CC3BIT; /* not found, so CC3 */ return SCPE_OK; /* not found, CC3 */ @@ -818,8 +831,8 @@ t_stat startxio(uint16 lchsa, uint32 *status) { chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */ chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */ iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */ - sim_debug(DEBUG_CMD, &cpu_dev, "startxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x\n", - chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]); + sim_debug(DEBUG_CMD, &cpu_dev, "startxio busy test chsa %0x chan %x cmd %x iocla %x flags %x IOCD1 %x IOCD2 %x\n", + chsa, chan, chp->ccw_cmd, iocla, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]); sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO %x %x cmd %x flags %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags); @@ -850,15 +863,18 @@ t_stat startxio(uint16 lchsa, uint32 *status) { chp->chan_caw = iocla; /* get iocla address in memory */ /* set status words in memory to first IOCD information */ tempa = chp->chan_inch_addr; /* get inch status buffer address */ +#ifdef NOT_HERE // if (tempa != 0) { if (tempa >= 0) { M[tempa >> 2] = (chsa & 0xff) << 24 | iocla; /* suba & IOCD address to status */ M[(tempa+4) >> 2] = 0; /* null status and residual byte count */ } - sim_debug(DEBUG_CMD, &cpu_dev, "$$ SIO starting IOCL processing chsa %02x\n", chsa); -//fprintf(stderr, "$$ SIO starting IOCL processing chsa %02x\n", chsa); -//fflush(stderr); +#endif + sim_debug(DEBUG_CMD, &cpu_dev, "@ startxio 4 chsa %x chan %x iocla %x tempa %x loc 0=%x\n", + chsa, chan, iocla, tempa, M[0]); + + sim_debug(DEBUG_CMD, &cpu_dev, "$$ SIO starting IOCL processing chsa %02x iocla %x\n", chsa, iocla); /* start processing the IOCL */ if (load_ccw(chp, 0) || (chp->chan_status & STATUS_PCI)) { @@ -871,33 +887,28 @@ t_stat startxio(uint16 lchsa, uint32 *status) { return SCPE_OK; /* CC1 (0x40) status stored */ } - if ((chp->ccw_cmd & 0xFF) == 0) /* see if this is an initialize channel cmd */ - *status = CC1BIT; /* request accepted, no status, so CC1 TRY THIS */ - else -// *status = 0; /* CCs = 0, SIO accepted, will echo status */ - *status = CC1BIT; /* CCs = 0, SIO accepted, will echo status */ -// *status = CC1BIT; /* CCs = 0, SIO accepted, will echo status */ - sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO done chsa %x status %08x\n", chsa, chp->chan_status); -//fprintf(stderr, "$$$ SIO done chsa %x status %08x\n", chsa, chp->chan_status); -//fflush(stderr); + *status = CC1BIT; /* CCs = 1, SIO accepted & queued, will not echo status */ + sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO done chsa %x status %08x iocla %x M[0] %x\n", + chsa, chp->chan_status, iocla, M[0]); return SCPE_OK; /* No CC's all OK */ } /* TIO - I/O status */ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */ - uint32 chan = get_chan(lchsa); +// uint32 chan = get_chan(lchsa); + int lchan = get_chan(lchsa); /* get the logical channel number */ DIB *dibp; UNIT *uptr; uint32 chan_ivl; /* Interrupt Level ICB address for channel */ uint32 iocla; /* I/O channel IOCL address int ICB */ - uint32 tempa, inta, spadent; + uint32 tempa, inta, spadent, chan; uint16 chsa; /* chan/subaddr */ CHANP *chp, *pchp; /* Channel prog pointers */ uint32 sw1, sw2; /* status word 1 & 2 */ /* get the device entry for the logical channel in SPAD */ - spadent = SPAD[chan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ +// spadent = SPAD[chan]; /* get spad device entry for logical channel */ + spadent = SPAD[lchan]; /* get spad device entry for logical channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ dibp = dev_unit[chsa]; /* get the device information pointer */ @@ -929,8 +940,8 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */ chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */ iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */ - sim_debug(DEBUG_CMD, &cpu_dev, "testxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x\n", - chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]); + sim_debug(DEBUG_CMD, &cpu_dev, "testxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x IOCLA %x\n", + chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2], iocla); sim_debug(DEBUG_CMD, &cpu_dev, "$$$ TIO %x %x %x %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags); @@ -956,7 +967,7 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */ goto tioret; /* CC2 and OK */ } /* nothing going on, so say all OK */ - *status = CC1BIT; /* request accepted, no status, so CC1 TRY THIS */ + *status = CC1BIT; /* request accepted, no status, so CC1 */ tioret: sim_debug(DEBUG_CMD, &cpu_dev, "$$$ TIO END chsa %x chan %x cmd %x flags %x chan_stat %x CCs %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags, chp->chan_status, *status); @@ -976,7 +987,6 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ /* get the device entry for the logical channel in SPAD */ spadent = SPAD[chan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ dibp = dev_unit[chsa]; /* get the device information pointer */ @@ -1059,7 +1069,6 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */ dibp->chan_fifo_in = 0; dibp->chan_fifo_out = 0; dev_status[chan] = 0; /* clear the channel status location */ -// chp->chan_inch_addr = 0; /* remove inch status buffer address */ chp->chan_inch_addr = 0; /* remove inch status buffer address */ lev = find_int_lev(chan); /* get our int level */ INTS[lev] &= ~INTS_ACT; /* clear level active */ @@ -1105,7 +1114,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ /* get the device entry for the logical channel in SPAD */ spadent = SPAD[chan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ dibp = dev_unit[chsa]; /* get the device information pointer */ @@ -1143,7 +1151,6 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ /* check for a Command or data chain operation in progresss */ if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) { sim_debug(DEBUG_CMD, &cpu_dev, "haltxio busy return CC4 chsa %x chan %x\n", chsa, chan); - fprintf(stderr, "HIO haltxio busy return CC4 chsa %x chan %x\r\n", chsa, chan); /* reset the DC or CC bits to force completion after current IOCD */ chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */ dev_status[chsa] |= STATUS_ECHO; /* show we stopped the cmd */ @@ -1168,7 +1175,6 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u /* get the device entry for the logical channel in SPAD */ spadent = SPAD[chan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ chp = find_chanp_ptr(chsa); /* find the chanp pointer */ @@ -1193,7 +1199,6 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */ /* get the device entry for the logical channel in SPAD */ spadent = SPAD[chan]; /* get spad device entry for logical channel */ -// chan = (spadent & 0xff00) >> 8; /* get real channel */ chan = (spadent & 0x7f00) >> 8; /* get real channel */ chsa = (chan << 8) | (lchsa & 0xff); /* merge sa to real channel */ chp = find_chanp_ptr(chsa); /* find the chanp pointer */ @@ -1269,30 +1274,19 @@ uint32 scan_chan(void) { continue; /* skip this one */ if (SPAD[i+0x80] == 0xffffffff) /* not initialize? */ continue; /* skip this one */ -//fprintf(stderr, "done checking interrupt INTS[%d] %x\n", i, INTS[i]); -//fflush(stderr); /* see if there is pending status for this channel */ /* if there is and the level is not requesting, do it */ if ((INTS[i] & INTS_ENAB) && !(INTS[i] & INTS_REQ)) { /* get the device entry for the logical channel in SPAD */ -/*070219*/ chan = (SPAD[i+0x80] & 0xff00); /* get real channel and zero sa */ chan = (SPAD[i+0x80] & 0x7f00); /* get real channel and zero sa */ -//fprintf(stderr, "getting dibp chan %x\n", chan); -//fflush(stderr); dibp = dev_unit[chan]; /* get the device information pointer */ -//fprintf(stderr, "got dibp %x chan %x\n", dibp, chan); -//fflush(stderr); if (dibp == 0) continue; /* skip unconfigured channel */ -//fprintf(stderr, "checking fifo chan %x\n", chan); -//fflush(stderr); /* see if the FIFO is empty */ if (dibp->chan_fifo_in != dibp->chan_fifo_out) { uint32 sw1, sw2; /* fifo is not empty, so post status and request an interrupt */ if ((FIFO_Get(chan, &sw1) == 0) && (FIFO_Get(chan, &sw2) == 0)) { -//fprintf(stderr, "found fifo chan %x\n", chan); -//fflush(stderr); /* we have status to return, do it now */ chp = find_chanp_ptr(chan); /* find the chanp pointer for channel */ /* get the address of the interrupt IVL table in main memory */ @@ -1310,42 +1304,26 @@ uint32 scan_chan(void) { } /* look for the highest requesting interrupt */ /* that is enabled */ -//fprintf(stderr, "checking interrupt INTS[%d] %x\n", i, INTS[i]); -//fflush(stderr); if (((INTS[i] & INTS_ENAB) && (INTS[i] & INTS_REQ)) || ((SPAD[i+0x80] & INTS_ENAB) && (INTS[i] & INTS_REQ))) { /* requesting, make active and turn off request flag */ -//fprintf(stderr, "found interrupt %x\n", INTS[i]); -//fflush(stderr); INTS[i] &= ~INTS_REQ; /* turn off request */ INTS[i] |= INTS_ACT; /* turn on active */ SPAD[i+0x80] |= SINT_ACT; /* show active in SPAD too */ -//fprintf(stderr, "enable interrupt INT[%d] %x\n", i, INTS[i]); -//fflush(stderr); /* make sure both enabled too */ INTS[i] |= INTS_ENAB; /* turn on enable */ SPAD[i+0x80] |= SINT_ENAB; /* show enabled in SPAD too */ /* get the address of the interrupt IVL table in main memory */ chan_ivl = SPAD[0xf1] + (i<<2); /* contents of spad f1 points to chan ivl in mem */ chan_icba = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */ -//fprintf(stderr, "scan_chan INTS REQ irq %x found chan_icba %x INTS %x\n", i, chan_icba, INTS[i]); -//fflush(stderr); sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan INTS REQ irq %x found chan_icba %x INTS %x\n", i, chan_icba, INTS[i]); return(chan_icba); /* return ICB address */ } -//fprintf(stderr, "done checking interrupt INTS[%d] %x\n", i, INTS[i]); -//fflush(stderr); } -//fprintf(stderr, "done checking interrupt loop\n"); -//fflush(stderr); } -//fprintf(stderr, "scan_chan irq_pend not pending\n"); -//fflush(stderr); if (irq_pend == 0) /* pending int? */ return 0; /* no, so just return */ -//fprintf(stderr, "scan_chan irq_pend %x\n", irq_pend); -//fflush(stderr); irq_pend = 0; /* not pending anymore */ /* loop through all the channels/units for channel with pending I/O completion */ @@ -1364,24 +1342,26 @@ uint32 scan_chan(void) { /* Check if address is in unit or dev entry */ for (j = 0; j < dibp->numunits; j++) { /* loop through unit entries */ chsa = GET_UADDR(uptr->u3); /* ch/sa value */ -//fprintf(stderr, "checking chsa %x i %d j %d units %d name %s\n", chsa, i, j, dibp->numunits, dptr->name); -//fflush(stderr); /* If channel end, check if we should continue */ if (chp->chan_status & STATUS_CEND) { /* do we have channel end */ - sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end chsa %x flags %x status %x\n", loading, chsa, chp->ccw_flags, chp->chan_status); + sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end chsa %x flags %x status %x\n", + loading, chsa, chp->ccw_flags, chp->chan_status); if (chp->ccw_flags & FLAG_CC) { /* command chain flag */ /* we have channel end and CC flag, continue channel prog */ - sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & CC chsa %x status %x\n", loading, chsa, chp->chan_status); + sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & CC chsa %x status %x\n", + loading, chsa, chp->chan_status); if (chp->chan_status & STATUS_DEND) { /* device end? */ - sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x dev end & CC chsa %x status %x\n", loading, chsa, chp->chan_status); + sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x dev end & CC chsa %x status %x\n", + loading, chsa, chp->chan_status); (void)load_ccw(chp, 1); /* go load the next IOCB */ } else irq_pend = 1; /* still pending int */ } else { /* we have channel end and no CC flag, end command */ chsa = chp->chan_dev; /* get the chan/sa */ - sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & no CC chsa %x status %x\n", loading, chsa, chp->chan_status); + sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & no CC chsa %x status %x\n", + loading, chsa, chp->chan_status); dev_status[chsa] = 0; /* no device status anymore */ /* handle case where we are loading the O/S on boot */ if (loading) { @@ -1390,21 +1370,10 @@ uint32 scan_chan(void) { } irq_pend = 0; /* no pending int */ chp->chan_status = 0; /* no channel status */ -//fprintf(stderr, "chp = %x loading complete\n", chp); -//fflush(stderr); return chsa; /* if loading, just channel number */ } /* we are not loading, but have completed channel program */ -//fprintf(stderr, "chp = %x complete\n", chp); -//fflush(stderr); store_csw(chp); /* store the status */ - lev = find_int_lev(chsa); /* get interrupt level */ -//fprintf(stderr, "lev = %x complete\n", lev); -//fflush(stderr); - if (lev == 0) { - irq_pend = 1; /* still pending int */ - return 0; /* just return */ - } irq_pend = 1; /* still pending int */ return 0; /* just return */ } @@ -1445,7 +1414,6 @@ t_stat chan_set_devs() { /* zero some channel data loc's for device */ dev_status[chsa] = 0; /* zero device status flags */ dev_status[chsa&0x7f00] = 0; /* clear the channel status location */ -// dev_status[chsa] = 0; /* device status too */ chp->chan_status = 0; /* clear the channel status */ chp->chan_dev = chsa; /* save our address (ch/sa) */ chp->chan_byte = BUFF_EMPTY; /* no data yet */ @@ -1454,7 +1422,6 @@ t_stat chan_set_devs() { chp->ccw_count = 0; /* channel byte count 0 bytes*/ chp->ccw_flags = 0; /* Command chain and supress incorrect length */ chp->ccw_cmd = 0; /* read command */ -// chp->chan_inch_addr = 0; /* clear address of stat dw in memory */ chp->chan_inch_addr = 0; /* clear address of stat dw in memory */ if ((uptr->flags & UNIT_DIS) == 0) /* is unit marked disabled? */ dev_unit[chsa] = dibp; /* no, save the dib address */ From c7af4f15a4b719d75d79eb1d9503d34eb1d2476c Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:17:35 -0700 Subject: [PATCH 02/10] SEL32: Change clock initialization call. SEL32: Remove unused pld debug code. --- SEL32/sel32_clk.c | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/SEL32/sel32_clk.c b/SEL32/sel32_clk.c index 69c4fec..02b99ac 100644 --- a/SEL32/sel32_clk.c +++ b/SEL32/sel32_clk.c @@ -130,7 +130,6 @@ void rtc_setup(uint32 ss, uint32 level) rtc_lvl = level; /* save the interrupt level */ addr = M[addr>>2]; /* get the interrupt context block addr */ -//fprintf(stderr, "rtc_setup called ss %x level %x SPAD %x icba %x\r\n", ss, level, val, addr); if (ss == 1) { /* starting? */ INTS[level] |= INTS_ENAB; /* make sure enabled */ SPAD[level+0x80] |= SINT_ENAB; /* in spad too */ @@ -147,7 +146,8 @@ void rtc_setup(uint32 ss, uint32 level) t_stat rtc_reset(DEVICE *dptr) { rtc_pie = 0; /* disable pulse */ - rtc_unit.wait = sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* initialize clock calibration */ +//MARKFIX rtc_unit.wait = sim_rtcn_init(rtc_unit.wait, TMR_RTC); /* initialize clock calibration */ + rtc_unit.wait = sim_rtcn_init_unit(&rtc_unit, rtc_unit.wait, TMR_RTC); /* initialize clock calibration */ sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */ return SCPE_OK; } @@ -250,12 +250,6 @@ DEVICE itm_dev = { /* cause interrupt */ t_stat itm_srv (UNIT *uptr) { -// uint32 val = SPAD[itm_lvl+0x80]; /* get SPAD value for interrupt vector */ -// uint32 addr = SPAD[0xf1] + (itm_lvl<<2); /* vector address in SPAD */ -// addr = M[addr>>2]; /* get the interrupt context block addr */ -//fprintf(stderr, "itm_srv level %x itm_pie %x wait %x spad %x icba %x\r\n", -// itm_lvl, itm_pie, itm_unit.wait, val, addr); - if (itm_pie) { /* interrupt enabled? */ INTS[itm_lvl] |= INTS_REQ; /* request the interrupt on zero value */ irq_pend = 1; /* make sure we scan for int */ @@ -274,30 +268,27 @@ t_stat itm_srv (UNIT *uptr) int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level) { uint32 temp; -// uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */ - -// itm_lvl = level; /* save the interrupt level */ -// uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */ -// addr = M[addr>>2]; /* get the interrupt context block addr */ -//fprintf(stderr, "itm_rdwr called ss %x level %x SPAD %x icba %x\r\n", ss, level, val, addr); -//fprintf(stderr, "itm_rdwr called cmd %x count %x (%d) level %x return cnt %x (%d)\r\n", -// cmd, cnt, cnt, level); switch (cmd) { case 0x39: /* load timer with new value and start*/ if (cnt < 0) cnt = 26042; /* TRY ??*/ - sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0);/* start timer with value from user */ + /* start timer with value from user */ + sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0); return 0; /* does not matter, no value returned */ case 0x60: /* read and stop timer */ - temp = (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100);/* get timer value and stop timer */ + /* get timer value and stop timer */ + temp = (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100); sim_cancel (&itm_unit); return temp; /* return current count value */ case 0x79: /* read the current timer value */ - temp = (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100); /* get timer value, load new value and start timer */ - sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0);/* start timer to fire after cnt ticks */ + /* get timer value, load new value and start timer */ + temp = (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100); + /* start timer to fire after cnt ticks */ + sim_activate_after_abs_d (&itm_unit, ((double)cnt * itm_tick_size_x_100) / 100.0); return temp; /* return current count value */ case 0x40: /* read the current timer value */ - return (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100);/* return current count value */ + /* return current count value */ + return (uint32)(100.0 * sim_activate_time_usecs (&itm_unit) / itm_tick_size_x_100); break; } return 0; /* does not matter, no value returned */ @@ -310,7 +301,6 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level) void itm_setup(uint32 ss, uint32 level) { itm_lvl = level; /* save the interrupt level */ -// fprintf(stderr, "itm_setup called ss %x level %x\r\n", ss, level); if (ss == 1) { /* starting? */ INTS[level] |= INTS_ENAB; /* make sure enabled */ SPAD[level+0x80] |= SINT_ENAB; /* in spad too */ @@ -326,8 +316,6 @@ void itm_setup(uint32 ss, uint32 level) /* Clock reset */ t_stat itm_reset (DEVICE *dptr) { -// int intlev = 0x5f; /* interrupt level for itm */ -//fprintf(stderr, "itm_reset called\r\n"); itm_pie = 0; /* disable pulse */ sim_cancel (&itm_unit); /* not running yet */ return SCPE_OK; From a928745c554b59ee9af966fce75e28a8c95593a3 Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:23:39 -0700 Subject: [PATCH 03/10] SEL32: Change INCH/NOP command handling for UTX. SEL32: Remove unused debug code. --- SEL32/sel32_com.c | 45 ++++++++++++++++++----- SEL32/sel32_con.c | 44 ++++++++++++++++++----- SEL32/sel32_disk.c | 84 ++++++++++++++++++++++++------------------- SEL32/sel32_mt.c | 90 ++++++++++++++++++---------------------------- 4 files changed, 155 insertions(+), 108 deletions(-) diff --git a/SEL32/sel32_com.c b/SEL32/sel32_com.c index c611a4c..d9c43da 100644 --- a/SEL32/sel32_com.c +++ b/SEL32/sel32_com.c @@ -395,13 +395,17 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) return SNS_BSY; /* yes, return busy */ } - sim_debug(DEBUG_CMD, dptr, "CMD unit %x chan %x cmd %x", unit, chan, cmd); + sim_debug(DEBUG_CMD, &com_dev, "CMD unit %x chan %x cmd %x", unit, chan, cmd); /* process the commands */ switch (cmd & 0xFF) { case COM_INCH: /* 00 */ /* INCH command */ sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: CMD INCH\n", chan); - return SNS_CHNEND|SNS_DEVEND; /* all is well */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= (0x7f & COM_MSK); /* save 0x7f as INCH cmd command */ + uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ + sim_activate(uptr, 20); /* start us up */ +// return SNS_CHNEND|SNS_DEVEND; /* all is well */ break; /* write commands must use address 8-f */ @@ -444,7 +448,10 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) case COM_NOP: /* 0x03 */ /* NOP has do nothing */ sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x NOP\n", chan, cmd); uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ - return SNS_CHNEND|SNS_DEVEND; /* good return */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= (cmd & COM_MSK); /* save command */ + sim_activate(uptr, 20); /* start us up */ +// return SNS_CHNEND|SNS_DEVEND; /* good return */ break; case COM_SNS: /* 0x04 */ /* Sense (8 bytes) */ @@ -639,6 +646,17 @@ t_stat comi_srv(UNIT *uptr) int cmd = uptr->u3 & 0xff; uint32 cln = (uptr - coml_unit) & 0x7; /* use line # 0-7 for 8-15 */ + ln = uptr - com_unit; /* line # */ + sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd); + /* handle NOP and INCH cmds */ + sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd); + if (cmd == COM_NOP || cmd == 0x7f) { /* check for NOP or INCH */ + uptr->u3 &= LMASK; /* leave only chsa */ + sim_debug(DEBUG_CMD, &com_dev, "comi_srv NOP or INCH done chsa %x line %x cmd %x\n", chsa, ln, cmd); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ + return SCPE_OK; /* return */ + } + ln = uptr - com_unit; /* line # */ if ((com_unit[COMC].flags & UNIT_ATT) == 0){ /* attached? */ return SCPE_OK; @@ -723,6 +741,14 @@ t_stat como_srv(UNIT *uptr) int cmd = uptr->u3 & 0xff; /* get active cmd */ uint8 ch; + /* handle NOP and INCH cmds */ + sim_debug(DEBUG_CMD, &com_dev, "como_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd); + if (cmd == COM_NOP || cmd == 0x7f) { /* check for NOP or INCH */ + uptr->u3 &= LMASK; /* leave only chsa */ + sim_debug(DEBUG_CMD, &com_dev, "como_srv NOP or INCH done chsa %x line %x cmd %x\n", chsa, ln, cmd); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ + return SCPE_OK; /* return */ + } sim_debug(DEBUG_CMD, &com_dev, "como_srv entry 1 chsa %x line %x cmd %x\n", chsa, ln, cmd); if (cmd) { @@ -786,13 +812,15 @@ t_stat com_reset (DEVICE *dptr) { int32 i; - if (com_dev.flags & DEV_DIS) /* master disabled? */ - com_dev.flags |= DEV_DIS; /* disable lines */ +#ifndef JUNK + if (com_dev.flags & DEV_DIS) /* master disabled? */ + com_dev.flags |= DEV_DIS; /* disable lines */ else com_dev.flags &= ~DEV_DIS; - if (com_unit[COMC].flags & UNIT_ATT) /* master att? */ - sim_clock_coschedule(&com_unit[0], 200); /* activate */ - for (i = 0; i < COM_LINES; i++) /* reset lines */ +#endif + if (com_unit[COMC].flags & UNIT_ATT) /* master att? */ + sim_clock_coschedule(&com_unit[0], 200); /* activate */ + for (i = 0; i < COM_LINES; i++) /* reset lines */ com_reset_ln(i); return SCPE_OK; } @@ -808,6 +836,7 @@ t_stat com_attach(UNIT *uptr, CONST char *cptr) r = tmxr_attach(&com_desc, uptr, cptr); /* attach */ if (r != SCPE_OK) /* error? */ return r; /* return error */ + sim_debug(DEBUG_CMD, &com_dev, "com_srv com is now attached chsa %x\n", chsa); sim_activate(uptr, 0); /* start poll at once */ return SCPE_OK; } diff --git a/SEL32/sel32_con.c b/SEL32/sel32_con.c index f2a48b1..56ebae3 100644 --- a/SEL32/sel32_con.c +++ b/SEL32/sel32_con.c @@ -30,6 +30,7 @@ Change History: 12/10/2018 - force input chars to upper case if lower case + 07/18/2019 - generate interrupt for INCH/NOP commands for UTX */ @@ -166,12 +167,16 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { if ((uptr->u3 & CON_MSK) != 0) /* is unit busy */ return SNS_BSY; /* yes, return busy */ -//fprintf(stderr, "COM process command %x\n", cmd); + sim_debug(DEBUG_CMD, &con_dev, "con_startcmd chan %x cmd %x enter\n", chan, cmd); /* process the commands */ switch (cmd & 0xFF) { case CON_INCH: /* 0x00 */ /* INCH command */ sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd INCH\n", chan); - return SNS_CHNEND|SNS_DEVEND; /* all is well */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= CON_MSK; /* save INCH command as 0xff */ + uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ + sim_activate(uptr, 20); /* start us off */ + return 0; /* no status change */ break; case CON_RWD: /* 0x37 */ /* TOF and write line */ @@ -184,7 +189,7 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { uptr->u3 &= LMASK; /* leave only chsa */ uptr->u3 |= (cmd & CON_MSK); /* save command */ uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ - sim_activate(uptr, 20); /* TRY 06-09-18 */ + sim_activate(uptr, 20); /* start us off */ return 0; /* no status change */ break; @@ -203,12 +208,16 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { atbuf = 0; /* reset attention buffer */ uptr->u4 = 0; /* no I/O yet */ uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ + sim_activate(uptr, 20); /* start us off */ return 0; break; case CON_NOP: /* 0x03 */ /* NOP has do nothing */ uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ - return SNS_CHNEND|SNS_DEVEND; /* good return */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= (cmd & CON_MSK); /* save command */ + sim_activate(uptr, 20); /* start us off */ + return 0; /* no status change */ break; case CON_CON: /* 0x1f */ /* Connect, return Data Set ready */ @@ -217,7 +226,7 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { return SNS_CHNEND|SNS_DEVEND; /* good return */ break; - case CON_DIS: /* 0x23 */ /* NOP has do nothing */ + case CON_DIS: /* 0x23 */ /* Disconnect has do nothing */ sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x NOP\n", chan, cmd); uptr->u5 &= ~(SNS_DSR|SNS_DCD); /* Data set not ready */ return SNS_CHNEND|SNS_DEVEND; /* good return */ @@ -233,8 +242,8 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { break; default: /* invalid command */ -//fprintf(stderr, "Invalid command %x\n", cmd); uptr->u5 |= SNS_CMDREJ; /* command rejected */ + sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Invalid command Sense %02x\n", chan, uptr->u5); return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */ break; } @@ -247,10 +256,18 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) { /* Handle output transfers for console */ t_stat con_srvo(UNIT *uptr) { uint16 chsa = GET_UADDR(uptr->u3); - int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */ + int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */ int cmd = uptr->u3 & CON_MSK; uint8 ch; + sim_debug(DEBUG_CMD, &con_dev, "con_srvo enter chsa %x cmd = %x\n", chsa, cmd); + if ((cmd == CON_NOP) || (cmd == CON_MSK)) { /* NOP has to do nothing */ + uptr->u3 &= LMASK; /* nothing left, command complete */ + sim_debug(DEBUG_CMD, &con_dev, "con_srvo NOP or INCH chsa %x cmd = %x\n", chsa, cmd); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ + return SCPE_OK; + } + if ((cmd == CON_WR) || (cmd == CON_RWD)) { /* Write to device */ if (chan_read_byte(chsa, &ch)) { /* get byte from memory */ @@ -258,8 +275,8 @@ t_stat con_srvo(UNIT *uptr) { chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ } else { sim_debug(DEBUG_CMD, &con_dev, "con_srvo write %d: putch %02x %c\n", unit, ch, ch); - sim_putchar(ch); /* output next char to device */ - sim_activate(uptr, 20); /* TRY 07-18-18 */ + sim_putchar(ch); /* output next char to device */ + sim_activate(uptr, 20); /* start us off */ } } return SCPE_OK; @@ -273,6 +290,15 @@ t_stat con_srvi(UNIT *uptr) { uint8 ch; t_stat r; + sim_debug(DEBUG_CMD, &con_dev, "con_srvi enter chsa %x cmd = %x\n", chsa, cmd); + + if ((cmd == CON_NOP) || (cmd == CON_MSK)) { /* NOP has do nothing */ + uptr->u3 &= LMASK; /* nothing left, command complete */ + sim_debug(DEBUG_CMD, &con_dev, "con_srvi NOP or INCH chsa %x cmd = %x\n", chsa, cmd); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ + /* drop through to poll input */ + } + switch (cmd) { case CON_RD: /* 0x02 */ /* read from device */ diff --git a/SEL32/sel32_disk.c b/SEL32/sel32_disk.c index 10841f7..4737d26 100644 --- a/SEL32/sel32_disk.c +++ b/SEL32/sel32_disk.c @@ -119,9 +119,9 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option /* u4 - sector target address register (STAR) */ /* Holds the current cylinder, head(track), sector */ -#define DISK_CYL 0xFFFF0000 /* cylinder mask */ -#define DISK_TRACK 0x0000FF00 /* track mask */ -#define DISK_SECTOR 0x000000ff /* sector mask */ +#define DISK_CYL 0xFFFF0000 /* cylinder mask */ +#define DISK_TRACK 0x0000FF00 /* track mask */ +#define DISK_SECTOR 0x000000ff /* sector mask */ /* u5 */ /* Sense byte 0 - mode register */ @@ -410,7 +410,7 @@ uint8 disk_preio(UNIT *uptr, uint16 chan) return SNS_BSY; } - sim_debug(DEBUG_CMD, dptr, "dsk_preio unit=%d\n", unit); + sim_debug(DEBUG_CMD, dptr, "dsk_preio unit=%d OK\n", unit); return 0; /* good to go */ } @@ -435,7 +435,7 @@ uint8 disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) if ((uptr->u3 & 0xff00) != 0) { /* if any status info, we are busy */ return SNS_BSY; } - sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD 2 unit=%d %02x\n", unit, cmd); + sim_debug(DEBUG_CMD, dptr, "disk_startcmd CMD continue unit=%d %02x\n", unit, cmd); if ((uptr->flags & UNIT_ATT) == 0) { /* see if unit is attached */ if (cmd == DSK_SNS) { /* not attached, is cmd Sense 0x04 */ @@ -487,7 +487,7 @@ dosns: uptr->u5 &= 0xff000000; /* clear status bytes, but leave mode data */ return SNS_CHNEND|SNS_DEVEND; } - if (cmd == 0x0) /* INCH cmd gives unit check */ + if (cmd == 0x0) /* INCH cmd gives unit check here */ return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; uptr->u5 |= (SNS_INTVENT|SNS_CMDREJ); /* set new error status */ @@ -521,33 +521,38 @@ dosns: up++; /* next unit for this device */ } sim_debug(DEBUG_CMD, dptr, "disk_startcmd done inch cmd addr %x\n", addr); - return SNS_CHNEND|SNS_DEVEND; - break; + uptr->u3 |= DSK_CMDMSK; /* use 0xff for inch, just need int */ + sim_activate(uptr, 20); /* start things off */ + return 0; } case DSK_SCK: /* Seek command 0x07 */ case DSK_XEZ: /* Rezero & Read IPL record 0x1f */ - uptr->u3 &= ~(DSK_STAR); /* show we do not have seek STAR in u4 */ + uptr->u3 &= ~(DSK_STAR); /* show we do not have seek STAR in u4 */ case DSK_WD: /* Write command 0x01 */ case DSK_RD: /* Read command 0x02 */ case DSK_LMR: /* read mode register */ - uptr->u3 |= cmd; /* save cmd */ - sim_debug(DEBUG_CMD, dptr, "disk_startcmd done with disk seek r/w cmd %x addr %x\n", cmd, addr); - sim_activate(uptr, 20); /* start things off */ + uptr->u3 |= cmd; /* save cmd */ + sim_debug(DEBUG_CMD, dptr, "disk_startcmd starting disk seek r/w cmd %x addr %x\n", cmd, addr); + sim_activate(uptr, 20); /* start things off */ return 0; - case DSK_NOP: /* NOP 0x03 */ - return SNS_CHNEND|SNS_DEVEND; /* return OK */ + case DSK_NOP: /* NOP 0x03 */ + uptr->u3 |= cmd; /* save cmd */ + sim_activate(uptr, 20); /* start things off */ + return 0; - case DSK_SNS: /* Sense 0x04 */ - goto dosns; /* use code above */ + case DSK_SNS: /* Sense 0x04 */ + uptr->u3 |= cmd; /* save cmd */ + sim_activate(uptr, 20); /* start things off */ +// goto dosns; /* use code above */ break; } sim_debug(DEBUG_CMD, dptr, "disk_startcmd done with disk_startcmd %x addr %x u5 %x\n", cmd, addr, uptr->u5); - if (uptr->u5 & 0xff) + if (uptr->u5 & 0xff) /* any other cmd is error */ return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; - sim_activate(uptr, 20); /* start things off */ + sim_activate(uptr, 20); /* start things off */ return SNS_CHNEND|SNS_DEVEND; } @@ -583,26 +588,33 @@ t_stat disk_srv(UNIT * uptr) sim_debug(DEBUG_CMD, dptr, "disk_srv cmd=%x chsa %04x count %x\n", cmd, chsa, chp->ccw_count); switch (cmd) { - case 0: /* No command, stop disk */ - break; + case 0: /* No command, stop disk */ + break; + + case DSK_CMDMSK: /* use 0xff for inch, just need int */ + case DSK_NOP: /* NOP 0x03 */ + uptr->u3 &= ~(0xffff); /* remove old cmd */ + sim_debug(DEBUG_CMD, dptr, "disk_srv cmd=%x chsa %04x count %x completed\n", cmd, chsa, chp->ccw_count); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* return OK */ + break; case DSK_SNS: /* 0x4 */ - ch = uptr->u5 & 0xff; - sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 1 %x\n", unit, ch); - chan_write_byte(chsa, &ch) ; - ch = (uptr->u5 >> 8) & 0xff; - sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 2 %x\n", unit, ch); - chan_write_byte(chsa, &ch) ; - ch = 0; - sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 3 %x\n", unit, ch); - chan_write_byte(chsa, &ch) ; - ch = unit; - sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 4 %x\n", unit, ch); - chan_write_byte(chsa, &ch) ; - ch = 4; - uptr->u3 &= ~(0xff00); - chan_end(chsa, SNS_CHNEND|SNS_DEVEND); - break; + ch = uptr->u5 & 0xff; + sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 1 %x\n", unit, ch); + chan_write_byte(chsa, &ch) ; + ch = (uptr->u5 >> 8) & 0xff; + sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 2 %x\n", unit, ch); + chan_write_byte(chsa, &ch) ; + ch = 0; + sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 3 %x\n", unit, ch); + chan_write_byte(chsa, &ch) ; + ch = unit; + sim_debug(DEBUG_DETAIL, dptr, "dsk_srv sense unit=%d 4 %x\n", unit, ch); + chan_write_byte(chsa, &ch) ; + ch = 4; + uptr->u3 &= ~(0xff00); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); + break; case DSK_SCK: /* Seek cylinder, track, sector 0x07 */ diff --git a/SEL32/sel32_mt.c b/SEL32/sel32_mt.c index c8d2a6f..4b7da5a 100644 --- a/SEL32/sel32_mt.c +++ b/SEL32/sel32_mt.c @@ -362,7 +362,7 @@ UNIT mta_unit[] = { 0, /* uint16 us9 */ /* device specific */ 0, /* uint16 us10 */ /* device specific */ NULL, /* void *tmxr */ /* TMXR linkage */ - NULL, /* t_bool(*cancel)(UNIT *) *//* Cancel I/O routine */ + 0, /* t_bool(*cancel)(UNIT *) *//* Cancel I/O routine */ 0, /* double usecs_remaining */ /* time balance for long delays */ NULL, /* char *uname */ /* Unit name */ }, @@ -482,7 +482,7 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd entry chan %x cmd %x\n", chan, cmd); if (mt_busy[GET_DEV_BUF(dptr->flags)] != 0 || (uptr->u3 & MT_CMDMSK) != 0) { - sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd busy chan %d cmd %x\n", chan, cmd); + sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd busy chan %x cmd %x\n", chan, cmd); uptr->flags |= MT_BUSY; /* Flag we need to send CUE */ return SNS_BSY; } @@ -493,14 +493,12 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) case 0x0: /* INCH command */ /* u4 has INCH buffer address and us9 the count */ /* just return OK and channel software will use u4 as status buffer */ - sim_debug(DEBUG_DETAIL, &mta_dev, "mt_startcmd INCH done unit %x cmd %x\n", unit, cmd); - return SNS_CHNEND|SNS_DEVEND; - break; - + sim_debug(DEBUG_DETAIL, &mta_dev, "mt_startcmd INCH done unit %x cmd %x\n", unit, cmd); + /* UTX_needs_interrupt */ + cmd = MT_CMDMSK; /* insert INCH cmd as 0xff */ + /* fall through */ case 0x3: /* Tape motion commands */ - if (cmd == MT_NOP) { /* nop */ - return SNS_CHNEND|SNS_DEVEND; /* done doing nothing */ - } + /* UTX_needs_interrupt */ /* fall through */ case 0x1: /* Write command */ case 0x2: /* Read command */ @@ -521,20 +519,11 @@ uint8 mt_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) uptr->u3 &= ~(MT_CMDMSK); /* clear out last cmd */ uptr->u3 |= cmd & MT_CMDMSK; /* insert new cmd */ CLR_BUF(uptr); /* buffer is empty */ - uptr->u4 = 0; /* reset buffer position pointer */ -// sim_activate(uptr, 100); /* Start unit off */ - sim_activate(uptr, 10); /* Start unit off */ + /* INCH cmd has iNCH buffer address in u4, so leave it */ + if (cmd != MT_CMDMSK) + uptr->u4 = 0; /* reset buffer position pointer */ + sim_activate(uptr, 100); /* Start unit off */ mt_busy[GET_DEV_BUF(dptr->flags)] = 1; /* show we are busy */ - if ((cmd & 0x3) == 0x3) { /* Quick end channel on control */ - if (cmd != MT_SETM) { /* mode set command */ - sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd ret CHNEND chan %x unit %x cmd %x\n", chan, unit, cmd); -//fprintf(stderr, "mt_startcmd ret CHNEND chan %x unit %x cmd %x\n", chan, unit, cmd); - return 0; -// return SNS_CHNEND; - } - return SNS_CHNEND; -// return SNS_CHNEND|SNS_DEVEND; /* done */ - } sim_debug(DEBUG_EXP, &mta_dev, "mt_startcmd sense return 0 chan %x cmd %x\n", chan, cmd); return 0; @@ -597,7 +586,7 @@ t_stat mt_error(UNIT *uptr, uint16 addr, t_stat r, DEVICE *dptr) } /* Handle processing of tape requests. */ -t_stat mt_srv(UNIT * uptr) +t_stat mt_srv(UNIT *uptr) { uint16 addr = GET_UADDR(uptr->u3); DEVICE *dptr = find_dev_from_unit(uptr); @@ -616,9 +605,16 @@ t_stat mt_srv(UNIT * uptr) } switch (cmd) { - case MT_INCH: /* 0x00 */ /* INCH is for channel, nothing for us */ + case MT_CMDMSK: /* 0x0ff for inch 0x00 */ /* INCH is for channel, nothing for us */ +// case MT_INCH: /* 0x00 */ /* INCH is for channel, nothing for us */ + /* uptr->u4 has INCH buffer address, just leave it */ sim_debug(DEBUG_CMD, &mta_dev, "mt_srv cmd 0 INCH unit=%d\n", unit); - //NEWCODE follows, but not ever executed! + uptr->u3 &= ~MT_CMDMSK; /* clear the cmd */ + mt_busy[bufnum] &= ~1; /* make our buffer not busy */ + chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */ + break; + + case MT_NOP: /* 0x03 */ /* NOP motion command */ uptr->u3 &= ~MT_CMDMSK; /* clear the cmd */ mt_busy[bufnum] &= ~1; /* make our buffer not busy */ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */ @@ -655,7 +651,7 @@ t_stat mt_srv(UNIT * uptr) uptr->u3 &= ~(MT_CMDMSK|MT_READDONE); /* clear all but readdone & cmd */ mt_busy[bufnum] &= ~1; /* not busy anymore */ chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* set chan end, dev end status */ - sim_debug(DEBUG_CMD, &mta_dev, "mt_srv READ %x char complete unit=%d\n", uptr->u4, unit); + sim_debug(DEBUG_CMD, &mta_dev, "mt_srv READ %x char complete unit=%d sense %x\n", uptr->u4, unit, uptr->u5); break; } /* read is not completed, get an input char */ @@ -667,6 +663,7 @@ t_stat mt_srv(UNIT * uptr) uptr->u3 &= ~(MT_CMDMSK|MT_READDONE); /* clear all but readdone & cmd */ return mt_error(uptr, addr, r, dptr); /* process any error & return status */ } + uptr->u5 &= ~(SNS_LOAD|SNS_EOT); /* reset BOT & EOT */ uptr->u4 = 0; /* reset buffer position */ uptr->hwmark = reclen; /* set buffer chars read in */ sim_debug(DEBUG_DETAIL, &mta_dev, "mt_srv READ fill buffer complete count %x\n", reclen); @@ -694,7 +691,7 @@ t_stat mt_srv(UNIT * uptr) } else { sim_debug(DEBUG_DATA, &mta_dev, "Read data @2 unit %d cnt %x ch %02x hwm %x\n", unit, uptr->u4, ch, uptr->hwmark); - if ((uint32)uptr->u4 >= uptr->hwmark) { /* In IRG */ + if ((uint32)uptr->u4 >= uptr->hwmark) { /* In IRG */ /* Handle end of record */ uptr->u3 &= ~MT_CMDMSK; /* clear the cmd */ mt_busy[bufnum] &= ~1; /* set not busy */ @@ -752,7 +749,6 @@ t_stat mt_srv(UNIT * uptr) mt_buffer[bufnum][uptr->u4++] = ch; sim_debug(DEBUG_DATA, &mta_dev, "Write data unit=%d %d %02x\n", unit, uptr->u4, ch); uptr->hwmark = uptr->u4; -//FIX break; } sim_activate(uptr, 20); break; @@ -822,7 +818,6 @@ t_stat mt_srv(UNIT * uptr) sim_debug(DEBUG_DETAIL, &mta_dev, "Write Mark unit=%d\n", unit); uptr->u3 &= ~(MT_CMDMSK); r = sim_tape_wrtmk(uptr); -// set_devattn(addr, SNS_DEVEND); chan_end(addr, SNS_DEVEND); mt_busy[bufnum] &= ~1; } @@ -842,23 +837,21 @@ t_stat mt_srv(UNIT * uptr) sim_activate(uptr, 50); break; case 1: - uptr->u4++; - sim_debug(DEBUG_DETAIL, &mta_dev, "Backspace rec unit %x u4 %x\n", unit, uptr->u4); - r = sim_tape_sprecr(uptr, &reclen); - /* We don't set EOF on BSR */ - if (r == MTSE_TMK) { - uptr->u4++; - sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n"); - sim_activate(uptr, 50); - } else { - sim_debug(DEBUG_DETAIL, &mta_dev, "Backspace reclen %x\n", reclen); -// sim_activate(uptr, 10 + (10 * reclen)); + uptr->u4++; + sim_debug(DEBUG_DETAIL, &mta_dev, "Backspace rec unit %x u4 %x\n", unit, uptr->u4); + r = sim_tape_sprecr(uptr, &reclen); + /* We don't set EOF on BSR */ + if (r == MTSE_TMK) { + uptr->u4++; + sim_debug(DEBUG_DETAIL, &mta_dev, "MARK\n"); + sim_activate(uptr, 50); + } else { + sim_debug(DEBUG_DETAIL, &mta_dev, "Backspace reclen %x\n", reclen); sim_activate(uptr, 50); } break; case 2: uptr->u3 &= ~(MT_CMDMSK); -// chan_end(addr, SNS_CHNEND); mt_busy[bufnum] &= ~1; chan_end(addr, SNS_CHNEND|SNS_DEVEND); break; @@ -894,7 +887,6 @@ t_stat mt_srv(UNIT * uptr) uptr->u4+= 2; sim_activate(uptr, 50); } else { -// sim_activate(uptr, 10 + (10 * reclen)); sim_activate(uptr, 20); } break; @@ -935,7 +927,6 @@ t_stat mt_srv(UNIT * uptr) break; case 2: uptr->u3 &= ~(MT_CMDMSK); -// set_devattn(addr, SNS_DEVEND); mt_busy[bufnum] &= ~1; chan_end(addr, SNS_DEVEND); break; @@ -956,13 +947,10 @@ t_stat mt_srv(UNIT * uptr) switch(uptr->u4) { case 0: uptr->u4++; -// sim_activate(uptr, 500); sim_activate(uptr, 50); -//fprintf(stderr, "Start adv file unit %d cnt %d\n", unit, uptr->u4); break; case 1: sim_debug(DEBUG_DETAIL, &mta_dev, "Skip rec unit=%d\n", unit); -//fprintf(stderr, "Skip 1 rec unit=%d cnt %d reclen %d\n", unit, uptr->u4, reclen); r = sim_tape_sprecf(uptr, &reclen); if (r == MTSE_TMK) { uptr->u4++; @@ -974,14 +962,11 @@ t_stat mt_srv(UNIT * uptr) sim_activate(uptr, 50); } else { sim_debug(DEBUG_DETAIL, &mta_dev, "%d\n", reclen); -// sim_activate(uptr, 10 + (10 * reclen)); sim_activate(uptr, 50); } break; case 2: -//fprintf(stderr, "Skip 2 rec unit=%d cnt %d reclen %d\n", unit, uptr->u4, reclen); uptr->u3 &= ~(MT_CMDMSK); -// chan_end(addr, SNS_DEVEND); mt_busy[bufnum] &= ~1; chan_end(addr, SNS_CHNEND|SNS_DEVEND); /* we are done dev|chan end */ sim_debug(DEBUG_DETAIL, &mta_dev, "Skip done unit=%d\n", unit); @@ -1001,7 +986,6 @@ t_stat mt_srv(UNIT * uptr) uptr->u5 |= SNS_CMDREJ; uptr->u3 &= ~MT_CMDMSK; mt_busy[bufnum] &= ~1; -// set_devattn(addr, SNS_DEVEND|SNS_UNITCHK); chan_end(addr, SNS_DEVEND|SNS_UNITCHK); } else { uptr->u4 ++; @@ -1016,7 +1000,6 @@ t_stat mt_srv(UNIT * uptr) break; case 2: uptr->u3 &= ~(MT_CMDMSK); -// set_devattn(addr, SNS_DEVEND); mt_busy[bufnum] &= ~1; chan_end(addr, SNS_DEVEND); } @@ -1025,13 +1008,10 @@ t_stat mt_srv(UNIT * uptr) case MT_REW: /* 0x23 */ /* rewind tape */ if (uptr->u4 == 0) { uptr->u4++; -// sim_activate(uptr, 30000); -//fprintf(stderr, "Start rewind unit %d\n", unit); sim_debug(DEBUG_DETAIL, &mta_dev, "Start rewind unit %d\n", unit); - sim_activate(uptr, 500); + sim_activate(uptr, 1500); } else { sim_debug(DEBUG_DETAIL, &mta_dev, "Rewind complete unit %d\n", unit); -//fprintf(stderr, "Rewind complete unit %d\n", unit); uptr->u3 &= ~(MT_CMDMSK); r = sim_tape_rewind(uptr); uptr->u5 |= SNS_LOAD; /* set BOT */ From 90939994bfc5cd10e458b451803242251886e185 Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:26:40 -0700 Subject: [PATCH 04/10] SEL32: Correct basemode instruction decoding for several instructions. SEL32: Remode unused debug code. --- SEL32/sel32_cpu.c | 446 ++++++++++++++++++++++++++++------------------ 1 file changed, 270 insertions(+), 176 deletions(-) diff --git a/SEL32/sel32_cpu.c b/SEL32/sel32_cpu.c index 83e7dd7..f40f255 100644 --- a/SEL32/sel32_cpu.c +++ b/SEL32/sel32_cpu.c @@ -29,6 +29,20 @@ #include "sel32_defs.h" +/* instruction trace controls */ +//#define UTXBUG /* debugging for UTX */ +//#define TRME /* set defined to enable instruction trace */ +//#define TRMEMPX /* set defined to enable instruction trace for MPX */ +//#undef TRME +int traceme = 0; /* dynamic trace function */ +/* start on second diag starting */ +//int trstart = 4; /* count of when to start tracing */ +/* start on J.INIT */ +//int trstart = 12; /* count of when to start tracing */ +//int trstart = 0x8000000; /* count of when to start tracing */ +//int trstart = 37; /* count of when to start tracing */ +int trstart = 0; /* count of when to start tracing */ + /* 32/7x PSW/PSD Mode Trap/Interrupt Priorities */ /* Relative Logical Int Vect TCW IOCD Description */ /* Priority Priority Location Addr Addr */ @@ -164,19 +178,6 @@ /* Wd 4 - Input/Output Command List Address (IOCL) for the Class F I/O CHannel */ /* Wd 5 - 24 bit real address of the channel status word */ -/* instruction trace controls */ -//#define TRME /* set defined to enable instruction trace */ -//#define TRMEMPX /* set defined to enable instruction trace in MPX */ -//#undef TRME -int traceme = 0; /* dynamic trace function */ -/* start on second diag starting */ -//int trstart = 4; /* count of when to start tracing */ -/* start on J.INIT */ -//int trstart = 12; /* count of when to start tracing */ -//int trstart = 0x8000000; /* count of when to start tracing */ -//int trstart = 37; /* count of when to start tracing */ -int trstart = 0; /* count of when to start tracing */ - /* CPU registers, map cache, spad, and other variables */ int cpu_index; /* Current CPU running */ uint32 PSD[2]; /* the PC for the instruction */ @@ -449,7 +450,7 @@ int nobase_mode[] = { /* 70 74 78 7C */ /* SRL SRC SRAD SRLD */ - SD|HLF, SD|HLF, HLF, HLF, + HLF, HLF, HLF, HLF, /* 80 84 88 8C */ /* LEAR ANM ORM EOM */ @@ -487,7 +488,7 @@ int nobase_mode[] = { int base_mode[] = { /* 00 04 08 0C */ /* 00 AND, OR, EOR */ - HLF, SCC|RR|SD|HLF, SCC|RR|SD|HLF, SCC|RR|SD|HLF, + HLF, SCC|R1|RR|SD|HLF, SCC|R1|RR|SD|HLF, SCC|R1|RR|SD|HLF, /* 10 14 18 1C */ /* SACZ CMR xBR SRx */ HLF, HLF, HLF, HLF, @@ -496,13 +497,13 @@ int base_mode[] = { HLF, HLF, HLF, HLF, /* 30 34 38 3C */ /* LA FLRop SUR */ - INV, INV, SD|HLF, SD|HLF, + INV, INV, HLF, HLF, /* 40 44 48 4C */ /* */ INV, INV, INV, INV, /* 50 54 58 5C */ /* LA BASE BASE CALLM */ - SD|ADR, SM|ADR, SB|RM|ADR, ADR, + SD|ADR, SM|ADR, SB|ADR, RM|ADR, /* 60 64 68 6C */ /* */ @@ -514,36 +515,35 @@ int base_mode[] = { /* LEAR ANM ORM EOM */ /* 80 84 88 8C */ - SD|ADR, SD|RNX|ADR, SD|RNX|ADR, SD|RNX|ADR, + SD|ADR, SD|RR|RNX|ADR, SD|RR|RNX|ADR, SD|RR|RNX|ADR, /* CAM CMM SBM ZBM */ /* 90 94 98 9C */ - RM|ADR, RM|ADR, ADR, ADR, + SCC|RR|RM|ADR, RR|RM|ADR, ADR, ADR, /* A0 A4 A8 AC */ /* ABM TBM EXM L */ - ADR, ADR, ADR, SD|RM|ADR, + ADR, ADR, ADR, SCC|SD|RM|ADR, /* B0 B4 B8 BC */ /* LM LN ADM SUM */ - SD|RM|ADR, SD|RM|ADR, SD|RM|ADR, SD|RM|ADR, + SCC|SD|RM|ADR, SCC|SD|RM|ADR, SCC|SD|RR|RM|ADR, SCC|SD|RR|RM|ADR, /* C0 C4 C8 CC */ /* MPM DVM IMM LF */ - SD|RM|ADR, RM|ADR, IMM, ADR, + SCC|SD|RM|ADR, RM|ADR, IMM, ADR, /* D0 D4 D8 DC */ /* LEA ST STM STFBR */ - INV, RR|SM|ADR, SM|ADR, ADR, + INV, RR|SM|ADR, RR|SM|ADR, ADR, /* E0 E4 E8 EC */ /* ADF MPF ARM BCT */ - ADR, ADR, SM|RM|ADR, ADR, + ADR, ADR, SM|RR|RNX|ADR, ADR, /* F0 F4 F8 FC */ /* BCF BI MISC IO */ -//// ADR, RR|SB|WRD, ADR, IMM, - ADR, RR|SD|WRD, ADR, IMM, + ADR, RR|SD|WRD, ADR, IMM, }; /* set up the map registers for the current task in the cpu */ @@ -1056,6 +1056,11 @@ wait_loop: reason = STOP_IBKPT; break; } +///*UTX*/ if (M[0] == 0xfd023f0c) { +///*UTX*/ if ((M[0] != 0xec0000ad) && (traceme > 0)) { +// reason = STOP_IBKPT; +// break; +// } sim_interval--; /* count down */ @@ -1514,7 +1519,7 @@ exec: } if (wait4int == 0) { time_t result = time(NULL); - sim_debug(DEBUG_CMD, &cpu_dev, "Starting WAIT mode %u\n", (uint32)result); + sim_debug(DEBUG_CMD, &cpu_dev, "Starting WAIT mode %x\n", (uint32)result); } wait4int = 1; /* show we are waiting for interrupt */ /* tell simh we will be waiting */ @@ -1679,7 +1684,7 @@ exec: break; case 0x10>>2: /* 0x10 HLF - HLF */ /* CAR or (basemode SACZ ) */ - if (modes & BASEBIT) { /* handle basemode SACZ instruction */ + if ((modes & BASEBIT) && (IR & 0x8000)) { /* handle basemode SACZ instruction */ sacz: /* non basemode SCZ enters here */ temp = GPR[reg]; /* get destination reg contents to shift */ CC = 0; /* zero the CC's */ @@ -1706,7 +1711,7 @@ sacz: /* non basemode SCZ enters h PSD1 &= 0x87FFFFFE; /* clear the old CC's */ PSD1 |= (CC & 0x78000000); /* update the CC's in the PSD */ } else { - /* handle non basemode CAR instr */ + /* handle non basemode/basemode CAR instr */ if ((int32)GPR[reg] < (int32)GPR[sreg]) CC = CC3BIT; /* negative */ else @@ -1760,14 +1765,50 @@ sbr: /* handle basemode too */ case 0x1C>>2: /* 0x1C HLF - HLF */ /* ZBR (basemode SRA, SRL, SLA, SLL) */ if (modes & BASEBIT) { /* handle basemode SRA, SRL, SLA, SLL */ - if ((opr & 0x60) == 0x00) /* SRA instruction */ - goto sra; /* use nonbase SRA code */ - if ((opr & 0x60) == 0x20) /* SRL instruction */ - goto srl; /* use nonbase SRL code */ - if ((opr & 0x60) == 0x40) /* SLA instruction */ - goto sla; /* use nonbase SLA code */ - if ((opr & 0x60) == 0x60) /* SLL instruction */ - goto sll; /* use nonbase SLL code */ + bc = opr & 0x1f; /* get bit shift count */ + if ((opr & 0x60) == 0x00) { /* SRA instruction */ + temp = GPR[reg]; /* get reg value to shift */ + t = temp & FSIGN; /* sign value */ + for (ix=0; ix>= 1; /* shift bit 0 right one bit */ + temp |= t; /* restore original sign bit */ + } + GPR[reg] = temp; /* save the new value */ + break; + } + if ((opr & 0x60) == 0x20) { /* SRL instruction */ + GPR[reg] >>= bc; /* value to be output */ + break; + } + if ((opr & 0x60) == 0x40) { /* SLA instruction */ + temp = GPR[reg]; /* get reg value to shift */ + t = temp & FSIGN; /* sign value */ + ovr = 0; /* set ovr off */ + for (ix=0; ix>2: /* 0x20 HLF - HLF */ /* ABR (basemode SRAD, SRLD, SLAD, SLLD) */ - if (modes & BASEBIT) { /* handle basemode SRA, SRL, SLA, SLL */ - if ((opr & 0x60) == 0x00) /* SRAD instruction */ - goto sra; /* use nonbase SRAD code */ - if ((opr & 0x60) == 0x20) /* SRLD instruction */ - goto srl; /* use nonbase SRLD code */ - if ((opr & 0x60) == 0x40) /* SLAD instruction */ - goto sla; /* use nonbase SLAD code */ - if ((opr & 0x60) == 0x60) /* SLLD instruction */ - goto sll; /* use nonbase SLLD code */ + if (modes & BASEBIT) { /* handle basemode SRAD, SRLD, SLAD, SLLD */ + if (reg & 1) { /* see if odd reg specified */ + TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ + goto newpsd; /* go execute the trap now */ + } + dest = (t_uint64)GPR[reg+1]; /* get low order reg value */ + dest |= (((t_uint64)GPR[reg]) << 32); /* insert upper reg value */ + bc = opr & 0x1f; /* get bit shift count */ + source = dest & DMSIGN; /* 64 bit sign value */ + switch (opr & 0x60) { + case 0x00: /* SRAD instruction */ + for (ix=0; ix>= 1; /* shift bit 0 right one bit */ + dest |= source; /* restore original sign bit */ + } + break; + + case 0x20: /* SRLD */ + dest >>= bc; /* shift right #bits */ + break; + + case 0x40: /* SLAD instruction */ + ovr = 0; /* set ovr off */ + for (ix=0; ix>32) & FMASK);/* save the hi order reg */ + PSD1 &= 0x87FFFFFE; /* clear the old CC's */ + if (ovr) + PSD1 |= BIT1; /* CC1 in PSD */ + /* the arithmetic exception will be handled */ + /* after instruction is completed */ + /* check for arithmetic exception trap enabled */ + if (ovr && (modes & AEXPBIT)) { + TRAPME = AEXPCEPT_TRAP; /* set the trap type */ +/*DIAG*/ goto newpsd; /* go execute the trap now */ + } + break; + + case 0x60: /* SLLD */ + dest <<= bc; /* shift left #bits */ + break; + } + GPR[reg+1] = (uint32)(dest & FMASK); /* save the low order reg */ + GPR[reg] = (uint32)((dest>>32) & FMASK);/* save the hi order reg */ + break; + } else { /* handle nonbase mode ABR */ abr: /* basemode ABR too */ /* move the byte field bits 14-15 to bits 27-28 */ @@ -1823,11 +1907,24 @@ abr: /* basemode ABR too */ case 0x24>>2: /* 0x24 HLF - HLF */ /* TBR (basemode SRC) */ if (modes & BASEBIT) { /* handle SRC basemode */ - if ((opr & 0x60) == 0x00) /* SRC instruction */ - goto src; /* use nonbase code */ - if ((opr & 0x60) == 0x40) /* SLC instruction */ - goto slc; /* use nonbase code */ - goto inv; /* else invalid */ + bc = opr & 0x1f; /* get bit shift count */ + temp = GPR[reg]; /* get reg value to shift */ + if ((opr & 0x60) == 0x40) { /* SLC instruction */ + for (ix=0; ix>= 1; /* shift the bit out */ + if (t) + temp |= BIT0; /* put in new sign bit */ + } + } + GPR[reg] = temp; /* shift result */ } else { /* handle TBR non basemode */ tbr: /* handle basemode TBR too */ /* move the byte field bits 14-15 to bits 27-28 */ @@ -2084,11 +2181,12 @@ tbr: /* handle basemode TBR too * } break; - case 0x38>>2: /* 0x38 HLF - SD|HLF */ /* REG - REG floating point */ + case 0x38>>2: /* 0x38 HLF - HLF */ /* REG - REG floating point */ switch(opr & 0xF) { case 0x0: /* ADR */ temp = GPR[reg]; /* reg contents specified by Rd */ addr = GPR[sreg]; /* reg contents specified by Rs */ +//fprintf(stderr, "ADR addr %x reg %x sreg %x temp %x\n", addr, reg, sreg, temp); t = (temp & FSIGN) != 0; /* set flag for sign bit not set in temp value */ t |= ((addr & FSIGN) != 0) ? 2 : 0; /* ditto for the reg value */ temp = temp + addr; /* add the values */ @@ -2410,14 +2508,13 @@ doovr4: TRAPME = AEXPCEPT_TRAP; /* set the trap type */ goto newpsd; /* go execute the trap now */ } -/// GPR[reg] = temp; /* temp has destination reg value */ -/// set_CCs(temp, ovr); /* set the CC's */ } break; case 0x3C>>2: /* 0x3C HLF - HLF */ /* SUR and SURM */ temp = GPR[reg]; /* get negative value to add */ addr = NEGATE32(GPR[sreg]); /* reg contents specified by Rs */ +//fprintf(stderr, "SUR addr %x reg %x sreg %x temp %x tot %x\n", addr, reg, sreg, temp, temp+addr); switch(opr & 0xF) { case 0x0: /* SUR */ t = (temp & FSIGN) != 0; /* set flag for sign bit not set in temp value */ @@ -2532,16 +2629,10 @@ doovr3: break; case 0x50>>2: /* 0x50 INV - SD|ADR */ /* LA basemode */ -//fprintf(stderr, "place @ LABR op = %.8x modes %x addr %lx\r\n", IR, modes, addr); +//fprintf(stderr, "place @ LABM op = %.8x modes %x addr %lx\r\n", IR, modes, addr); if ((modes & BASEBIT) == 0) /* see if nonbased */ goto inv; /* invalid instruction in nonbased mode */ -//fprintf(stderr, "place @ LABR op = %.8x modes %x addr %lx\r\n", IR, modes, addr); - if (modes & (BASEBIT|EXTDBIT)) { - dest = (t_uint64)addr; /* just pure 24 bit address */ - } else { - dest = (t_uint64)(addr | ((FC & 4) << 17)); /* F bit to bit 12 */ - } -//fprintf(stderr, "place @ LABR op = %.8x modes %x addr %lx\r\n", IR, modes, addr); + dest = (t_uint64)addr; /* just pure 24 bit address */ break; case 0x54>>2: /* 0x54 SM|ADR - INV */ /* (basemode STWBR) */ @@ -2557,20 +2648,21 @@ doovr3: case 0x58>>2: /* 0x58 SB|ADR - INV */ /* (basemode SUABR and LABR) */ if ((modes & BASEBIT) == 0) /* see if nonbased */ goto inv; /* invalid instruction in nonbased mode */ - if ((FC & 4) != 0) { /* see if SUABR F=0 */ + if ((FC & 4) == 0) { /* see if SUABR F=0 */ dest = BR[reg] - addr; /* subtract addr from the BR and store back to BR */ } else { /* LABR if F=1 */ dest = addr; /* addr goes to specified BR */ } break; - case 0x5C>>2: /* 0x5C RM|SB|ADR - INV */ /* (basemode LWBR and BSUBM) */ + case 0x5C>>2: /* 0x5C ADR - INV */ /* (basemode LWBR and BSUBM) */ if ((modes & BASEBIT) == 0) /* see if nonbased */ goto inv; /* invalid instruction in nonbased mode */ if (FC != 0) { /* word address only */ TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ goto newpsd; /* go execute the trap now */ } - if ((FC & 0x4) != 0x4) { /* this is a LWBR instruction */ + if ((FC & 0x4) == 0) { /* this is a LWBR instruction */ +//fprintf(stderr, "LWBR addr %x reg %x sreg %x source %lx dest %lx\n", addr, reg, sreg, source, dest); BR[reg] = (uint32)source; /* load memory location in BR */ } else { /* this is a CALLM/BSUBM instruction */ /* if Rd field is 0 (reg is b6-8), this is a BSUBM instruction */ @@ -2619,13 +2711,13 @@ doovr3: break; case 0x64>>2: /* 0x64 SD|HLF - INV */ /* NORD */ - if ((modes & BASEBIT)) { /* only for nonbased mode */ - TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */ - goto newpsd; /* handle trap */ + if ((modes & BASEBIT)) { /* only for nonbased mode */ + TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */ + goto newpsd; /* handle trap */ } - if (reg & 1) { /* see if odd reg specified */ - TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ - goto newpsd; /* go execute the trap now */ + if (reg & 1) { /* see if odd reg specified */ + TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ + goto newpsd; /* go execute the trap now */ } /* shift until upper 5 bits are neither 0 or all 1's */ /* merge the GPR[reg] & GPR[reg+1] into a 64bit value */ @@ -2638,121 +2730,113 @@ doovr3: case 0x68>>2: /* 0x68 HLF - INV */ /* non basemode SCZ */ if (modes & BASEBIT) - goto inv; /* invalid instruction */ - goto sacz; /* use basemode sacz instruction */ + goto inv; /* invalid instruction */ + goto sacz; /* use basemode sacz instruction */ case 0x6C>>2: /* 0x6C HLF - INV */ /* non basemode SRA & SLA */ if (modes & BASEBIT) - goto inv; /* invalid instruction */ -sra: -sla: - bc = opr & 0x1f; /* get bit shift count */ - temp = GPR[reg]; /* get reg value to shift */ - t = temp & FSIGN; /* sign value */ - if (opr & 0x0040) { /* is this SLA */ - ovr = 0; /* set ovr off */ + goto inv; /* invalid instruction */ + bc = opr & 0x1f; /* get bit shift count */ + temp = GPR[reg]; /* get reg value to shift */ + t = temp & FSIGN; /* sign value */ + if (opr & 0x0040) { /* is this SLA */ + ovr = 0; /* set ovr off */ for (ix=0; ix>= 1; /* shift bit 0 right one bit */ - temp |= t; /* restore original sign bit */ + temp >>= 1; /* shift bit 0 right one bit */ + temp |= t; /* restore original sign bit */ } - GPR[reg] = temp; /* save the new value */ + GPR[reg] = temp; /* save the new value */ } break; case 0x70>>2: /* 0x70 SD|HLF - INV */ /* non-basemode SRL & SLL */ if (modes & BASEBIT) - goto inv; /* invalid instruction in basemode */ -sll: -srl: - bc = opr & 0x1f; /* get bit shift count */ - temp = GPR[reg]; /* get reg value to shift */ - if (opr & 0x0040) /* is this SLL, bit 9 set */ - temp <<= bc; /* shift left #bits */ + goto inv; /* invalid instruction in basemode */ + bc = opr & 0x1f; /* get bit shift count */ + if (opr & 0x0040) /* is this SLL, bit 9 set */ + GPR[reg] <<= bc; /* shift left #bits */ else - temp >>= bc; /* shift right #bits */ - dest = temp; /* value to be output */ + GPR[reg] >>= bc; /* shift right #bits */ break; case 0x74>>2: /* 0x74 SD|HLF - INV */ /* non-basemode SRC & SLC */ if (modes & BASEBIT) - goto inv; /* invalid instruction in basemode */ -slc: -src: - bc = opr & 0x1f; /* get bit shift count */ - temp = GPR[reg]; /* get reg value to shift */ - if (opr & 0x0040) { /* is this SLC, bit 9 set */ + goto inv; /* invalid instruction in basemode */ + bc = opr & 0x1f; /* get bit shift count */ + temp = GPR[reg]; /* get reg value to shift */ + if (opr & 0x0040) { /* is this SLC, bit 9 set */ for (ix=0; ix>= 1; /* shift the bit out */ + t = temp & 1; /* get bit 31 status */ + temp >>= 1; /* shift the bit out */ if (t) - temp |= BIT0; /* put in new sign bit */ + temp |= BIT0; /* put in new sign bit */ } } - dest = temp; /* shift result */ + GPR[reg] = temp; /* shift result */ break; case 0x78>>2: /* 0x78 HLF - INV */ /* non-basemode SRAD & SLAD */ - if (modes & BASEBIT) /* Base mode? */ - goto inv; /* invalid instruction in basemode */ - if (reg & 1) { /* see if odd reg specified */ - TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ - goto newpsd; /* go execute the trap now */ + if (modes & BASEBIT) /* Base mode? */ + goto inv; /* invalid instruction in basemode */ + if (reg & 1) { /* see if odd reg specified */ + TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ + goto newpsd; /* go execute the trap now */ } - bc = opr & 0x1f; /* get bit shift count */ - dest = (t_uint64)GPR[reg+1]; /* get low order reg value */ + bc = opr & 0x1f; /* get bit shift count */ + dest = (t_uint64)GPR[reg+1]; /* get low order reg value */ dest |= (((t_uint64)GPR[reg]) << 32); /* insert upper reg value */ - source = dest & DMSIGN; /* 64 bit sign value */ - if (opr & 0x0040) { /* is this SLAD */ - ovr = 0; /* set ovr off */ + source = dest & DMSIGN; /* 64 bit sign value */ + if (opr & 0x0040) { /* is this SLAD */ + ovr = 0; /* set ovr off */ for (ix=0; ix>32) & FMASK);/* save the hi order reg */ - PSD1 &= 0x87FFFFFE; /* clear the old CC's */ + PSD1 &= 0x87FFFFFE; /* clear the old CC's */ if (ovr) - PSD1 |= BIT1; /* CC1 in PSD */ + PSD1 |= BIT1; /* CC1 in PSD */ /* the arithmetic exception will be handled */ /* after instruction is completed */ /* check for arithmetic exception trap enabled */ if (ovr && (modes & AEXPBIT)) { - TRAPME = AEXPCEPT_TRAP; /* set the trap type */ + TRAPME = AEXPCEPT_TRAP; /* set the trap type */ /*DIAG*/ goto newpsd; /* go execute the trap now */ } - } else { /* this is a SRAD */ + } else { /* this is a SRAD */ for (ix=0; ix>= 1; /* shift bit 0 right one bit */ - dest |= source; /* restore original sign bit */ + dest >>= 1; /* shift bit 0 right one bit */ + dest |= source; /* restore original sign bit */ } GPR[reg+1] = (uint32)(dest & FMASK); /* save the low order reg */ GPR[reg] = (uint32)((dest>>32) & FMASK);/* save the hi order reg */ @@ -2761,18 +2845,18 @@ src: case 0x7C>>2: /* 0x7C HLF - INV */ /* non-basemode SRLD & SLLD */ if (modes & BASEBIT) - goto inv; /* invalid instruction in basemode */ - if (reg & 1) { /* see if odd reg specified */ - TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ - goto newpsd; /* go execute the trap now */ + goto inv; /* invalid instruction in basemode */ + if (reg & 1) { /* see if odd reg specified */ + TRAPME = ADDRSPEC_TRAP; /* bad reg address, error */ + goto newpsd; /* go execute the trap now */ } - dest = (t_uint64)GPR[reg+1]; /* get low order reg value */ + dest = (t_uint64)GPR[reg+1]; /* get low order reg value */ dest |= (((t_uint64)GPR[reg]) << 32); /* insert upper reg value */ - bc = opr & 0x1f; /* get bit shift count */ - if (opr & 0x0040) /* is this SLL, bit 9 set */ - dest <<= bc; /* shift left #bits */ + bc = opr & 0x1f; /* get bit shift count */ + if (opr & 0x0040) /* is this SLL, bit 9 set */ + dest <<= bc; /* shift left #bits */ else - dest >>= bc; /* shift right #bits */ + dest >>= bc; /* shift right #bits */ GPR[reg+1] = (uint32)(dest & FMASK); /* save the low order reg */ GPR[reg] = (uint32)((dest>>32) & FMASK);/* save the hi order reg */ break; @@ -2781,12 +2865,12 @@ src: /* convert address to real physical address */ TRAPME = RealAddr(addr, &temp, &t); if (TRAPME != ALLOK) - goto newpsd; /* memory read error or map fault */ + goto newpsd; /* memory read error or map fault */ /* OS code says F bit is not transferred, so just ignore it */ /* DIAGS need it, so put it back */ - if (FC & 4) /* see if F bit was set */ - temp |= 0x01000000; /* set bit 7 of address */ - dest = temp; /* put in dest to go out */ + if (FC & 4) /* see if F bit was set */ + temp |= 0x01000000; /* set bit 7 of address */ + dest = temp; /* put in dest to go out */ break; case 0x84>>2: /* 0x84 SD|RR|RNX|ADR - SD|RNX|ADR */ /* ANMx */ @@ -2876,7 +2960,7 @@ meoa: CC |= CC4BIT; /* byte is zero, so CC4 */ else if (dest & MSIGN) { - CC |= CC3BIT; /* assume negative */ + CC |= CC3BIT; /* assume negative */ dest |= D32LMASK; /* force upper word to all ones */ } else @@ -2891,7 +2975,7 @@ meoa: CC |= CC4BIT; /* byte is zero, so CC4 */ else if (dest & MSIGN) { - CC |= CC3BIT; /* assume negative */ + CC |= CC3BIT; /* assume negative */ dest |= D32LMASK; /* force upper word to all ones */ } else @@ -2905,7 +2989,7 @@ meoa: CC |= CC4BIT; /* byte is zero, so CC4 */ else if (dest & DMSIGN) - CC |= CC3BIT; /* assume negative */ + CC |= CC3BIT; /* assume negative */ else CC |= CC2BIT; /* then td > 0, so CC2 */ break; @@ -2926,6 +3010,9 @@ meoa: // dest -= source; /* old */ td = dest; dest = dest + NEGATE32(source); /* sub mem from reg */ +#ifdef UTXBUG +// fprintf(stderr, "CAMX dest %lx source %lx result %lx\n", td, source, dest); +#endif #ifndef HACK if (dbl && (dest == DMSIGN)) { /* HACK HACK HACK for diags */ @@ -3013,6 +3100,9 @@ meoa: } if ((TRAPME = Mem_read(addr, &temp))) /* get the word from memory */ goto newpsd; /* memory read error or map fault */ +#ifdef UTXBUG + fprintf(stderr, "ABM before @ addr %x val %x\n", addr, temp); +#endif /* use C bits and bits 6-8 (reg) to generate shift bit count */ bc = ((FC & 3) << 3) | reg; /* get # bits to shift right */ @@ -3027,6 +3117,9 @@ meoa: ovr = 1; /* we have an overflow */ } set_CCs(temp, ovr); /* set the CC's, CC1 = ovr */ +#ifdef UTXBUG + fprintf(stderr, "ABM after @ addr %x val %x\n", addr, temp); +#endif if ((TRAPME = Mem_write(addr, &temp))) /* put word into memory */ goto newpsd; /* memory write error or map fault */ /* the arithmetic exception will be handled */ @@ -3113,8 +3206,9 @@ meoa: goto exec; /* go execute the instruction */ break; - case 0xAC>>2: /* 0xAC SCC|SD|RM|ADR - SD|RM|ADR */ /* Lx */ + case 0xAC>>2: /* 0xAC SCC|SD|RM|ADR - SD|RM|ADR */ /* Lx */ dest = source; /* set value to load into reg */ +//fprintf(stderr, "LW addr %x reg %x sreg %x source %lx dest %lx\n", addr, reg, sreg, source, dest); break; case 0xB0>>2: /* 0xB0 SCC|SD|RM|ADR - SD|RM|ADR */ /* LMx */ @@ -3148,6 +3242,7 @@ meoa: case 0xBC>>2: /* 0xBC SCC|SD|RR|RM|ADR - SD|RM|ADR */ /* SUMx */ source = NEGATE32(source); +//fprintf(stderr, "SUMW addr %x reg %x sreg %x source %lx dest %lx\n", addr, reg, sreg, source, dest); /* Fall through */ case 0xB8>>2: /* 0xB8 SCC|SD|RR|RM|ADR - SD|RM|ADR */ /* ADMx */ @@ -3367,6 +3462,7 @@ doovr2: /* */ case 0x6: { /* SVC none - none */ /* Supervisor Call Trap */ #ifdef TRMEMPX /* set to 1 for traceme to work */ + /* get current MPX task name */ int j; char n[9]; uint32 dqe = M[0x8e8>>2]; /* get DQE of current task */ @@ -3822,7 +3918,7 @@ doovr2: /* update the PSD with new address */ PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ i_flags |= BT; /* we branched, so no PC update */ - if (IR & IND) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */ } /* branch not taken, go do next instruction */ @@ -3853,7 +3949,7 @@ doovr2: /* update the PSD with new address */ PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ i_flags |= BT; /* we branched, so no PC update */ - if (IR & IND) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */ } break; @@ -3864,14 +3960,15 @@ doovr2: /* we are taking the branch, set CC's if indirect, else leave'm */ /* update the PSD with new address */ #if 1 /* set to 1 to stop branch to self, for now */ -/* FIXME */ if (PC == (addr & 0x7FFFC)) { /* BIB to current PC, bump branch addr */ +///* FIXME */ if (PC == (addr & 0x7FFFC)) { /* BIB to current PC, bump branch addr */ +/* FIXME */ if (PC == (addr & 0xFFFFFC)) { /* BIB to current PC, bump branch addr */ addr += 4; // fprintf(stderr, "BI? stopping BIB $ addr %x PC %x\r\n", addr, PC); dest = 0; /* force reg to zero */ } #endif PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ - if (IR & IND) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */ i_flags |= BT; /* we branched, so no PC update */ } @@ -3886,9 +3983,8 @@ doovr2: case 0x1: /* BL F880 */ /* copy CC's from instruction and PC incremented by 4 */ GPR[0] = ((PSD1 & 0xff000000) | ((PSD1 + 4) & 0xfffffe)); - if (IR & IND) { /* see if CC from last indirect are wanted */ + if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */ - } /* update the PSD with new address */ if (modes & BASEBIT) PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* bit 8-30 */ @@ -4189,6 +4285,9 @@ syscheck: /* the channel must be defined as a class F I/O channel in SPAD */ /* if not class F, the system will generate a system check trap */ t = SPAD[lchan]; /* get spad entry for channel */ +#ifdef UTXBUG + fprintf(stderr, "XIO step 1 lchan = %x, spad[%x] %x mem[0] %x\n", lchan, lchan, t, M[0]); +#endif if (t == 0 || t == 0xffffffff) /* if not set up, die */ goto syscheck; /* machine check */ /* sim_debug(DEBUG_EXP, &cpu_dev, "$$ XIO lchan %x sa %x spad %.8x\n", lchan, suba, t); */ @@ -4219,10 +4318,8 @@ mcheck: if (((temp & MASK24) == 0) && (((opr >> 2) & 0xf) == 2)) goto mcheck; /* bad iocl address */ -//fprintf(stderr, "XIO ready chan %x intr %x icb %x iocla %x iocd1 %.8x iocd2 %0.x8\r\n", -// chan, ix, addr, addr+16, M[temp>>2], M[(temp+4)>>2]); -//sim_debug(DEBUG_EXP, &cpu_dev, "XIO ready chan %x intr %x icb %x iocla %x iocd1 %.8x iocd2 %.8x\n", -// chan, ix, addr, addr+16, M[temp>>2], M[(temp+4)>>2]); + sim_debug(DEBUG_EXP, &cpu_dev, "XIO ready chan %x intr %x icb %x iocla %x iocd1 %.8x iocd2 %.8x\n", + chan, ix, addr, addr+16, M[temp>>2], M[(temp+4)>>2]); /* at this point, the channel has a valid SPAD channel entry */ /* t is SPAD entry contents for chan device */ /* temp2 has IR + reg contents if reg != 0 */ @@ -4232,8 +4329,8 @@ mcheck: /* ix - positive interrupt level */ /* addr - ICB for specified interrupt level, points to 6 wd block */ /* temp - First IOCD address */ -//fprintf(stderr, "XIO switch %x lchan %x chan %x intr %x chsa %x IOCDa %x\r\n", ((opr>>3)&0xf), lchan, chan, ix, (chan<<8)|suba, temp); -//sim_debug(DEBUG_EXP, &cpu_dev, "XIO switch chan %x intr %x chsa %x IOCDa %.8x\n", chan, ix, (chan<<8)|suba, temp); + sim_debug(DEBUG_EXP, &cpu_dev, "XIO switch %x lchan %x, chan %x intr %x chsa %x IOCDa %.8x\n", + ((opr>>3)&0x0f), lchan, chan, ix, (chan<<8)|suba, temp); switch((opr >> 3) & 0xf) { /* use bits 9-12 to determine I/O instruction */ uint32 status; /* status returned by various functions */ uint16 chsa; /* logical device address */ @@ -4269,10 +4366,8 @@ mcheck: if ((TRAPME = startxio(chsa, &status))) goto newpsd; /* error returned, trap cpu */ PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */ -// fprintf(stderr, "XIO SIO ret chan %x chsa %x status %x\r\n", chan, (chan<<8)|suba, status); -// fflush(stderr); - sim_debug(DEBUG_EXP, &cpu_dev, "XIO SIO ret chan %x chsa %x status %x\n", - chan, (chan<<8)|suba, status); + sim_debug(DEBUG_EXP, &cpu_dev, "XIO SIO ret chan %x chsa %x status %x M[0] %x\n", + chan, (chan<<8)|suba, status, M[0]); break; case 0x03: /* Test I/O TIO */ @@ -4346,7 +4441,7 @@ mcheck: INTS[ix] |= INTS_ENAB; /* enable specified int level */ SPAD[ix+0x80] |= SINT_ENAB; /* enable in SPAD too */ INTS[ix] &= ~INTS_REQ; /* clears any requests also TRY 06-09-18 */ -//TRY 06-09-18 irq_pend = 1; /* start scanning interrupts again */ +//TRY 06-09-18 irq_pend = 1; /* start scanning interrupts again */ PSD1 = ((PSD1 & 0x87fffffe) | (0x40000000 & 0x78000000)); /* insert cc1 status */ break; @@ -4507,8 +4602,9 @@ mcheck: } else { PSD1 = (PSD1 + 4) | (((PSD1 & 2) >> 1) & 1); } - } else + } else { EXM_EXR = 0; /* reset PC increment for EXR */ + } OPSD1 &= 0x87FFFFFE; /* clear the old CC's */ OPSD1 |= PSD1 & 0x78000000; /* update the CC's in the PSD */ @@ -4602,7 +4698,7 @@ newpsd: case ADDRSPEC_TRAP: /* 0xB0 Address Specification Trap */ case CONSOLEATN_TRAP: /* 0xB4 Console Attention Trap */ case PRIVHALT_TRAP: /* 0xB8 Privlege Mode Halt Trap */ -//DIAG case AEXPCEPT_TRAP: /* 0xBC Arithmetic Exception Trap */ +//DIAG case AEXPCEPT_TRAP: /* 0xBC Arithmetic Exception Trap */ default: sim_debug(DEBUG_EXP, &cpu_dev, "TRAP PSD1 %x PSD2 %x CPUSTATUS %x TRAPME %x\n", PSD1, PSD2, CPUSTATUS, TRAPME); @@ -4725,7 +4821,7 @@ dumpi: fprintf(stderr, " B4=%x B5=%x B6=%x B7=%x", BR[4], BR[5], BR[6], BR[7]); fprintf(stderr, "\r\n"); } -#if 1 +#if 0 fprintf(stderr, "Current MAPC PSD2 %x modes %x\r\n", PSD2, modes); for (ix=0; ix<16; ix++) { fprintf(stderr, "MAP %x MPC %x\r\n", ix/2, MAPC[ix]); @@ -4835,7 +4931,6 @@ t_stat cpu_ex(t_value *vptr, t_addr baddr, UNIT *uptr, int32 sw) if (vptr == NULL) /* any address specified by user */ return SCPE_OK; /* no, just ignore the request */ *vptr = (M[addr] >> (8 * (3 - (baddr & 0x3)))); /* return memory contents */ -//printf("exam addr %x sw %x mem %x retv %x\r\n", baddr, sw, M[addr], *vptr); return SCPE_OK; /* we are all ok */ } @@ -4851,7 +4946,6 @@ t_stat cpu_dep(t_value val, t_addr baddr, UNIT *uptr, int32 sw) if (addr >= MEMSIZE) /* see if address is within our memory */ return SCPE_NXM; /* no, none existant memory error */ val = (M[addr] & bmasks[baddr & 0x3]) | (val << (8 * (3 - (baddr & 0x3)))); -//printf("dep addr %x sw %x mem %x retv %x\r\n", baddr, sw, M[addr], val); M[addr] = val; /* set new value */ return SCPE_OK; /* all OK */ } From 3ed0c046e87098da9b20be0ba094461ab4135dbe Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:28:06 -0700 Subject: [PATCH 05/10] SEL32: Remove unused debug code. --- SEL32/sel32_lpr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/SEL32/sel32_lpr.c b/SEL32/sel32_lpr.c index 1e4b2a2..ac095aa 100644 --- a/SEL32/sel32_lpr.c +++ b/SEL32/sel32_lpr.c @@ -218,6 +218,7 @@ uint8 lpr_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) switch (cmd & LPR_CMDMSK) { case 0x00: /* INCH command */ sim_debug(DEBUG_CMD, &lpr_dev, "lpr_startcmd %x: Cmd INCH\n", chan); +//fprintf(stderr, "lpr_startcmd %x: Cmd INCH\n", chan); return SNS_CHNEND|SNS_DEVEND; /* all is well */ break; From f89e8aefa8f6bb34bfc38f79f06d4621da997e98 Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:28:43 -0700 Subject: [PATCH 06/10] SEL32: Fix basemode instruction display code. --- SEL32/sel32_sys.c | 54 ++++++++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/SEL32/sel32_sys.c b/SEL32/sel32_sys.c index 532f6e2..d343bfd 100644 --- a/SEL32/sel32_sys.c +++ b/SEL32/sel32_sys.c @@ -618,18 +618,18 @@ t_opcode optab[] = { { 0x1808, 0xFC0C, B|H|TYPE_K, "ABR", }, /* Add Bit In Register # BR */ { 0x180C, 0xFC0C, B|H|TYPE_K, "TBR", }, /* Test Bit in Register # BR */ { 0x1C00, 0xFC0C, N|H|TYPE_K, "ZBR", }, /* Zero Bit in Register # NBR */ /* CON SRABR */ - { 0x1C00, 0xFC0F, B|H|TYPE_I, "SRABR", }, /* Shift Right Arithmetic # BR */ /* CON ZBM */ - { 0x1C20, 0xFC0F, B|H|TYPE_I, "SRLBR", }, /* Shift Right Logical # BR */ - { 0x1C40, 0xFC0F, B|H|TYPE_I, "SLABR", }, /* Shift Left Arithmetic # BR */ - { 0x1C60, 0xFC0F, B|H|TYPE_I, "SLLBR", }, /* Shift Left Logical # BR */ + { 0x1C00, 0xFC60, B|H|TYPE_I, "SRABR", }, /* Shift Right Arithmetic # BR */ /* CON ZBM */ + { 0x1C20, 0xFC60, B|H|TYPE_I, "SRLBR", }, /* Shift Right Logical # BR */ + { 0x1C40, 0xFC60, B|H|TYPE_I, "SLABR", }, /* Shift Left Arithmetic # BR */ + { 0x1C60, 0xFC60, B|H|TYPE_I, "SLLBR", }, /* Shift Left Logical # BR */ { 0x2000, 0xFC0C, N|H|TYPE_K, "ABR", }, /* Add Bit in Register # NBR */ /* CON SRADBR */ - { 0x2000, 0xFC0F, B|H|TYPE_I, "SRADBR", }, /* Shift Right Arithmetic Double # BR */ /* CON ABR */ - { 0x2020, 0xFC0F, B|H|TYPE_I, "SRLDBR", }, /* Shift Left Logical Double # BR */ - { 0x2040, 0xFC0F, B|H|TYPE_I, "SLADBR", }, /* Shift Right Arithmetic Double # BR */ - { 0x2060, 0xFC0F, B|H|TYPE_I, "SLLDBR", }, /* Shift Left Logical Double # BR */ + { 0x2000, 0xFC60, B|H|TYPE_I, "SRADBR", }, /* Shift Right Arithmetic Double # BR */ /* CON ABR */ + { 0x2020, 0xFC60, B|H|TYPE_I, "SRLDBR", }, /* Shift Left Logical Double # BR */ + { 0x2040, 0xFC60, B|H|TYPE_I, "SLADBR", }, /* Shift Right Arithmetic Double # BR */ + { 0x2060, 0xFC60, B|H|TYPE_I, "SLLDBR", }, /* Shift Left Logical Double # BR */ { 0x2400, 0xFC0C, N|H|TYPE_K, "TBR", }, /* Test Bit in Register # NBR */ /* CON SRCBR */ - { 0x2400, 0xFC0F, B|H|TYPE_I, "SRCBR", }, /* Shift Right Circular # BR */ /* CON TBR */ - { 0x2440, 0xFC0F, B|H|TYPE_F, "SLCBR", }, /* Shift Left Circular # BR */ + { 0x2400, 0xFC60, B|H|TYPE_I, "SRCBR", }, /* Shift Right Circular # BR */ /* CON TBR */ + { 0x2440, 0xFC60, B|H|TYPE_F, "SLCBR", }, /* Shift Left Circular # BR */ { 0x2800, 0xFC0F, H|TYPE_G, "TRSW", }, /* Transfer GPR to PSD */ { 0x2802, 0xFC0F, B|H|TYPE_F, "XCBR", }, /* Exchange Base Registers # BR Only */ { 0x2804, 0xFC0F, B|H|TYPE_G, "TCCR", }, /* Transfer CC to GPR # BR Only */ @@ -675,13 +675,13 @@ t_opcode optab[] = { { 0x3C08, 0xFC0F, H|TYPE_F, "SURM", }, /* Subtract Register to Register Masked # */ { 0x4000, 0xFC0F, N|H|TYPE_F, "MPR", }, /* Multiply Register to Register # NBR */ { 0x4400, 0xFC0F, N|H|TYPE_F, "DVR", }, /* Divide Register to Register # NBR */ - { 0x5000, 0xFC0F, B|TYPE_D, "LABRM", }, /* Load Address BR Mode */ - { 0x5400, 0xFC0F, B|TYPE_A, "STWBR", }, /* Store Base Register BR Only */ - { 0x5800, 0xFC0F, B|TYPE_A, "SUABR", }, /* Subtract Base Register BR Only */ - { 0x5808, 0xFC0F, B|TYPE_D, "LABR", }, /* Load Address Base Register BR Only */ - { 0x5C00, 0xFC0F, B|TYPE_A, "LWBR", }, /* Load Base Register BR Only */ - { 0x5C08, 0xFC0F, B|H|TYPE_A, "BSUBM", }, /* Branch Subroutine Memory BR Only */ - { 0x5C08, 0xFC0F, B|H|TYPE_A, "CALLM", }, /* Call Memory BR Only */ + { 0x5000, 0xFC08, B|TYPE_D, "LABRM", }, /* Load Address BR Mode */ + { 0x5400, 0xFC08, B|TYPE_A, "STWBR", }, /* Store Base Register BR Only */ + { 0x5800, 0xFC08, B|TYPE_A, "SUABR", }, /* Subtract Base Register BR Only */ + { 0x5808, 0xFC08, B|TYPE_D, "LABR", }, /* Load Address Base Register BR Only */ + { 0x5C00, 0xFC08, B|TYPE_A, "LWBR", }, /* Load Base Register BR Only */ + { 0x5C08, 0xFC08, B|H|TYPE_A, "BSUBM", }, /* Branch Subroutine Memory BR Only */ + { 0x5C08, 0xFC08, B|H|TYPE_A, "CALLM", }, /* Call Memory BR Only */ { 0x6000, 0xFC0F, N|H|TYPE_F, "NOR", }, /* Normalize # NBR Only */ { 0x6400, 0xFC0F, N|H|TYPE_F, "NORD", }, /* Normalize Double # NBR Only */ { 0x6800, 0xFC0F, N|H|TYPE_F, "SCZ", }, /* Shift and Count Zeros # */ @@ -818,7 +818,7 @@ int fprint_inst(FILE *of, uint32 val, int32 sw) if (mode && (tab->type & (X | N))) continue; /* non basemode instruction in base mode, skip */ if (!mode && (tab->type & B)) - continue; /* basemode instruction in nonbase mde, skip */ + continue; /* basemode instruction in nonbase mode, skip */ /* TODO? Maybe want to make sure MODEL is 32/7X for X type instructions */ @@ -833,7 +833,12 @@ int fprint_inst(FILE *of, uint32 val, int32 sw) case TYPE_E: /* [*]o[,x] or o[(b)][,x] */ /* append B, H, W, D to base instruction using F & C bits */ i = (val & 3) | ((inst >> 1) & 04); - if (((inst&0xfc00) != 0xdc00) && ((inst&0xfc00) != 0xcc00) && + if (((inst&0xfc00) != 0xdc00) && + ((inst&0xfc00) != 0x5400) && + ((inst&0xfc00) != 0x5800) && + ((inst&0xfc00) != 0x5c00) && + ((inst&0xfc00) != 0xcc00) && + ((inst&0xfc00) != 0xcc08) && ((inst&0xfc00) != 0x8000)) fputc(fc_type[i], of); /* Fall through */ @@ -854,7 +859,8 @@ int fprint_inst(FILE *of, uint32 val, int32 sw) fputc(' ', of); if (mode) { /* base reg mode */ - fprint_val(of, val&0xffff, 16, 16, PV_RZRO); /* output 16 bit offset */ +//UTX fprint_val(of, val&0xffff, 16, 16, PV_RZRO); /* output 16 bit offset */ + fprint_val(of, val&0xffff, 16, 16, PV_LEFT); /* output 16 bit offset */ if (inst & 07) { fputc('(', of); fputc(('0'+(inst & 07)), of); /* output the base reg number */ @@ -958,10 +964,12 @@ int fprint_inst(FILE *of, uint32 val, int32 sw) } /* FIXME - should we just return error here? or dump as hex data? */ /* we get here if opcode not found, print data value */ - fputs(" invld ", of); /* output error message */ + if (mode) + fputs(" Binvld ", of); /* output basemode error message */ + else + fputs(" Ninvld ", of); /* output non-basmode error message */ fprint_val(of, val, 16, 32, PV_RZRO); /* output unknown 32 bit instruction code */ return 4; /* show as full word size */ -// return SCPE_UNK; /* unknown opcode */ } /* Symbolic decode @@ -978,7 +986,6 @@ int fprint_inst(FILE *of, uint32 val, int32 sw) t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw) { int i; -//old int l = 1; /* default to bytes */ int l = 4; /* default to full words */ int rdx = 16; /* default radex is hex */ uint32 num, tmp=*val; @@ -1112,7 +1119,6 @@ t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 { int i; int x; -//old int l = 1; /* default to bytes */ int l = 4; /* default to full words */ int rdx = 16; /* default radex is hex */ char mod = 0; From cf44e63bf6ecf927a702e089a1d8fb812acf218a Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:38:33 -0700 Subject: [PATCH 07/10] SEL32: Fix typo. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2e9d1ca..ce26852 100644 --- a/README.md +++ b/README.md @@ -180,7 +180,7 @@ This is a working copy of a simulator for the SEL Concept/32 computer. The current test version is for the SEL 32/27, 32/67, 32/87, 32/97 computers. Support for 32/55, 32/75, V6, and V9 computers may be added in the future. This simulator is co-authors with James C. Bevier. I did the initial parts -of the simulator, James took it to a working simulator, I m assisting him +of the simulator, James took it to a working simulator, I am assisting him in maintaining and enhancing the simulator. # SEL Concept/32 From 5cf0ee326ba437ea046831f2083d1a52905ffe6e Mon Sep 17 00:00:00 2001 From: AZBevier Date: Thu, 18 Jul 2019 17:39:03 -0700 Subject: [PATCH 08/10] SEL32: Add channel INCH support code. --- SEL32/sel32_iop.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/SEL32/sel32_iop.c b/SEL32/sel32_iop.c index b55ddb6..06241e5 100644 --- a/SEL32/sel32_iop.c +++ b/SEL32/sel32_iop.c @@ -55,6 +55,7 @@ const char *iop_desc(DEVICE *dptr); /* Held in u3 is the device command and status */ #define IOP_INCH 0x00 /* Initialize channel command */ +#define IOP_NOP 0x03 /* NOP command */ #define IOP_MSK 0xff /* Command mask */ /* Status held in u3 */ @@ -152,14 +153,30 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) /* process the commands */ switch (cmd & 0xFF) { case IOP_INCH: /* INCH command */ + uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ + uptr->u3 &= LMASK; /* leave only chsa */ sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd INCH\n", chan); - return SNS_CHNEND|SNS_DEVEND; /* all is well */ + uptr->u3 |= IOP_MSK; /* save INCH command as 0xff */ + sim_activate(uptr, 20); /* TRY 07-13-19 */ + return 0; /* no status change */ + break; + + case IOP_NOP: /* NOP command */ + sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd NOP\n", chan); + uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= (cmd & IOP_MSK); /* save NOP command */ + sim_activate(uptr, 20); /* TRY 07-13-19 */ + return 0; /* no status change */ break; default: /* invalid command */ uptr->u5 |= SNS_CMDREJ; /* command rejected */ sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd Invald %x status %02x\n", chan, cmd, uptr->u5); - return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */ + uptr->u3 &= LMASK; /* leave only chsa */ + uptr->u3 |= (cmd & IOP_MSK); /* save command */ + sim_activate(uptr, 20); /* force interrupt */ + return 0; /* no status change */ break; } @@ -172,11 +189,17 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) t_stat iop_srv(UNIT *uptr) { uint16 chsa = GET_UADDR(uptr->u3); - int unit = (uptr - iop_unit); /* unit 0 is channel */ + int cmd = uptr->u3 & IOP_MSK; - uptr->u3 &= LMASK; /* nothing left, command complete */ - sim_debug(DEBUG_CMD, &iop_dev, "iop_srv chan %d: devend|devend\n", unit); -// chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* TRY 6/12/18 done */ + /* test for NOP or INCH cmds */ + if ((cmd == IOP_NOP) || (cmd == IOP_MSK)) { /* NOP has do nothing */ + uptr->u3 &= LMASK; /* nothing left, command complete */ + sim_debug(DEBUG_CMD, &iop_dev, "iop_srv INCH/NOP chan %d: chnend|devend\n", chsa); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */ + } else + if (cmd) { + chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* done */ + } return SCPE_OK; } From a3359d9a23744b8ee1e229ba2f0e181bb659a6b9 Mon Sep 17 00:00:00 2001 From: AZBevier Date: Fri, 19 Jul 2019 12:31:48 -0700 Subject: [PATCH 09/10] SEL32: Update diag initialization file for testing. --- SEL32/tests/diag.ini | 98 ++++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/SEL32/tests/diag.ini b/SEL32/tests/diag.ini index 7029425..63a3ce3 100644 --- a/SEL32/tests/diag.ini +++ b/SEL32/tests/diag.ini @@ -1,49 +1,49 @@ -set debug -n sel.log -set CPU 32/67 4M -;set CPU 32/97 4M -;set CPU V6 4M -;set CPU V9 4M -;set CPU 32/27 2M -;set debug stderr -;set mta debug=cmd;detail;exp;data -;set mta debug=inst;cmd;detail;exp -;set inq debug=cmd;detail -;set cpu debug=cmd;exp -;set cpu debug=cmd;exp;inst;detail;data -;set cpu debug=cmd;exp;inst;detail -;set cpu debug=exp; -;set con debug=cmd;exp;data -;set mta debug=cmd;exp;inst;data;detail -;set mta debug=cmd -;set dma debug=cmd;exp;detail;data -;set dma debug=cmd;exp;detail;data -; -set coml0 enable -set coml1 enable -set coml2 enable -set coml3 enable -set coml4 enable -set coml5 enable -set coml6 enable -set coml7 enable -; -set comc enable -at comc 4747 -; -;set con debug=CMD -; -set lpr enable -at lpr lprout -; -;at mta0 mpxsdt4.tap -;at mta0 mpxsdt5.tap -;at sda0 diskfile4 -;at sda1 diskfile5 -; -;at mta0 sim32sdt.tap -at mta0 diag.tap -at mta1 temptape.tap -at mta2 output.tap -;at dma0 diagdisk -;bo dma0 -bo mta0 +set debug -n sel.log +set CPU 32/67 4M +;set CPU 32/97 4M +;set CPU V6 4M +;set CPU V9 4M +;set CPU 32/27 2M +;set debug stderr +;set mta debug=cmd;detail;exp;data +;set mta debug=inst;cmd;detail;exp +;set inq debug=cmd;detail +;set cpu debug=cmd;exp +;set cpu debug=cmd;exp;inst;detail;data +;set cpu debug=cmd;exp;inst;detail +;set cpu debug=exp; +;set con debug=cmd;exp;data +;set mta debug=cmd;exp;inst;data;detail +;set mta debug=cmd +;set dma debug=cmd;exp;detail;data +;set dma debug=cmd;exp;detail;data +; +set coml0 enable +set coml1 enable +set coml2 enable +set coml3 enable +set coml4 enable +set coml5 enable +set coml6 enable +set coml7 enable +; +set comc enable +at comc 4747 +; +;set con debug=CMD +; +set lpr enable +at lpr lprout +; +;at mta0 mpxsdt4.tap +;at mta0 mpxsdt5.tap +;at sda0 diskfile4 +;at sda1 diskfile5 +; +;at mta0 sim32sdt.tap +at mta0 diag.tap +at mta1 temptape.tap +at mta2 output.tap +;at dma0 diagdisk +;bo dma0 +bo mta0 From 79eff596c99e526eedef97201e707a0949e89c01 Mon Sep 17 00:00:00 2001 From: AZBevier Date: Fri, 19 Jul 2019 12:36:22 -0700 Subject: [PATCH 10/10] SEL32: Correct test code for indirect branches that was missing an &. --- SEL32/sel32_cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/SEL32/sel32_cpu.c b/SEL32/sel32_cpu.c index f40f255..87bd9b3 100644 --- a/SEL32/sel32_cpu.c +++ b/SEL32/sel32_cpu.c @@ -36,12 +36,12 @@ //#undef TRME int traceme = 0; /* dynamic trace function */ /* start on second diag starting */ -//int trstart = 4; /* count of when to start tracing */ +int trstart = 900; /* count of when to start tracing */ /* start on J.INIT */ //int trstart = 12; /* count of when to start tracing */ //int trstart = 0x8000000; /* count of when to start tracing */ //int trstart = 37; /* count of when to start tracing */ -int trstart = 0; /* count of when to start tracing */ +//int trstart = 0; /* count of when to start tracing */ /* 32/7x PSW/PSD Mode Trap/Interrupt Priorities */ /* Relative Logical Int Vect TCW IOCD Description */ @@ -3918,7 +3918,7 @@ doovr2: /* update the PSD with new address */ PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ i_flags |= BT; /* we branched, so no PC update */ - if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) && (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */ } /* branch not taken, go do next instruction */ @@ -3949,7 +3949,7 @@ doovr2: /* update the PSD with new address */ PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ i_flags |= BT; /* we branched, so no PC update */ - if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) && (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last indirect CCs */ } break; @@ -3968,7 +3968,7 @@ doovr2: } #endif PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */ - if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) && (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */ i_flags |= BT; /* we branched, so no PC update */ } @@ -3983,7 +3983,7 @@ doovr2: case 0x1: /* BL F880 */ /* copy CC's from instruction and PC incremented by 4 */ GPR[0] = ((PSD1 & 0xff000000) | ((PSD1 + 4) & 0xfffffe)); - if (((modes & BASEBIT) == 0) & (IR & IND)) /* see if CCs from last indirect are wanted */ + if (((modes & BASEBIT) == 0) && (IR & IND)) /* see if CCs from last indirect are wanted */ PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */ /* update the PSD with new address */ if (modes & BASEBIT) @@ -4040,10 +4040,10 @@ doovr2: if (CPUSTATUS & 0x80) /* see if old mode is blocked */ PSD2 |= 0x00004000; /* set to blocked state */ - if (opr & 0x0200) { /* Was it LPSDCM? */ #ifdef TRME /* set to 1 for traceme to work */ traceme++; /* start trace (maybe) if traceme >= trstart */ #endif + if (opr & 0x0200) { /* Was it LPSDCM? */ /* map bit must be on to load maps */ if (PSD2 & MAPBIT) { #ifdef TRMEMPX /* set to 1 for traceme to work */ @@ -4640,6 +4640,7 @@ mcheck: fprintf(stderr, " B0=%x B1=%x B2=%x B3=%x", BR[0], BR[1], BR[2], BR[3]); fprintf(stderr, " B4=%x B5=%x B6=%x B7=%x", BR[4], BR[5], BR[6], BR[7]); fprintf(stderr, "\r\n"); + fflush(stderr); } } #endif