From baa7791b974dcdf53fe8947f1959a6c7cc2ad24c Mon Sep 17 00:00:00 2001 From: Richard Cornwell Date: Tue, 15 Oct 2019 23:49:02 -0400 Subject: [PATCH] KA10: KL10B working, RH20 support added. --- PDP10/kl10_fe.c | 8 +- PDP10/kx10_cpu.c | 1021 ++++++++++++++++++++++++++++++++++----------- PDP10/kx10_defs.h | 92 +++- PDP10/kx10_df.c | 12 +- PDP10/kx10_dp.c | 3 +- PDP10/kx10_rh.c | 750 +++++++++++++++++++++++++++++++++ PDP10/kx10_rp.c | 704 ++++++++++--------------------- PDP10/kx10_rs.c | 503 ++++++---------------- PDP10/kx10_sys.c | 37 +- PDP10/kx10_tu.c | 581 +++++++------------------- README.md | 1 - makefile | 29 +- 12 files changed, 2175 insertions(+), 1566 deletions(-) create mode 100644 PDP10/kx10_rh.c diff --git a/PDP10/kl10_fe.c b/PDP10/kl10_fe.c index 050334b..13e900d 100644 --- a/PDP10/kl10_fe.c +++ b/PDP10/kl10_fe.c @@ -533,7 +533,6 @@ void dte_second(UNIT *uptr) { cty_out.in_ptr = (cty_out.in_ptr + 1) & 0xff; M[SEC_DTCHR + base] = ch; M[SEC_DTMTD + base] = FMASK; - M[SEC_DTF11 + base] = 0; sim_activate(&dte_unit[1], 100); break; case SEC_SETPRI: @@ -554,8 +553,9 @@ enter_pri: break; case SEC_SETDDT: /* Read character from console */ if (cty_in.in_ptr == cty_in.out_ptr) { - sim_activate(uptr, 100); - return; + M[SEC_DTF11 + base] = 0; + M[SEC_DTMTI + base] = FMASK; + break; } ch = cty_in.buff[cty_in.out_ptr]; cty_in.out_ptr = (cty_in.out_ptr + 1) & 0xff; @@ -1543,8 +1543,6 @@ lpt_printline(UNIT *uptr, int nl) { uptr->pos += uptr->POS; uptr->COL = 0; uptr->POS = 0; -// if (uptr->LINE == 0) - // (void)dte_queue(PRI_EMHDS, PRI_EMLPT, 1, &data1); return; } diff --git a/PDP10/kx10_cpu.c b/PDP10/kx10_cpu.c index c277ddf..d8e6f9d 100644 --- a/PDP10/kx10_cpu.c +++ b/PDP10/kx10_cpu.c @@ -312,6 +312,8 @@ InstHistory *hst = NULL; /* instruction history */ /* Forward and external declarations */ #if KL +int Mem_read(int flag, int cur_context, int fetch); +int Mem_write(int flag, int cur_context); int do_extend(uint32 IA); #endif t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw); @@ -414,9 +416,15 @@ REG cpu_reg[] = { #endif { FLDATA (PIHOLD, pi_hold, 0), REG_HRO}, { FLDATA (PIREST, pi_restore, 0), REG_HRO}, -#if KI | KL +#if KI { ORDATAD (UB, ub_ptr, 18, "User Base Pointer") }, { ORDATAD (EB, eb_ptr, 18, "Executive Base Pointer") }, +#endif +#if KL + { ORDATAD (UB, ub_ptr, 22, "User Base Pointer") }, + { ORDATAD (EB, eb_ptr, 22, "Executive Base Pointer") }, +#endif +#if KI | KL { ORDATAD (FMSEL, fm_sel, 8, "Register set select") }, { ORDATAD (SERIAL, apr_serial, 10, "System Serial Number") }, { FLDATA (INOUT, inout_fail, 0), REG_RO}, @@ -1163,8 +1171,21 @@ t_stat dev_pi(uint32 dev, uint64 *data) { case DATAO: #if KL - if (dev & 040) { /* SDIAG */ -// fprintf(stderr, "SDIAG %012llo\n\r", *data); + if (dev & 040) { /* SBDIAG */ + AB = (AB + 1) & RMASK; + res = 0; +// fprintf(stderr, "SBDIAG %012llo\n\r", *data); + if (((*data >> 31) & 037) == 010) { + switch(*data & 037) { + case 0: res = 06000000000LL; break; + case 1: res = 0500000000LL; break; + case 2: res = 0; break; + default: res = 0; break; + } + // fprintf(stderr, "SBDIAG return %012llo\n\r", res); + } + MB = res; + (void)Mem_write(0, 0); break; } #else @@ -1280,7 +1301,7 @@ t_stat dev_pag(uint32 dev, uint64 *data) { #if KLB if (res & BIT1) { /* Load previous section */ - prev_sect = (res >> 18) & 07777; + prev_sect = (res >> 18) & 037; } #endif if ((res & RSIGN) == 0) { @@ -1314,6 +1335,10 @@ t_stat dev_pag(uint32 dev, uint64 *data) { res |= ((uint64)(prev_ctx & 0160)) << 20; res |= ((uint64)(fm_sel & 0160)) << 23; res |= SMASK|BIT1|BIT2; +#if KLB + if (QKLB) + res |= ((uint64)prev_sect & 037) << 18; +#endif *data = res; sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI PAG %012llo\n", *data); break; @@ -1346,7 +1371,6 @@ void check_apr_irq() { } } -int Mem_write(int flag, int cur_context); /* * APR device for KL10. @@ -2009,12 +2033,11 @@ load_tlb(int uf, int page, int upmp, int wr, int trap, int flag) #define PG_WRT 0020000 #define PG_CAC 0004000 #define PG_STG 0000037 -#define PG_IDX 0000377 +#define PG_IDX 0000777 #define PG_MASK 0000003777777LL #define PG_AGE 0770000000000LL #define PG_PAG 0007777 -//fprintf(stderr, "Lookup Page %03o %0o %o %o\r\n", page, t20_page, upmp, uf); if (t20_page) { /* Start with full access */ int acc_bits = PG_PUB|PG_WRT|PG_CAC; uint64 spt = FM[(06<<4)|3] & PG_MASK; @@ -2024,8 +2047,13 @@ load_tlb(int uf, int page, int upmp, int wr, int trap, int flag) int index; int match = 0; int pg; +#if EPT440 int base = 0440; +#else + int base = 0540; +#endif +//fprintf(stderr, "Lookup Page %o %03o %0o %o %o\r\n", sect, page, t20_page, upmp, uf); /* Get segment pointer */ /* And save it */ #if KLB @@ -2108,7 +2136,7 @@ load_tlb(int uf, int page, int upmp, int wr, int trap, int flag) /* Get address of page */ data = M[(pg << 9) + page]; -//fprintf(stderr, "YMap %012llo\n\r", data); +//fprintf(stderr, "YMap %012llo %o %o\n\r", data, pg << 9, page); /* Decode map pointer */ switch ((data >> 33) & 07) { @@ -2134,16 +2162,9 @@ load_tlb(int uf, int page, int upmp, int wr, int trap, int flag) case 3: /* Indirect page */ acc_bits &= (data >> 18) & RMASK; - index = (data >> 18) & PG_IDX; + page = (data >> 18) & PG_IDX; data = M[(data & RMASK) + spt]; - if ((data >> 18) & PG_STG) { - if (trap) { - fault_data = 0; - page_fault = 1; - } - return 0; - } - data = M[(data & RMASK) + index]; +//fprintf(stderr, "IMap %012llo %o %o\n\r", data, pg << 9, page); break; } @@ -2247,9 +2268,6 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch int pub = (FLAGS & PUBLIC) != 0; int upmp = 0; - if (page_fault) - return 0; - /* If paging is not enabled, address is direct */ if (!page_enable) { *loc = addr; @@ -2326,6 +2344,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context, int fetch if (QKLB) fault_data = (((uint64)sect) << 18); #endif +//fprintf(stderr, "Page fault %06o a=%o wr=%o w=%o %06o\n\r", addr, (data & RSIGN) == 0, wr, (data & 0100000) == 0, data); /* Ignore faults if flag set */ if (FLAGS & ADRFLT) { page_fault = 0; @@ -2464,7 +2483,8 @@ int Mem_read(int flag, int cur_context, int fetch) { return 0; } - if ((glb_sect == 0 || sect == 0 || (glb_sect && sect == 1)) && AB < 020) { + if ((QKLB && (glb_sect == 0 || sect == 0 || (glb_sect && sect == 1)) && AB < 020) || + (!QKLB && AB < 020)) { #else if (AB < 020) { #endif @@ -2510,7 +2530,8 @@ int Mem_write(int flag, int cur_context) { return 0; } - if ((glb_sect == 0 || sect == 0 || (glb_sect && sect == 1)) && AB < 020) { + if ((QKLB && (glb_sect == 0 || sect == 0 || (glb_sect && sect == 1)) && AB < 020) || + (!QKLB && AB < 020)) { #else if (AB < 020) { #endif @@ -3917,6 +3938,7 @@ int pi_rq; /* Interrupt request */ int pi_ov; /* Overflow during PI cycle */ int pi_cycle; /* Executing an interrupt */ int ind; /* Indirect bit */ +int ix; int f_load_pc; /* Load AB from PC at start of instruction */ int f_inst_fetch; /* Fetch new instruction */ int f_pc_inh; /* Inhibit PC increment after instruction */ @@ -4075,7 +4097,6 @@ no_fetch: /* Handle indirection repeat until no longer indirect */ do { - int ix; if ((!pi_cycle) & pi_pending #if KI | KL & (!trap_flag) @@ -4084,7 +4105,7 @@ no_fetch: pi_rq = check_irq_level(); } #if KLB - if (QKLB && ptr_flg && pc_sect != 0 && (AR & 040000000LL) != 0) { /* Full pointer */ + if (QKLB && ptr_flg && pc_sect != 0 && (AR & BIT12) != 0) { /* Full pointer */ ind = 1; goto in_loop; } @@ -4102,8 +4123,6 @@ no_fetch: #endif if (ix) { #if KL -// if (xct_flag != 0) -//fprintf(stderr, "PXCT ir=%03o pc=%06o ad=%06o x=%02o m=%012llo\n\r", IR, PC, AB, xct_flag, MB); if (((xct_flag & 8) != 0 && (FLAGS & USER) == 0) || ((xct_flag & 2) != 0 && (FLAGS & USER) == 0 && ptr_flg)) AR = FM[prev_ctx|ix]; @@ -4112,11 +4131,9 @@ no_fetch: #if KLB /* Check if extended indexing */ if (QKLB && cur_sect != 0 && (AR & SMASK) == 0 && (AR & SECTM) != 0) { -fprintf(stderr, "Index %06o %012llo %06o\n\r", AB, AR, cur_sect); AR = (AR + ((AB & RSIGN) ? SECTM|((uint64)AB): (uint64)AB)) & (SECTM|RMASK); sect = cur_sect = (AR >> 18) & 07777; glb_sect = 1; -fprintf(stderr, "Index2 %06o %012llo %06o\n\r", AB, AR, cur_sect); AB = 0; } else glb_sect = 0; @@ -4139,6 +4156,7 @@ in_loop: #if KL & KLB /* Check if extended indexing */ if (QKLB && cur_sect != 0) { +// fprintf(stderr, "Ind %06o %012llo\n\r", AB, MB); if (MB & SMASK) { /* Instruction format IFIW */ if (MB & BIT1) { /* Illegal index word */ fault_data = 024LL << 30 | (((FLAGS & USER) != 0)?SMASK:0) | @@ -4147,31 +4165,55 @@ in_loop: goto last; } glb_sect = 0; - if (ptr_flg && (AR & 040000000LL) != 0) { /* Full pointer */ - ind = 0; + ind = TST_IND(MB) != 0; + ix = GET_XR(MB); + AB = MB & RMASK; + if (ix) { + if (((xct_flag & 8) != 0 && (FLAGS & USER) == 0) || + ((xct_flag & 2) != 0 && (FLAGS & USER) == 0 && ptr_flg)) + AR = FM[prev_ctx|ix]; + else + AR = get_reg(ix); + /* Check if extended indexing */ + if ((AR & SMASK) != 0 || (AR & SECTM) == 0) { /* Local index word */ + AR = (AR + AB) & RMASK; + } else { + AR = (AR + AB) & FMASK; + glb_sect = 1; + sect = cur_sect = (AR >> 18) & 07777; + } + MB = AR; + } else AR = MB; - AB = AR & RMASK; - } + AB = AR & RMASK; + if (!glb_sect && AB < 020) /* Map to global AC */ + sect = cur_sect = 1; +//fprintf(stderr, "IFIW %012llo %o %02o %06o %06o\n\r", MB, ind, ix, cur_sect, AB); } else { /* Extended index EFIW */ ind = (MB & BIT1) != 0; ix = (MB >> 30) & 017; - if (ix != 0) { + AB = MB & (SECTM|RMASK); + if (ix) { if (((xct_flag & 8) != 0 && (FLAGS & USER) == 0) || ((xct_flag & 2) != 0 && (FLAGS & USER) == 0 && ptr_flg)) AR = FM[prev_ctx|ix]; else AR = get_reg(ix); - AR = (AR + MB) & (SECTM|RMASK); + if ((AR & SMASK) != 0 || (AR & SECTM) == 0) { /* Local index word */ + AR = AB + (((AR & RSIGN) ? 0: 0)|(AR & RMASK)); + } else + AR = AR + AB; + AR &= FMASK; + MB = AR; } else AR = MB; sect = cur_sect = (AR >> 18) & 07777; AB = AR & RMASK; glb_sect = 1; - ix = 0; -fprintf(stderr, "EFIW %012llo %o %02o %06o %06o\n\r", MB, ind, ix, cur_sect, AB); - if (ind) - goto in_loop; +//fprintf(stderr, "EFIW %012llo %o %02o %06o %06o\n\r", MB, ind, ix, cur_sect, AB); } + if (ind) + goto in_loop; } #endif } @@ -4304,7 +4346,7 @@ st_pi: if (extend) { if (IR == 0 || IR > 031 || AC != 0 || do_extend(IA)) { IR = 0123; - AC = IA; + AC = ext_ac; goto muuo; } goto last; @@ -4371,9 +4413,10 @@ muuo: unasign: /* Save Opcode */ #if KL & KLB - if (QKLB) - MB = ((uint64)(IR) << 12) | ((uint64)(AC) << 8) | ((uint64)(FLAGS) << 23) | ((uint64)cur_sect & 037); - else + if (QKLB && t20_page) { + AR = (((uint64)cur_sect) << 18) | (uint64)AB; /* Save address */ + MB = (((uint64)((IR << 9) | (AC << 5))) | ((uint64)(FLAGS) << 23)) & FMASK; + } else #endif MB = ((uint64)(IR) << 27) | ((uint64)(AC) << 23) | (uint64)(AB); AB = ub_ptr | 0424; @@ -4381,7 +4424,7 @@ unasign: /* Save flags */ AB++; #if KL & KLB - if (QKLB) + if (QKLB && t20_page) MB = ((uint64)(pc_sect) << 18) | ((PC + (trap_flag == 0)) & RMASK); else #endif @@ -4394,18 +4437,25 @@ unasign: #if KL extend = 0; #if KLB - if (QKLB) { /* Save address */ - MB = ((uint64)(cur_sect) << 18) | (AB & RMASK); + if (QKLB && t20_page) { /* Save address */ + MB = AR; AB ++; Mem_write_nopage(); } #endif /* Save context */ AB ++; - MB = (ub_ptr >> 9) | ((uint64)(prev_ctx & 0160)) << 20 | - ((uint64)(fm_sel & 0160)) << 23 | SMASK|BIT1|BIT2; + MB = SMASK|BIT1 | + ((uint64)(fm_sel & 0160) << 23) | + ((uint64)(prev_ctx & 0160) << 20) | +#if KLB + ((uint64)(prev_sect & 037) << 18) | +#endif + (ub_ptr >> 9); +#if KLB + prev_sect = pc_sect; +#endif Mem_write_nopage(); -// prev_ctx = fm_sel; #endif /* Read in new PC and flags */ FLAGS &= ~ (PRV_PUB|BYTI|ADRFLT|TRP1|TRP2); @@ -4419,14 +4469,14 @@ unasign: Mem_read_nopage(); #if KL & KLB - if (QKLB) { + if (QKLB && t20_page) { pc_sect = (MB >> 18) & 07777; FLAGS = 0; } else #endif FLAGS = (MB >> 23) & 017777; /* If transistioning from user to executive adjust flags */ - if ((FLAGS & USER) != 0 && (AB & 4) != 0) + if ((FLAGS & USER) == 0 && (AB & 4) != 0) FLAGS |= USERIO; if ((FLAGS & USER) == 0 && (AB & 2 || (FLAGS & OVR) != 0)) FLAGS |= PRV_PUB|OVR; @@ -4446,6 +4496,40 @@ unasign: case 0024: case 0025: case 0026: case 0027: case 0030: case 0031: case 0032: case 0033: case 0034: case 0035: case 0036: case 0037: +#if KL & KLB + /* LUUO's in non-zero section are different */ + if (QKLB && t20_page && pc_sect != 0) { + AR = (((uint64)cur_sect) << 18) | AB; /* Save address */ + /* Grab address of LUUO block from user base 420 */ + AB = ((FLAGS & USER) ? ub_ptr : eb_ptr) + 0420; + Mem_read_nopage(); + /* Now save like MUUO */ + AB = MB & RMASK; + sect = (MB >> 18) & 07777; + MB = (((uint64)((IR << 9) | (AC << 5))) | ((uint64)(FLAGS) << 23)) & FMASK; + if ((FLAGS & USER) == 0) { + MB &= ~SMASK; + MB |= (FLAGS & PRV_PUB) ? SMASK : 0; + } + Mem_write_nopage(); + /* Save PC */ + AB++; + MB = ((uint64)(pc_sect) << 18) | ((PC + (trap_flag == 0)) & RMASK); + Mem_write_nopage(); + extend = 0; + /* Save Effective address */ + MB = AR; + AB ++; + Mem_write_nopage(); + AB ++; + /* Read PC */ + Mem_read_nopage(); + pc_sect = (MB >> 18) & 07777; + PC = MB & RMASK; + f_pc_inh = 1; + break; + } +#endif #if PDP6 ill_op = 1; ex_uuo_sync = 1; @@ -5645,17 +5729,22 @@ unasign: case 0133: /* IBP/ADJBP */ #if KL if (AC != 0) { /* ADJBP */ - modify = 1; - if (Mem_read(0, 0, 0)) { + if (Mem_read(0, 0, 0)) goto last; - } AR = MB; SC = (AR >> 24) & 077; /* S */ if (SC) { - int bpw, left, newb, adjw, adjb, c; + int bpw, left, newb, adjw, adjb; + f = 0; FE = (AR >> 30) & 077; /* P */ - AB = AR & RMASK; /* Address */ +#if KLB + if (QKLB && FE > 36) { + f = 1; + SC = _byte_adj[(FE - 37)].s; + FE = _byte_adj[(FE - 37)].p; + } +#endif left = (36 - FE) / SC; /* Number bytes left (36 - P)/S */ bpw = left + (FE / SC); /* Bytes per word */ if (bpw == 0) { @@ -5676,6 +5765,36 @@ unasign: adjw--; } FE = 36 - (adjb * SC) - ((36 - FE) % SC); /* New P */ +#if KLB + if (f) { + /* Short pointer */ + f = (AR >> 30) & 077; /* P */ + AR = (((uint64)((f + adjb) & 077)) << 30) | /* Make new BP */ + ((AR + adjw) & (SECTM|RMASK)); + set_reg(AC, AR); + break; + } else if (QKLB && pc_sect != 0 && (AR & BIT12) != 0) { + /* Full pointer */ + AB = (AB + 1) & RMASK; + if (Mem_read(0, 0, 0)) + goto last; + AR = (((uint64)(FE & 077)) << 30) | /* Make new BP */ + (AR & PMASK); /* S and below */ + if (MB & SMASK) { + if (MB & BIT1) { + fault_data = 024LL << 30 | (((FLAGS & USER) != 0)?SMASK:0) | + (AB & RMASK) | ((uint64)cur_sect << 18); + page_fault = 1; + goto last; + } + BR = (MB + adjw) & RMASK | (MB & LMASK); + } else + BR = (MB + adjw) & (SECTM|RMASK) | (MB & ~(SECTM|RMASK)); + set_reg(AC, AR); + set_reg(AC+1, BR); + break; + } +#endif AR = (((uint64)(FE & 077)) << 30) | /* Make new BP */ (AR & PMASK & LMASK) | /* S,IX,I */ ((AR + adjw) & RMASK); @@ -5716,22 +5835,30 @@ unasign: SCAD = (SCAD + (0777 ^ SC) + 1) & 0777; if (SCAD & 0400) { SC = ((0777 ^ SC) + 044 + 1) & 0777; -#if KI | KL +#if KL #if KLB - if (QKLB && pc_sect != 0 && (AR & 040000000LL) != 0) { /* Full pointer */ - uint32 AT = AB; + if (QKLB && pc_sect != 0 && (AR & BIT12) != 0) { /* Full pointer */ AB = (AB + 1) & RMASK; if (Mem_read(0, 0, 0)) goto last; - if (MB & SMASK) - MB = (MB & LMASK) | ((MB + 1) & RMASK); - else - MB++; +//fprintf(stderr, "ILBP %o %o %06o %012llo\n\r", SC, SCAD, AB, MB); + if (MB & SMASK) { + if (MB & BIT1) { + fault_data = 024LL << 30 | (((FLAGS & USER) != 0)?SMASK:0) | + (AB & RMASK) | ((uint64)cur_sect << 18); + page_fault = 1; + goto last; + } + MB = (MB + 1) & RMASK | (MB & LMASK); + } else + MB = (MB + 1) & (SECTM|RMASK) | (MB & ~(SECTM|RMASK)); if (Mem_write(0,0)) goto last; - AB = AT; + AB = (AB - 1) & RMASK; } else + AR = (AR & LMASK) | ((AR + 1) & RMASK); #endif +#elif KI AR = (AR & LMASK) | ((AR + 1) & RMASK); #else AR = (AR + 1) & FMASK; @@ -5790,8 +5917,10 @@ ldb_ptr: #if KL ptr_flg = 1; #if KLB - if (QKLB && pc_sect != 0 && (AR & 040000000LL) != 0) { /* Full pointer */ + if (QKLB && pc_sect != 0 && (AR & BIT12) != 0) { + /* Full pointer */ AB = (AB + 1) & RMASK; +//fprintf(stderr, "LBP %o %o %06o %012llo\n\r", SC, SCAD, AB, MB); } #endif #endif @@ -7023,7 +7152,9 @@ xjrstf: #if KLB if (QKLB) { pc_sect = (AR >> 18) & 07777; - prev_sect = BR & 037; + if ((FLAGS & USER) == 0 && ((BR >> 23) & USER) == 0) + prev_sect = BR & 037; +//fprintf(stderr, "XJRST %06o %06o %06o %012llo\r\n", pc_sect, prev_sect, FLAGS, BR); } #endif BR = BR >> 23; /* Move flags into position */ @@ -7097,7 +7228,8 @@ jrstf: case 014: /* SFM */ #if KLB if (QKLB) { - MB = (((uint64)FLAGS) << 23) | (prev_sect & 037); + MB = ((((uint64)FLAGS) << 23) | (uint64)(prev_sect & 037)) & FMASK; +//fprintf(stderr, "SFM %012llo\n\r", MB); (void)Mem_write(0, 0); goto last; } @@ -7419,6 +7551,23 @@ jrstf: #endif AR = AOB(AR); AB = AR & RMASK; +#if KLB + flag1 = glb_sect; + if (QKLB) { + f = (pc_sect != 0); + if ((FLAGS & USER) == 0 && (xct_flag & 1) != 0) { + sect = prev_sect; + f = (prev_sect != 0); + } + if (f && (AR & SMASK) == 0 && (AR & SECTM) != 0) { + sect = (AR >> 18) & 07777; + glb_sect = 1; + } + } else + f = 0; +//fprintf(stderr, "Pop %o %o %06o %06o %06o %012llo %012llo\n\r", f, xct_flag, prev_sect, sect, cur_sect, AR, BR); + if (QKLB && !f) +#endif if (AR & C1) { #if KI | KL if (!pi_cycle) @@ -7440,14 +7589,17 @@ jrstf: flag1 = glb_sect; if (QKLB) { f = (pc_sect != 0); - if ((FLAGS & USER) == 0 && (xct_flag & 1) != 0) + if ((FLAGS & USER) == 0 && (xct_flag & 1) != 0) { + sect = prev_sect; f = (prev_sect != 0); + } if (f && (AR & SMASK) == 0 && (AR & SECTM) != 0) { sect = (AR >> 18) & 07777; glb_sect = 1; } } else f = 0; +//fprintf(stderr, "Pop %o %o %06o %06o %06o %012llo %012llo\n\r", f, xct_flag, prev_sect, sect, cur_sect, AR, BR); #endif #endif AB = AR & RMASK; @@ -7490,8 +7642,10 @@ jrstf: #if KLB if (QKLB) { f = (pc_sect != 0); - if ((FLAGS & USER) == 0 && (xct_flag & 1) != 0) + if ((FLAGS & USER) == 0 && (xct_flag & 1) != 0) { f = (prev_sect != 0); + sect = prev_sect; + } if (f && (AR & SMASK) == 0 && (AR & SECTM) != 0) { sect = (AR >> 18) & 07777; glb_sect = 1; @@ -8206,6 +8360,7 @@ fetch_opr: AR = MB; } dev_tab[d](040|DATAO|(d<<2), &AR); +if (d == 1) fprintf(stderr, "SBDIAG return %012llo\n\r", AR); } else { dev_tab[d](040|DATAI|(d<<2), &AR); MB = AR; @@ -8430,6 +8585,11 @@ last: pi_rq = check_irq_level(); goto st_pi; } + if (trap_flag != 0) { + pi_hold = pi_ov = 0; + f_pc_inh = 0; + trap_flag = 0; + } #endif if ((IR & 0700) == 0700 && ((AC & 04) == 0)) { @@ -8504,78 +8664,281 @@ return reason; #if KL +/* Handle indirection for extended byte instructions */ +int +do_byte_setup(int n, int wr, int *pos, int *sz) +{ + uint64 val1; + uint64 val2; + uint64 temp; + int s; + int p; + int np; + int ix; + int ind; + + /* Get pointer */ + val1 = get_reg(n+1); + val2 = get_reg(n+2); + /* Extract index */ + *sz = s = (val1 >> 24) & 077; + p = (val1 >> 30) & 077; + np = (p + (0777 ^ s) + 1) & 0777; + /* Advance pointer */ +//fprintf(stderr, "%s %012llo %012llo %2o %2o %03o\n\r", (wr)?"store":"load", val1, val2, s, p, np); +#if KLB + if (QKLB) { + if (p > 36) { /* Extended pointer */ + int i = p - 37; + s = _byte_adj[i].s; + p = _byte_adj[i].p; + np = p = (p + (0777 ^ s) + 1) & 0777; + val2 = val1 & (SECTM|RMASK); /* Convert to long pointer */ + val1 = ((uint64)s << 24) | BIT12; + if (p & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val2 = (val2 & ~(SECTM|RMASK)) | ((val2 + 1) & (SECTM|RMASK)); + } + ind = 0; + ix = 0; + MB = val2 & (SECTM|RMASK); + sect = (MB >> 18) & 07777; + glb_sect = 1; + } else if (pc_sect != 0 && (val1 & BIT12) != 0) { /* Full pointer */ + if (np & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + if (val2 & SMASK) + val2 = (val2 & LMASK) | ((val2 + 1) & RMASK); + else + val2 = (val2 & ~(SECTM|RMASK)) | ((val2 + 1) & (SECTM|RMASK)); + } + if (val2 & SMASK) { + if (val2 & BIT1) { + fault_data = 024LL << 30 | (((FLAGS & USER) != 0)?SMASK:0) | + (val2 & RMASK) | ((uint64)sect << 18); + page_fault = 1; + return 1; + } + ind = TST_IND(val2) != 0; + ix = GET_XR(val2); + MB = (val2 & RMASK) | ((val2 & RSIGN)? LMASK:0); + sect = cur_sect; + if ((FLAGS & USER) == 0 && + (((xct_flag & 2) != 0 && !wr) || ((xct_flag & 1) != 0 && wr))) + sect = prev_sect; + glb_sect = 0; +//fprintf(stderr, "Load_byte1 %012llo %012llo %2o %2o\n\r", val1, val2, s, p); + } else { + ind = (val2 & BIT1) != 0; + ix = (val2 >> 30) & 017; + MB = val2 & (SECTM|RMASK); + sect = (MB >> 18) & 07777; + glb_sect = 1; +//fprintf(stderr, "Load_byte2 %012llo %012llo %2o %2o\n\r", val1, val2, s, p); + } + } else { + if (np & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val1 = (val1 & LMASK) | ((val1 + 1) & RMASK); + } + ix = GET_XR(val1); + ind = TST_IND(val1) != 0; + MB = (val1 & RMASK) | ((val1 & RSIGN)? LMASK:0); + sect = cur_sect; + if ((FLAGS & USER) == 0 && + (((xct_flag & 2) != 0 && !wr) || ((xct_flag & 1) != 0 && wr))) + sect = prev_sect; + glb_sect = 0; +//fprintf(stderr, "Load_byte3 %012llo %012llo %2o %2o\n\r", val1, val2, s, p); + } + } else +#endif + { + if (np & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val1 = (val1 & LMASK) | ((val1 + 1) & RMASK); + } + ix = GET_XR(val1); + ind = TST_IND(val1) != 0; + MB = (val1 & RMASK) | ((val1 & RSIGN)? LMASK:0); +#if KLB + sect = cur_sect; + if ((FLAGS & USER) == 0 && + (((xct_flag & 2) != 0 && !wr) || ((xct_flag & 1) != 0 && wr))) + sect = prev_sect; + glb_sect = 0; +#endif +//fprintf(stderr, "Load_byte4 %012llo %012llo %2o %2o\n\r", val1, val2, s, p); + } + *pos = np & 077; + + AB = MB & RMASK; + if (ix) { + temp = get_reg(ix); +#if KLB + /* Check if extended indexing */ + if (QKLB && glb_sect != 0 && (temp & SMASK) == 0 && (temp & SECTM) != 0) { +//fprintf(stderr, "Index %06o %012llo %06o\n\r", AB, temp, sect); + temp = (temp + MB) & (SECTM|RMASK); + sect = (temp >> 18) & 07777; + MB = 0; + glb_sect = 1; +//fprintf(stderr, "Index2 %06o %012llo %06o\n\r", AB, temp, sect); + } else + glb_sect = 0; +#endif + temp = MB = (MB + temp) & FMASK; + AB = MB & RMASK; + } + while (ind & !check_irq_level()) { + ptr_flg = 1; + if (Mem_read(0, 1, 0)) { + ptr_flg = 0; + return 1; + } + ptr_flg = 0; +#if KLB + /* Check if extended indexing */ + if (QKLB && sect != 0) { +inx: + if (MB & SMASK) { /* Instruction format IFIW */ + if (MB & BIT1) { /* Illegal index word */ + fault_data = 024LL << 30 | (((FLAGS & USER) != 0)?SMASK:0) | + (temp & RMASK) | ((uint64)sect << 18); + page_fault = 1; + return 1; + } + glb_sect = 0; + ix = GET_XR(MB); + ind = TST_IND(MB) != 0; + AB = MB & RMASK; + if (ix) { + temp = get_reg(ix); + /* Check if extended indexing */ + if ((temp & SMASK) != 0 || (temp & SECTM) == 0) { /* Local index word */ + temp = (temp + AB) & RMASK; + } else { + temp = (temp + AB) & FMASK; + glb_sect = 1; + sect = cur_sect = (temp >> 18) & 07777; + } + MB = temp; + } else + temp = MB; + AB = temp & RMASK; +//fprintf(stderr, "IFIW %012llo %o %02o %06o %06o\n\r", MB, ind, ix, cur_sect, AB); + } else { /* Extended index EFIW */ + ind = (MB & BIT1) != 0; + ix = (MB >> 30) & 017; + AB = MB & (SECTM|RMASK); + if (ix) { + temp = get_reg(ix); + if ((temp & SMASK) != 0 || (temp & SECTM) == 0) { /* Local index word */ + temp = AB + (((temp & RSIGN) ? 0: 0)|(temp & RMASK)); + } else + temp = temp + AB; + temp &= FMASK; + MB = temp; + } else + temp = MB; + sect = cur_sect = (temp >> 18) & 07777; + AB = temp & RMASK; + glb_sect = 1; +//fprintf(stderr, "EFIW %012llo %o %02o %06o %06o\n\r", MB, ind, ix, sect, AB); + } + } else { +#endif + ix = GET_XR(MB); + ind = TST_IND(MB) != 0; + AB = MB & RMASK; + if (ix) { + temp = get_reg(ix); +#if KLB + /* Check if extended indexing */ + if (QKLB && sect != 0 && (temp & SMASK) == 0 && (temp & SECTM) != 0) { +//fprintf(stderr, "Index %06o %012llo %06o\n\r", AB, temp, sect); + temp = (temp + ((AB & RSIGN) ? SECTM|((uint64)AB): (uint64)AB)) & (SECTM|RMASK); + sect = (temp >> 18) & 07777; + MB = 0; + glb_sect = 1; +//fprintf(stderr, "Index2 %06o %012llo %06o\n\r", AB, temp, sect); + AB = 0; + } else + glb_sect = 0; +#endif + temp = MB = (MB + temp) & FMASK; + AB = MB & RMASK; + } +#if KLB + } +#endif + /* Handle events during a indirect loop */ + if (sim_interval-- <= 0) { + if (sim_process_event() != SCPE_OK) { + return 1; + } + } + }; + /* Update pointer */ + val1 &= PMASK; + val1 |= (uint64)(np) << 30; + + /* Save pointer */ + set_reg(n+1, val1); + set_reg(n+2, val2); + + modify = wr; + ptr_flg = !wr; + BYF5 = wr; + /* Read final value */ + if (Mem_read(0, 0, 0)) { + modify = ptr_flg = BYF5 = 0; + return 1; + } +//fprintf(stderr, "Load %06o %06llo -> %012llo\n\r", sect, AB, MB); + modify = 0; + return 0; +} + /* Get data from pointer */ int load_byte(int n, uint64 *data, uint64 fill, int cnt) { - uint64 val, msk; - int s, p, addr, ind, np; + uint64 val1, val2, msk; + int s, p, addr, ind, np, ix; /* Check if should return fill */ - val = get_reg(n); - if (cnt && (val & MANT) == 0) { + val1 = get_reg(n); + if (cnt && (val1 & MANT) == 0) { *data = fill; return 1; } - /* Get pointer */ - val = get_reg(n+1); - /* Extract index */ - s = (val >> 24) & 077; - p = (((val >> 30) & 077) + (0777 ^ s) + 1) & 0777; - /* Advance pointer */ - if (p & 0400) { - np = p = ((0777 ^ s) + 044 + 1) & 0777; - val = (val & LMASK) | ((val + 1) & RMASK); - } else - np = p; - np &= 077; - /* Update pointer */ - val &= PMASK; - val |= (uint64)(np) << 30; - AB = val & RMASK; - MB = val; - /* Handle indirection repeat until no longer indirect */ - do { - ind = (MB & 020000000) != 0; - if (MB & 017000000) { - AB = (AB + get_reg((MB >> 18) & 017)) & RMASK; - } - if (ind) { - if (Mem_read(0, 1, 0)) - goto back; - AB = MB & RMASK; - } - if (sim_interval <= 0) { - sim_process_event(); - } - } while (ind & pi_pending); - - /* Save pointer */ - set_reg(n+1, val); - - /* Read final value */ - if (Mem_read(0, 0, 0)) + /* Fetch Pointer word */ + if (do_byte_setup(n, 0, &p, &s)) goto back; /* Generate mask for given size */ msk = (uint64)(1) << s; msk--; *data = (MB >> p) & msk; +//fprintf(stderr, "Load_bytes %2o %2o %06o %06o %012llo\n\r", s, p, sect, AB, *data); if (cnt) { /* Decrement count */ - val = get_reg(n); - val--; - set_reg(n, val); + val1 = get_reg(n); + val1--; + set_reg(n, val1); } return 1; back: - val = get_reg(n+1); - val &= PMASK; - val |= (uint64)(p + s) << 30; - set_reg(n+1, val); +//fprintf(stderr, "Load_bytef %2o %2o %06o %06o %012llo\n\r", s, p, sect, AB, *data); + ptr_flg = 0; + val1 = get_reg(n+1); + val1 &= PMASK; + val1 |= (uint64)(p + s) << 30; + set_reg(n+1, val1); return 0; } @@ -8583,76 +8946,39 @@ back: int store_byte(int n, uint64 data, int cnt) { - uint64 val, msk; - int s, p, addr, ind, np; - - /* Get pointer */ - val = get_reg(n+1); - /* Extract index */ - s = (val >> 24) & 077; - p = (((val >> 30) & 077) + (0777 ^ s) + 1) & 0777; - /* Advance pointer */ - if (p & 0400) { - np = p = ((0777 ^ s) + 044 + 1) & 0777; - val = (val & LMASK) | ((val + 1) & RMASK); - } else - np = p; - np &= 077; - /* Update pointer */ - val &= PMASK; - val |= (uint64)(np) << 30; - AB = val & RMASK; - MB = val; - - /* Handle indirection repeat until no longer indirect */ - do { - ind = (MB & 020000000) != 0; - if (MB & 017000000) { - AB = (AB + get_reg((MB >> 18) & 017)) & RMASK; - } - if (ind) { - if (Mem_read(0, 1, 0)) - goto back; - AB = MB & RMASK; - } - if (sim_interval <= 0) { - sim_process_event(); - } - } while (ind & pi_pending); - - /* Save pointer */ - set_reg(n+1, val); + uint64 val1, val2, msk; + int s, p, addr, ind, np, ix; + /* Fetch Pointer word */ + if (do_byte_setup(n, 1, &p, &s)) + goto back; /* Generate mask for given size */ msk = (uint64)(1) << s; msk--; - - /* Read final value */ - modify = 1; - if (Mem_read(0, 0, 0)) - goto back; - msk <<= p; MB &= CM(msk); MB |= msk & ((uint64)(data) << p); +//fprintf(stderr, "store_bytes %2o %2o %06o %06o %012llo\n\r", s, p, sect, AB, data); + BYF5 = 1; if (Mem_write(0, 0)) goto back; if (cnt) { /* Decrement count */ - val = get_reg(n); - val--; - set_reg(n, val); + val1 = get_reg(n); + val1--; + set_reg(n, val1); } return 1; back: - val = get_reg(n+1); - val &= PMASK; - val |= (uint64)(p + s) << 30; - set_reg(n+1, val); + BYF5 = 0; + val1 = get_reg(n+1); + val1 &= PMASK; + val1 |= (uint64)(p + s) << 30; + set_reg(n+1, val1); return 0; } @@ -8670,40 +8996,120 @@ get_mask(int n, uint64 *msk) *msk = ((uint64)(1) << s) - 1; } +/* Adjust a pointer to be valid */ +void +adj_byte(int n) +{ + uint64 val1, val2; + int s, p, np; + + /* Get pointer */ + val1 = get_reg(n+1); + val2 = get_reg(n+2); + /* Extract index */ + s = (val1 >> 24) & 077; + p = (val2 >> 30) & 077; + /* Advance pointer */ + np = (p + (0777 ^ s) + 1) & 0777; +#if KLB + if (QKLB) { + if (p > 36) { /* Extended pointer */ + int i = p - 37; + s = _byte_adj[i].s; + p = _byte_adj[i].p; + val2 = val1 & (SECTM|RMASK); /* Convert to long pointer */ + val1 = ((uint64)s << 24) | BIT12; + /* Save pointer */ + set_reg(n+1, val1); + set_reg(n+2, val2); + return; + } else if (pc_sect != 0 && (val1 & BIT12) != 0) { /* Full pointer */ + if (np & 0400) + val2 = (val2 & ~(SECTM|RMASK)) | ((val2 + 1) & (SECTM|RMASK)); + } else { + if (np & 0400) + val1 = (val1 & LMASK) | ((val1 + 1) & RMASK); + } + } else +#endif + { + if (np & 0400) + val1 = (val1 & LMASK) | ((val1 + 1) & RMASK); + } + if ((np & 0400) == 0) + return; + /* Update pointer */ + val1 &= PMASK; + val1 |= (uint64)(044) << 30; + + /* Save pointer */ + set_reg(n+1, val1); + set_reg(n+2, val2); +} + + /* Advance a pointer by 1 */ void adv_byte(int n) { - uint64 val; + uint64 val1, val2; int s, p, np; /* Check if should return fill */ - val = get_reg(n); - if ((val & MANT) == 0) + val1 = get_reg(n); + if ((val1 & MANT) == 0) return; /* Decrement count */ - val--; - set_reg(n, val); + val1--; + set_reg(n, val1); /* Get pointer */ - val = get_reg(n+1); + val1 = get_reg(n+1); + val2 = get_reg(n+2); /* Extract index */ - s = (val >> 24) & 077; - p = (((val >> 30) & 077) + (0777 ^ s) + 1) & 0777; + s = (val1 >> 24) & 077; + p = (val2 >> 30) & 077; /* Advance pointer */ - if (p & 0400) { - p = np = (36 + (0777 ^ s) + 1) & 0777; - val = (val & LMASK) | ((val + 1) & RMASK); - } else - np = p; +#if KLB + if (QKLB) { + if (p > 36) { /* Extended pointer */ + int i = p - 37; + s = _byte_adj[i].s; + p = _byte_adj[i].p; + p = (p + (0777 ^ s) + 1) & 0777; + val2 = val1 & (SECTM|RMASK); /* Convert to long pointer */ + val1 = ((uint64)s << 24) | BIT12; + if (p & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val2 = (val2 & ~(SECTM|RMASK)) | ((val2 + 1) & (SECTM|RMASK)); + } else + np = p; + } else if (pc_sect != 0 && (val1 & BIT12) != 0) { /* Full pointer */ + p = (p + (0777 ^ s) + 1) & 0777; + if (p & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val2 = (val2 & ~(SECTM|RMASK)) | ((val2 + 1) & (SECTM|RMASK)); + } else + np = p; + } + } else +#endif + { + p = (p + (0777 ^ s) + 1) & 0777; + if (p & 0400) { + np = p = ((0777 ^ s) + 044 + 1) & 0777; + val1 = (val1 & LMASK) | ((val1 + 1) & RMASK); + } else + np = p; + } np &= 077; /* Update pointer */ - val &= PMASK; - val |= (uint64)(np) << 30; - MB = val; + val1 &= PMASK; + val1 |= (uint64)(np) << 30; /* Save pointer */ - set_reg(n+1, val); + set_reg(n+1, val1); + set_reg(n+2, val2); } /* back a pointer by 1 */ @@ -8828,6 +9234,7 @@ do_extend(uint32 ia) uint64 val1, val2; uint64 msk; uint64 reg; + int xlat_sect; int f, i; @@ -8883,6 +9290,12 @@ do_extend(uint32 ia) case 004: /* EDIT */ val2 = MB; /* Save address of translate table */ +#if KLB + if (QKLB && pc_sect != 0 && glb_sect) + xlat_sect = (val2 >> 18) & 07777; + else + xlat_sect = cur_sect; +#endif /* Fetch filler values */ AB = (ia + 1) & RMASK; if (Mem_read(0, 1, 0)) @@ -8900,6 +9313,15 @@ do_extend(uint32 ia) /* Read in pattern control */ reg = get_reg(ext_ac); AB = reg & RMASK; +#if KLB + if (QKLB && pc_sect != 0) { + sect = (reg >> 18) & 07777; + glb_sect = 1; + } else { + sect = cur_sect; + glb_sect = 0; + } +#endif if (Mem_read(0, 0, 0)) return 0; i = (reg >> 30) & 03; @@ -8907,23 +9329,32 @@ do_extend(uint32 ia) val1 = (MB >> ((3 - i) * 9)) & 0777; i++; if (i > 3) { - reg++; +#if KLB + if (QKLB && pc_sect != 0) + reg = (reg & ~(SECTM|RMASK)) | ((reg + 1) & (SECTM|RMASK)); + else +#endif + reg = (reg & LMASK) | ((reg+1) & RMASK); i = 0; } reg |= ((uint64)i) << 30; i = 0; a = 0; +//fprintf(stderr, "Edit pat %03o %012llo %012llo\n\r", val1, reg, MB); switch ((val1 >> 6) & 07) { case 0: /* Individual options */ switch (val1 & 077) { case 0: /* Stop */ f = 0; break; - case 1: + case 1: /* SELECT */ if (!load_byte(ext_ac, &val1, 0, 0)) return 0; a = 1; AB = (val2 + (val1 >> 1)) & RMASK; +#if KLB + sect = xlat_sect; +#endif if (Mem_read(0, 0, 0)) return 0; if ((val1 & 1) == 0) @@ -8951,16 +9382,38 @@ do_extend(uint32 ia) case 4: func4: if ((reg & SMASK) == 0) { - AB = get_reg(ext_ac+3) & RMASK; + adj_byte(ext_ac+3); + reg |= SMASK; + AR = get_reg(ext_ac+3); +#if KLB + if (QKLB && pc_sect != 0) { + sect = (AR >> 18) & 07777; + glb_sect = 1; + } else { + sect = cur_sect; + glb_sect = 0; + } +#endif + AB = AR & RMASK; MB = get_reg(ext_ac+4); if (Mem_write(0, 0)) return 0; - if (fill2 != 0) { - val1 = fill2; - i = 1; +#if KLB + if (QKLB && pc_sect != 0 && (MB & BIT12) != 0) { + AB = (++AR) & RMASK; + sect = (AR >> 18) & 07777; + MB = get_reg(ext_ac+5); + if (Mem_write(0,0)) + return 0; } - } else - i = 1; +#endif + if (fill2 != 0) { + if (!store_byte(ext_ac+3, fill1, 0)) { + return 0; + } + } + } + i = 1; reg |= SMASK|BIT1; /* Set S & N */ break; case 5: @@ -8976,10 +9429,29 @@ do_extend(uint32 ia) break; case 2: /* Set signifigance */ if ((reg & SMASK) == 0) { - AB = get_reg(ext_ac+3) & RMASK; + AR = get_reg(ext_ac+3); +#if KLB + if (QKLB && pc_sect != 0) { + sect = (AR >> 18) & 07777; + glb_sect = 1; + } else { + sect = cur_sect; + glb_sect = 0; + } +#endif + AB = AR & RMASK; MB = get_reg(ext_ac+4); if (Mem_write(0, 0)) return 0; +#if KLB + if (QKLB && pc_sect != 0 && (MB & BIT12) != 0) { + AB = (++AR) & RMASK; + sect = (AR >> 18) & 07777; + MB = get_reg(ext_ac+5); + if (Mem_write(0,0)) + return 0; + } +#endif if (fill2 != 0) { val1 = fill2; i = 1; @@ -8991,22 +9463,56 @@ do_extend(uint32 ia) reg &= ~(SMASK|BIT1|BIT2); /* Clear S & N */ break; case 4: /* Exchange Mark */ - AB = get_reg(ext_ac+3) & RMASK; + AR = get_reg(ext_ac+3); +#if KLB + if (QKLB && pc_sect != 0) { + sect = (AR >> 18) & 07777; + glb_sect = 1; + } else { + sect = cur_sect; + glb_sect = 0; + } +#endif + AB = AR & RMASK; if (Mem_read(0, 0, 0)) return 0; - AR = MB; + BR = MB; MB = get_reg(ext_ac+4); +#if KLB + /* Make sure byte pointers are same size */ + if (QKLB && (MB & BIT12) != (BR & BIT12)) + return 0; +#endif if (Mem_write(0, 0)) return 0; - set_reg(ext_ac+4, AR); - AB = (AB + 1) & RMASK; - if (Mem_read(0, 0, 0)) - return 0; - AR = MB; - MB = get_reg(ext_ac+5); - if (Mem_write(0, 0)) - return 0; - set_reg(ext_ac+5, AR); +//fprintf(stderr, "Edit exchange %06o %06o %012llo %012llo\n\r", sect, AB, BR, MB); +#if KLB + if (QKLB && pc_sect != 0 && (BR & BIT12) != 0) { + AB = (AR + 1) & RMASK; + sect = ((AR + 1)>> 18) & 07777; + if (Mem_read(0, 0, 0)) { + AB = AR & RMASK; /* Restore lower pointer */ + sect = (AR >> 18) & 07777; + MB = BR; +//fprintf(stderr, "Restore %06o %06o %012llo\n\r", sect, AB, MB); + (void)Mem_write(0, 0); + return 0; + } + AD = MB; + MB = get_reg(ext_ac+5); +//fprintf(stderr, "Edit exchange2 %06o %06o %012llo %012llo\n\r", sect, AB, AD, MB); + if (Mem_write(0, 0)) { + AB = AR & RMASK; /* Restore lower pointer */ + sect = (AR >> 18) & 07777; + MB = BR; +//fprintf(stderr, "Restore %06o %06o %012llo\n\r", sect, AB, MB); + (void)Mem_write(0, 0); + return 0; + } + set_reg(ext_ac+5, AD); + } +#endif + set_reg(ext_ac+4, BR); break; case 5: i = 0; @@ -9016,6 +9522,9 @@ do_extend(uint32 ia) case 1: /* Insert Message char */ if ((reg & SMASK) != 0) { AB = (ia + (val1 & 077) + 1) & RMASK; +#if KLB + sect = cur_sect; +#endif if (Mem_read(0, 0, 0)) return 0; i = 1; @@ -9058,6 +9567,12 @@ do_extend(uint32 ia) case 010: /* CVTDBO */ case 011: /* CVTDBT */ +#if KLB + if (QKLB && pc_sect != 0 && glb_sect) + xlat_sect = (val2 >> 18) & 07777; + else + xlat_sect = cur_sect; +#endif val2 = ((AR & RSIGN) ? LMASK : 0) | (AR & RMASK); /* Check if conversion started */ if ((get_reg(ext_ac) & SMASK) == 0) { @@ -9071,17 +9586,22 @@ do_extend(uint32 ia) fill2 |= SMASK; set_reg(ext_ac, fill2); } +//fprintf(stderr, "CVD %04llo %012lld %012llo\n\r", val1, ARX, AR); while ((get_reg(ext_ac) & MANT) != 0) { f = 1; if (!load_byte(ext_ac, &val1, 0, 1)) { - set_reg(ext_ac+3, ARX); - set_reg(ext_ac+4, AR); + set_reg(ext_ac+3, AR); + set_reg(ext_ac+4, ARX); return 0; } - if (IR == 010) + if (IR == 010) { val1 = (val1 + val2) & FMASK; - else + } else { +#if KLB + sect = xlat_sect; +#endif f = do_xlate((uint32)(val2 & RMASK), val1, 017); + } if (f < 0) break; if (f) { @@ -9105,6 +9625,7 @@ do_extend(uint32 ia) AR = AR + BR + f; ARX &= CMASK; AR &= FMASK; +//fprintf(stderr, "CVD %04llo %012lld %012llo\n\r", val1, ARX, AR); } } ARX &= CMASK; @@ -9127,6 +9648,12 @@ do_extend(uint32 ia) val2 = AB; else val2 = ((AR & RSIGN) ? LMASK : 0) | (AR & RMASK); +#if KLB + if (QKLB && pc_sect != 0 && glb_sect) + xlat_sect = (val2 >> 18) & 07777; + else + xlat_sect = cur_sect; +#endif /* Get fill */ AB = (ia + 1) & RMASK; if (Mem_read(0, 1, 0)) @@ -9180,6 +9707,9 @@ do_extend(uint32 ia) if (IR == 013) { /* Read first translation entry */ AB = (val1 + val2) & RMASK; +#if KLB + sect = xlat_sect; +#endif if (Mem_read(0, 0, 0)) { set_reg(ext_ac + 3, (reg & (SMASK|EXPO)) | (f+1)); return 0; @@ -9210,9 +9740,15 @@ do_extend(uint32 ia) get_mask(ext_ac+3, &msk); if ((((get_reg(ext_ac) & (077LL << 26))| get_reg(ext_ac+3)) & EMASK) != 0) return 1; - if (IR == 014) + if (IR == 014) { val2 = ((AR & RSIGN) ? LMASK : 0) | (AR & RMASK); - else if (IR == 015) { +#if KLB + if (QKLB && pc_sect != 0 && glb_sect) + xlat_sect = (val2 >> 18) & 07777; + else + xlat_sect = cur_sect; +#endif + } else if (IR == 015) { AB = ia; if (Mem_read(0, 1, 0)) return 0; @@ -9233,10 +9769,14 @@ do_extend(uint32 ia) if (!load_byte(ext_ac, &val1, fill1, 1)) { return 0; } - if (IR == 014) + if (IR == 014) { val1 = (val1 + val2) & FMASK; - else if (IR == 015) + } else if (IR == 015) { +#if KLB + sect = xlat_sect; +#endif f = do_xlate((uint32)(val2), val1, 07777); + } if (f < 0) return 0; if (f) { @@ -9294,56 +9834,59 @@ do_extend(uint32 ia) case 020: /* XBLT */ #if KLB if (QKLB) { + glb_sect = 1; reg = get_reg(ext_ac); -// if ((xct_flag & 2) != 0 && (FLAGS & USER) == 0) - // val1 = FM[prev_ctx|(ext_ac + 1)]; - // else - val1 = get_reg(ext_ac + 1); - // if ((xct_flag & 1) != 0 && (FLAGS & USER) == 0) - // val2 = FM[prev_ctx|(ext_ac + 2)]; - // else - val2 = get_reg(ext_ac + 2); -fprintf(stderr, "XBLT: %012llo %012llo %012llo\n\r", reg, val1, val2); + val1 = get_reg(ext_ac + 1); + val2 = get_reg(ext_ac + 2); +//fprintf(stderr, "XBLT: %012llo %012llo %012llo\n\r", reg, val1, val2); while (reg != 0) { if (reg & SMASK) { + val1 = (val1 - 1) & (SECTM|RMASK); sect = (val1 >> 18) & 07777; AB = val1 & RMASK; - if (Mem_read(0, 0, 0)) + ptr_flg = 1; + if (Mem_read(0, 0, 0)) { + val1 = (val1 + 1) & (SECTM|RMASK); goto xblt_done; -fprintf(stderr, " XBLT: D=%012llo 1-%012llo 2-%012llo\n\r", MB, val1, val2); + } +//fprintf(stderr, " XBLT: D=%012llo 1-%012llo 2-%012llo\n\r", MB, val1, val2); + val2 = (val2 - 1) & (SECTM|RMASK); sect = (val2 >> 18) & 07777; AB = val2 & RMASK; - if (Mem_write(0, 0)) + ptr_flg = 0; + BYF5 = 1; + if (Mem_write(0, 0)) { + val1 = (val1 + 1) & (SECTM|RMASK); + val2 = (val2 + 1) & (SECTM|RMASK); goto xblt_done; + } + BYF5 = 0; reg = (reg + 1) & FMASK; - val1 = (val1 - 1) & (SECTM|RMASK); - val2 = (val2 - 1) & (SECTM|RMASK); } else { sect = (val1 >> 18) & 07777; AB = val1 & RMASK; + ptr_flg = 1; if (Mem_read(0, 0, 0)) goto xblt_done; -fprintf(stderr, " XBLT: D=%012llo 1-%012llo 2-%012llo\n\r", MB, val1, val2); +//fprintf(stderr, " XBLT: D=%012llo 1-%012llo 2-%012llo\n\r", MB, val1, val2); sect = (val2 >> 18) & 07777; AB = val2 & RMASK; + ptr_flg = 0; + BYF5 = 1; if (Mem_write(0, 0)) goto xblt_done; val1 = (val1 + 1) & (SECTM|RMASK); val2 = (val2 + 1) & (SECTM|RMASK); reg = (reg - 1) & FMASK; + BYF5 = 0; } } xblt_done: -fprintf(stderr, "XBLT done: %012llo %012llo %012llo\n\r", reg, val1, val2); +//fprintf(stderr, "XBLT done: %012llo %012llo %012llo\n\r", reg, val1, val2); + ptr_flg = BYF5 = 0; set_reg(ext_ac, reg); - // if ((xct_flag & 2) != 0 && (FLAGS & USER) == 0) - // FM[prev_ctx|(ext_ac + 1)] = val1; - // else - set_reg(ext_ac + 1, val1); - // if ((xct_flag & 1) != 0 && (FLAGS & USER) == 0) - // FM[prev_ctx|(ext_ac + 2)] = val2; - // else - set_reg(ext_ac + 2, val2); + set_reg(ext_ac + 1, val1); + set_reg(ext_ac + 2, val2); return 0; } #endif @@ -9356,6 +9899,7 @@ fprintf(stderr, "XBLT done: %012llo %012llo %012llo\n\r", reg, val1, val2); case 027: /* DGFLTR */ case 030: /* GFLTR */ case 031: /* GFSC */ + default: return 1; } return 0; @@ -9651,6 +10195,7 @@ for (j = i = 0; (dptr = rh_devs[i]) != NULL; i++) { dev_irqv[(d >> 2)] = dibp->irq; rh[j].dev_num = d; rh[j].dev = dptr; + rh[j].rh = dibp->rh; j++; } } diff --git a/PDP10/kx10_defs.h b/PDP10/kx10_defs.h index 669a6fe..6ba7e7d 100644 --- a/PDP10/kx10_defs.h +++ b/PDP10/kx10_defs.h @@ -52,7 +52,8 @@ #if KL #define KLA 1 -#define KLB 0 +#define KLB 1 +#define EPT440 0 /* Force KL10A to 440 section address */ #endif #ifndef KLA @@ -183,6 +184,7 @@ extern DEBTAB crd_debug[]; #define BIT9 00000400000000LL #define BIT10 00000200000000LL #define BIT10_35 00000377777777LL +#define BIT12 00000040000000LL #define BIT17 00000001000000LL #define MANT 00000777777777LL #define EXPO 00377000000000LL @@ -293,6 +295,12 @@ extern DEBTAB crd_debug[]; #define AMASK 00000017777777LL #define WMASK 0037777LL #define CSHIFT 22 +#if KL +#define RH20_WMASK 003777LL +#define RH20_XFER SMASK +#define RH20_HALT BIT1 +#define RH20_REV BIT2 +#endif #else #define AMASK RMASK #define WMASK RMASK @@ -303,6 +311,10 @@ extern DEBTAB crd_debug[]; #define PI_ENABLE 0000000010 /* Clear DONE */ #define BUSY 0000000020 /* STOP */ #define CCW_COMP 0000000040 /* Write Final CCW */ +/* RH10 / RH20 interrupt */ +#define IADR_ATTN 0000000000040LL /* Interrupt on attention */ +#define IARD_RAE 0000000000100LL /* Interrupt on register access error */ +#define CCW_COMP_1 0000000040000LL /* Control word written. */ #if KI #define DEF_SERIAL 514 /* Default DEC test machine */ @@ -353,7 +365,12 @@ extern DEBTAB crd_debug[]; #define UNIT_V_MPX (UNIT_V_WAITS + 1) #define UNIT_M_MPX (1 << UNIT_V_MPX) #define UNIT_MPX (UNIT_M_MPX) /* MPX Device for ITS */ -#define DEV_V_RH (DEV_V_UF + 8) /* Type RH20 */ +#define CNTRL_V_RH (UNIT_V_UF + 4) +#define CNTRL_M_RH 7 +#define GET_CNTRL_RH(x) (((x) >> CNTRL_V_RH) & CNTRL_M_RH) +#define CNTRL_RH(x) (((x) & CNTRL_M_RH) << CNTRL_V_RH) +#define DEV_V_RH (DEV_V_UF + 1) /* Type RH20 */ +#define DEV_M_RH (1 << DEV_V_RH) #define TYPE_RH10 (0 << DEV_V_RH) #define TYPE_RH20 (1 << DEV_V_RH) @@ -432,39 +449,64 @@ extern t_stat (*dev_tab[128])(uint32 dev, t_uint64 *data); #define VEC_DEVMAX 8 /* max device vec */ +/* DF10 Interface */ +struct df10 { + uint32 status; /* DF10 status word */ + uint32 cia; /* Initial transfer address */ + uint32 ccw; /* Next control word address */ + uint32 wcr; /* CUrrent word count */ + uint32 cda; /* Current transfer address */ + uint32 devnum; /* Device number */ + t_uint64 buf; /* Data buffer */ + uint8 nxmerr; /* Bit to set for NXM */ + uint8 ccw_comp; /* Have we written out CCW */ +} ; + +/* RH10/RH20 Interface */ +struct rh_if { + void (*rh_write)(DEVICE *dptr, struct rh_if *rh, int reg, uint32 data); + uint32 (*rh_read)(DEVICE *dptr, struct rh_if *rh, int reg); + void (*rh_reset)(DEVICE *dptr); + t_uint64 buf; /* Data buffer */ + uint32 status; /* DF10 status word */ + uint32 cia; /* Initial transfer address */ + uint32 ccw; /* Current word count */ + uint32 wcr; + uint32 cda; /* Current transfer address */ + uint32 devnum; /* Device number */ + int ivect; /* Interrupt vector */ + uint8 imode; /* Mode of vector */ + int cop; /* RH20 Channel operator */ + uint32 sbar; /* RH20 Starting address */ + uint32 stcr; /* RH20 Count */ + uint32 pbar; + uint32 ptcr; + int reg; /* Last register selected */ + int drive; /* Last drive selected */ + int rae; /* Access register error */ + int attn; /* Attention bits */ + int xfer_drive; /* Current transfering drive */ +}; + /* Device context block */ struct pdp_dib { uint32 dev_num; /* device address */ uint32 num_devs; /* length */ t_stat (*io)(uint32 dev, t_uint64 *data); int (*irq)(uint32 dev, int addr); + struct rh_if *rh; }; - + #define RH10_DEV 01000 #define RH20_DEV 02000 struct rh_dev { uint32 dev_num; DEVICE *dev; + struct rh_if *rh; }; - typedef struct pdp_dib DIB; - -/* DF10 Interface */ -struct df10 { - uint32 status; - uint32 cia; - uint32 ccw; - uint32 wcr; - uint32 cda; - uint32 devnum; - t_uint64 buf; - uint8 nxmerr; - uint8 ccw_comp; -} ; - - void df10_setirq(struct df10 *df) ; void df10_writecw(struct df10 *df) ; void df10_finish_op(struct df10 *df, int flags) ; @@ -478,6 +520,18 @@ int dct_write(int u, t_uint64 *data, int c); int dct_is_connect(int u); #endif +/* Define RH10/RH20 functions */ +t_stat rh_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat rh_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat rh_devio(uint32 dev, t_uint64 *data); +int rh_devirq(uint32 dev, int addr); +void rh_setattn(struct rh_if *rh, int unit); +int rh_blkend(struct rh_if *rh); +void rh_setirq(struct rh_if *rh) ; +void rh_finish_op(struct rh_if *rh, int flags); +int rh_read(struct rh_if *rh); +int rh_write(struct rh_if *rh); + int ten11_read (int addr, t_uint64 *data); int ten11_write (int addr, t_uint64 data); diff --git a/PDP10/kx10_df.c b/PDP10/kx10_df.c index ceeb46e..841ca9f 100644 --- a/PDP10/kx10_df.c +++ b/PDP10/kx10_df.c @@ -1,6 +1,6 @@ -/* ka10_df.c: DF10 common routines. +/* kx10_df.c: DF10 common routines. - Copyright (c) 2015-2017, Richard Cornwell + Copyright (c) 2015-2019, Richard Cornwell Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -23,11 +23,14 @@ #include "kx10_defs.h" + +/* Set an IRQ for a DF10 device */ void df10_setirq(struct df10 *df) { df->status |= PI_ENABLE; set_interrupt(df->devnum, df->status); } +/* Generate the DF10 complete word */ void df10_writecw(struct df10 *df) { df->status |= 1 << df->ccw_comp; if (df->wcr != 0) @@ -35,6 +38,7 @@ void df10_writecw(struct df10 *df) { M[df->cia|1] = ((uint64)(df->ccw & WMASK) << CSHIFT) | ((uint64)(df->cda) & AMASK); } +/* Finish off a DF10 transfer */ void df10_finish_op(struct df10 *df, int flags) { df->status &= ~BUSY; df->status |= flags; @@ -42,6 +46,7 @@ void df10_finish_op(struct df10 *df, int flags) { df10_setirq(df); } +/* Setup for a DF10 transfer */ void df10_setup(struct df10 *df, uint32 addr) { df->cia = addr & ICWA; df->ccw = df->cia; @@ -50,6 +55,7 @@ void df10_setup(struct df10 *df, uint32 addr) { df->status &= ~(1 << df->ccw_comp); } +/* Fetch the next IO control word */ int df10_fetch(struct df10 *df) { uint64 data; if (df->ccw > MEMSIZE) { @@ -84,6 +90,7 @@ int df10_fetch(struct df10 *df) { return 1; } +/* Read next word */ int df10_read(struct df10 *df) { uint64 data; if (df->wcr == 0) { @@ -113,6 +120,7 @@ int df10_read(struct df10 *df) { return 1; } +/* Write next word */ int df10_write(struct df10 *df) { if (df->wcr == 0) { if (!df10_fetch(df)) diff --git a/PDP10/kx10_dp.c b/PDP10/kx10_dp.c index 2f41a4f..15f8d62 100644 --- a/PDP10/kx10_dp.c +++ b/PDP10/kx10_dp.c @@ -423,7 +423,6 @@ t_stat dp_devio(uint32 dev, uint64 *data) { if (*data & BUSY) { /* Stop controller */ sim_cancel(uptr); - uptr->STATUS &= ~BUSY; df10_finish_op(df10, 0); } /* Clear flags */ @@ -722,7 +721,7 @@ t_stat dp_svc (UNIT *uptr) CLR_BUF(uptr); } if (r) - sim_activate(uptr, 25); + sim_activate(uptr, 10); else { uptr->STATUS &= ~(SRC_DONE|END_CYL|BUSY); uptr->UFLAGS |= DONE; diff --git a/PDP10/kx10_rh.c b/PDP10/kx10_rh.c new file mode 100644 index 0000000..b337018 --- /dev/null +++ b/PDP10/kx10_rh.c @@ -0,0 +1,750 @@ +/* kx10_rh.c: RH10/RH20 interace routines. + + Copyright (c) 2015-2019, Richard Cornwell + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ + +#include "kx10_defs.h" + + +/* CONI Flags */ +#define IADR_ATTN 0000000000040LL /* Interrupt on attention */ +#define IARD_RAE 0000000000100LL /* Interrupt on register access error */ +#define DIB_CBOV 0000000000200LL /* Control bus overrun */ +#define CXR_PS_FAIL 0000000002000LL /* Power supply fail (not implemented) */ +#define CXR_ILC 0000000004000LL /* Illegal function code */ +#define CR_DRE 0000000010000LL /* Or Data and Control Timeout */ +#define DTC_OVER 0000000020000LL /* DF10 did not supply word on time (not implemented) */ +#define CCW_COMP_1 0000000040000LL /* Control word written. */ +#define CXR_CHAN_ER 0000000100000LL /* Channel Error */ +#define CXR_EXC 0000000200000LL /* Error in drive transfer */ +#define CXR_DBPE 0000000400000LL /* Device Parity error (not implemented) */ +#define CXR_NXM 0000001000000LL /* Channel non-existent memory (not implemented) */ +#define CXR_CWPE 0000002000000LL /* Channel Control word parity error (not implemented) */ +#define CXR_CDPE 0000004000000LL /* Channel Data Parity Error (not implemented) */ +#define CXR_SD_RAE 0000200000000LL /* Register access error */ +#define CXR_ILFC 0000400000000LL /* Illegal CXR function code */ +#define B22_FLAG 0004000000000LL /* 22 bit channel */ +#define CC_CHAN_PLS 0010000000000LL /* Channel transfer pulse (not implemented) */ +#define CC_CHAN_ACT 0020000000000LL /* Channel in use */ +#define CC_INH 0040000000000LL /* Disconnect channel */ +#define CB_FULL 0200000000000LL /* Set when channel buffer is full (not implemented) */ +#define AR_FULL 0400000000000LL /* Set when AR is full (not implemented) */ + +/* RH20 CONI Flags */ +#define RH20_PCR_FULL 0000000000020LL /* Primary command file full */ +#define RH20_ATTN_ENA 0000000000040LL /* Attention enable */ +#define RH20_SCR_FULL 0000000000100LL /* Secondary command full */ +#define RH20_ATTN 0000000000200LL /* Attention */ +#define RH20_MASS_ENA 0000000000400LL /* Mass bus enable */ +#define RH20_DATA_OVR 0000000001000LL /* Data overrun */ +#define RH20_CHAN_RDY 0000000002000LL /* Channel ready to start */ +#define RH20_RAE 0000000004000LL /* Register access error */ +#define RH20_DR_RESP 0000000010000LL /* Drive no response */ +#define RH20_CHAN_ERR 0000000020000LL /* Channel error */ +#define RH20_SHRT_WC 0000000040000LL /* Short word count */ +#define RH20_LONG_WC 0000000100000LL /* Long word count */ +#define RH20_DR_EXC 0000000200000LL /* Exception */ +#define RH20_DATA_PRI 0000000400000LL /* Data parity error */ +#define RH20_SBAR 0000001000000LL /* SBAR set */ +#define RH20_XEND 0000002000000LL /* Transfer ended */ + +/* CONO Flags */ +#define ATTN_EN 0000000000040LL /* enable attention interrupt. */ +#define REA_EN 0000000000100LL /* enable register error interrupt */ +#define CBOV_CLR 0000000000200LL /* Clear CBOV */ +#define CONT_RESET 0000000002000LL /* Clear All error bits */ +#define ILC_CLR 0000000004000LL /* Clear ILC and SD RAE */ +#define DRE_CLR 0000000010000LL /* Clear CR_CBTO and CR_DBTO */ +#define OVER_CLR 0000000020000LL /* Clear DTC overrun */ +#define WRT_CW 0000000040000LL /* Write control word */ +#define CHN_CLR 0000000100000LL /* Clear Channel Error */ +#define DR_EXC_CLR 0000000200000LL /* Clear DR_EXC */ +#define DBPE_CLR 0000000400000LL /* Clear CXR_DBPE */ + +/* RH20 CONO Flags */ +#define RH20_DELETE_SCR 0000000000100LL /* Clear SCR */ +#define RH20_RCLP 0000000000200LL /* Reset command list */ +#define RH20_MASS_EN 0000000000400LL /* Mass bus enable */ +#define RH20_XFER_CLR 0000000001000LL /* Clear XFER error */ +#define RH20_CLR_MBC 0000000002000LL /* Clear MBC */ +#define RH20_CLR_RAE 0000000004000LL /* Clear RAE error */ + +/* DATAO/DATAI */ +#define CR_REG 0770000000000LL /* Register number */ +#define LOAD_REG 0004000000000LL /* Load register */ +#define CR_MAINT_MODE 0000100000000LL /* Maint mode... not implemented */ +#define CR_DRIVE 0000007000000LL +#define CR_GEN_EVD 0000000400000LL /* Enable Parity */ +#define CR_DXES 0000000200000LL /* Disable DXES errors */ +#define CR_INAD 0000000077600LL +#define CR_WTEVM 0000000000100LL /* Verify Parity */ +#define CR_FUNC 0000000000076LL +#define CR_GO 0000000000001LL + +#define IRQ_VECT 0000000000177LL /* Interupt vector */ +#define IRQ_KI10 0000002000000LL +#define IRQ_KA10 0000001000000LL +#define FNC_XFER 024 /* >=? data xfr */ + +/* Status register settings */ +#define DS_OFF 0000001 /* offset mode */ +#define DS_VV 0000100 /* volume valid */ +#define DS_DRY 0000200 /* drive ready */ +#define DS_DPR 0000400 /* drive present */ +#define DS_PGM 0001000 /* programable NI */ +#define DS_LST 0002000 /* last sector */ +#define DS_WRL 0004000 /* write locked */ +#define DS_MOL 0010000 /* medium online */ +#define DS_PIP 0020000 /* pos in progress */ +#define DS_ERR 0040000 /* error */ +#define DS_ATA 0100000 /* attention active */ + +/* RH20 channel status flags */ +#define RH20_MEM_PAR 00200000000000LL /* Memory parity error */ +#define RH20_ADR_PAR 00100000000000LL /* Address parity error */ +#define RH20_NOT_WC0 00040000000000LL /* Word count not zero */ +#define RH20_NXM_ERR 00020000000000LL /* Non existent memory */ +#define RH20_LAST_ERR 00000400000000LL /* Last transfer error */ +#define RH20_ERROR 00000200000000LL /* RH20 error */ +#define RH20_LONG_STS 00000100000000LL /* Did not reach wc */ +#define RH20_SHRT_STS 00000040000000LL /* WC reached zero */ +#define RH20_OVER 00000020000000LL /* Overrun error */ + +/* 0-37 mass bus register. + 70 SBAR, block address. + 71 STCR, neg block count, func + 72 PBAR + 73 PTCR + 74 IVIR Interrupt vector address. + 75 Diags read. + 76 Diags write. + 77 Status (tra,cb test, bar test, ev par, r/w, exc,ebl, 0, attn, sclk +*/ + +/* + * CCW 000..... New channel comand list pointer HALT. + 010..... Next CCW Address JUMP + 1xycount-address. x=halt last xfer, y=reverse +*/ + +extern uint32 eb_ptr; +void rh20_setup(struct rh_if *rhc); +void rh_setup(struct rh_if *rh, uint32 addr); +void rh_writecw(struct rh_if *rh, int nxm); + + +t_stat +rh_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ + DEVICE *dptr; + DIB *dibp; + dptr = find_dev_from_unit (uptr); + if (dptr == NULL) + return SCPE_IERR; + dibp = (DIB *) dptr->ctxt; + dptr->flags &= ~DEV_M_RH; + dptr->flags |= val; + dibp->dev_num &= ~(RH10_DEV|RH20_DEV); + dibp->dev_num |= (val) ? RH20_DEV: RH10_DEV; + return SCPE_OK; +} + +t_stat rh_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ + DEVICE *dptr; + + if (uptr == NULL) + return SCPE_IERR; + + dptr = find_dev_from_unit(uptr); + if (dptr == NULL) + return SCPE_IERR; + fprintf (st, "%s", (dptr->flags & TYPE_RH20) ? "RH20" : "RH10"); + return SCPE_OK; +} + + +t_stat rh_devio(uint32 dev, uint64 *data) { + DEVICE *dptr = NULL; + struct rh_if *rhc = NULL; + int drive; + + for (drive = 0; rh[drive].dev_num != 0; drive++) { + if (rh[drive].dev_num == (dev & 0774)) { + rhc = rh[drive].rh; + dptr = rh[drive].dev; + break; + } + } + if (rhc == NULL) + return SCPE_OK; + rhc->devnum = dev & 0774; +#if KL + if (dptr->flags & TYPE_RH20) { + switch(dev & 3) { + case CONI: + *data = rhc->status & RMASK; + if (rhc->attn != 0) + *data |= RH20_ATTN; + if (rhc->rae != 0) + *data |= RH20_RAE; + if ((rhc->status & PI_ENABLE) == 0) + *data |= RH20_CHAN_RDY; + sim_debug(DEBUG_CONI, dptr, "%s %03o CONI %06o PC=%o %o\n", + dptr->name, dev, (uint32)*data, PC, rhc->attn); + return SCPE_OK; + + case CONO: + clr_interrupt(dev); + rhc->status &= ~(07LL|IADR_ATTN|RH20_MASS_EN); + rhc->status |= *data & (07LL|IADR_ATTN|RH20_MASS_EN); + /* Clear flags */ + if (*data & RH20_CLR_MBC) { + if (rhc->rh_reset != NULL) + rhc->rh_reset(dptr); + rhc->imode = 2; + } + if (*data & RH20_DELETE_SCR) + rhc->status &= ~(RH20_SBAR|RH20_SCR_FULL); + if (*data & (RH20_RCLP|RH20_CLR_MBC)) + rhc->cia = eb_ptr | (rhc->devnum - 0540); + if (*data & (RH20_CLR_RAE|RH20_CLR_MBC)) + rhc->rae = 0; + if (*data & PI_ENABLE) + rhc->status &= ~PI_ENABLE; + if (((rhc->status & IADR_ATTN) != 0 && rhc->attn != 0) + || (rhc->status & PI_ENABLE)) + set_interrupt(rhc->devnum, rhc->status); + sim_debug(DEBUG_CONO, dptr, "%s %03o CONO %06o PC=%06o %06o\n", + dptr->name, dev, (uint32)*data, PC, rhc->status); + return SCPE_OK; + + case DATAI: + *data = 0; + if (rhc->status & BUSY && rhc->reg != 04) { + rhc->status |= CC_CHAN_ACT; + return SCPE_OK; + } + if (rhc->reg < 040) { + int parity; + *data = (uint64)(rhc->rh_read(dptr, rhc, rhc->reg) & 0177777); + parity = (int)((*data >> 8) ^ *data); + parity = (parity >> 4) ^ parity; + parity = (parity >> 2) ^ parity; + parity = ((parity >> 1) ^ parity) & 1; + *data |= ((uint64)(parity ^ 1)) << 17; + *data |= ((uint64)(rhc->drive)) << 18; + *data |= BIT10; + } else if ((rhc->reg & 070) != 070) { + rhc->rae = 1; + break; + } else { + switch(rhc->reg & 07) { + case 0: *data = rhc->sbar; break; + case 1: *data = rhc->stcr; break; + case 2: *data = rhc->pbar; break; + case 3: *data = rhc->ptcr; break; + case 4: *data = rhc->ivect; break; + case 5: + case 6: break; + case 7: *data = 0; break; + } + } + *data |= ((uint64)(rhc->reg)) << 30; + sim_debug(DEBUG_DATAIO, dptr, "%s %03o DATI %012llo %d PC=%06o\n", + dptr->name, dev, *data, rhc->drive, PC); + return SCPE_OK; + + case DATAO: + sim_debug(DEBUG_DATAIO, dptr, "%s %03o DATO %012llo PC=%06o %06o\n", + dptr->name, dev, *data, PC, rhc->status); + rhc->reg = ((int)(*data >> 30)) & 077; + rhc->imode |= 2; + if (rhc->reg < 040 && rhc->reg != 04) { + rhc->drive = (int)(*data >> 18) & 07; + } + if (*data & LOAD_REG) { + if (rhc->reg < 040) { + clr_interrupt(dev); + /* Check if access error */ + if (rhc->rae & (1 << rhc->drive) && (*data & BIT9) == 0) { + set_interrupt(rhc->devnum, rhc->status); + return SCPE_OK; + } + rhc->rh_write(dptr, rhc, rhc->reg & 037, (int)(*data & 0777777)); + if (((rhc->status & IADR_ATTN) != 0 && rhc->attn != 0) + || (rhc->status & PI_ENABLE)) + set_interrupt(rhc->devnum, rhc->status); + /* Check if access error */ + if (rhc->rae & (1 << rhc->drive) && (*data & BIT9) == 0) + set_interrupt(rhc->devnum, rhc->status); + else + rhc->rae &= ~(1 << rhc->drive); + } else if ((rhc->reg & 070) != 070) { + if ((*data & BIT9) == 0) { + rhc->rae = (1 << rhc->drive); + set_interrupt(rhc->devnum, rhc->status); + } + } else { + switch(rhc->reg & 07) { + case 0: + rhc->sbar = (*data) & (CR_DRIVE|RMASK); + rhc->status |= RH20_SBAR; + break; + case 1: + rhc->stcr = (*data) & (BIT10|BIT7|CR_DRIVE|RMASK); + rhc->status |= RH20_SCR_FULL; + break; + case 4: + rhc->ivect = (*data & IRQ_VECT); + break; + case 2: + case 3: + case 5: + case 6: + case 7: + break; + } + } + } + } + if ((rhc->status & (RH20_SCR_FULL|RH20_PCR_FULL)) == (RH20_SCR_FULL)) + rh20_setup(rhc); + return SCPE_OK; + } +#endif + switch(dev & 3) { + case CONI: + *data = rhc->status & ~(IADR_ATTN|IARD_RAE); + if (rhc->attn != 0 && (rhc->status & IADR_ATTN)) + *data |= IADR_ATTN; + if (rhc->rae != 0 && (rhc->status & IARD_RAE)) + *data |= IARD_RAE; +#if KI_22BIT + *data |= B22_FLAG; +#endif + sim_debug(DEBUG_CONI, dptr, "%s %03o CONI %06o PC=%o %o\n", + dptr->name, dev, (uint32)*data, PC, rhc->attn); + return SCPE_OK; + + case CONO: + clr_interrupt(dev); + rhc->status &= ~(07LL|IADR_ATTN|IARD_RAE); + rhc->status |= *data & (07LL|IADR_ATTN|IARD_RAE); + /* Clear flags */ + if (*data & CONT_RESET && rhc->rh_reset != NULL) + rhc->rh_reset(dptr); + if (*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)) + rhc->status &= ~(*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)); + if (*data & OVER_CLR) + rhc->status &= ~(DTC_OVER); + if (*data & CBOV_CLR) + rhc->status &= ~(DIB_CBOV); + if (*data & CXR_ILC) + rhc->status &= ~(CXR_ILFC|CXR_SD_RAE); + if (*data & WRT_CW) + rh_writecw(rhc, 0); + if (*data & PI_ENABLE) + rhc->status &= ~PI_ENABLE; + if (rhc->status & PI_ENABLE) + set_interrupt(dev, rhc->status); + if ((rhc->status & IADR_ATTN) != 0 && rhc->attn != 0) + set_interrupt(dev, rhc->status); + sim_debug(DEBUG_CONO, dptr, "%s %03o CONO %06o PC=%06o %06o\n", + dptr->name, dev, (uint32)*data, PC, rhc->status); + return SCPE_OK; + + case DATAI: + *data = 0; + if (rhc->status & BUSY && rhc->reg != 04) { + rhc->status |= CC_CHAN_ACT; + return SCPE_OK; + } + if (rhc->reg == 040) { + *data = (uint64)(rhc->rh_read(dptr, rhc, 0) & 077); + *data |= ((uint64)(rhc->cia)) << 6; + *data |= ((uint64)(rhc->xfer_drive)) << 18; + } else if (rhc->reg == 044) { + *data = (uint64)rhc->ivect; + if (rhc->imode) + *data |= IRQ_KI10; + else + *data |= IRQ_KA10; + } else if (rhc->reg == 054) { + *data = (uint64)(rhc->rae); + } else if ((rhc->reg & 040) == 0) { + int parity; + *data = (uint64)(rhc->rh_read(dptr, rhc, rhc->reg) & 0177777); + parity = (int)((*data >> 8) ^ *data); + parity = (parity >> 4) ^ parity; + parity = (parity >> 2) ^ parity; + parity = ((parity >> 1) ^ parity) & 1; + *data |= ((uint64)(parity ^ 1)) << 17; + *data |= ((uint64)(rhc->drive)) << 18; + } + *data |= ((uint64)(rhc->reg)) << 30; + sim_debug(DEBUG_DATAIO, dptr, "%s %03o DATI %012llo %d PC=%06o\n", + dptr->name, dev, *data, rhc->drive, PC); + return SCPE_OK; + + case DATAO: + sim_debug(DEBUG_DATAIO, dptr, "%s %03o DATO %012llo PC=%06o %06o\n", + dptr->name, dev, *data, PC, rhc->status); + rhc->reg = ((int)(*data >> 30)) & 077; + rhc->imode &= ~2; + if (rhc->reg < 040 && rhc->reg != 04) { + rhc->drive = (int)(*data >> 18) & 07; + } + if (*data & LOAD_REG) { + if (rhc->reg == 040) { + if ((*data & 1) == 0) { + return SCPE_OK; + } + + if (rhc->status & BUSY) { + rhc->status |= CC_CHAN_ACT; + return SCPE_OK; + } + + rhc->status &= ~(CCW_COMP_1|PI_ENABLE); + if (((*data >> 1) & 037) < FNC_XFER) { + rhc->status |= CXR_ILC; + rh_setirq(rhc); + sim_debug(DEBUG_DATAIO, dptr, + "%s %03o command abort %012llo, %d PC=%06o %06o\n", + dptr->name, dev, *data, rhc->drive, PC, rhc->status); + return SCPE_OK; + } + /* Check if access error */ + if (rhc->rae & (1 << rhc->drive)) + return SCPE_OK; + /* Start command */ + rh_setup(rhc, (uint32)(*data >> 6)); + rhc->xfer_drive = (int)(*data >> 18) & 07; + rhc->rh_write(dptr, rhc, 0, (uint32)(*data & 077)); + sim_debug(DEBUG_DATAIO, dptr, + "%s %03o command %012llo, %d PC=%06o %06o\n", + dptr->name, dev, *data, rhc->drive, PC, rhc->status); + } else if (rhc->reg == 044) { + /* Set KI10 Irq vector */ + rhc->ivect = (int)(*data & IRQ_VECT); + rhc->imode = (*data & IRQ_KI10) != 0; + } else if (rhc->reg == 050) { + ; /* Diagnostic access to mass bus. */ + } else if (rhc->reg == 054) { + /* clear flags */ + rhc->rae &= ~(*data & 0377); + if (rhc->rae == 0) + clr_interrupt(dev); + } else if ((rhc->reg & 040) == 0) { + rhc->drive = (int)(*data >> 18) & 07; + /* Check if access error */ + if (rhc->rae & (1 << rhc->drive)) { + return SCPE_OK; + } + rhc->rh_write(dptr, rhc, rhc->reg & 037, (int)(*data & 0777777)); + } + } + clr_interrupt(dev); + if (((rhc->status & (IADR_ATTN|BUSY)) == IADR_ATTN && rhc->attn != 0) + || (rhc->status & PI_ENABLE)) + set_interrupt(rhc->devnum, rhc->status); + return SCPE_OK; + } + return SCPE_OK; /* Unreached */ +} + +/* Handle KI and KL style interrupt vectors */ +int +rh_devirq(uint32 dev, int addr) { + DEVICE *dptr = NULL; + struct rh_if *rhc = NULL; + int drive; + + for (drive = 0; rh[drive].dev_num != 0; drive++) { + if (rh[drive].dev_num == (dev & 0774)) { + rhc = rh[drive].rh; + break; + } + } + if (rhc != NULL) { + return (rhc->imode ? rhc->ivect : addr); + } + return addr; +} + +/* Set the attention flag for a unit */ +void rh_setattn(struct rh_if *rhc, int unit) +{ + rhc->attn |= 1<status & IADR_ATTN) != 0) + rh_setirq(rhc); +} + +/* Decrement block count for RH20, nop for RH10 */ +int rh_blkend(struct rh_if *rhc) +{ +#if KL + if (rhc->imode == 2) { + rhc->cia = (rhc->cia + 1) & RH20_WMASK; + if (rhc->cia == 0) { + rhc->status |= RH20_XEND; + return 1; + } + } +#endif + return 0; +} + +/* Set an IRQ for a DF10 device */ +void rh_setirq(struct rh_if *rhc) { + rhc->status |= PI_ENABLE; + set_interrupt(rhc->devnum, rhc->status); +} + +/* Generate the DF10 complete word */ +void rh_writecw(struct rh_if *rhc, int nxm) { +#if KL + if (rhc->imode == 2) { + uint32 chan = (rhc->devnum - 0540); + if (rhc->ptcr & BIT10) { + int wc = (rhc->wcr ^ RH20_WMASK) + 1; + uint64 wrd1 = SMASK|(uint64)(rhc->ccw); + if (nxm) + wrd1 |= RH20_NXM_ERR; + if (wc != 0) { + wrd1 |= RH20_NOT_WC0; + if (rhc->status & RH20_XEND) { + wrd1 |= RH20_LONG_STS; + rhc->status |= RH20_LONG_WC; + } + } else if ((rhc->status & RH20_XEND) == 0) { + wrd1 |= RH20_SHRT_STS; + rhc->status |= RH20_SHRT_WC; + } + M[eb_ptr|chan|1] = wrd1; + M[eb_ptr|chan|2] = ((uint64)rhc->cop << 30) | + (((uint64)wc & RH20_WMASK) << CSHIFT) | + ((uint64)(rhc->cda) & AMASK); + } + rhc->status &= ~(RH20_PCR_FULL); + return; + } +#endif + if (nxm) + rhc->status |= CXR_NXM; + rhc->status |= CCW_COMP_1; + if (rhc->wcr != 0) + rhc->cda++; + M[rhc->cia|1] = ((uint64)(rhc->ccw & WMASK) << CSHIFT) | ((uint64)(rhc->cda) & AMASK); +} + +/* Finish off a DF10 transfer */ +void rh_finish_op(struct rh_if *rhc, int nxm) { +#if KL + if (rhc->imode != 2) +#endif + rhc->status &= ~BUSY; + rh_writecw(rhc, nxm); + rh_setirq(rhc); +#if KL + if (rhc->imode == 2 && + (rhc->status & (RH20_SCR_FULL|RH20_PCR_FULL)) == (RH20_SCR_FULL)) + rh20_setup(rhc); +#endif +} + +#if KL + +/* Set up for a RH20 transfer */ +void rh20_setup(struct rh_if *rhc) +{ + int reg; + DEVICE *dptr; + + for (reg = 0; rh[reg].dev_num != 0; reg++) { + if (rh[reg].rh == rhc) { + dptr = rh[reg].dev; + break; + } + } + if (dptr == 0) + return; + rhc->pbar = rhc->sbar; + rhc->ptcr = rhc->stcr; + /* Read drive status */ + rhc->drive = (rhc->ptcr >> 18) & 07; + rhc->status &= ~(RH20_SCR_FULL|PI_ENABLE|RH20_XEND); + rhc->status |= RH20_PCR_FULL; + reg = rhc->rh_read(dptr, rhc, 1); + if ((reg & (DS_DRY|DS_DPR|DS_ERR)) != (DS_DRY|DS_DPR)) + return; + if (rhc->status & RH20_SBAR) { + rhc->drive = (rhc->pbar >> 18) & 07; + rhc->rh_write(dptr, rhc, 5, (rhc->pbar & 0177777)); + rhc->status &= ~RH20_SBAR; + } + if (rhc->ptcr & BIT7) { /* If RCPL reset I/O pointers */ + rhc->ccw = eb_ptr + (rhc->devnum - 0540); + rhc->wcr = 0; + } + /* Hold block count in cia */ + rhc->cia = (rhc->ptcr >> 6); + rhc->rh_write(dptr, rhc, 0, (rhc->ptcr & 077)); + rhc->cop = 0; +} +#endif + +/* Setup for a DF10 transfer */ +void rh_setup(struct rh_if *rhc, uint32 addr) +{ + rhc->cia = addr & ICWA; + rhc->ccw = rhc->cia; + rhc->wcr = 0; + rhc->status |= BUSY; +} + + +/* Fetch the next IO control word */ +int rh_fetch(struct rh_if *rhc) { + uint64 data; +#if KL + if (rhc->imode == 2 && (rhc->cop & 2) != 0) { + rh_finish_op(rhc, 0); + return 0; + } +#endif + if (rhc->ccw > MEMSIZE) { + rh_finish_op(rhc, 1); + return 0; + } + data = M[rhc->ccw]; +#if KL + if (rhc->imode == 2) { + while((data & RH20_XFER) == 0) { + rhc->ccw = (uint32)(data & AMASK); + if ((data & (BIT1|BIT2)) == 0) { + rh_finish_op(rhc, 0); + break; + } + if (rhc->ccw > MEMSIZE) { + rh_finish_op(rhc, 1); + return 0; + } + data = M[rhc->ccw]; + } + rhc->wcr = (((data >> CSHIFT) & RH20_WMASK) ^ WMASK) + 1; + rhc->cda = (data & AMASK); + rhc->cop = (data >> 33) & 07; + rhc->ccw = (uint32)((rhc->ccw + 1) & AMASK); + return 1; + } +#endif + while((data & (WMASK << CSHIFT)) == 0) { + if ((data & AMASK) == 0 || (uint32)(data & AMASK) == rhc->ccw) { + rh_finish_op(rhc,0); + return 0; + } + rhc->ccw = (uint32)(data & AMASK); + if (rhc->ccw > MEMSIZE) { + rh_finish_op(rhc, 1); + return 0; + } + data = M[rhc->ccw]; + } + rhc->wcr = (uint32)((data >> CSHIFT) & WMASK); + rhc->cda = (uint32)(data & AMASK); + rhc->ccw = (uint32)((rhc->ccw + 1) & AMASK); + return 1; +} + +/* Read next word */ +int rh_read(struct rh_if *rhc) { + uint64 data; + if (rhc->wcr == 0) { + if (!rh_fetch(rhc)) + return 0; + } + rhc->wcr = (uint32)((rhc->wcr + 1) & WMASK); + if (rhc->cda != 0) { + if (rhc->cda > MEMSIZE) { + rh_finish_op(rhc, 1); + return 0; + } +#if KL + if (rhc->imode == 2) { + data = M[rhc->cda]; + if (rhc->cop & 01) + rhc->cda = (uint32)((rhc->cda - 1) & AMASK); + else + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + } else { + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + data = M[rhc->cda]; + } +#else + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + data = M[rhc->cda]; +#endif + } else { + data = 0; + } + rhc->buf = data; + if (rhc->wcr == 0) { + return rh_fetch(rhc); + } + return 1; +} + +/* Write next word */ +int rh_write(struct rh_if *rhc) { + if (rhc->wcr == 0) { + if (!rh_fetch(rhc)) + return 0; + } + rhc->wcr = (uint32)((rhc->wcr + 1) & WMASK); + if (rhc->cda != 0) { + if (rhc->cda > MEMSIZE) { + rh_finish_op(rhc, 1); + return 0; + } +#if KL + if (rhc->imode == 2) { + M[rhc->cda] = rhc->buf; + if (rhc->cop & 01) + rhc->cda = (uint32)((rhc->cda - 1) & AMASK); + else + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + } else { + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + M[rhc->cda] = rhc->buf; + } +#else + rhc->cda = (uint32)((rhc->cda + 1) & AMASK); + M[rhc->cda] = rhc->buf; +#endif + } + if (rhc->wcr == 0) { + return rh_fetch(rhc); + } + return 1; +} + diff --git a/PDP10/kx10_rp.c b/PDP10/kx10_rp.c index 37eb5e9..9c421f6 100644 --- a/PDP10/kx10_rp.c +++ b/PDP10/kx10_rp.c @@ -45,79 +45,13 @@ #define DTYPE(x) (((x) & UNIT_M_DTYPE) << UNIT_V_DTYPE) #define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE) #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */ -#define CNTRL_V_CTYPE (UNIT_V_UF + 4) -#define CNTRL_M_CTYPE 7 -#define GET_CNTRL(x) (((x) >> CNTRL_V_CTYPE) & CNTRL_M_CTYPE) -#define CNTRL(x) (((x) & CNTRL_M_CTYPE) << CNTRL_V_CTYPE) /* Parameters in the unit descriptor */ - -/* CONI Flags */ -#define IADR_ATTN 0000000000040LL /* Interrupt on attention */ -#define IARD_RAE 0000000000100LL /* Interrupt on register access error */ -#define DIB_CBOV 0000000000200LL /* Control bus overrun */ -#define CXR_PS_FAIL 0000000002000LL /* Power supply fail (not implemented) */ -#define CXR_ILC 0000000004000LL /* Illegal function code */ -#define CR_DRE 0000000010000LL /* Or Data and Control Timeout */ -#define DTC_OVER 0000000020000LL /* DF10 did not supply word on time (not implemented) */ -#define CCW_COMP_1 0000000040000LL /* Control word written. */ -#define CXR_CHAN_ER 0000000100000LL /* Channel Error */ -#define CXR_EXC 0000000200000LL /* Error in drive transfer */ -#define CXR_DBPE 0000000400000LL /* Device Parity error (not implemented) */ -#define CXR_NXM 0000001000000LL /* Channel non-existent memory (not implemented) */ -#define CXR_CWPE 0000002000000LL /* Channel Control word parity error (not implemented) */ -#define CXR_CDPE 0000004000000LL /* Channel Data Parity Error (not implemented) */ -#define CXR_SD_RAE 0000200000000LL /* Register access error */ -#define CXR_ILFC 0000400000000LL /* Illegal CXR function code */ -#define B22_FLAG 0004000000000LL /* 22 bit channel */ -#define CC_CHAN_PLS 0010000000000LL /* Channel transfer pulse (not implemented) */ -#define CC_CHAN_ACT 0020000000000LL /* Channel in use */ -#define CC_INH 0040000000000LL /* Disconnect channel */ -#define CB_FULL 0200000000000LL /* Set when channel buffer is full (not implemented) */ -#define AR_FULL 0400000000000LL /* Set when AR is full (not implemented) */ - -/* CONO Flags */ -#define ATTN_EN 0000000000040LL /* enable attention interrupt. */ -#define REA_EN 0000000000100LL /* enable register error interrupt */ -#define CBOV_CLR 0000000000200LL /* Clear CBOV */ -#define CONT_RESET 0000000002000LL /* Clear All error bits */ -#define ILC_CLR 0000000004000LL /* Clear ILC and SD RAE */ -#define DRE_CLR 0000000010000LL /* Clear CR_CBTO and CR_DBTO */ -#define OVER_CLR 0000000020000LL /* Clear DTC overrun */ -#define WRT_CW 0000000040000LL /* Write control word */ -#define CHN_CLR 0000000100000LL /* Clear Channel Error */ -#define DR_EXC_CLR 0000000200000LL /* Clear DR_EXC */ -#define DBPE_CLR 0000000400000LL /* Clear CXR_DBPE */ - -/* RH20 CONO Flags */ -#define RH20_DELETE_SCR 0000000000100LL /* Clear SCR */ -#define RH20_RCLP 0000000000200LL /* Reset command list */ -#define RH20_MASS_EN 0000000000400LL /* Mass bus enable */ -#define RH20_XFER_CLR 0000000001000LL /* Clear XFER error */ -#define RH20_CLR_MBC 0000000002000LL /* Clear MBC */ -#define RH20_CLR_RAE 0000000004000LL /* Clear RAE error */ - -/* DATAO/DATAI */ -#define CR_REG 0770000000000LL /* Register number */ -#define LOAD_REG 0004000000000LL /* Load register */ -#define CR_MAINT_MODE 0000100000000LL /* Maint mode... not implemented */ -#define CR_DRIVE 0000007000000LL -#define CR_GEN_EVD 0000000400000LL /* Enable Parity */ -#define CR_DXES 0000000200000LL /* Disable DXES errors */ -#define CR_INAD 0000000077600LL -#define CR_WTEVM 0000000000100LL /* Verify Parity */ -#define CR_FUNC 0000000000076LL -#define CR_GO 0000000000001LL - -#define IRQ_VECT 0000000000177LL /* Interupt vector */ -#define IRQ_KI10 0000002000000LL -#define IRQ_KA10 0000001000000LL - #define CMD u3 /* u3 low */ /* RPC - 00 - control */ -#define CS1_GO CR_GO /* go */ +#define CS1_GO 1 /* go */ #define CS1_V_FNC 1 /* function pos */ #define CS1_M_FNC 037 /* function mask */ #define CS1_FNC (CS1_M_FNC << CS1_V_FNC) @@ -291,20 +225,11 @@ struct drvtyp rp_drv_tab[] = { }; -struct df10 rp_df10[NUM_DEVS_RP]; -int rp_xfer_drive[NUM_DEVS_RP]; -uint64 rp_buf[NUM_DEVS_RP][RP_NUMWD]; -int rp_reg[NUM_DEVS_RP]; -int rp_ivect[NUM_DEVS_RP]; -int rp_imode[NUM_DEVS_RP]; -int rp_drive[NUM_DEVS_RP]; -int rp_rae[NUM_DEVS_RP]; -int rp_attn[NUM_DEVS_RP]; - t_stat rp_devio(uint32 dev, uint64 *data); int rp_devirq(uint32 dev, int addr); -void rp_write(int ctlr, int unit, int reg, uint32 data); -uint32 rp_read(int ctlr, int unit, int reg); +void rp_write(DEVICE *dptr, struct rh_if *rh, int reg, uint32 data); +uint32 rp_read(DEVICE *dptr, struct rh_if *rh, int reg); +void rp_rst(DEVICE *dptr); t_stat rp_svc(UNIT *); t_stat rp_boot(int32, DEVICE *); void rp_ini(UNIT *, t_bool); @@ -315,92 +240,107 @@ t_stat rp_set_type(UNIT *uptr, int32 val, CONST char *cptr, void *desc); t_stat rp_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); const char *rp_description (DEVICE *dptr); +uint64 rp_buf[NUM_DEVS_RP][RP_NUMWD]; UNIT rp_unit[] = { /* Controller 1 */ { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(0), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(0), RP06_SIZE) }, #if (NUM_DEVS_RP > 1) /* Controller 2 */ { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(1), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(1), RP06_SIZE) }, #if (NUM_DEVS_RP > 2) /* Controller 3 */ { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(2), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(2), RP06_SIZE) }, #if (NUM_DEVS_RP > 3) /* Controller 4 */ { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, { UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL(3), RP06_SIZE) }, + UNIT_ROABLE+DTYPE(RP06_DTYPE)+CNTRL_RH(3), RP06_SIZE) }, #endif #endif #endif }; +struct rh_if rp_rh[NUM_DEVS_RP] = { + { &rp_write, &rp_read, &rp_rst}, + { &rp_write, &rp_read, &rp_rst}, + { &rp_write, &rp_read, &rp_rst}, + { &rp_write, &rp_read, &rp_rst} +}; + DIB rp_dib[] = { - {RH10_DEV, 1, &rp_devio, &rp_devirq}, - {RH10_DEV, 1, &rp_devio, &rp_devirq}, - {RH10_DEV, 1, &rp_devio, &rp_devirq}, - {RH10_DEV, 1, &rp_devio, &rp_devirq}}; + {RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[0]}, + {RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[1]}, + {RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[2]}, + {RH10_DEV, 1, &rh_devio, &rh_devirq, &rp_rh[3]}}; + MTAB rp_mod[] = { +#if KL + {MTAB_XTD|MTAB_VDV, TYPE_RH10, NULL, "RH10", &rh_set_type, NULL, + NULL, "Sets controller to RH10" }, + {MTAB_XTD|MTAB_VDV, TYPE_RH20, "RH20", "RH20", &rh_set_type, &rh_show_type, + NULL, "Sets controller to RH20"}, +#endif {UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL}, {UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL}, {UNIT_DTYPE, (RP07_DTYPE << UNIT_V_DTYPE), "RP07", "RP07", &rp_set_type }, @@ -410,22 +350,20 @@ MTAB rp_mod[] = { }; REG rpa_reg[] = { - {ORDATA(IVECT, rp_ivect[0], 18)}, - {FLDATA(IMODE, rp_imode[0], 0)}, - {ORDATA(XFER, rp_xfer_drive[0], 3), REG_HRO}, - {ORDATA(DRIVE, rp_drive[0], 3), REG_HRO}, - {ORDATA(REG, rp_reg[0], 6), REG_RO}, - {ORDATA(RAE, rp_rae[0], 8), REG_RO}, - {ORDATA(ATTN, rp_attn[0], 8), REG_RO}, - {ORDATA(STATUS, rp_df10[0].status, 18), REG_RO}, - {ORDATA(CIA, rp_df10[0].cia, 18)}, - {ORDATA(CCW, rp_df10[0].ccw, 18)}, - {ORDATA(WCR, rp_df10[0].wcr, 18)}, - {ORDATA(CDA, rp_df10[0].cda, 18)}, - {ORDATA(DEVNUM, rp_df10[0].devnum, 9), REG_HRO}, - {ORDATA(BUF, rp_df10[0].buf, 36), REG_HRO}, - {ORDATA(NXM, rp_df10[0].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, rp_df10[0].ccw_comp, 8), REG_HRO}, + {ORDATA(IVECT, rp_rh[0].ivect, 18)}, + {FLDATA(IMODE, rp_rh[0].imode, 0)}, + {ORDATA(XFER, rp_rh[0].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, rp_rh[0].drive, 3), REG_HRO}, + {ORDATA(REG, rp_rh[0].reg, 6), REG_RO}, + {ORDATA(RAE, rp_rh[0].rae, 8), REG_RO}, + {ORDATA(ATTN, rp_rh[0].attn, 8), REG_RO}, + {ORDATA(STATUS, rp_rh[0].status, 18), REG_RO}, + {ORDATA(CIA, rp_rh[0].cia, 18)}, + {ORDATA(CCW, rp_rh[0].ccw, 18)}, + {ORDATA(WCR, rp_rh[0].wcr, 18)}, + {ORDATA(CDA, rp_rh[0].cda, 18)}, + {ORDATA(DEVNUM, rp_rh[0].devnum, 9), REG_HRO}, + {ORDATA(BUF, rp_rh[0].buf, 36), REG_HRO}, {BRDATA(BUFF, &rp_buf[0][0], 16, 64, RP_NUMWD), REG_HRO}, {0} }; @@ -440,22 +378,20 @@ DEVICE rpa_dev = { #if (NUM_DEVS_RP > 1) REG rpb_reg[] = { - {ORDATA(IVECT, rp_ivect[1], 18)}, - {FLDATA(IMODE, rp_imode[1], 0)}, - {ORDATA(XFER, rp_xfer_drive[1], 3), REG_HRO}, - {ORDATA(DRIVE, rp_drive[1], 3), REG_HRO}, - {ORDATA(REG, rp_reg[1], 6), REG_RO}, - {ORDATA(RAE, rp_rae[1], 8), REG_RO}, - {ORDATA(ATTN, rp_attn[1], 8), REG_RO}, - {ORDATA(STATUS, rp_df10[1].status, 18), REG_RO}, - {ORDATA(CIA, rp_df10[1].cia, 18)}, - {ORDATA(CCW, rp_df10[1].ccw, 18)}, - {ORDATA(WCR, rp_df10[1].wcr, 18)}, - {ORDATA(CDA, rp_df10[1].cda, 18)}, - {ORDATA(DEVNUM, rp_df10[1].devnum, 9), REG_HRO}, - {ORDATA(BUF, rp_df10[1].buf, 36), REG_HRO}, - {ORDATA(NXM, rp_df10[1].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, rp_df10[1].ccw_comp, 8), REG_HRO}, + {ORDATA(IVECT, rp_rh[1].ivect, 18)}, + {FLDATA(IMODE, rp_rh[1].imode, 0)}, + {ORDATA(XFER, rp_rh[1].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, rp_rh[1].drive, 3), REG_HRO}, + {ORDATA(REG, rp_rh[1].reg, 6), REG_RO}, + {ORDATA(RAE, rp_rh[1].rae, 8), REG_RO}, + {ORDATA(ATTN, rp_rh[1].attn, 8), REG_RO}, + {ORDATA(STATUS, rp_rh[1].status, 18), REG_RO}, + {ORDATA(CIA, rp_rh[1].cia, 18)}, + {ORDATA(CCW, rp_rh[1].ccw, 18)}, + {ORDATA(WCR, rp_rh[1].wcr, 18)}, + {ORDATA(CDA, rp_rh[1].cda, 18)}, + {ORDATA(DEVNUM, rp_rh[1].devnum, 9), REG_HRO}, + {ORDATA(BUF, rp_rh[1].buf, 36), REG_HRO}, {BRDATA(BUFF, &rp_buf[1][0], 16, 64, RP_NUMWD), REG_HRO}, {0} }; @@ -470,22 +406,20 @@ DEVICE rpb_dev = { #if (NUM_DEVS_RP > 2) REG rpc_reg[] = { - {ORDATA(IVECT, rp_ivect[2], 18)}, - {FLDATA(IMODE, rp_imode[2], 0)}, - {ORDATA(XFER, rp_xfer_drive[2], 3), REG_HRO}, - {ORDATA(DRIVE, rp_drive[2], 3), REG_HRO}, - {ORDATA(REG, rp_reg[2], 6), REG_RO}, - {ORDATA(RAE, rp_rae[2], 8), REG_RO}, - {ORDATA(ATTN, rp_attn[2], 8), REG_RO}, - {ORDATA(STATUS, rp_df10[2].status, 18), REG_RO}, - {ORDATA(CIA, rp_df10[2].cia, 18)}, - {ORDATA(CCW, rp_df10[2].ccw, 18)}, - {ORDATA(WCR, rp_df10[2].wcr, 18)}, - {ORDATA(CDA, rp_df10[2].cda, 18)}, - {ORDATA(DEVNUM, rp_df10[2].devnum, 9), REG_HRO}, - {ORDATA(BUF, rp_df10[2].buf, 36), REG_HRO}, - {ORDATA(NXM, rp_df10[2].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, rp_df10[2].ccw_comp, 8), REG_HRO}, + {ORDATA(IVECT, rp_rh[2].ivect, 18)}, + {FLDATA(IMODE, rp_rh[2].imode, 0)}, + {ORDATA(XFER, rp_rh[2].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, rp_rh[2].drive, 3), REG_HRO}, + {ORDATA(REG, rp_rh[2].reg, 6), REG_RO}, + {ORDATA(RAE, rp_rh[2].rae, 8), REG_RO}, + {ORDATA(ATTN, rp_rh[2].attn, 8), REG_RO}, + {ORDATA(STATUS, rp_rh[2].status, 18), REG_RO}, + {ORDATA(CIA, rp_rh[2].cia, 18)}, + {ORDATA(CCW, rp_rh[2].ccw, 18)}, + {ORDATA(WCR, rp_rh[2].wcr, 18)}, + {ORDATA(CDA, rp_rh[2].cda, 18)}, + {ORDATA(DEVNUM, rp_rh[2].devnum, 9), REG_HRO}, + {ORDATA(BUF, rp_rh[2].buf, 36), REG_HRO}, {BRDATA(BUFF, &rp_buf[2][0], 16, 64, RP_NUMWD), REG_HRO}, {0} }; @@ -500,22 +434,20 @@ DEVICE rpc_dev = { #if (NUM_DEVS_RP > 3) REG rpd_reg[] = { - {ORDATA(IVECT, rp_ivect[3], 18)}, - {FLDATA(IMODE, rp_imode[3], 0)}, - {ORDATA(XFER, rp_xfer_drive[3], 3), REG_HRO}, - {ORDATA(DRIVE, rp_drive[3], 3), REG_HRO}, - {ORDATA(REG, rp_reg[3], 6), REG_RO}, - {ORDATA(RAE, rp_rae[3], 8), REG_RO}, - {ORDATA(ATTN, rp_attn[3], 8), REG_RO}, - {ORDATA(STATUS, rp_df10[3].status, 18), REG_RO}, - {ORDATA(CIA, rp_df10[3].cia, 18)}, - {ORDATA(CCW, rp_df10[3].ccw, 18)}, - {ORDATA(WCR, rp_df10[3].wcr, 18)}, - {ORDATA(CDA, rp_df10[3].cda, 18)}, - {ORDATA(DEVNUM, rp_df10[3].devnum, 9), REG_HRO}, - {ORDATA(BUF, rp_df10[3].buf, 36), REG_HRO}, - {ORDATA(NXM, rp_df10[3].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, rp_df10[3].ccw_comp, 8), REG_HRO}, + {ORDATA(IVECT, rp_rh[3].ivect, 18)}, + {FLDATA(IMODE, rp_rh[3].imode, 0)}, + {ORDATA(XFER, rp_rh[3].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, rp_rh[3].drive, 3), REG_HRO}, + {ORDATA(REG, rp_rh[3].reg, 6), REG_RO}, + {ORDATA(RAE, rp_rh[3].rae, 8), REG_RO}, + {ORDATA(ATTN, rp_rh[3].attn, 8), REG_RO}, + {ORDATA(STATUS, rp_rh[3].status, 18), REG_RO}, + {ORDATA(CIA, rp_rh[3].cia, 18)}, + {ORDATA(CCW, rp_rh[3].ccw, 18)}, + {ORDATA(WCR, rp_rh[3].wcr, 18)}, + {ORDATA(CDA, rp_rh[3].cda, 18)}, + {ORDATA(DEVNUM, rp_rh[3].devnum, 9), REG_HRO}, + {ORDATA(BUF, rp_rh[3].buf, 36), REG_HRO}, {BRDATA(BUFF, &rp_buf[3][0], 16, 64, RP_NUMWD), REG_HRO}, {0} }; @@ -546,214 +478,48 @@ DEVICE *rp_devs[] = { }; -t_stat rp_devio(uint32 dev, uint64 *data) { - int ctlr = -1; - DEVICE *dptr = NULL; - struct df10 *df10; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - if (dptr == NULL) - return SCPE_OK; - ctlr = GET_CNTRL(dptr->units[0].flags); - df10 = &rp_df10[ctlr]; - df10->devnum = dev; - switch(dev & 3) { - case CONI: - *data = df10->status & ~(IADR_ATTN|IARD_RAE); - if (rp_attn[ctlr] != 0 && (df10->status & IADR_ATTN)) - *data |= IADR_ATTN; - if (rp_rae[ctlr] != 0 && (df10->status & IARD_RAE)) - *data |= IARD_RAE; -#if KI_22BIT - *data |= B22_FLAG; -#endif - sim_debug(DEBUG_CONI, dptr, "RP %03o CONI %06o PC=%o %o\n", - dev, (uint32)*data, PC, rp_attn[ctlr]); - return SCPE_OK; - - case CONO: - clr_interrupt(dev); - df10->status &= ~(07LL|IADR_ATTN|IARD_RAE); - df10->status |= *data & (07LL|IADR_ATTN|IARD_RAE); - /* Clear flags */ - if (*data & CONT_RESET) { - UNIT *uptr=dptr->units; - for(drive = 0; drive < NUM_UNITS_RP; drive++, uptr++) { - uptr->CMD &= DS_MOL|DS_WRL|DS_DPR|DS_DRY|DS_VV|076; - uptr->DA &= 003400177777; - uptr->CCYL &= 0177777; - uptr->ERR2 = 0; - uptr->ERR3 = 0; - } - } - if (*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)) - df10->status &= ~(*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)); - if (*data & OVER_CLR) - df10->status &= ~(DTC_OVER); - if (*data & CBOV_CLR) - df10->status &= ~(DIB_CBOV); - if (*data & CXR_ILC) - df10->status &= ~(CXR_ILFC|CXR_SD_RAE); - if (*data & WRT_CW) - df10_writecw(df10); - if (*data & PI_ENABLE) - df10->status &= ~PI_ENABLE; - if (df10->status & PI_ENABLE) - set_interrupt(dev, df10->status); - if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) - set_interrupt(dev, df10->status); - sim_debug(DEBUG_CONO, dptr, "RP %03o CONO %06o %d PC=%06o %06o\n", - dev, (uint32)*data, ctlr, PC, df10->status); - return SCPE_OK; - - case DATAI: - *data = 0; - if (df10->status & BUSY && rp_reg[ctlr] != 04) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } - if (rp_reg[ctlr] == 040) { - *data = (uint64)(rp_read(ctlr, rp_drive[ctlr], 0) & 077); - *data |= ((uint64)(df10->cia)) << 6; - *data |= ((uint64)(rp_xfer_drive[ctlr])) << 18; - } else if (rp_reg[ctlr] == 044) { - *data = (uint64)rp_ivect[ctlr]; - if (rp_imode[ctlr]) - *data |= IRQ_KI10; - else - *data |= IRQ_KA10; - } else if (rp_reg[ctlr] == 054) { - *data = (uint64)(rp_rae[ctlr]); - } else if ((rp_reg[ctlr] & 040) == 0) { - int parity; - *data = (uint64)(rp_read(ctlr, rp_drive[ctlr], rp_reg[ctlr]) & 0177777); - parity = (int)((*data >> 8) ^ *data); - parity = (parity >> 4) ^ parity; - parity = (parity >> 2) ^ parity; - parity = ((parity >> 1) ^ parity) & 1; - *data |= ((uint64)(parity ^ 1)) << 17; - *data |= ((uint64)(rp_drive[ctlr])) << 18; - } - *data |= ((uint64)(rp_reg[ctlr])) << 30; - sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d %d PC=%06o\n", - dev, *data, ctlr, rp_drive[ctlr], PC); - return SCPE_OK; - - case DATAO: - sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATO %012llo, %d PC=%06o %06o\n", - dev, *data, ctlr, PC, df10->status); - rp_reg[ctlr] = ((int)(*data >> 30)) & 077; - if (rp_reg[ctlr] < 040 && rp_reg[ctlr] != 04) { - rp_drive[ctlr] = (int)(*data >> 18) & 07; - } - if (*data & LOAD_REG) { - if (rp_reg[ctlr] == 040) { - if ((*data & 1) == 0) { - return SCPE_OK; - } - - if (df10->status & BUSY) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } - - df10->status &= ~(1 << df10->ccw_comp); - df10->status &= ~PI_ENABLE; - if (((*data >> 1) & 037) < FNC_XFER) { - df10->status |= CXR_ILC; - df10_setirq(df10); - sim_debug(DEBUG_DATAIO, dptr, - "RP %03o command abort %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, rp_drive[ctlr], PC, df10->status); - return SCPE_OK; - } - /* Start command */ - df10_setup(df10, (uint32)(*data >> 6)); - rp_xfer_drive[ctlr] = (int)(*data >> 18) & 07; - rp_write(ctlr, rp_drive[ctlr], 0, (uint32)(*data & 077)); - sim_debug(DEBUG_DATAIO, dptr, - "RP %03o command %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, rp_drive[ctlr], PC, df10->status); - } else if (rp_reg[ctlr] == 044) { - /* Set KI10 Irq vector */ - rp_ivect[ctlr] = (int)(*data & IRQ_VECT); - rp_imode[ctlr] = (*data & IRQ_KI10) != 0; - } else if (rp_reg[ctlr] == 050) { - ; /* Diagnostic access to mass bus. */ - } else if (rp_reg[ctlr] == 054) { - /* clear flags */ - rp_rae[ctlr] &= ~(*data & 0377); - if (rp_rae[ctlr] == 0) - clr_interrupt(dev); - } else if ((rp_reg[ctlr] & 040) == 0) { - rp_drive[ctlr] = (int)(*data >> 18) & 07; - /* Check if access error */ - if (rp_rae[ctlr] & (1 << rp_drive[ctlr])) { - return SCPE_OK; - } - rp_write(ctlr, rp_drive[ctlr], rp_reg[ctlr] & 037, - (int)(*data & 0777777)); - } - } - return SCPE_OK; - } - return SCPE_OK; /* Unreached */ -} - -/* Handle KI and KL style interrupt vectors */ -int -rp_devirq(uint32 dev, int addr) { - DEVICE *dptr = NULL; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - if (dptr != NULL) { - drive = GET_CNTRL(dptr->units[0].flags); - return (rp_imode[drive] ? rp_ivect[drive] : addr); - } - return addr; +void +rp_rst(DEVICE *dptr) +{ + UNIT *uptr=dptr->units; + int drive; + for(drive = 0; drive < NUM_UNITS_RP; drive++, uptr++) { + uptr->CMD &= DS_MOL|DS_WRL|DS_DPR|DS_DRY|DS_VV|076; + uptr->DA &= 003400177777; + uptr->CCYL &= 0177777; + uptr->ERR2 = 0; + uptr->ERR3 = 0; + } } void -rp_write(int ctlr, int unit, int reg, uint32 data) { +rp_write(DEVICE *dptr, struct rh_if *rhc, int reg, uint32 data) { int i; - DEVICE *dptr = rp_devs[ctlr]; + int unit = rhc->drive; UNIT *uptr = &dptr->units[unit]; - struct df10 *df10 = &rp_df10[ctlr]; int dtype = GET_DTYPE(uptr->flags); - if ((uptr->CMD & CR_GO) && reg != 04) { + if ((uptr->CMD & CS1_GO) && reg != 04) { uptr->CMD |= (ER1_RMR << 16)|DS_ERR; return; } switch(reg) { case 000: /* control */ - sim_debug(DEBUG_DETAIL, dptr, "RP%o %d Status=%06o\n", unit, ctlr, uptr->CMD); + sim_debug(DEBUG_DETAIL, dptr, "%s%o Status=%06o\n", dptr->name, unit, uptr->CMD); /* Set if drive not writable */ if (uptr->flags & UNIT_WLK) uptr->CMD |= DS_WRL; /* If drive not ready don't do anything */ if ((uptr->CMD & DS_DRY) == 0) { uptr->CMD |= (ER1_RMR << 16)|DS_ERR; - sim_debug(DEBUG_DETAIL, dptr, "RP%o %d not ready\n", unit, ctlr); + sim_debug(DEBUG_DETAIL, dptr, "%s%o not ready\n", dptr->name, unit); return; } /* Check if GO bit set */ if ((data & 1) == 0) { uptr->CMD &= ~076; uptr->CMD |= data & 076; - sim_debug(DEBUG_DETAIL, dptr, "RP%o %d no go\n", unit, ctlr); + sim_debug(DEBUG_DETAIL, dptr, "%s%o no go\n", dptr->name, unit); return; /* No, nop */ } uptr->CMD &= DS_ATA|DS_VV|DS_DPR|DS_MOL|DS_WRL; @@ -785,16 +551,13 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { if (GET_CY(uptr->DA) >= rp_drv_tab[dtype].cyl || GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) { - rp_attn[ctlr] &= ~(1<attn &= ~(1<CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; uptr->CMD &= ~DS_PIP; - df10->status &= ~BUSY; - if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) - df10_setirq(df10); break; } - uptr->CMD |= CR_GO; + uptr->CMD |= CS1_GO; CLR_BUF(uptr); uptr->DATAPTR = 0; break; @@ -802,14 +565,12 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { case FNC_DCLR: /* drive clear */ uptr->CMD |= DS_DRY; - uptr->CMD &= ~(DS_ATA|CR_GO); + uptr->CMD &= ~(DS_ATA|CS1_GO); uptr->DA &= 003400177777; uptr->CCYL &= 0177777; uptr->ERR2 = 0; uptr->ERR3 = 0; - rp_attn[ctlr] &= ~(1<status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) - df10_setirq(df10); + rhc->attn &= ~(1<flags & UNIT_ATT) != 0) uptr->CMD |= DS_VV; uptr->CMD |= DS_DRY; - if ((df10->status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) - df10_setirq(df10); break; default: uptr->CMD |= DS_DRY|DS_ERR|DS_ATA; uptr->CMD |= (ER1_ILF << 16); - rp_attn[ctlr] |= (1<status & IADR_ATTN) != 0 && rp_attn[ctlr] != 0) - df10_setirq(df10); + rhc->attn |= (1<CMD & CR_GO) + if (uptr->CMD & CS1_GO) sim_activate(uptr, 1000); - clr_interrupt(df10->devnum); - if ((df10->status & (IADR_ATTN|BUSY)) == IADR_ATTN && rp_attn[ctlr] != 0) - df10_setirq(df10); - sim_debug(DEBUG_DETAIL, dptr, "RP%o AStatus=%06o\n", unit, uptr->CMD); + sim_debug(DEBUG_DETAIL, dptr, "%s%o AStatus=%06o\n", dptr->name, unit, uptr->CMD); return; case 001: /* status */ break; @@ -855,14 +609,11 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { case 004: /* atten summary */ for (i = 0; i < 8; i++) { if (data & (1<units[i]; + u->CMD &= ~DS_ATA; + rhc->attn &= ~(1<devnum); break; case 005: /* sector/track */ uptr->DA &= 0177777; @@ -898,15 +649,14 @@ rp_write(int ctlr, int unit, int reg, uint32 data) { break; default: uptr->CMD |= (ER1_ILR<<16)|DS_ERR; - rp_rae[ctlr] &= ~(1<rae |= 1 << unit; } } uint32 -rp_read(int ctlr, int unit, int reg) { - DEVICE *dptr = rp_devs[ctlr]; +rp_read(DEVICE *dptr, struct rh_if *rhc, int reg) { + int unit = rhc->drive; UNIT *uptr = &dptr->units[unit]; - struct df10 *df10; uint32 temp = 0; int i; @@ -915,11 +665,10 @@ rp_read(int ctlr, int unit, int reg) { } switch(reg) { case 000: /* control */ - df10 = &rp_df10[ctlr]; temp = uptr->CMD & 076; if (uptr->flags & UNIT_ATT) temp |= CS1_DVA; - if (df10->status & BUSY || uptr->CMD & CR_GO) + if (uptr->CMD & CS1_GO) temp |= CS1_GO; break; case 001: /* status */ @@ -932,7 +681,8 @@ rp_read(int ctlr, int unit, int reg) { break; case 004: /* atten summary */ for (i = 0; i < 8; i++) { - if (rp_unit[(ctlr * 8) + i].CMD & DS_ATA) { + UNIT *u = &dptr->units[i]; + if (u->CMD & DS_ATA) { temp |= 1 << i; } } @@ -953,7 +703,8 @@ rp_read(int ctlr, int unit, int reg) { temp = uptr->CCYL & 0177777; break; case 010: /* serial no */ - temp = (020 * ctlr) + (unit + 1); + i = GET_CNTRL_RH(uptr->flags); + temp = (020 * i) + (unit + 1); break; case 014: /* error register 2 */ temp = uptr->ERR2; @@ -967,7 +718,7 @@ rp_read(int ctlr, int unit, int reg) { break; default: uptr->CMD |= (ER1_ILR<<16); - rp_rae[ctlr] &= ~(1<rae |= 1 << unit; } return temp; } @@ -975,31 +726,29 @@ rp_read(int ctlr, int unit, int reg) { t_stat rp_svc (UNIT *uptr) { - int dtype = GET_DTYPE(uptr->flags); - int ctlr = GET_CNTRL(uptr->flags); - int unit; - DEVICE *dptr; - struct df10 *df; - int cyl = GET_CY(uptr->DA); - int diff, da; - t_stat r; + int dtype = GET_DTYPE(uptr->flags); + int ctlr = GET_CNTRL_RH(uptr->flags); + int cyl = GET_CY(uptr->DA); + int unit; + DEVICE *dptr; + struct rh_if *rhc; + int diff, da; + t_stat r; - /* Find dptr, and df10 */ dptr = rp_devs[ctlr]; + rhc = &rp_rh[ctlr]; unit = uptr - dptr->units; - df = &rp_df10[ctlr]; if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */ uptr->CMD |= (ER1_UNS << 16) | DS_ATA|DS_ERR; /* set drive error */ if (GET_FNC(uptr->CMD) >= FNC_XFER) { /* xfr? set done */ - df->status &= ~BUSY; - df10_setirq(df); + rh_setirq(rhc); } return (SCPE_OK); } /* Check if seeking */ if (uptr->CMD & DS_PIP) { - sim_debug(DEBUG_DETAIL, dptr, "RP%o seek %d %d\n", unit, cyl, uptr->CCYL); + sim_debug(DEBUG_DETAIL, dptr, "%s%o seek %d %d\n", dptr->name, unit, cyl, uptr->CCYL); if (cyl >= rp_drv_tab[dtype].cyl) { uptr->CMD &= ~DS_PIP; uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; @@ -1054,31 +803,27 @@ t_stat rp_svc (UNIT *uptr) if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) uptr->CMD |= (ER1_IAE << 16)|DS_ERR; - rp_attn[ctlr] |= 1<CMD |= DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - if ((df->status & (IADR_ATTN|BUSY)) == IADR_ATTN) - df10_setirq(df); - sim_debug(DEBUG_DETAIL, dptr, "RP%o seekdone %d %o\n", unit, cyl, uptr->CMD); + uptr->CMD &= ~CS1_GO; + rh_setattn(rhc, unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o seekdone %d %o\n", dptr->name, unit, cyl, uptr->CMD); break; case FNC_SEARCH: /* search */ if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) uptr->CMD |= (ER1_IAE << 16)|DS_ERR; - rp_attn[ctlr] |= 1<CMD |= DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - if ((df->status & (IADR_ATTN|BUSY)) == IADR_ATTN) - df10_setirq(df); - sim_debug(DEBUG_DETAIL, dptr, "RP%o searchdone %d %o\n", unit, cyl, uptr->CMD); + uptr->CMD &= ~CS1_GO; + rh_setattn(rhc, unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o searchdone %d %o\n", dptr->name, unit, cyl, uptr->CMD); break; case FNC_READ: /* read */ case FNC_READH: /* read w/ headers */ case FNC_WCHK: /* write check */ if (uptr->CMD & DS_ERR) { - sim_debug(DEBUG_DETAIL, dptr, "RP%o read error\n", unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read error\n", dptr->name, unit); goto rd_end; } @@ -1088,12 +833,12 @@ t_stat rp_svc (UNIT *uptr) if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) { uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); - sim_debug(DEBUG_DETAIL, dptr, "RP%o readx done\n", unit); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); + sim_debug(DEBUG_DETAIL, dptr, "%s%o readx done\n", dptr->name, unit); return SCPE_OK; } - sim_debug(DEBUG_DETAIL, dptr, "RP%o read (%d,%d,%d)\n", unit, cyl, + sim_debug(DEBUG_DETAIL, dptr, "%s%o read (%d,%d,%d)\n", dptr->name, unit, cyl, GET_SF(uptr->DA), GET_SC(uptr->DA)); da = GET_DA(uptr->DA, dtype) * RP_NUMWD; (void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); @@ -1105,24 +850,24 @@ t_stat rp_svc (UNIT *uptr) uptr->DATAPTR = 0; /* On read headers, transfer 2 words to start */ if (GET_FNC(uptr->CMD) == FNC_READH) { - df->buf = (((uint64)cyl) << 18) | + rhc->buf = (((uint64)cyl) << 18) | ((uint64)((GET_SF(uptr->DA) << 8) | GET_SF(uptr->DA))); - sim_debug(DEBUG_DATA, dptr, "RP%o read word h1 %012llo %09o %06o\n", - unit, df->buf, df->cda, df->wcr); - if (df10_write(df) == 0) + sim_debug(DEBUG_DATA, dptr, "%s%o read word h1 %012llo %09o %06o\n", + dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr); + if (rh_write(rhc) == 0) goto rd_end; - df->buf = ((uint64)((020 * ctlr) + (unit + 1)) << 18) | (uint64)(unit); - sim_debug(DEBUG_DATA, dptr, "RP%o read word h2 %012llo %09o %06o\n", - unit, df->buf, df->cda, df->wcr); - if (df10_write(df) == 0) + rhc->buf = ((uint64)((020 * ctlr) + (unit + 1)) << 18) | (uint64)(unit); + sim_debug(DEBUG_DATA, dptr, "%s%o read word h2 %012llo %09o %06o\n", + dptr->name, unit, rhc->buf, rhc->cda, rhc->wcr); + if (rh_write(rhc) == 0) goto rd_end; } } - df->buf = rp_buf[ctlr][uptr->DATAPTR++]; - sim_debug(DEBUG_DATA, dptr, "RP%o read word %d %012llo %09o %06o\n", - unit, uptr->DATAPTR, df->buf, df->cda, df->wcr); - if (df10_write(df)) { + rhc->buf = rp_buf[ctlr][uptr->DATAPTR++]; + sim_debug(DEBUG_DATA, dptr, "%s%o read word %d %012llo %09o %06o\n", + dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr); + if (rh_write(rhc)) { if (uptr->DATAPTR == RP_NUMWD) { /* Increment to next sector. Set Last Sector */ uptr->DATAPTR = 0; @@ -1137,14 +882,16 @@ t_stat rp_svc (UNIT *uptr) uptr->CMD |= DS_PIP; } } + if (rh_blkend(rhc)) + goto rd_end; } - sim_activate(uptr, 50); + sim_activate(uptr, 10); } else { rd_end: - sim_debug(DEBUG_DETAIL, dptr, "RP%o read done\n", unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read done\n", dptr->name, unit); uptr->CMD |= DS_DRY; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -1152,7 +899,7 @@ rd_end: case FNC_WRITE: /* write */ case FNC_WRITEH: /* write w/ headers */ if (uptr->CMD & DS_ERR) { - sim_debug(DEBUG_DETAIL, dptr, "RP%o read error\n", unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read error\n", dptr->name, unit); goto wr_end; } @@ -1160,34 +907,34 @@ rd_end: if (GET_SC(uptr->DA) >= rp_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rp_drv_tab[dtype].surf) { uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); - sim_debug(DEBUG_DETAIL, dptr, "RP%o writex done\n", unit); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); + sim_debug(DEBUG_DETAIL, dptr, "%s%o writex done\n", dptr->name, unit); return SCPE_OK; } /* On Write headers, transfer 2 words to start */ if (GET_FNC(uptr->CMD) == FNC_WRITEH) { - if (df10_read(df) == 0) + if (rh_read(rhc) == 0) goto wr_end; - sim_debug(DEBUG_DATA, dptr, "RP%o write word h1 %012llo %06o\n", - unit, df->buf, df->wcr); - if (df10_read(df) == 0) + sim_debug(DEBUG_DATA, dptr, "%s%o write word h1 %012llo %06o\n", + dptr->name, unit, rhc->buf, rhc->wcr); + if (rh_read(rhc) == 0) goto wr_end; - sim_debug(DEBUG_DATA, dptr, "RP%o write word h2 %012llo %06o\n", - unit, df->buf, df->wcr); + sim_debug(DEBUG_DATA, dptr, "%s%o write word h2 %012llo %06o\n", + dptr->name, unit, rhc->buf, rhc->wcr); } uptr->DATAPTR = 0; uptr->hwmark = 0; } - r = df10_read(df); - sim_debug(DEBUG_DATA, dptr, "RP%o write word %d %012llo %06o\n", - unit, uptr->DATAPTR, df->buf, df->wcr); - rp_buf[ctlr][uptr->DATAPTR++] = df->buf; + r = rh_read(rhc); + sim_debug(DEBUG_DATA, dptr, "%s%o write word %d %012llo %06o\n", + dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->wcr); + rp_buf[ctlr][uptr->DATAPTR++] = rhc->buf; if (r == 0 || uptr->DATAPTR == RP_NUMWD) { while (uptr->DATAPTR < RP_NUMWD) rp_buf[ctlr][uptr->DATAPTR++] = 0; - sim_debug(DEBUG_DETAIL, dptr, "RP%o write (%d,%d,%d)\n", unit, cyl, - GET_SF(uptr->DA), GET_SC(uptr->DA)); + sim_debug(DEBUG_DETAIL, dptr, "%s%o write (%d,%d,%d)\n", dptr->name, + unit, cyl, GET_SF(uptr->DA), GET_SC(uptr->DA)); da = GET_DA(uptr->DA, dtype) * RP_NUMWD; (void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); (void)sim_fwrite (&rp_buf[ctlr][0], sizeof(uint64), RP_NUMWD, @@ -1205,16 +952,18 @@ rd_end: uptr->CMD |= DS_PIP; } } + if (rh_blkend(rhc)) + goto wr_end; } } if (r) { - sim_activate(uptr, 50); + sim_activate(uptr, 10); } else { wr_end: sim_debug(DEBUG_DETAIL, dptr, "RP%o write done\n", unit); uptr->CMD |= DS_DRY; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -1242,12 +991,10 @@ rp_reset(DEVICE * rptr) { int ctlr; for (ctlr = 0; ctlr < NUM_DEVS_RP; ctlr++) { - rp_df10[ctlr].devnum = rp_dib[ctlr].dev_num; - rp_df10[ctlr].nxmerr = 19; - rp_df10[ctlr].ccw_comp = 14; - rp_df10[ctlr].status = 0; - rp_attn[ctlr] = 0; - rp_rae[ctlr] = 0; + rp_rh[ctlr].devnum = rp_dib[ctlr].dev_num; + rp_rh[ctlr].status = 0; + rp_rh[ctlr].attn = 0; + rp_rh[ctlr].rae = 0; } return SCPE_OK; } @@ -1257,14 +1004,16 @@ t_stat rp_boot(int32 unit_num, DEVICE * rptr) { UNIT *uptr = &rptr->units[unit_num]; - int ctlr = GET_CNTRL(uptr->flags); + int ctlr = GET_CNTRL_RH(uptr->flags); DEVICE *dptr; - struct df10 *df; + struct rh_if *rhc; uint32 addr; uint32 ptr = 0; uint64 word; int wc; + rhc = &rp_rh[ctlr]; + dptr = rp_devs[ctlr]; #if KL int sect; /* KL does not support readin, so fake it by reading in sectors 4 to 7 */ @@ -1280,11 +1029,8 @@ rp_boot(int32 unit_num, DEVICE * rptr) } PC = (MEMSIZE - 512) & RMASK; #else - df = &rp_df10[ctlr]; - dptr = rp_devs[ctlr]; (void)sim_fseek(uptr->fileref, 0, SEEK_SET); (void)sim_fread (&rp_buf[0][0], sizeof(uint64), RP_NUMWD, uptr->fileref); - uptr->CMD |= DS_VV; addr = rp_buf[0][ptr] & RMASK; wc = (rp_buf[0][ptr++] >> 18) & RMASK; while (wc != 0) { @@ -1299,12 +1045,12 @@ rp_boot(int32 unit_num, DEVICE * rptr) addr = rp_buf[0][ptr] & RMASK; wc = (rp_buf[0][ptr++] >> 18) & RMASK; word = rp_buf[0][ptr++]; - - rp_reg[ctlr] = 040; - rp_drive[ctlr] = uptr - dptr->units; - df->status |= CCW_COMP_1|PI_ENABLE; PC = word & RMASK; #endif + uptr->CMD |= DS_VV; + rhc->reg = 040; + rhc->drive = uptr - dptr->units; + rhc->status |= CCW_COMP_1|PI_ENABLE; return SCPE_OK; } @@ -1325,14 +1071,18 @@ t_stat rp_attach (UNIT *uptr, CONST char *cptr) if (rptr == 0) return SCPE_OK; dib = (DIB *) rptr->ctxt; + for (ctlr = 0; rh[ctlr].dev_num != 0; ctlr++) { + if (rh[ctlr].dev == rptr) + break; + } ctlr = dib->dev_num & 014; uptr->DA = 0; uptr->CMD &= ~DS_VV; uptr->CMD |= DS_DPR|DS_MOL|DS_DRY; if (uptr->flags & UNIT_WLK) uptr->CMD |= DS_WRL; - rp_df10[ctlr].status |= PI_ENABLE; - set_interrupt(dib->dev_num, rp_df10[ctlr].status); + rp_rh[ctlr].status |= PI_ENABLE; + set_interrupt(dib->dev_num, rp_rh[ctlr].status); return SCPE_OK; } diff --git a/PDP10/kx10_rs.c b/PDP10/kx10_rs.c index 81fae05..cb7ab6d 100644 --- a/PDP10/kx10_rs.c +++ b/PDP10/kx10_rs.c @@ -42,72 +42,14 @@ #define DTYPE(x) (((x) & UNIT_M_DTYPE) << UNIT_V_DTYPE) #define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE) #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */ -#define CNTRL_V_CTYPE (UNIT_V_UF + 4) -#define CNTRL_M_CTYPE 7 -#define GET_CNTRL(x) (((x) >> CNTRL_V_CTYPE) & CNTRL_M_CTYPE) -#define CNTRL(x) (((x) & CNTRL_M_CTYPE) << CNTRL_V_CTYPE) /* Parameters in the unit descriptor */ - -/* CONI Flags */ -#define IADR_ATTN 0000000000040LL /* Interrupt on attention */ -#define IARD_RAE 0000000000100LL /* Interrupt on register access error */ -#define DIB_CBOV 0000000000200LL /* Control bus overrun */ -#define CXR_PS_FAIL 0000000002000LL /* Power supply fail (not implemented) */ -#define CXR_ILC 0000000004000LL /* Illegal function code */ -#define CR_DRE 0000000010000LL /* Or Data and Control Timeout */ -#define DTC_OVER 0000000020000LL /* DF10 did not supply word on time (not implemented) */ -#define CCW_COMP_1 0000000040000LL /* Control word written. */ -#define CXR_CHAN_ER 0000000100000LL /* Channel Error */ -#define CXR_EXC 0000000200000LL /* Error in drive transfer */ -#define CXR_DBPE 0000000400000LL /* Device Parity error (not implemented) */ -#define CXR_NXM 0000001000000LL /* Channel non-existent memory (not implemented) */ -#define CXR_CWPE 0000002000000LL /* Channel Control word parity error (not implemented) */ -#define CXR_CDPE 0000004000000LL /* Channel Data Parity Error (not implemented) */ -#define CXR_SD_RAE 0000200000000LL /* Register access error */ -#define CXR_ILFC 0000400000000LL /* Illegal CXR function code */ -#define B22_FLAG 0004000000000LL /* 22 bit channel */ -#define CC_CHAN_PLS 0010000000000LL /* Channel transfer pulse (not implemented) */ -#define CC_CHAN_ACT 0020000000000LL /* Channel in use */ -#define CC_INH 0040000000000LL /* Disconnect channel */ -#define CB_FULL 0200000000000LL /* Set when channel buffer is full (not implemented) */ -#define AR_FULL 0400000000000LL /* Set when AR is full (not implemented) */ - -/* CONO Flags */ -#define ATTN_EN 0000000000040LL /* enable attention interrupt. */ -#define REA_EN 0000000000100LL /* enable register error interrupt */ -#define CBOV_CLR 0000000000200LL /* Clear CBOV */ -#define CONT_RESET 0000000002000LL /* Clear All error bits */ -#define ILC_CLR 0000000004000LL /* Clear ILC and SD RAE */ -#define DRE_CLR 0000000010000LL /* Clear CR_CBTO and CR_DBTO */ -#define OVER_CLR 0000000020000LL /* Clear DTC overrun */ -#define WRT_CW 0000000040000LL /* Write control word */ -#define CHN_CLR 0000000100000LL /* Clear Channel Error */ -#define DR_EXC_CLR 0000000200000LL /* Clear DR_EXC */ -#define DBPE_CLR 0000000400000LL /* Clear CXR_DBPE */ - -/* DATAO/DATAI */ -#define CR_REG 0770000000000LL /* Register number */ -#define LOAD_REG 0004000000000LL /* Load register */ -#define CR_MAINT_MODE 0000100000000LL /* Maint mode... not implemented */ -#define CR_DRIVE 0000007000000LL -#define CR_GEN_EVD 0000000400000LL /* Enable Parity */ -#define CR_DXES 0000000200000LL /* Disable DXES errors */ -#define CR_INAD 0000000077600LL -#define CR_WTEVM 0000000000100LL /* Verify Parity */ -#define CR_FUNC 0000000000076LL -#define CR_GO 0000000000001LL - -#define IRQ_VECT 0000000000177LL /* Interupt vector */ -#define IRQ_KI10 0000002000000LL -#define IRQ_KA10 0000001000000LL - #define CMD u3 /* u3 low */ /* RSC - 00 - control */ -#define CS1_GO CR_GO /* go */ +#define CS1_GO 1 /* go */ #define CS1_V_FNC 1 /* function pos */ #define CS1_M_FNC 037 /* function mask */ #define CS1_FNC (CS1_M_FNC << CS1_V_FNC) @@ -228,20 +170,21 @@ struct drvtyp rs_drv_tab[] = { }; -struct df10 rs_df10[NUM_DEVS_RS]; -uint32 rs_xfer_drive[NUM_DEVS_RS]; +//struct df10 rs_df10[NUM_DEVS_RS]; +//uint32 rs_xfer_drive[NUM_DEVS_RS]; uint64 rs_buf[NUM_DEVS_RS][RS_NUMWD]; -int rs_reg[NUM_DEVS_RS]; -int rs_ivect[NUM_DEVS_RS]; -int rs_imode[NUM_DEVS_RS]; -int rs_drive[NUM_DEVS_RS]; -int rs_rae[NUM_DEVS_RS]; -int rs_attn[NUM_DEVS_RS]; +//int rs_reg[NUM_DEVS_RS]; +//int rs_ivect[NUM_DEVS_RS]; +//int rs_imode[NUM_DEVS_RS]; +//int rs_drive[NUM_DEVS_RS]; +//int rs_rae[NUM_DEVS_RS]; +//int rs_attn[NUM_DEVS_RS]; -t_stat rs_devio(uint32 dev, uint64 *data); -int rs_devirq(uint32 dev, int addr); -void rs_write(int ctlr, int unit, int reg, uint32 data); -uint32 rs_read(int ctlr, int unit, int reg); +//t_stat rs_devio(uint32 dev, uint64 *data); +//int rs_devirq(uint32 dev, int addr); +void rs_write(DEVICE *dptr, struct rh_if *rhc, int reg, uint32 data); +uint32 rs_read(DEVICE *dptr, struct rh_if *rhc, int reg); +void rs_rst(DEVICE *dptr); t_stat rs_svc(UNIT *); t_stat rs_boot(int32, DEVICE *); void rs_ini(UNIT *, t_bool); @@ -257,28 +200,38 @@ const char *rs_description (DEVICE *dptr); UNIT rs_unit[] = { /* Controller 1 */ { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, { UDATA (&rs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+ - UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL(0), RS04_SIZE) }, + UNIT_ROABLE+DTYPE(RS04_DTYPE)+CNTRL_RH(0), RS04_SIZE) }, +}; + +struct rh_if rs_rh[] = { + { &rs_write, &rs_read, &rs_rst}, }; DIB rs_dib[] = { - {RH10_DEV, 1, &rs_devio, &rs_devirq} + {RH10_DEV, 1, &rh_devio, &rh_devirq, &rs_rh[0]} }; MTAB rs_mod[] = { +#if KL + {MTAB_XTD|MTAB_VDV, TYPE_RH10, NULL, "RH10", &rh_set_type, NULL, + NULL, "Sets controller to RH10" }, + {MTAB_XTD|MTAB_VDV, TYPE_RH20, "RH20", "RH20", &rh_set_type, &rh_show_type, + NULL, "Sets controller to RH20"}, +#endif {UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL}, {UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL}, {UNIT_DTYPE, (RS03_DTYPE << UNIT_V_DTYPE), "RS03", "RS03", &rs_set_type }, @@ -287,22 +240,20 @@ MTAB rs_mod[] = { }; REG rsa_reg[] = { - {ORDATA(IVECT, rs_ivect[0], 18)}, - {FLDATA(IMODE, rs_imode[0], 0)}, - {ORDATA(XFER, rs_xfer_drive[0], 3), REG_HRO}, - {ORDATA(DRIVE, rs_drive[0], 3), REG_HRO}, - {ORDATA(REG, rs_reg[0], 6), REG_RO}, - {ORDATA(RAE, rs_rae[0], 8), REG_RO}, - {ORDATA(ATTN, rs_attn[0], 8), REG_RO}, - {ORDATA(STATUS, rs_df10[0].status, 18), REG_RO}, - {ORDATA(CIA, rs_df10[0].cia, 18)}, - {ORDATA(CCW, rs_df10[0].ccw, 18)}, - {ORDATA(WCR, rs_df10[0].wcr, 18)}, - {ORDATA(CDA, rs_df10[0].cda, 18)}, - {ORDATA(DEVNUM, rs_df10[0].devnum, 9), REG_HRO}, - {ORDATA(BUF, rs_df10[0].buf, 36), REG_HRO}, - {ORDATA(NXM, rs_df10[0].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, rs_df10[0].ccw_comp, 8), REG_HRO}, + {ORDATA(IVECT, rs_rh[0].ivect, 18)}, + {FLDATA(IMODE, rs_rh[0].imode, 0)}, + {ORDATA(XFER, rs_rh[0].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, rs_rh[0].drive, 3), REG_HRO}, + {ORDATA(REG, rs_rh[0].reg, 6), REG_RO}, + {ORDATA(RAE, rs_rh[0].rae, 8), REG_RO}, + {ORDATA(ATTN, rs_rh[0].attn, 8), REG_RO}, + {ORDATA(STATUS, rs_rh[0].status, 18), REG_RO}, + {ORDATA(CIA, rs_rh[0].cia, 18)}, + {ORDATA(CCW, rs_rh[0].ccw, 18)}, + {ORDATA(WCR, rs_rh[0].wcr, 18)}, + {ORDATA(CDA, rs_rh[0].cda, 18)}, + {ORDATA(DEVNUM, rs_rh[0].devnum, 9), REG_HRO}, + {ORDATA(BUF, rs_rh[0].buf, 36), REG_HRO}, {BRDATA(BUFF, &rs_buf[0][0], 16, 64, RS_NUMWD), REG_HRO}, {0} }; @@ -320,213 +271,44 @@ DEVICE *rs_devs[] = { }; -t_stat rs_devio(uint32 dev, uint64 *data) { - int ctlr = -1; - DEVICE *dptr = NULL; - struct df10 *df10; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - if (dptr == NULL) - return SCPE_OK; - ctlr = GET_CNTRL(dptr->units[0].flags); - df10 = &rs_df10[ctlr]; - df10->devnum = dev; - switch(dev & 3) { - case CONI: - *data = df10->status & ~(IADR_ATTN|IARD_RAE); - if (rs_attn[ctlr] != 0 && (df10->status & IADR_ATTN)) - *data |= IADR_ATTN; - if (rs_rae[ctlr] != 0 && (df10->status & IARD_RAE)) - *data |= IARD_RAE; -#if KI_22BIT - *data |= B22_FLAG; -#endif - sim_debug(DEBUG_CONI, dptr, "RS %03o CONI %06o PC=%o %o\n", - dev, (uint32)*data, PC, rs_attn[ctlr]); - return SCPE_OK; - - case CONO: - clr_interrupt(dev); - df10->status &= ~(07LL|IADR_ATTN|IARD_RAE); - df10->status |= *data & (07LL|IADR_ATTN|IARD_RAE); - /* Clear flags */ - if (*data & CONT_RESET) { - UNIT *uptr=dptr->units; - for(drive = 0; drive < NUM_UNITS_RS; drive++, uptr++) { - uptr->CMD &= DS_MOL|DS_WRL|DS_DPR|DS_DRY|DS_VV|076; - uptr->DA &= 003400177777; - } - } - if (*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)) - df10->status &= ~(*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)); - if (*data & OVER_CLR) - df10->status &= ~(DTC_OVER); - if (*data & CBOV_CLR) - df10->status &= ~(DIB_CBOV); - if (*data & CXR_ILC) - df10->status &= ~(CXR_ILFC|CXR_SD_RAE); - if (*data & WRT_CW) - df10_writecw(df10); - if (*data & PI_ENABLE) - df10->status &= ~PI_ENABLE; - if (df10->status & PI_ENABLE) - set_interrupt(dev, df10->status); - if ((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) - set_interrupt(dev, df10->status); - sim_debug(DEBUG_CONO, dptr, "RS %03o CONO %06o %d PC=%06o %06o\n", - dev, (uint32)*data, ctlr, PC, df10->status); - return SCPE_OK; - - case DATAI: - *data = 0; - if (df10->status & BUSY && rs_reg[ctlr] != 04) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } - if (rs_reg[ctlr] == 040) { - *data = (uint64)(rs_read(ctlr, rs_drive[ctlr], 0) & 077); - *data |= ((uint64)(df10->cia)) << 6; - *data |= ((uint64)(rs_xfer_drive[ctlr])) << 18; - } else if (rs_reg[ctlr] == 044) { - *data = (uint64)rs_ivect[ctlr]; - if (rs_imode[ctlr]) - *data |= IRQ_KI10; - else - *data |= IRQ_KA10; - } else if (rs_reg[ctlr] == 054) { - *data = (uint64)(rs_rae[ctlr]); - } else if ((rs_reg[ctlr] & 040) == 0) { - int parity; - - *data = (uint64)(rs_read(ctlr, rs_drive[ctlr], rs_reg[ctlr]) & 0177777); - parity = (int)((*data >> 8) ^ *data); - parity = (parity >> 4) ^ parity; - parity = (parity >> 2) ^ parity; - parity = ((parity >> 1) ^ parity) & 1; - *data |= ((uint64)(parity ^ 1)) << 17; - *data |= ((uint64)(rs_drive[ctlr])) << 18; - } - *data |= ((uint64)(rs_reg[ctlr])) << 30; - sim_debug(DEBUG_DATAIO, dptr, "RS %03o DATI %012llo, %d %d PC=%06o\n", - dev, *data, ctlr, rs_drive[ctlr], PC); - return SCPE_OK; - - case DATAO: - sim_debug(DEBUG_DATAIO, dptr, "RS %03o DATO %012llo, %d PC=%06o %06o\n", - dev, *data, ctlr, PC, df10->status); - rs_reg[ctlr] = ((int)(*data >> 30)) & 077; - if (rs_reg[ctlr] < 040 && rs_reg[ctlr] != 04) { - rs_drive[ctlr] = (int)(*data >> 18) & 07; - } - if (*data & LOAD_REG) { - if (rs_reg[ctlr] == 040) { - if ((*data & 1) == 0) { - return SCPE_OK; - } - - if (df10->status & BUSY) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } - - df10->status &= ~(1 << df10->ccw_comp); - df10->status &= ~PI_ENABLE; - if (((*data >> 1) & 077) < FNC_XFER) { - df10->status |= CXR_ILC; - df10_setirq(df10); - sim_debug(DEBUG_DATAIO, dptr, - "RS %03o command abort %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, rs_drive[ctlr], PC, df10->status); - return SCPE_OK; - } - - /* Start command */ - df10_setup(df10, (uint32)(*data >> 6)); - rs_xfer_drive[ctlr] = (int)(*data >> 18) & 07; - rs_write(ctlr, rs_drive[ctlr], 0, (uint32)(*data & 077)); - sim_debug(DEBUG_DATAIO, dptr, - "RS %03o command %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, rs_drive[ctlr], PC, df10->status); - } else if (rs_reg[ctlr] == 044) { - /* Set KI10 Irq vector */ - rs_ivect[ctlr] = (int)(*data & IRQ_VECT); - rs_imode[ctlr] = (*data & IRQ_KI10) != 0; - } else if (rs_reg[ctlr] == 050) { - ; /* Diagnostic access to mass bus. */ - } else if (rs_reg[ctlr] == 054) { - /* clear flags */ - rs_rae[ctlr] &= ~(*data & 0377); - if (rs_rae[ctlr] == 0) - clr_interrupt(dev); - } else if ((rs_reg[ctlr] & 040) == 0) { - rs_drive[ctlr] = (int)(*data >> 18) & 07; - /* Check if access error */ - if (rs_rae[ctlr] & (1 << rs_drive[ctlr])) { - return SCPE_OK; - } - rs_drive[ctlr] = (int)(*data >> 18) & 07; - rs_write(ctlr, rs_drive[ctlr], rs_reg[ctlr] & 037, - (int)(*data & 0777777)); - } - } - return SCPE_OK; - } - return SCPE_OK; /* Unreached */ -} - -/* Handle KI and KL style interrupt vectors */ -int -rs_devirq(uint32 dev, int addr) { - DEVICE *dptr = NULL; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - if (dptr != NULL) { - drive = GET_CNTRL(dptr->units[0].flags); - return (rs_imode[drive] ? rs_ivect[drive] : addr); - } - return addr; +void +rs_rst(DEVICE *dptr) +{ + UNIT *uptr=dptr->units; + int drive; + for(drive = 0; drive < NUM_UNITS_RS; drive++, uptr++) { + uptr->CMD &= DS_MOL|DS_WRL|DS_DPR|DS_DRY|DS_VV|076; + uptr->DA &= 003400177777; + } } void -rs_write(int ctlr, int unit, int reg, uint32 data) { +rs_write(DEVICE *dptr, struct rh_if *rhc, int reg, uint32 data) { int i; - DEVICE *dptr = rs_devs[ctlr]; - struct df10 *df10 = &rs_df10[ctlr]; + int unit = rhc->drive; UNIT *uptr = &dptr->units[unit]; - if ((uptr->CMD & CR_GO) && reg != 04) { + if ((uptr->CMD & CS1_GO) && reg != 04) { uptr->CMD |= (ER1_RMR << 16)|DS_ERR; return; } switch(reg) { case 000: /* control */ - sim_debug(DEBUG_DETAIL, dptr, "RSA%o %d Status=%06o\n", unit, ctlr, uptr->CMD); + sim_debug(DEBUG_DETAIL, dptr, "%s%o Status=%06o\n", dptr->name, unit, uptr->CMD); /* Set if drive not writable */ if (uptr->flags & UNIT_WLK) uptr->CMD |= DS_WRL; /* If drive not ready don't do anything */ if ((uptr->CMD & DS_DRY) == 0) { uptr->CMD |= (ER1_RMR << 16)|DS_ERR; - sim_debug(DEBUG_DETAIL, dptr, "RSA%o %d busy\n", unit, ctlr); + sim_debug(DEBUG_DETAIL, dptr, "%s%o busy\n", dptr->name, unit); return; } /* Check if GO bit set */ if ((data & 1) == 0) { uptr->CMD &= ~076; uptr->CMD |= data & 076; - sim_debug(DEBUG_DETAIL, dptr, "RSA%o %d no go\n", unit, ctlr); + sim_debug(DEBUG_DETAIL, dptr, "%s%o no go\n", dptr->name, unit); return; /* No, nop */ } uptr->CMD &= DS_ATA|DS_VV|DS_DPR|DS_MOL|DS_WRL; @@ -540,7 +322,7 @@ rs_write(int ctlr, int unit, int reg, uint32 data) { case FNC_WCHK: /* write check */ case FNC_WRITE: /* write */ case FNC_READ: /* read */ - uptr->CMD |= DS_PIP|CR_GO; + uptr->CMD |= DS_PIP|CS1_GO; uptr->DATAPTR = 0; break; @@ -549,30 +331,26 @@ rs_write(int ctlr, int unit, int reg, uint32 data) { if ((uptr->flags & UNIT_ATT) != 0) uptr->CMD |= DS_VV; uptr->CMD |= DS_DRY; - df10_setirq(df10); + rh_setirq(rhc); break; case FNC_DCLR: /* drive clear */ uptr->CMD |= DS_DRY; - uptr->CMD &= ~(DS_ATA|CR_GO); - rs_attn[ctlr] = 0; - clr_interrupt(df10->devnum); + uptr->CMD &= ~(DS_ATA|CS1_GO); + rhc->attn = 0; + clr_interrupt(rhc->devnum); for (i = 0; i < 8; i++) { - if (rs_unit[(ctlr * 8) + i].CMD & DS_ATA) - rs_attn[ctlr] = 1; + if (dptr->units[i].CMD & DS_ATA) + rhc->attn |= 1 << i; } - if ((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) - df10_setirq(df10); break; default: uptr->CMD |= DS_DRY|DS_ERR|DS_ATA; uptr->CMD |= (ER1_ILF << 16); - if ((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) - df10_setirq(df10); } - if (uptr->CMD & CR_GO) + if (uptr->CMD & CS1_GO) sim_activate(uptr, 100); - sim_debug(DEBUG_DETAIL, dptr, "RSA%o AStatus=%06o\n", unit, uptr->CMD); + sim_debug(DEBUG_DETAIL, dptr, "%s%o AStatus=%06o\n", dptr->name, unit, uptr->CMD); return; case 001: /* status */ break; @@ -585,17 +363,13 @@ rs_write(int ctlr, int unit, int reg, uint32 data) { case 003: /* maintenance */ break; case 004: /* atten summary */ - rs_attn[ctlr] = 0; + rhc->attn = 0; for (i = 0; i < 8; i++) { if (data & (1<units[i].CMD &= ~DS_ATA; + if (dptr->units[i].CMD & DS_ATA) + rhc->attn |= 1 << i; } - clr_interrupt(df10->devnum); - if (((df10->status & IADR_ATTN) != 0 && rs_attn[ctlr] != 0) || - (df10->status & PI_ENABLE)) - df10_setirq(df10); break; case 005: /* sector/track */ uptr->DA = data & 0177777; @@ -605,14 +379,13 @@ rs_write(int ctlr, int unit, int reg, uint32 data) { break; default: uptr->CMD |= (ER1_ILR<<16)|DS_ERR; - rs_rae[ctlr] &= ~(1<rae |= 1 << unit; } } uint32 -rs_read(int ctlr, int unit, int reg) { - DEVICE *dptr = rs_devs[ctlr]; - struct df10 *df10 = &rs_df10[ctlr]; +rs_read(DEVICE *dptr, struct rh_if *rhc, int reg) { + int unit = rhc->drive; UNIT *uptr = &dptr->units[unit]; uint32 temp = 0; int i; @@ -626,7 +399,7 @@ rs_read(int ctlr, int unit, int reg) { temp = uptr->CMD & 077; if (uptr->flags & UNIT_ATT) temp |= CS1_DVA; - if ((df10->status & BUSY) == 0 && (uptr->CMD & CR_GO) == 0) + if ((uptr->CMD & CS1_GO) == 0) temp |= CS1_GO; break; case 001: /* status */ @@ -637,7 +410,7 @@ rs_read(int ctlr, int unit, int reg) { break; case 004: /* atten summary */ for (i = 0; i < 8; i++) { - if (rs_unit[(ctlr * 8) + i].CMD & DS_ATA) { + if (dptr->units[i].CMD & DS_ATA) { temp |= 1 << i; } } @@ -653,7 +426,7 @@ rs_read(int ctlr, int unit, int reg) { break; default: uptr->CMD |= (ER1_ILR<<16); - rs_rae[ctlr] &= ~(1<rae |= 1 << unit; } return temp; } @@ -661,22 +434,21 @@ rs_read(int ctlr, int unit, int reg) { t_stat rs_svc (UNIT *uptr) { - int dtype = GET_DTYPE(uptr->flags); - int ctlr = GET_CNTRL(uptr->flags); - int unit; - DEVICE *dptr; - struct df10 *df; - int da; - t_stat r; + int dtype = GET_DTYPE(uptr->flags); + int ctlr = GET_CNTRL_RH(uptr->flags); + int unit; + DEVICE *dptr; + struct rh_if *rhc; + int da; + t_stat r; /* Find dptr, and df10 */ dptr = rs_devs[ctlr]; + rhc = &rs_rh[ctlr]; unit = uptr - dptr->units; - df = &rs_df10[ctlr]; if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */ uptr->CMD |= (ER1_UNS << 16) | DS_ATA|DS_ERR; /* set drive error */ - df->status &= ~BUSY; - df10_setirq(df); + rh_setirq(rhc); return (SCPE_OK); } @@ -691,26 +463,20 @@ t_stat rs_svc (UNIT *uptr) case FNC_DCLR: /* drive clear */ break; case FNC_PRESET: /* read-in preset */ - rs_attn[ctlr] = 1; uptr->CMD |= DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - df->status &= ~BUSY; - if (df->status & IADR_ATTN) - df10_setirq(df); - sim_debug(DEBUG_DETAIL, dptr, "RSA%o seekdone\n", unit); + uptr->CMD &= ~CS1_GO; + rh_setattn(rhc, unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o seekdone\n", dptr->name, unit); break; case FNC_SEARCH: /* search */ if (GET_SC(uptr->DA) >= rs_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rs_drv_tab[dtype].surf) uptr->CMD |= (ER1_IAE << 16)|DS_ERR; - rs_attn[ctlr] = 1; uptr->CMD |= DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - df->status &= ~BUSY; - if ((df->status & (IADR_ATTN|BUSY)) == IADR_ATTN) - df10_setirq(df); - sim_debug(DEBUG_DETAIL, dptr, "RSA%o searchdone\n", unit); + uptr->CMD &= ~CS1_GO; + rh_setattn(rhc, unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o searchdone\n", dptr->name, unit); break; case FNC_READ: /* read */ @@ -720,13 +486,12 @@ t_stat rs_svc (UNIT *uptr) if (GET_SC(uptr->DA) >= rs_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rs_drv_tab[dtype].surf) { uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; - df->status &= ~BUSY; - uptr->CMD &= ~CR_GO; - sim_debug(DEBUG_DETAIL, dptr, "RSA%o readx done\n", unit); - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + sim_debug(DEBUG_DETAIL, dptr, "%s%o readx done\n", dptr->name, unit); + rh_finish_op(rhc, 0); return SCPE_OK; } - sim_debug(DEBUG_DETAIL, dptr, "RSA%o read (%d,%d)\n", unit, + sim_debug(DEBUG_DETAIL, dptr, "%s%o read (%d,%d)\n", dptr->name, unit, GET_SC(uptr->DA), GET_SF(uptr->DA)); da = GET_DA(uptr->DA, dtype) * RS_NUMWD; (void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); @@ -737,10 +502,10 @@ t_stat rs_svc (UNIT *uptr) uptr->hwmark = RS_NUMWD; } - df->buf = rs_buf[ctlr][uptr->DATAPTR++]; - sim_debug(DEBUG_DATA, dptr, "RSA%o read word %d %012llo %09o %06o\n", - unit, uptr->DATAPTR, df->buf, df->cda, df->wcr); - if (df10_write(df)) { + rhc->buf = rs_buf[ctlr][uptr->DATAPTR++]; + sim_debug(DEBUG_DATA, dptr, "%s%o read word %d %012llo %09o %06o\n", + dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr); + if (rh_write(rhc)) { if (uptr->DATAPTR == uptr->hwmark) { /* Increment to next sector. Set Last Sector */ uptr->DATAPTR = 0; @@ -751,13 +516,16 @@ t_stat rs_svc (UNIT *uptr) if (GET_SF(uptr->DA) >= rs_drv_tab[dtype].surf) uptr->CMD |= DS_LST; } + if (rh_blkend(rhc)) + goto rd_end; } sim_activate(uptr, 20); } else { - sim_debug(DEBUG_DETAIL, dptr, "RSA%o read done\n", unit); +rd_end: + sim_debug(DEBUG_DETAIL, dptr, "%s%o read done\n", dptr->name, unit); uptr->CMD |= DS_DRY; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -767,20 +535,20 @@ t_stat rs_svc (UNIT *uptr) if (GET_SC(uptr->DA) >= rs_drv_tab[dtype].sect || GET_SF(uptr->DA) >= rs_drv_tab[dtype].surf) { uptr->CMD |= (ER1_IAE << 16)|DS_ERR|DS_DRY|DS_ATA; - uptr->CMD &= ~CR_GO; - sim_debug(DEBUG_DETAIL, dptr, "RSA%o writex done\n", unit); - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + sim_debug(DEBUG_DETAIL, dptr, "%s%o writex done\n", dptr->name, unit); + rh_finish_op(rhc, 0); return SCPE_OK; } } - r = df10_read(df); - rs_buf[ctlr][uptr->DATAPTR++] = df->buf; - sim_debug(DEBUG_DATA, dptr, "RSA%o write word %d %012llo %09o %06o\n", - unit, uptr->DATAPTR, df->buf, df->cda, df->wcr); + r = rh_read(rhc); + rs_buf[ctlr][uptr->DATAPTR++] = rhc->buf; + sim_debug(DEBUG_DATA, dptr, "%s%o write word %d %012llo %09o %06o\n", + dptr->name, unit, uptr->DATAPTR, rhc->buf, rhc->cda, rhc->wcr); if (r == 0 || uptr->DATAPTR == RS_NUMWD) { while (uptr->DATAPTR < RS_NUMWD) rs_buf[ctlr][uptr->DATAPTR++] = 0; - sim_debug(DEBUG_DETAIL, dptr, "RSA%o write (%d,%d)\n", unit, + sim_debug(DEBUG_DETAIL, dptr, "%s%o write (%d,%d)\n", dptr->name, unit, GET_SC(uptr->DA), GET_SF(uptr->DA)); da = GET_DA(uptr->DA, dtype) * RS_NUMWD; (void)sim_fseek(uptr->fileref, da * sizeof(uint64), SEEK_SET); @@ -795,15 +563,18 @@ t_stat rs_svc (UNIT *uptr) if (GET_SF(uptr->DA) >= rs_drv_tab[dtype].surf) uptr->CMD |= DS_LST; } + if (rh_blkend(rhc)) + goto wr_end; } } if (r) { sim_activate(uptr, 20); } else { - sim_debug(DEBUG_DETAIL, dptr, "RSA%o write done\n", unit); +wr_end: + sim_debug(DEBUG_DETAIL, dptr, "%s%o write done\n", dptr->name, unit); uptr->CMD |= DS_DRY; - uptr->CMD &= ~CR_GO; - df10_finish_op(df, 0); + uptr->CMD &= ~CS1_GO; + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -831,12 +602,10 @@ rs_reset(DEVICE * rstr) { int ctlr; for (ctlr = 0; ctlr < NUM_DEVS_RS; ctlr++) { - rs_df10[ctlr].devnum = rs_dib[ctlr].dev_num; - rs_df10[ctlr].nxmerr = 19; - rs_df10[ctlr].ccw_comp = 14; - rs_df10[ctlr].status = 0; - rs_attn[ctlr] = 0; - rs_rae[ctlr] = 0; + rs_rh[ctlr].devnum = rs_dib[ctlr].dev_num; + rs_rh[ctlr].status = 0; + rs_rh[ctlr].attn = 0; + rs_rh[ctlr].rae = 0; } return SCPE_OK; } @@ -846,16 +615,16 @@ t_stat rs_boot(int32 unit_num, DEVICE * rptr) { UNIT *uptr = &rptr->units[unit_num]; - int ctlr = GET_CNTRL(uptr->flags); + int ctlr = GET_CNTRL_RH(uptr->flags); + struct rh_if *rhc; DEVICE *dptr; - struct df10 *df; uint32 addr; uint32 ptr = 0; uint64 word; int wc; - df = &rs_df10[ctlr]; dptr = rs_devs[ctlr]; + rhc = &rs_rh[ctlr]; (void)sim_fseek(uptr->fileref, 0, SEEK_SET); (void)sim_fread (&rs_buf[0][0], sizeof(uint64), RS_NUMWD, uptr->fileref); uptr->CMD |= DS_VV; @@ -873,9 +642,9 @@ rs_boot(int32 unit_num, DEVICE * rptr) addr = rs_buf[0][ptr] & RMASK; wc = (rs_buf[0][ptr++] >> 18) & RMASK; word = rs_buf[0][ptr++]; - rs_reg[ctlr] = 040; - rs_drive[ctlr] = uptr - dptr->units; - df->status |= CCW_COMP_1|PI_ENABLE; + rhc->reg = 040; + rhc->drive = uptr - dptr->units; + rhc->status |= CCW_COMP_1|PI_ENABLE; PC = word & RMASK; return SCPE_OK; @@ -905,8 +674,8 @@ t_stat rs_attach (UNIT *uptr, CONST char *cptr) uptr->CMD |= DS_DPR|DS_MOL|DS_DRY; if (uptr->flags & UNIT_WLK) uptr->CMD |= DS_WRL; - rs_df10[ctlr].status |= PI_ENABLE; - set_interrupt(dib->dev_num, rs_df10[ctlr].status); + rs_rh[ctlr].status |= PI_ENABLE; + set_interrupt(dib->dev_num, rs_rh[ctlr].status); return SCPE_OK; } diff --git a/PDP10/kx10_sys.c b/PDP10/kx10_sys.c index a7ae6e1..1840edb 100644 --- a/PDP10/kx10_sys.c +++ b/PDP10/kx10_sys.c @@ -523,12 +523,22 @@ int get_word(FILE *fileref, uint64 *word) if (sim_fread(cbuf, 1, 5, fileref) != 5) return 1; - *word = ((uint64)(cbuf[0]) << 29) | - ((uint64)(cbuf[1]) << 22) | - ((uint64)(cbuf[2]) << 15) | - ((uint64)(cbuf[3]) << 8) | - ((uint64)(cbuf[4] & 0177) << 1) | - ((uint64)(cbuf[4] & 0200) >> 7); +#if 1 + *word = ((uint64)(cbuf[0] & 0177) << 29) | + ((uint64)(cbuf[1] & 0177) << 22) | + ((uint64)(cbuf[2] & 0177) << 15) | + ((uint64)(cbuf[3] & 0177) << 8) | + ((uint64)(cbuf[4] & 0177) << 1); + if (cbuf[4] & 0200) + *word |= 1; +#endif +#if 0 + *word = ((uint64)(cbuf[0] & 0377) << 28) | + ((uint64)(cbuf[1] & 0377) << 20) | + ((uint64)(cbuf[2] & 0377) << 12) | + ((uint64)(cbuf[3] & 0377) << 4) | + (uint64)(cbuf[4] & 017); +#endif return 0; } @@ -613,7 +623,6 @@ cont = 1; do { wc = get_word(fileref, &data); -// wc = sim_fread (&data, sizeof (uint64), 1, fileref);/* read blk hdr */ if (wc != 0) /* error? */ return SCPE_FMT; bsz = (int32) ((data & RMASK) - 1); /* get count */ @@ -630,9 +639,6 @@ do { return SCPE_FMT; } ndir = bsz; -// ndir = sim_fread (dirbuf, sizeof (uint64), bsz, fileref); - // if (ndir < bsz) /* error */ - // return SCPE_FMT; break; case EXE_PDV: /* optional */ @@ -646,9 +652,6 @@ do { if (get_word(fileref, &entbuf[i])) return SCPE_FMT; } -// entvec = sim_fread (entbuf, sizeof (uint64), bsz, fileref); - // if (entvec < 2) /* error? */ - // return SCPE_FMT; entvec = bsz; cont = 0; /* stop */ break; @@ -673,24 +676,22 @@ for (i = 0; i < ndir; i = i + 2) { /* loop thru dir */ (void)sim_fseek (fileref, (fpage << PAG_V_PN) * 5, SEEK_SET); for (k = 0; k < PAG_SIZE; k++) { if (get_word(fileref, &pagbuf[k])) - return SCPE_FMT; + break; } -// wc = sim_fread (pagbuf, sizeof (uint64), PAG_SIZE, fileref); - // if (wc < PAG_SIZE) - // return SCPE_FMT; fpage++; } ma = mpage << PAG_V_PN; /* mem addr */ for (k = 0; k < PAG_SIZE; k++, ma++) { /* copy buf to mem */ if (ma > MEMSIZE) return SCPE_NXM; -fprintf(stderr, "M %06o %012llo\n", ma, pagbuf[k]); M[ma] = fpage? (pagbuf[k] & FMASK): 0; } /* end copy */ } /* end rpt */ } /* end directory */ if (entvec && entbuf[1]) PC = (int32) (entbuf[1] & RMASK); /* start addr */ +else if (entvec == 0) + PC = (int32) (M[0120] & RMASK); return SCPE_OK; } diff --git a/PDP10/kx10_tu.c b/PDP10/kx10_tu.c index 2870106..34fb4ef 100644 --- a/PDP10/kx10_tu.c +++ b/PDP10/kx10_tu.c @@ -39,69 +39,12 @@ /* Flags in the unit flags word */ #define TU_UNIT UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE -#define CNTRL_V_CTYPE (MTUF_V_UF) -#define CNTRL_M_CTYPE 7 -#define GET_CNTRL(x) (((x) >> CNTRL_V_CTYPE) & CNTRL_M_CTYPE) -#define CNTRL(x) (((x) & CNTRL_M_CTYPE) << CNTRL_V_CTYPE) - -/* CONI Flags */ -#define IADR_ATTN 0000000000040LL /* Interrupt on attention */ -#define IARD_RAE 0000000000100LL /* Interrupt on register access error */ -#define DIB_CBOV 0000000000200LL /* Control bus overrun */ -#define CXR_PS_FAIL 0000000002000LL /* Power supply fail (not implemented) */ -#define CXR_ILC 0000000004000LL /* Illegal function code */ -#define CR_DRE 0000000010000LL /* Or Data and Control Timeout */ -#define DTC_OVER 0000000020000LL /* DF10 did not supply word on time (not implemented) */ -#define CCW_COMP_1 0000000040000LL /* Control word written. */ -#define CXR_CHAN_ER 0000000100000LL /* Channel Error */ -#define CXR_EXC 0000000200000LL /* Error in drive transfer */ -#define CXR_DBPE 0000000400000LL /* Device Parity error (not implemented) */ -#define CXR_NXM 0000001000000LL /* Channel non-existent memory (not implemented) */ -#define CXR_CWPE 0000002000000LL /* Channel Control word parity error (not implemented) */ -#define CXR_CDPE 0000004000000LL /* Channel Data Parity Error (not implemented) */ -#define CXR_SD_RAE 0000200000000LL /* Register access error */ -#define CXR_ILFC 0000400000000LL /* Illegal CXR function code */ -#define B22_FLAG 0004000000000LL /* 22 bit channel */ -#define CC_CHAN_PLS 0010000000000LL /* Channel transfer pulse (not implemented) */ -#define CC_CHAN_ACT 0020000000000LL /* Channel in use */ -#define CC_INH 0040000000000LL /* Disconnect channel */ -#define CB_FULL 0200000000000LL /* Set when channel buffer is full (not implemented) */ -#define AR_FULL 0400000000000LL /* Set when AR is full (not implemented) */ - -/* CONO Flags */ -#define ATTN_EN 0000000000040LL /* enable attention interrupt. */ -#define REA_EN 0000000000100LL /* enable register error interrupt */ -#define CBOV_CLR 0000000000200LL /* Clear CBOV */ -#define CONT_RESET 0000000002000LL /* Clear All error bits */ -#define ILC_CLR 0000000004000LL /* Clear ILC and SD RAE */ -#define DRE_CLR 0000000010000LL /* Clear CR_CBTO and CR_DBTO */ -#define OVER_CLR 0000000020000LL /* Clear DTC overrun */ -#define WRT_CW 0000000040000LL /* Write control word */ -#define CHN_CLR 0000000100000LL /* Clear Channel Error */ -#define DR_EXC_CLR 0000000200000LL /* Clear DR_EXC */ -#define DBPE_CLR 0000000400000LL /* Clear CXR_DBPE */ - -/* DATAO/DATAI */ -#define CR_REG 0770000000000LL /* Register number */ -#define LOAD_REG 0004000000000LL /* Load register */ -#define CR_MAINT_MODE 0000100000000LL /* Maint mode... not implemented */ -#define CR_DRIVE 0000007000000LL -#define CR_GEN_EVD 0000000400000LL /* Enable Parity */ -#define CR_DXES 0000000200000LL /* Disable DXES errors */ -#define CR_INAD 0000000077600LL -#define CR_WTEVM 0000000000100LL /* Verify Parity */ -#define CR_FUNC 0000000000076LL -#define CR_GO 0000000000001LL - -#define IRQ_VECT 0000000000177LL /* Interupt vector */ -#define IRQ_KI10 0000002000000LL -#define IRQ_KA10 0000001000000LL #define CMD u3 /* u3 low */ /* TUC - 00 - control */ -#define CS1_GO CR_GO /* go */ +#define CS1_GO 1 /* go */ #define CS1_V_FNC 1 /* function pos */ #define CS1_M_FNC 037 /* function mask */ #define CS1_FNC (CS1_M_FNC << CS1_V_FNC) @@ -213,23 +156,15 @@ #define CPOS u4 #define DATAPTR u6 -struct df10 tu_df10[NUM_DEVS_TU]; -int tu_xfer_drive[NUM_DEVS_TU]; +struct rh_if tu_rh[NUM_DEVS_TU]; uint8 tu_buf[NUM_DEVS_TU][TU_NUMFR]; -int tu_reg[NUM_DEVS_TU]; -int tu_ivect[NUM_DEVS_TU]; -int tu_imode[NUM_DEVS_TU]; -int tu_drive[NUM_DEVS_TU]; -int tu_rae[NUM_DEVS_TU]; -int tu_attn[NUM_DEVS_TU]; uint16 tu_frame[NUM_DEVS_TU]; uint16 tu_tcr[NUM_DEVS_TU]; static uint64 tu_boot_buffer; -t_stat tu_devio(uint32 dev, uint64 *data); -int tu_devirq(uint32 dev, int addr); -void tu_write(int ctlr, int unit, int reg, uint32 data); -uint32 tu_read(int ctlr, int unit, int reg); +void tu_write(DEVICE *dptr, struct rh_if *rhc, int reg, uint32 data); +uint32 tu_read(DEVICE *dptr, struct rh_if *rhc, int reg); +void tu_rst(DEVICE *dptr); t_stat tu_srv(UNIT *); t_stat tu_boot(int32, DEVICE *); void tu_ini(UNIT *, t_bool); @@ -243,21 +178,31 @@ const char *tu_description (DEVICE *dptr); UNIT tu_unit[] = { /* Controller 1 */ - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, - { UDATA (&tu_srv, TU_UNIT+CNTRL(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, + { UDATA (&tu_srv, TU_UNIT+CNTRL_RH(0), 0) }, +}; + +struct rh_if tu_rh[] = { + { &tu_write, &tu_read} }; DIB tu_dib[] = { - {RH10_DEV, 1, &tu_devio, &tu_devirq} + {RH10_DEV, 1, &rh_devio, &rh_devirq, &tu_rh[0]} }; MTAB tu_mod[] = { +#if KL + {MTAB_XTD|MTAB_VDV, TYPE_RH10, NULL, "RH10", &rh_set_type, NULL, + NULL, "Sets controller to RH10" }, + {MTAB_XTD|MTAB_VDV, TYPE_RH20, "RH20", "RH20", &rh_set_type, &rh_show_type, + NULL, "Sets controller to RH20"}, +#endif {MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL}, {MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL}, {MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT", @@ -270,24 +215,22 @@ MTAB tu_mod[] = { }; REG tua_reg[] = { - {ORDATA(IVECT, tu_ivect[0], 18)}, - {FLDATA(IMODE, tu_imode[0], 0)}, + {ORDATA(IVECT, tu_rh[0].ivect, 18)}, + {FLDATA(IMODE, tu_rh[0].imode, 0)}, {ORDATA(FRAME, tu_frame[0], 16)}, {ORDATA(TCR, tu_tcr[0], 16)}, - {ORDATA(XFER, tu_xfer_drive[0], 3), REG_HRO}, - {ORDATA(DRIVE, tu_drive[0], 3), REG_HRO}, - {ORDATA(REG, tu_reg[0], 6), REG_RO}, - {ORDATA(RAE, tu_rae[0], 8), REG_RO}, - {ORDATA(ATTN, tu_attn[0], 8), REG_RO}, - {ORDATA(STATUS, tu_df10[0].status, 18), REG_RO}, - {ORDATA(CIA, tu_df10[0].cia, 18)}, - {ORDATA(CCW, tu_df10[0].ccw, 18)}, - {ORDATA(WCR, tu_df10[0].wcr, 18)}, - {ORDATA(CDA, tu_df10[0].cda, 18)}, - {ORDATA(DEVNUM, tu_df10[0].devnum, 9), REG_HRO}, - {ORDATA(BUF, tu_df10[0].buf, 36), REG_HRO}, - {ORDATA(NXM, tu_df10[0].nxmerr, 8), REG_HRO}, - {ORDATA(COMP, tu_df10[0].ccw_comp, 8), REG_HRO}, + {ORDATA(XFER, tu_rh[0].xfer_drive, 3), REG_HRO}, + {ORDATA(DRIVE, tu_rh[0].drive, 3), REG_HRO}, + {ORDATA(REG, tu_rh[0].reg, 6), REG_RO}, + {ORDATA(RAE, tu_rh[0].rae, 8), REG_RO}, + {ORDATA(ATTN, tu_rh[0].attn, 8), REG_RO}, + {ORDATA(STATUS, tu_rh[0].status, 18), REG_RO}, + {ORDATA(CIA, tu_rh[0].cia, 18)}, + {ORDATA(CCW, tu_rh[0].ccw, 18)}, + {ORDATA(WCR, tu_rh[0].wcr, 18)}, + {ORDATA(CDA, tu_rh[0].cda, 18)}, + {ORDATA(DEVNUM, tu_rh[0].devnum, 9), REG_HRO}, + {ORDATA(BUF, tu_rh[0].buf, 36), REG_HRO}, {BRDATA(BUFF, &tu_buf[0][0], 16, 64, TU_NUMFR), REG_HRO}, {0} }; @@ -305,196 +248,22 @@ DEVICE *tu_devs[] = { &tua_dev, }; - -t_stat tu_devio(uint32 dev, uint64 *data) { - int ctlr = -1; - DEVICE *dptr = NULL; - struct df10 *df10; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - - if (dptr == NULL) - return SCPE_OK; - ctlr = GET_CNTRL(dptr->units[0].flags); - df10 = &tu_df10[ctlr]; - df10->devnum = dev; - switch(dev & 3) { - case CONI: - *data = df10->status & ~(IADR_ATTN|IARD_RAE); - if (tu_attn[ctlr] != 0 && (df10->status & IADR_ATTN)) - *data |= IADR_ATTN; - if (tu_rae[ctlr] != 0 && (df10->status & IARD_RAE)) - *data |= IARD_RAE; -#if KI_22BIT - *data |= B22_FLAG; -#endif - sim_debug(DEBUG_CONI, dptr, "TU %03o CONI %06o PC=%o %o\n", - dev, (uint32)*data, PC, tu_attn[ctlr]); - return SCPE_OK; - - case CONO: - clr_interrupt(dev); - df10->status &= ~07LL; - df10->status |= *data & (07LL|IADR_ATTN|IARD_RAE); - /* Clear flags */ - if (*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)) - df10->status &= ~(*data & (DBPE_CLR|DR_EXC_CLR|CHN_CLR)); - if (*data & OVER_CLR) - df10->status &= ~(DTC_OVER); - if (*data & CBOV_CLR) - df10->status &= ~(DIB_CBOV); - if (*data & CXR_ILC) - df10->status &= ~(CXR_ILFC|CXR_SD_RAE); - if (*data & WRT_CW) - df10_writecw(df10); - if (*data & PI_ENABLE) - df10->status &= ~PI_ENABLE; - if (df10->status & PI_ENABLE) - set_interrupt(dev, df10->status); - if ((df10->status & IADR_ATTN) != 0 && tu_attn[ctlr] != 0) - set_interrupt(dev, df10->status); - sim_debug(DEBUG_CONO, dptr, "TU %03o CONO %06o %d PC=%06o %06o\n", - dev, (uint32)*data, ctlr, PC, df10->status); - return SCPE_OK; - - case DATAI: - *data = 0; - if (df10->status & BUSY && tu_reg[ctlr] != 04) { - df10->status |= CC_CHAN_ACT; - return SCPE_OK; - } - if (tu_reg[ctlr] == 040) { - *data = (uint64)(tu_read(ctlr, tu_drive[ctlr], 0) & 077); - *data |= ((uint64)(df10->cia)) << 6; - *data |= ((uint64)(tu_xfer_drive[ctlr])) << 18; - } else if (tu_reg[ctlr] == 044) { - *data = (uint64)tu_ivect[ctlr]; - if (tu_imode[ctlr]) - *data |= IRQ_KI10; - else - *data |= IRQ_KA10; - } else if (tu_reg[ctlr] == 054) { - *data = (uint64)(tu_rae[ctlr]); - } else if ((tu_reg[ctlr] & 040) == 0) { - *data = (uint64)(tu_read(ctlr, tu_drive[ctlr], tu_reg[ctlr]) & 0177777); - *data |= ((uint64)(tu_drive[ctlr])) << 18; - } - *data |= ((uint64)(tu_reg[ctlr])) << 30; - sim_debug(DEBUG_DATAIO, dptr, "TU %03o DATI %012llo, %d %d PC=%06o\n", - dev, *data, ctlr, tu_drive[ctlr], PC); - return SCPE_OK; - - case DATAO: - sim_debug(DEBUG_DATAIO, dptr, "TU %03o DATO %012llo, %d PC=%06o %06o\n", - dev, *data, ctlr, PC, df10->status); - tu_reg[ctlr] = ((int)(*data >> 30)) & 077; - if (tu_reg[ctlr] < 040 && tu_reg[ctlr] != 04) { - tu_drive[ctlr] = (int)(*data >> 18) & 07; - } - if (*data & LOAD_REG) { - if (tu_reg[ctlr] == 040) { - if ((*data & 1) == 0) { - return SCPE_OK; - } - if (df10->status & BUSY) { - df10->status |= CC_CHAN_ACT; - sim_debug(DEBUG_DATAIO, dptr, - "TU %03o command busy %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, tu_drive[ctlr], PC, df10->status); - return SCPE_OK; - } - - df10->status &= ~(1 << df10->ccw_comp); - df10->status &= ~PI_ENABLE; - if (((*data >> 1) & 077) < FNC_XFER) { - df10->status |= CXR_ILC; - df10_setirq(df10); - sim_debug(DEBUG_DATAIO, dptr, - "TU %03o command abort %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, tu_drive[ctlr], PC, df10->status); - return SCPE_OK; - } - /* Check if access error */ - if (tu_rae[ctlr] & (1 << tu_drive[ctlr])) { - return SCPE_OK; - } - - /* Start command */ - df10_setup(df10, (uint32)(*data >> 6)); - tu_xfer_drive[ctlr] = (int)(*data >> 18) & 07; - tu_write(ctlr, tu_drive[ctlr], 0, (uint32)(*data & 077)); - sim_debug(DEBUG_DATAIO, dptr, - "TU %03o command %012llo, %d[%d] PC=%06o %06o\n", - dev, *data, ctlr, tu_drive[ctlr], PC, df10->status); - } else if (tu_reg[ctlr] == 044) { - /* Set KI10 Irq vector */ - tu_ivect[ctlr] = (int)(*data & IRQ_VECT); - tu_imode[ctlr] = (*data & IRQ_KI10) != 0; - } else if (tu_reg[ctlr] == 050) { - ; /* Diagnostic access to mass bus. */ - } else if (tu_reg[ctlr] == 054) { - /* clear flags */ - tu_rae[ctlr] &= ~(*data & 0377); - if (tu_rae[ctlr] == 0) - clr_interrupt(dev); - } else if ((tu_reg[ctlr] & 040) == 0) { - tu_drive[ctlr] = (int)(*data >> 18) & 07; - /* Check if access error */ - if (tu_rae[ctlr] & (1 << tu_drive[ctlr])) { - return SCPE_OK; - } - tu_drive[ctlr] = (int)(*data >> 18) & 07; - tu_write(ctlr, tu_drive[ctlr], tu_reg[ctlr] & 037, - (int)(*data & 0777777)); - } - } - return SCPE_OK; - } - return SCPE_OK; /* Unreached */ -} - -/* Handle KI and KL style interrupt vectors */ -int -tu_devirq(uint32 dev, int addr) { - DEVICE *dptr = NULL; - int drive; - - for (drive = 0; rh[drive].dev_num != 0; drive++) { - if (rh[drive].dev_num == (dev & 0774)) { - dptr = rh[drive].dev; - break; - } - } - if (dptr != NULL) { - drive = GET_CNTRL(dptr->units[0].flags); - return (tu_imode[drive] ? tu_ivect[drive] : addr); - } - return addr; -} - void -tu_write(int ctlr, int unit, int reg, uint32 data) { - UNIT *uptr = &tu_unit[(ctlr * 8) + (tu_tcr[ctlr] & 07)]; - DEVICE *dptr = tu_devs[ctlr]; - struct df10 *df10 = &tu_df10[ctlr]; +tu_write(DEVICE *dptr, struct rh_if *rhc, int reg, uint32 data) { + int ctlr = GET_CNTRL_RH(dptr->units[0].flags); + int unit = tu_tcr[ctlr] & 07; + UNIT *uptr = &dptr->units[unit]; int i; - if (uptr->CMD & CR_GO) { + if (uptr->CMD & CS1_GO) { uptr->STATUS |= (ER1_RMR); return; } switch(reg) { case 000: /* control */ - sim_debug(DEBUG_DETAIL, dptr, "TUA%o %d Status=%06o\n", - unit, ctlr, uptr->STATUS); - df10->status &= ~(1 << df10->ccw_comp); + sim_debug(DEBUG_DETAIL, dptr, "%s%o %d Status=%06o\n", + dptr->name, unit, ctlr, uptr->STATUS); if ((data & 01) != 0 && (uptr->flags & UNIT_ATT) != 0) { uptr->CMD = data & 076; switch (GET_FNC(data)) { @@ -516,34 +285,28 @@ tu_write(int ctlr, int unit, int reg, uint32 data) { case FNC_REWIND: /* rewind */ case FNC_UNLOAD: /* unload */ case FNC_WCHKREV: /* write w/ headers */ - uptr->CMD |= CS_PIP|CR_GO; + uptr->CMD |= CS_PIP|CS1_GO; uptr->CMD &= ~CS_TM; CLR_BUF(uptr); uptr->DATAPTR = 0; - df10->status &= ~PI_ENABLE; sim_activate(uptr, 100); break; case FNC_DCLR: /* drive clear */ - uptr->CMD &= ~(CS_ATA|CR_GO|CS_TM); + uptr->CMD &= ~(CS_ATA|CS1_GO|CS_TM); uptr->STATUS = 0; - tu_attn[ctlr] = 0; - clr_interrupt(df10->devnum); + rhc->attn = 0; for (i = 0; i < 8; i++) { - if (tu_unit[(ctlr * 8) + i].CMD & CS_ATA) - tu_attn[ctlr] = 1; + if (dptr->units[i].CMD & CS_ATA) + rhc->attn = 1; } - if ((df10->status & IADR_ATTN) != 0 && tu_attn[ctlr] != 0) - df10_setirq(df10); break; default: uptr->STATUS |= (ER1_ILF); uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; - if ((df10->status & IADR_ATTN) != 0) - df10_setirq(df10); + rhc->attn = 1; } - sim_debug(DEBUG_DETAIL, dptr, "TUA%o AStatus=%06o\n", unit, + sim_debug(DEBUG_DETAIL, dptr, "%s%o AStatus=%06o\n", dptr->name, unit, uptr->CMD); } return; @@ -556,17 +319,13 @@ tu_write(int ctlr, int unit, int reg, uint32 data) { case 003: /* maintenance */ break; case 004: /* atten summary */ - tu_attn[ctlr] = 0; + rhc->attn = 0; for (i = 0; i < 8; i++) { if (data & (1<units[i].CMD &= ~CS_ATA; + if (dptr->units[i].CMD & CS_ATA) + rhc->attn = 1; } - clr_interrupt(df10->devnum); - if (((df10->status & IADR_ATTN) != 0 && tu_attn[ctlr] != 0) || - (df10->status & PI_ENABLE)) - df10_setirq(df10); break; case 005: /* frame count */ tu_frame[ctlr] = data & 0177777; @@ -579,31 +338,30 @@ tu_write(int ctlr, int unit, int reg, uint32 data) { default: uptr->STATUS |= ER1_ILR; uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; - tu_rae[ctlr] |= (1<status & IADR_ATTN) != 0) - df10_setirq(df10); + rhc->attn = 1; + rhc->rae = 1; } } uint32 -tu_read(int ctlr, int unit, int reg) { - UNIT *uptr = &tu_unit[(ctlr * 8) + (tu_tcr[ctlr] & 07)]; - struct df10 *df10 = &tu_df10[ctlr]; - uint32 temp = 0; - int i; +tu_read(DEVICE *dptr, struct rh_if *rhc, int reg) { + int ctlr = GET_CNTRL_RH(dptr->units[0].flags); + int unit = tu_tcr[ctlr] & 07; + UNIT *uptr = &dptr->units[unit]; + uint32 temp = 0; + int i; switch(reg) { case 000: /* control */ temp = uptr->CMD & 076; if (uptr->flags & UNIT_ATT) temp |= CS1_DVA; - if (df10->status & BUSY || uptr->CMD & CR_GO) + if (uptr->CMD & CS1_GO) temp |= CS1_GO; break; case 001: /* status */ temp = DS_DPR; - if (tu_attn[ctlr] != 0) + if (rhc->attn != 0) temp |= DS_ATA; if (uptr->CMD & CS_CHANGE) temp |= DS_SSC; @@ -615,7 +373,7 @@ tu_read(int ctlr, int unit, int reg) { temp |= DS_TM; if (uptr->flags & MTUF_WLK) temp |= DS_WRL; - if ((uptr->CMD & (CS_MOTION|CS_PIP|CR_GO)) == 0) + if ((uptr->CMD & (CS_MOTION|CS_PIP|CS1_GO)) == 0) temp |= DS_DRY; if (sim_tape_bot(uptr)) temp |= DS_BOT; @@ -632,7 +390,7 @@ tu_read(int ctlr, int unit, int reg) { break; case 004: /* atten summary */ for (i = 0; i < 8; i++) { - if (tu_unit[(ctlr * 8) + i].CMD & CS_ATA) { + if (dptr->units[i].CMD & CS_ATA) { temp |= 1 << i; } } @@ -655,10 +413,8 @@ tu_read(int ctlr, int unit, int reg) { default: uptr->STATUS |= (ER1_ILR); uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; - tu_rae[ctlr] |= (1<status & IADR_ATTN) != 0) - df10_setirq(df10); + rhc->attn = 1; + rhc->rae = 1; } return temp; } @@ -667,8 +423,9 @@ tu_read(int ctlr, int unit, int reg) { /* Map simH errors into machine errors */ void tu_error(UNIT * uptr, t_stat r) { - int ctlr = GET_CNTRL(uptr->flags); - DEVICE *dptr = tu_devs[ctlr]; + int ctlr = GET_CNTRL_RH(uptr->flags); + DEVICE *dptr = tu_devs[ctlr]; + struct rh_if *rhc = &tu_rh[ctlr]; switch (r) { case MTSE_OK: /* no error */ @@ -706,66 +463,61 @@ void tu_error(UNIT * uptr, t_stat r) } if (uptr->CMD & CS_ATA) { - tu_attn[ctlr] = 1; + rh_setattn(rhc, 0); +// rhc->attn = 1; } - uptr->CMD &= ~(CS_MOTION|CS_PIP|CR_GO); + uptr->CMD &= ~(CS_MOTION|CS_PIP|CS1_GO); sim_debug(DEBUG_EXP, dptr, "Setting status %d\n", r); } /* Handle processing of tape requests. */ t_stat tu_srv(UNIT * uptr) { - int ctlr = GET_CNTRL(uptr->flags); - int unit; - DEVICE *dptr; - struct df10 *df; - t_stat r; - t_mtrlnt reclen; - uint8 ch; - int cc; - int cc_max; + int ctlr = GET_CNTRL_RH(uptr->flags); + int unit; + struct rh_if *rhc; + DEVICE *dptr; + t_stat r; + t_mtrlnt reclen; + uint8 ch; + int cc; + int cc_max; /* Find dptr, and df10 */ dptr = tu_devs[ctlr]; + rhc = &tu_rh[ctlr]; unit = uptr - dptr->units; - df = &tu_df10[ctlr]; cc_max = (4 + ((tu_tcr[ctlr] & TC_FMTSEL) == 0)); if ((uptr->flags & UNIT_ATT) == 0) { tu_error(uptr, MTSE_UNATT); /* attached? */ - df10_setirq(df); + rh_setirq(rhc); return SCPE_OK; } switch (GET_FNC(uptr->CMD)) { case FNC_NOP: case FNC_DCLR: - sim_debug(DEBUG_DETAIL, dptr, "TU%o nop\n", unit); + sim_debug(DEBUG_DETAIL, dptr, "%s%o nop\n", dptr->name, unit); tu_error(uptr, MTSE_OK); /* Nop */ - df10_setirq(df); + rh_setirq(rhc); return SCPE_OK; case FNC_REWIND: - sim_debug(DEBUG_DETAIL, dptr, "TU%o rewind\n", unit); - if (uptr->CMD & CR_GO) { + sim_debug(DEBUG_DETAIL, dptr, "%s%o rewind\n", dptr->name, unit); + if (uptr->CMD & CS1_GO) { sim_activate(uptr,40000); uptr->CMD |= CS_MOTION; - uptr->CMD &= ~(CR_GO); + uptr->CMD &= ~(CS1_GO); } else { uptr->CMD &= ~(CS_MOTION|CS_PIP); uptr->CMD |= CS_CHANGE|CS_ATA; - tu_attn[ctlr] = 1; - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); tu_error(uptr, sim_tape_rewind(uptr)); } return SCPE_OK; case FNC_UNLOAD: - sim_debug(DEBUG_DETAIL, dptr, "TU%o unload\n", unit); - uptr->CMD &= ~(CR_GO); + sim_debug(DEBUG_DETAIL, dptr, "%s%o unload\n", dptr->name, unit); + uptr->CMD &= ~(CS1_GO); uptr->CMD |= CS_CHANGE|CS_ATA; - tu_attn[ctlr] = 1; - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); tu_error(uptr, sim_tape_detach(uptr)); return SCPE_OK; @@ -775,18 +527,18 @@ t_stat tu_srv(UNIT * uptr) uptr->CMD &= ~CS_PIP; if ((r = sim_tape_rdrecr(uptr, &tu_buf[ctlr][0], &reclen, TU_NUMFR)) != MTSE_OK) { - sim_debug(DEBUG_DETAIL, dptr, "TU%o read error %d\n", unit, r); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read error %d\n", dptr->name, unit, r); if (r == MTSE_BOT) uptr->STATUS |= ER1_NEF; tu_error(uptr, r); - df10_finish_op(df, 0); + rh_finish_op(rhc, 0); } else { - sim_debug(DEBUG_DETAIL, dptr, "TU%o read %d\n", unit, reclen); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read %d\n", dptr->name, unit, reclen); uptr->CMD |= CS_MOTION; uptr->hwmark = reclen; uptr->DATAPTR = uptr->hwmark-1; uptr->CPOS = cc_max; - df->buf = 0; + rhc->buf = 0; sim_activate(uptr, 100); } return SCPE_OK; @@ -796,26 +548,27 @@ t_stat tu_srv(UNIT * uptr) cc = (8 * (3 - uptr->CPOS)) + 4; ch = tu_buf[ctlr][uptr->DATAPTR]; if (cc < 0) - df->buf |= (uint64)(ch & 0x0f); + rhc->buf |= (uint64)(ch & 0x0f); else - df->buf |= (uint64)(ch & 0xff) << cc; + rhc->buf |= (uint64)(ch & 0xff) << cc; uptr->DATAPTR--; uptr->CPOS--; if (uptr->CPOS == 0) { uptr->CPOS = cc_max; - if (GET_FNC(uptr->CMD) == FNC_READREV && - df10_write(df) == 0) { + if (GET_FNC(uptr->CMD) == FNC_READREV && rh_write(rhc) == 0) { tu_error(uptr, MTSE_OK); return SCPE_OK; } - sim_debug(DEBUG_DATA, dptr, "TU%o readrev %012llo\n", - unit, df->buf); - df->buf = 0; + sim_debug(DEBUG_DATA, dptr, "%s%o readrev %012llo\n", + dptr->name, unit, rhc->buf); + rhc->buf = 0; } } else { if (uptr->CPOS != cc_max) - df10_write(df); + rh_write(rhc); + (void)rh_blkend(rhc); tu_error(uptr, MTSE_OK); + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -827,15 +580,15 @@ t_stat tu_srv(UNIT * uptr) uptr->CMD |= CS_MOTION; if ((r = sim_tape_rdrecf(uptr, &tu_buf[ctlr][0], &reclen, TU_NUMFR)) != MTSE_OK) { - sim_debug(DEBUG_DETAIL, dptr, "TU%o read error %d\n", unit, r); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read error %d\n", dptr->name, unit, r); tu_error(uptr, r); - df10_finish_op(df, 0); + rh_finish_op(rhc, 0); } else { - sim_debug(DEBUG_DETAIL, dptr, "TU%o read %d\n", unit, reclen); + sim_debug(DEBUG_DETAIL, dptr, "%s%o read %d %d\n", dptr->name, unit, reclen, uptr->pos); uptr->hwmark = reclen; uptr->DATAPTR = 0; uptr->CPOS = 0; - df->buf = 0; + rhc->buf = 0; sim_activate(uptr, 100); } return SCPE_OK; @@ -845,30 +598,30 @@ t_stat tu_srv(UNIT * uptr) cc = (8 * (3 - uptr->CPOS)) + 4; ch = tu_buf[ctlr][uptr->DATAPTR]; if (cc < 0) - df->buf |= (uint64)(ch & 0x0f); + rhc->buf |= (uint64)(ch & 0x0f); else - df->buf |= (uint64)(ch & 0xff) << cc; + rhc->buf |= (uint64)(ch & 0xff) << cc; uptr->DATAPTR++; uptr->CPOS++; if (uptr->CPOS == cc_max) { uptr->CPOS = 0; - if (GET_FNC(uptr->CMD) == FNC_READ && - df10_write(df) == 0) { + if (GET_FNC(uptr->CMD) == FNC_READ && rh_write(rhc) == 0) { tu_error(uptr, MTSE_OK); return SCPE_OK; } - sim_debug(DEBUG_DATA, dptr, "TU%o read %012llo\n", - unit, df->buf); - df->buf = 0; + sim_debug(DEBUG_DATA, dptr, "%s%o read %012llo\n", + dptr->name, unit, rhc->buf); + rhc->buf = 0; } } else { if (uptr->CPOS != 0) { - sim_debug(DEBUG_DATA, dptr, "TU%o read %012llo\n", - unit, df->buf); - df10_write(df); + sim_debug(DEBUG_DATA, dptr, "%s%o read %012llo\n", + dptr->name, unit, rhc->buf); + rh_write(rhc); } tu_error(uptr, MTSE_OK); - df10_finish_op(df, 0); + (void)rh_blkend(rhc); + rh_finish_op(rhc, 0); return SCPE_OK; } break; @@ -878,38 +631,38 @@ t_stat tu_srv(UNIT * uptr) uptr->CMD &= ~CS_PIP; if (tu_frame[ctlr] == 0) { uptr->STATUS |= ER1_NEF; - uptr->CMD &= ~(CR_GO); + uptr->CMD &= ~(CS1_GO); uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; + rhc->attn = 1; tu_error(uptr, MTSE_OK); - df10_finish_op(df, 0); + rh_finish_op(rhc, 0); return SCPE_OK; } if ((uptr->flags & MTUF_WLK) != 0) { tu_error(uptr, MTSE_WRP); - df10_finish_op(df, 0); + rh_finish_op(rhc, 0); return SCPE_OK; } uptr->CMD |= CS_MOTION; - sim_debug(DEBUG_EXP, dptr, "TU%o Init write\n", unit); + sim_debug(DEBUG_EXP, dptr, "%s%o Init write\n", dptr->name, unit); uptr->hwmark = 0; uptr->CPOS = 0; uptr->DATAPTR = 0; - df->buf = 0; + rhc->buf = 0; } - if (tu_frame[ctlr] != 0 && uptr->CPOS == 0 && df10_read(df) == 0) + if (tu_frame[ctlr] != 0 && uptr->CPOS == 0 && rh_read(rhc) == 0) uptr->CPOS |= 010; if ((uptr->CMD & CS_MOTION) != 0) { if (uptr->CPOS == 0) - sim_debug(DEBUG_DATA, dptr, "TU%o write %012llo\n", - unit, df->buf); + sim_debug(DEBUG_DATA, dptr, "%s%o write %012llo\n", + dptr->name, unit, rhc->buf); /* Write next char out */ cc = (8 * (3 - (uptr->CPOS & 07))) + 4; if (cc < 0) - ch = df->buf & 0x0f; + ch = rhc->buf & 0x0f; else - ch = (df->buf >> cc) & 0xff; + ch = (rhc->buf >> cc) & 0xff; tu_buf[ctlr][uptr->DATAPTR] = ch; uptr->DATAPTR++; uptr->hwmark = uptr->DATAPTR; @@ -925,52 +678,44 @@ t_stat tu_srv(UNIT * uptr) /* Write out the block */ reclen = uptr->hwmark; r = sim_tape_wrrecf(uptr, &tu_buf[ctlr][0], reclen); - sim_debug(DEBUG_DETAIL, dptr, "TU%o Write %d %d\n", - unit, reclen, uptr->CPOS); + sim_debug(DEBUG_DETAIL, dptr, "%s%o Write %d %d\n", + dptr->name, unit, reclen, uptr->CPOS); uptr->DATAPTR = 0; uptr->hwmark = 0; - df10_finish_op(df,0 ); + (void)rh_blkend(rhc); tu_error(uptr, r); /* Record errors */ + rh_finish_op(rhc,0 ); return SCPE_OK; } break; case FNC_WTM: + uptr->CMD |= CS_ATA; if ((uptr->flags & MTUF_WLK) != 0) { tu_error(uptr, MTSE_WRP); } else { tu_error(uptr, sim_tape_wrtmk(uptr)); } - uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; - sim_debug(DEBUG_DETAIL, dptr, "TU%o WTM\n", unit); - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); + sim_debug(DEBUG_DETAIL, dptr, "%s%o WTM\n", dptr->name, unit); return SCPE_OK; case FNC_ERASE: + uptr->CMD |= CS_ATA; if ((uptr->flags & MTUF_WLK) != 0) { tu_error(uptr, MTSE_WRP); } else { tu_error(uptr, sim_tape_wrgap(uptr, 35)); } - uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; - sim_debug(DEBUG_DETAIL, dptr, "TU%o ERG\n", unit); - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); + sim_debug(DEBUG_DETAIL, dptr, "%s%o ERG\n", dptr->name, unit); return SCPE_OK; case FNC_SPACEF: case FNC_SPACEB: - sim_debug(DEBUG_DETAIL, dptr, "TU%o space %o\n", unit, GET_FNC(uptr->CMD)); + sim_debug(DEBUG_DETAIL, dptr, "%s%o space %o\n", dptr->name, unit, GET_FNC(uptr->CMD)); if (tu_frame[ctlr] == 0) { uptr->STATUS |= ER1_NEF; uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; tu_error(uptr, MTSE_OK); - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); return SCPE_OK; } uptr->CMD |= CS_MOTION; @@ -991,26 +736,22 @@ t_stat tu_srv(UNIT * uptr) case MTSE_EOM: /* end of medium */ if (tu_frame[ctlr] != 0) uptr->STATUS |= ER1_FCE; - uptr->CMD &= ~(CR_GO); + uptr->CMD &= ~(CS1_GO); uptr->CMD |= CS_ATA; - tu_attn[ctlr] = 1; /* Stop motion if we recieve any of these */ tu_error(uptr, r); - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); return SCPE_OK; } tu_frame[ctlr] = 0177777 & (tu_frame[ctlr] + 1); if (tu_frame[ctlr] == 0) { + uptr->CMD |= CS_ATA; tu_error(uptr, MTSE_OK); - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); return SCPE_OK; } else sim_activate(uptr, 5000); return SCPE_OK; } - sim_activate(uptr, 200); + sim_activate(uptr, 100); return SCPE_OK; } @@ -1022,11 +763,9 @@ tu_reset(DEVICE * dptr) { int ctlr; for (ctlr = 0; ctlr < NUM_DEVS_TU; ctlr++) { - tu_df10[ctlr].devnum = tu_dib[ctlr].dev_num; - tu_df10[ctlr].nxmerr = 19; - tu_df10[ctlr].ccw_comp = 14; - tu_attn[ctlr] = 0; - tu_rae[ctlr] = 0; + tu_rh[ctlr].devnum = tu_dib[ctlr].dev_num; + tu_rh[ctlr].attn = 0; + tu_rh[ctlr].rae = 0; } return SCPE_OK; } @@ -1100,20 +839,17 @@ tu_boot(int32 unit_num, DEVICE * dptr) t_stat tu_attach(UNIT * uptr, CONST char *file) { t_stat r; - int ctlr = GET_CNTRL(uptr->flags); - struct df10 *df; - - /* Find df10 */ - df = &tu_df10[ctlr]; + int ctlr = GET_CNTRL_RH(uptr->flags); + struct rh_if *rhc = &tu_rh[ctlr]; uptr->CMD = 0; uptr->STATUS = 0; r = sim_tape_attach_ex(uptr, file, 0, 0); if (r == SCPE_OK) { uptr->CMD = CS_ATA|CS_CHANGE; - tu_attn[ctlr] = 1; - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); + rhc->attn = 1; + if ((rhc->status & IADR_ATTN) != 0) + rh_setirq(rhc); } return r; } @@ -1121,16 +857,15 @@ tu_attach(UNIT * uptr, CONST char *file) t_stat tu_detach(UNIT * uptr) { - int ctlr = GET_CNTRL(uptr->flags); - struct df10 *df; + int ctlr = GET_CNTRL_RH(uptr->flags); + struct rh_if *rhc = &tu_rh[ctlr]; /* Find df10 */ - df = &tu_df10[ctlr]; uptr->STATUS = 0; uptr->CMD = CS_ATA|CS_CHANGE; - tu_attn[ctlr] = 1; - if ((df->status & IADR_ATTN) != 0) - df10_setirq(df); + rhc->attn = 1; + if ((rhc->status & IADR_ATTN) != 0) + rh_setirq(rhc); return sim_tape_detach(uptr); } diff --git a/README.md b/README.md index 979d60d..63798b9 100644 --- a/README.md +++ b/README.md @@ -100,7 +100,6 @@ The PDP6 runs TOPS 10 4.5 off Dectape. The KA10 sim has successfully run Tops 10 4.5, 5.03 and Tops 10 6.03, ITS and WAITS. The KI10 sim has successfully run Tops 10 6.03 with VMSER. The KL10 sim has successfully run Tops 10 6.03 with VMSER and ITS. -KL10 extended addressing support is still in development. Disk * RC10 RD10/RM10 diff --git a/makefile b/makefile index f32920e..e645ce4 100644 --- a/makefile +++ b/makefile @@ -1232,13 +1232,13 @@ KA10 = ${KA10D}/kx10_cpu.c ${KA10D}/kx10_sys.c ${KA10D}/kx10_df.c \ ${KA10D}/kx10_rp.c ${KA10D}/kx10_rc.c ${KA10D}/kx10_dt.c \ ${KA10D}/kx10_dk.c ${KA10D}/kx10_cr.c ${KA10D}/kx10_cp.c \ ${KA10D}/kx10_tu.c ${KA10D}/kx10_rs.c ${KA10D}/ka10_pd.c \ - ${KA10D}/kx10_imp.c ${KA10D}/ka10_tk10.c ${KA10D}/ka10_mty.c \ - ${KA10D}/ka10_imx.c ${KA10D}/ka10_ch10.c ${KA10D}/ka10_stk.c \ - ${KA10D}/ka10_ten11.c ${KA10D}/ka10_auxcpu.c $(KA10D)/ka10_pmp.c \ - ${KA10D}/ka10_dkb.c ${KA10D}/pdp6_dct.c ${KA10D}/pdp6_dtc.c \ - ${KA10D}/pdp6_mtc.c ${KA10D}/pdp6_dsk.c ${KA10D}/pdp6_dcs.c \ - ${KA10D}/ka10_dpk.c ${KA10D}/kx10_dpy.c ${PDP10D}/ka10_ai.c \ - ${KA10D}/ka10_iii.c ${DISPLAYL} $(DISPLAY340) + ${KA10D}/kx10_rh.c ${KA10D}/kx10_imp.c ${KA10D}/ka10_tk10.c \ + ${KA10D}/ka10_mty.c ${KA10D}/ka10_imx.c ${KA10D}/ka10_ch10.c \ + ${KA10D}/ka10_stk.c ${KA10D}/ka10_ten11.c ${KA10D}/ka10_auxcpu.c \ + $(KA10D)/ka10_pmp.c ${KA10D}/ka10_dkb.c ${KA10D}/pdp6_dct.c \ + ${KA10D}/pdp6_dtc.c ${KA10D}/pdp6_mtc.c ${KA10D}/pdp6_dsk.c \ + ${KA10D}/pdp6_dcs.c ${KA10D}/ka10_dpk.c ${KA10D}/kx10_dpy.c \ + ${PDP10D}/ka10_ai.c ${KA10D}/ka10_iii.c ${DISPLAYL} $(DISPLAY340) KA10_OPT = -DKA=1 -DUSE_INT64 -I $(KA10D) -DUSE_SIM_CARD ${NETWORK_OPT} $(DISPLAY_OPT) $(KA10_DISPLAY_OPT) ifneq ($(PANDA_LIGHTS),) # ONLY for Panda display. @@ -1254,10 +1254,10 @@ endif KI10 = ${KI10D}/kx10_cpu.c ${KI10D}/kx10_sys.c ${KI10D}/kx10_df.c \ ${KI10D}/kx10_dp.c ${KI10D}/kx10_mt.c ${KI10D}/kx10_cty.c \ ${KI10D}/kx10_lp.c ${KI10D}/kx10_pt.c ${KI10D}/kx10_dc.c \ - ${KI10D}/kx10_rp.c ${KI10D}/kx10_rc.c ${KI10D}/kx10_dt.c \ - ${KI10D}/kx10_dk.c ${KI10D}/kx10_cr.c ${KI10D}/kx10_cp.c \ - ${KI10D}/kx10_tu.c ${KI10D}/kx10_rs.c ${KI10D}/kx10_imp.c \ - ${KI10D}/kx10_dpy.c ${DISPLAYL} $(DISPLAY340) + ${KI10D}/kx10_rh.c ${KI10D}/kx10_rp.c ${KI10D}/kx10_rc.c \ + ${KI10D}/kx10_dt.c ${KI10D}/kx10_dk.c ${KI10D}/kx10_cr.c \ + ${KI10D}/kx10_cp.c ${KI10D}/kx10_tu.c ${KI10D}/kx10_rs.c \ + ${KI10D}/kx10_imp.c ${KI10D}/kx10_dpy.c ${DISPLAYL} $(DISPLAY340) KI10_OPT = -DKI=1 -DUSE_INT64 -I $(KI10D) -DUSE_SIM_CARD ${NETWORK_OPT} $(DISPLAY_OPT) $(KI10_DISPLAY_OPT) ifneq ($(PANDA_LIGHTS),) # ONLY for Panda display. @@ -1268,9 +1268,10 @@ endif KL10D = PDP10 KL10 = ${KL10D}/kx10_cpu.c ${KL10D}/kx10_sys.c ${KL10D}/kx10_df.c \ - ${KL10D}/kx10_mt.c ${KL10D}/kx10_dc.c ${KL10D}/kx10_rp.c \ - ${KL10D}/kx10_tu.c ${KL10D}/kx10_rs.c ${KL10D}/kx10_imp.c \ - ${KL10D}/kl10_fe.c ${KL10D}/ka10_pd.c ${KL10D}/ka10_ch10.c + ${KL10D}/kx10_mt.c ${KL10D}/kx10_dc.c ${KL10D}/kx10_rh.c \ + ${KL10D}/kx10_rp.c ${KL10D}/kx10_tu.c ${KL10D}/kx10_rs.c \ + ${KL10D}/kx10_imp.c ${KL10D}/kl10_fe.c ${KL10D}/ka10_pd.c \ + ${KL10D}/ka10_ch10.c KL10_OPT = -DKL=1 -DUSE_INT64 -I $(KL10D) -DUSE_SIM_CARD ${NETWORK_OPT} PDP1D = PDP1