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KA10: KI10 support improved. Added switch register.
This commit is contained in:
Richard Cornwell
parent
a6bd4512e3
commit
be6f5aa8bd
@ -130,6 +130,7 @@ uint32 PC; /* Program counter */
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uint32 IR; /* Instruction register */
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uint32 FLAGS; /* Flags */
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uint32 AC; /* Operand accumulator */
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uint64 SW; /* Switch register */
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int BYF5; /* Second half of LDB/DPB instruction */
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int uuo_cycle; /* Uuo cycle in progress */
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int sac_inh; /* Don't store AR in AC */
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@ -255,6 +256,7 @@ REG cpu_reg[] = {
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{ ORDATA (FM17, FM[017], 36) },
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{ ORDATA (PIENB, pi_enable, 7) },
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{ BRDATA (REG, FM, 8, 36, 017) },
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{ ORDATAD(SW, SW, 36, "Console SW Register"), REG_FIT},
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{ NULL }
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};
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@ -267,7 +269,7 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 8, "128K", "128K", &cpu_set_size },
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{ UNIT_MSIZE, 12, "196K", "196K", &cpu_set_size },
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{ UNIT_MSIZE, 16, "256K", "256K", &cpu_set_size },
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#if KI & KI_22BIT
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#if KI_22BIT
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{ UNIT_MSIZE, 32, "512K", "512K", &cpu_set_size },
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{ UNIT_MSIZE, 64, "1024K", "1024K", &cpu_set_size },
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{ UNIT_MSIZE, 128, "2048K", "2048K", &cpu_set_size },
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@ -724,10 +726,10 @@ t_stat dev_pag(uint32 dev, uint64 *data) {
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}
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if (res & SMASK) {
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ub_ptr = ((res >> 18) & 017777) << 9;
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user_addr_cmp = (res & 00020000000000LL) != 0;
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small_user = (res & 00040000000000LL) != 0;
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fm_sel = (uint8)(res >> 29) & 060;
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}
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user_addr_cmp = (res & 00020000000000LL) != 0;
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small_user = (res & 00040000000000LL) != 0;
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fm_sel = (uint8)(res >> 29) & 060;
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pag_reload = 0;
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sim_debug(DEBUG_DATAIO, &cpu_dev,
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"DATAO PAG %012llo ebr=%06o ubr=%06o\n",
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@ -817,6 +819,7 @@ t_stat dev_apr(uint32 dev, uint64 *data) {
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case DATAI:
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/* Read switches */
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*data = SW;
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI APR %012llo\n", *data);
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break;
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}
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@ -909,6 +912,7 @@ t_stat dev_apr(uint32 dev, uint64 *data) {
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case DATAI:
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/* Read switches */
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*data = SW;
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAI APR %012llo\n", *data);
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break;
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}
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@ -1019,6 +1023,7 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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fprintf(stderr, " %03o small fault\n\r", page);
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return 0;
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}
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data = M[base + (page >> 1)];
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} else {
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/* If paging is not enabled, address is direct */
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if (!page_enable) {
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@ -1026,14 +1031,12 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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return 1;
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}
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/* Pages 340-377 via UBR */
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// fprintf(stderr, "xlat %06o %03o ", addr, page >> 1);
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if ((page & 0740) == 0340) {
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page += 01000 - 0340;
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/* Pages 400-777 via EBR */
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} else if (page & 0400) {
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base = eb_ptr;
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} else {
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// fprintf(stderr, "\n\r");
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if (!flag && ((FLAGS & PUBLIC) != 0)) {
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/* Handle public violation */
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 27) | 021LL;
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@ -1045,18 +1048,14 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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}
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}
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data = M[base + (page >> 1)];
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// fprintf(stderr, " %06o %03o %012llo ", base, page, data);
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if ((page & 1) == 0)
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data >>= 18;
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data &= RMASK;
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// fprintf(stderr, " -> %06llo wr=%o ", data, wr);
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*loc = ((data & 017777) << 9) + (addr & 0777);
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// fprintf(stderr, " -> %06o\n", *loc);
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if (!flag && ((FLAGS & PUBLIC) != 0) && ((data & 0200000) == 0)) {
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/* Handle public violation */
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fault_data = (((uint64)(page))<<18) | ((uint64)(uf) << 27) | 021LL;
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private_page = 1;
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// fprintf(stderr, " public");
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}
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if (cur_context && ((data & 0200000) != 0))
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FLAGS |= PUBLIC;
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@ -1073,7 +1072,6 @@ int page_lookup(int addr, int flag, int *loc, int wr, int cur_context) {
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fprintf(stderr, " fault\n\r");
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return 0;
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}
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// fprintf(stderr, "\n\r");
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return 1;
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}
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@ -1405,29 +1403,6 @@ no_fetch:
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}
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} while (ind & !pi_rq);
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/* Update history */
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if (hst_lnt && PC > 020 && (PC & 0777774) != 0472174 &&
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(PC & 0777700) != 023700 && (PC != 0527154)) {
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hst_p = hst_p + 1;
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if (hst_p >= hst_lnt) {
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hst_p = 0;
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// reason = STOP_IBKPT;
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}
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hst[hst_p].pc = HIST_PC | ((BYF5)? (HIST_PC2|PC) : PC);
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hst[hst_p].ea = AB;
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hst[hst_p].ir = AD;
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hst[hst_p].flags = (FLAGS << 5) |(clk_flg << 2) | (nxm_flag << 1)
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#if KA
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| (mem_prot << 4) | (push_ovf << 3)
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#endif
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;
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hst[hst_p].ac = get_reg(AC);
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}
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// /* Update final address into history. */
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// if (hst_lnt) {
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// hst[hst_p].ea = AB;
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// }
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/* If there is a interrupt handle it. */
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if (pi_rq) {
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set_pi_hold(); /* Hold off all lower interrupts */
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@ -1464,6 +1439,30 @@ no_fetch:
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#endif
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}
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/* Update history */
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#if KI
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if (hst_lnt && (fm_sel || PC > 020) && (PC & 0777774) != 0472174 &&
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(PC & 0777700) != 023700 && (PC != 0527154)) {
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#else
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if (hst_lnt && PC > 020 && (PC & 0777774) != 0472174 &&
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(PC & 0777700) != 023700 && (PC != 0527154)) {
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#endif
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hst_p = hst_p + 1;
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if (hst_p >= hst_lnt) {
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hst_p = 0;
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// reason = STOP_IBKPT;
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}
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hst[hst_p].pc = HIST_PC | ((BYF5)? (HIST_PC2|PC) : PC);
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hst[hst_p].ea = AB;
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hst[hst_p].ir = AD;
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hst[hst_p].flags = (FLAGS << 5) |(clk_flg << 2) | (nxm_flag << 1)
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#if KA
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| (mem_prot << 4) | (push_ovf << 3)
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#endif
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;
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hst[hst_p].ac = get_reg(AC);
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}
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fetch_opr:
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/* Set up to execute instruction */
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@ -55,7 +55,8 @@
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#endif
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#ifndef KI_22BIT
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#define KI_22BIT KI|KL
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//#define KI_22BIT KI|KL
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#define KI_22BIT 0
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#endif
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/* Digital Equipment Corporation's 36b family had six implementations:
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@ -211,13 +212,13 @@ extern DEBTAB crd_debug[];
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#define ICWA 0000000000776
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#if KI_22BIT
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#define AMASK 0000017777777LL
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#define WMASK 037777LL
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#define CSHIFT 22
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#define AMASK 00000017777777LL
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#define WMASK 00777760LL
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#define CSHIFT 22
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#else
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#define AMASK RMASK
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#define WMASK RMASK
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#define CSHIFT 18
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#define AMASK RMASK
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#define WMASK RMASK
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#define CSHIFT 18
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#endif
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#define API_MASK 0000000007
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@ -30,7 +30,7 @@ void df10_setirq(struct df10 *df) {
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void df10_writecw(struct df10 *df) {
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df->status |= 1 << df->ccw_comp;
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M[df->cia|1] = (((uint64)(df->ccw)) << CSHIFT) | ((uint64)df->cda);
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M[df->cia|1] = ((uint64)(df->ccw & WMASK) << CSHIFT) | ((uint64)df->cda & AMASK);
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}
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void df10_finish_op(struct df10 *df, int flags) {
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@ -75,43 +75,43 @@ int df10_fetch(struct df10 *df) {
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int df10_read(struct df10 *df) {
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uint64 data;
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if (df->wcr == 0) {
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if (!df10_fetch(df))
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return 0;
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if (!df10_fetch(df))
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return 0;
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}
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df->wcr = (df->wcr + 1) & WMASK;
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df->wcr = (uint32)((df->wcr + 1) & WMASK);
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if (df->cda != 0) {
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if (df->cda > MEMSIZE) {
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df10_finish_op(df, 1<<df->nxmerr);
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return 0;
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}
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df->cda = (uint32)((df->cda + 1) & AMASK);
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data = M[df->cda];
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} else {
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data = 0;
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}
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df->buf = data;
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if (df->wcr == 0) {
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if (df->cda > MEMSIZE) {
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df10_finish_op(df, 1<<df->nxmerr);
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return 0;
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}
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df->cda = (uint32)((df->cda + 1) & AMASK);
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data = M[df->cda];
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} else {
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data = 0;
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}
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df->buf = data;
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if (df->wcr == 0) {
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return df10_fetch(df);
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}
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return 1;
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}
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return 1;
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}
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int df10_write(struct df10 *df) {
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if (df->wcr == 0) {
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if (!df10_fetch(df))
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return 0;
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if (!df10_fetch(df))
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return 0;
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}
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df->wcr = (uint32)((df->wcr + 1) & WMASK);
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if (df->cda != 0) {
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if (df->cda > MEMSIZE) {
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if (df->cda > MEMSIZE) {
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df10_finish_op(df, 1<<df->nxmerr);
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return 0;
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}
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df->cda = (uint32)((df->cda + 1) & AMASK);
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M[df->cda] = df->buf;
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}
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df->cda = (uint32)((df->cda + 1) & AMASK);
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M[df->cda] = df->buf;
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}
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if (df->wcr == 0) {
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return df10_fetch(df);
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return df10_fetch(df);
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}
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return 1;
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}
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