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SEL32: Change print fields in debug statements to fixed length.

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This commit is contained in:
AZBevier 2019-09-19 11:27:53 -07:00
parent 55bbf0d915
commit c5b3e17c43
5 changed files with 289 additions and 228 deletions
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211
SEL32/sel32_chan.c
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@ -186,7 +186,8 @@ uint32 find_int_lev(uint16 chsa)
level = ((val >> 16) & 0x7f); /* 1's comp of int level */
level = 127 - level; /* get positive number level */
sim_debug(DEBUG_EXP, &cpu_dev,
"find_int_lev class F SPAD %x chan %x chsa %x level %x\n", val, chan, chsa, level);
"find_int_lev class F SPAD %08x chan %04x chsa %04x level %04x\n",
val, chan, chsa, level);
return(level); /* return the level*/
}
}
@ -199,7 +200,7 @@ uint32 find_int_lev(uint16 chsa)
level = ((val >> 16) & 0x7f); /* 1's comp of int level */
level = 127 - level; /* get positive number level */
sim_debug(DEBUG_EXP, &cpu_dev,
"find_int_lev E SPAD %x chan %x chsa %x level %x\n", val, chan, chsa, level);
"find_int_lev E SPAD %08x chan %04x chsa %04x level %04x\n", val, chan, chsa, level);
return(level); /* return the level*/
}
}
@ -296,12 +297,12 @@ int readfull(CHANP *chp, uint32 maddr, uint32 *word)
maddr &= MASK24; /* mask addr to 24 bits */
if (maddr > (MEMSIZE*4)) { /* see if mem addr > MEMSIZE */
chp->chan_status |= STATUS_PCHK; /* program check error */
sim_debug(DEBUG_EXP, &cpu_dev, "readfull read %x from addr %x ERROR\n", *word, maddr<<2);
sim_debug(DEBUG_EXP, &cpu_dev, "readfull read %08x from addr %08x ERROR\n", *word, maddr<<2);
return 1; /* show we have error */
}
maddr >>= 2; /* get 32 bit word index */
*word = M[maddr]; /* get the contents */
sim_debug(DEBUG_EXP, &cpu_dev, "readfull read %x from addr %x\n", *word, maddr<<2);
sim_debug(DEBUG_EXP, &cpu_dev, "readfull read %08x from addr %08x\n", *word, maddr<<2);
return 0; /* return OK */
}
@ -347,13 +348,13 @@ int writebuff(CHANP *chp)
if ((addr & MASK24) > (MEMSIZE*4)) {
chp->chan_status |= STATUS_PCHK;
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff PCHK addr %x to big mem %x status %x\n", addr, MEMSIZE, chp->chan_status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff PCHK addr %08x to big mem %08x status %04x\n", addr, MEMSIZE, chp->chan_status);
chp->chan_byte = BUFF_CHNEND;
irq_pend = 1;
return 1;
}
addr &= MASK24;
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff WRITE addr %x MEMSIZE %x status %x\n", addr, MEMSIZE, chp->chan_status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "writebuff WRITE addr %08x MEMSIZE %08x status %04x\n", addr, MEMSIZE, chp->chan_status);
M[addr>>2] = chp->chan_buf;
return 0;
}
@ -370,10 +371,10 @@ int load_ccw(CHANP *chp, int tic_ok)
CHANP *pchp;
loop:
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw entry chan_status[%x] %x\n", chan, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw entry chan_status[%04x] %04x\n", chan, chp->chan_status);
/* Abort if we have any errors */
if (chp->chan_status & 0x3f03) { /* check channel status */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%x] %x\n", chan, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
return 1;
}
@ -386,7 +387,7 @@ loop:
/* Read in first or next CCW */
if (readfull(chp, chp->chan_caw, &word) != 0) { /* read word from memory */
chp->chan_status |= STATUS_PCHK; /* memory read error, program check */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%x] %x\n", chan, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
return 1; /* error return */
}
@ -401,7 +402,7 @@ loop:
goto loop; /* restart the IOCD processing */
}
chp->chan_status |= STATUS_PCHK; /* program check for invalid tic */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%x] %x\n", chan, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw ERROR chan_status[%04x] %04x\n", chan, chp->chan_status);
irq_pend = 1; /* status pending */
return 1; /* error return */
}
@ -410,7 +411,7 @@ loop:
/* Check if not chaining data */
if ((chp->ccw_flags & FLAG_DC) == 0) {
chp->ccw_cmd = (word >> 24) & 0xff; /* not DC, so set command from IOCD wd 1 */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw No DC, flags %x cmd %x\n", chp->ccw_flags, chp->ccw_cmd);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw No DC, flags %04x cmd %02x\n", chp->ccw_flags, chp->ccw_cmd);
docmd = 1; /* show we have a command */
}
/* Set up for this command */
@ -429,7 +430,8 @@ loop:
irq_pend = 1; /* interrupt pending */
}
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw read docmd %x irq_flag %x count %x chan %x ccw_flags %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"load_ccw read docmd %02x irq_flag %04x count %04x chan %04x ccw_flags %04x\n",
docmd, irq_pend, chp->ccw_count, chan, chp->ccw_flags);
/* LPR sends CC cmd only without data addr/count */
#ifdef HACK_FOR_LPR
@ -459,17 +461,18 @@ loop:
/*052619*/ chp->chan_inch_addr = uptr->u4; /* save INCH buffer address */
pchp = find_chanp_ptr(chp->chan_dev&0x7f00); /* get parent channel prog pointer */
/*091119*/ pchp->chan_inch_addr = uptr->u4; /* save INCH buffer address */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH buffer save %x chan %0x status %.8x count %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"load_ccw INCH buffer save %08x chan %04x status %04x count %04x\n",
uptr->u4, chan, chp->chan_status, chp->ccw_count);
}
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw before start_cmd chan %0x status %.8x count %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw before start_cmd chan %04x status %04x count %04x\n",
chan, chp->chan_status, chp->ccw_count);
/* call the device startcmd function to process command */
chp->chan_status = dibp->start_cmd(uptr, chan, chp->ccw_cmd);
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw after start_cmd chan %0x status %.8x count %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw after start_cmd chan %04x status %08x count %04x\n",
chan, chp->chan_status, chp->ccw_count);
/* see if bad status */
@ -478,7 +481,7 @@ loop:
chp->ccw_flags = 0; /* no flags */
chp->ccw_cmd = 0; /* stop IOCD processing */
irq_pend = 1; /* int coming */
sim_debug(DEBUG_CMD, &cpu_dev, "load_ccw bad status chan %0x status %.8x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "load_ccw bad status chan %04x status %04x\n",
chan, chp->chan_status);
return 1; /* error return */
}
@ -492,7 +495,7 @@ loop:
pchp = find_chanp_ptr(chp->chan_dev&0x7f00); /* get parent channel prog pointer */
pchp->chan_inch_addr = uptr->u4; /* save INCH buffer address */
chp->chan_status &= STATUS_DEND; /* inch has only channel end status */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH %x saved chan %0x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw INCH %08x saved chan %04x\n",
chp->chan_inch_addr, chan);
}
#endif
@ -503,11 +506,11 @@ loop:
chp->chan_byte = BUFF_NEWCMD; /* ready for new cmd */
chp->ccw_cmd = 0; /* stop IOCD processing */
irq_pend = 1; /* int coming */
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw cmd complete chan %0x status %.8x count %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw cmd complete chan %04x status %04x count %04x\n",
chan, chp->chan_status, chp->ccw_count);
}
}
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw return, chan %0x status %.8x count %x irq %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "load_ccw return, chan %04x status %04x count %04x irq %02x\n",
chan, chp->chan_status, chp->ccw_count, irq_pend);
return 0; /* good return */
}
@ -530,11 +533,11 @@ int chan_read_byte(uint16 chsa, uint8 *data)
if ((chp->ccw_flags & FLAG_DC) == 0) { /* see if Data Chain */
chp->chan_status |= STATUS_CEND; /* no, end of data */
chp->chan_byte = BUFF_CHNEND; /* buffer end too */
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte end status %x\n", chp->chan_status);
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte end status %04x\n", chp->chan_status);
return 1; /* return error */
} else {
/* we have data chaining, process iocl */
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte calling load_ccw chan %x\n", chan);
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte calling load_ccw chan %04x\n", chan);
if (load_ccw(chp, 1)) /* process data chaining */
return 1; /* return error */
}
@ -550,7 +553,7 @@ int chan_read_byte(uint16 chsa, uint8 *data)
byte = (chp->chan_buf >> (8 * (3 - (chp->chan_byte & 0x3)))) & 0xff;
chp->chan_byte++; /* next byte offset in word */
*data = byte; /* return the data */
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte transferred %x\n", byte);
sim_debug(DEBUG_DATA, &cpu_dev, "chan_read_byte transferred %02x\n", byte);
return 0; /* good return */
}
@ -600,7 +603,7 @@ int chan_write_byte(uint16 chsa, uint8 *data)
return 1; /* return error */
}
if (chp->ccw_count == 0) {
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte ccw_count is zero ccw_count[%x] %x\n",
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte ccw_count is zero ccw_count[%04x] %04x\n",
chan, chp->ccw_count);
if (chp->chan_byte & BUFF_DIRTY) {
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte 2 BUF DIRTY ret\n");
@ -614,12 +617,12 @@ int chan_write_byte(uint16 chsa, uint8 *data)
return 1; /* return error */
} else {
/* we have data chaining, process iocl */
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte calling load_ccw chan %x\n", chan);
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte calling load_ccw chan %04x\n", chan);
if (load_ccw(chp, 1)) /* process data chaining */
return 1; /* return error */
}
}
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte non zero ccw_count[%x]=%x\n", chan, chp->ccw_count);
sim_debug(DEBUG_DATA, &cpu_dev, "chan_write_byte non zero ccw_count[%04x]=%04x\n", chan, chp->ccw_count);
if (chp->ccw_flags & FLAG_SKIP) {
chp->ccw_count--;
chp->chan_byte = BUFF_EMPTY;
@ -627,7 +630,8 @@ int chan_write_byte(uint16 chsa, uint8 *data)
chp->ccw_addr--;
else
chp->ccw_addr++;
sim_debug(DEBUG_CMD, &cpu_dev, "chan_write_byte SKIP ret addr %x cnt %x\n", chp->ccw_addr, chp->ccw_count);
sim_debug(DEBUG_CMD, &cpu_dev, "chan_write_byte SKIP ret addr %08x cnt %04x\n",
chp->ccw_addr, chp->ccw_count);
return 0;
}
if (chp->chan_byte == (BUFF_EMPTY|BUFF_DIRTY)) {
@ -668,7 +672,7 @@ void set_devwake(uint16 chsa, uint16 flags)
/* save 16 bit channel status and residual byte count in SW 2 */
stwd2 = (uint32)flags << 16;
if ((FIFO_Put(chsa, stwd1) == -1) || (FIFO_Put(chsa, stwd2) == -1)) {
fprintf(stderr, "FIFO Overflow ERROR on chsa %x\r\n", chsa);
fprintf(stderr, "FIFO Overflow ERROR on chsa %04x\r\n", chsa);
}
irq_pend = 1; /* wakeup controller */
}
@ -679,13 +683,13 @@ void set_devattn(uint16 chsa, uint16 flags)
int chan = get_chan(chsa); /* get the channel number */
CHANP *chp = find_chanp_ptr(chsa); /* get channel prog pointer */
sim_debug(DEBUG_EXP, &cpu_dev, "set_devattn chsa %x, flags %x\n", chsa, flags);
sim_debug(DEBUG_EXP, &cpu_dev, "set_devattn chsa %04x, flags %04x\n", chsa, flags);
if (chp->chan_dev == chsa && (chp->chan_status & STATUS_CEND) != 0 && (flags & SNS_DEVEND) != 0) {
chp->chan_status |= ((uint16)flags);
} else
dev_status[chsa] = flags; /* save device status flags */
sim_debug(DEBUG_CMD, &cpu_dev, "set_devattn(%x, %x) %x\n", chsa, flags, chp->chan_dev);
sim_debug(DEBUG_CMD, &cpu_dev, "set_devattn(%04x, %04x) %04x\n", chsa, flags, chp->chan_dev);
irq_pend = 1;
}
@ -695,7 +699,8 @@ void chan_end(uint16 chsa, uint16 flags) {
uint32 chan_icb = find_int_icb(chsa); /* get icb address */
CHANP *chp = find_chanp_ptr(chsa); /* get channel prog pointer */
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end entry chsa %x flags %x ccw_flags %x status %x\n", chsa, flags, chp->ccw_flags, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end entry chsa %04x flags %04x ccw_flags %04x status %04x\n",
chsa, flags, chp->ccw_flags, chp->chan_status);
if (chp->chan_byte & BUFF_DIRTY) {
if (writebuff(chp)) /* write remaining data */
return; /* error */
@ -705,7 +710,7 @@ void chan_end(uint16 chsa, uint16 flags) {
chp->chan_status |= ((uint16)flags); /* add in the callers flags */
// chp->ccw_cmd = 0; /* reset the completed channel command */
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %x ccw_flags %x count %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %04x ccw_flags %04x count %04x status %04x\n",
chsa, chp->ccw_flags, chp->ccw_count, chp->chan_status);
#ifdef HACK_HACK
/* hack - rewind had byte count of 1, so triggered this error when it is not */
@ -725,14 +730,15 @@ void chan_end(uint16 chsa, uint16 flags) {
}
}
#endif
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %x ccw_flags %x status %x\n", chsa, chp->ccw_flags, chp->chan_status);
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end SLI test chsa %04x ccw_flags %04x status %04x\n",
chsa, chp->ccw_flags, chp->chan_status);
chp->ccw_cmd = 0; /* reset the completed channel command */
/* no flags for attention status */
if (flags & (SNS_ATTN|SNS_UNITCHK|SNS_UNITEXP)) {
chp->ccw_flags = 0; /* no flags */
}
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end test end chsa %x, flags %x\n", chsa, flags);
sim_debug(DEBUG_EXP, &cpu_dev, "chan_end test end chsa %04x, flags %04x\n", chsa, flags);
/* test for device or controller end */
if (chp->chan_status & (STATUS_DEND|STATUS_CEND)) {
chp->chan_byte = BUFF_NEWCMD; /* clear byte flag */
@ -761,9 +767,9 @@ void store_csw(CHANP *chp)
/* save 16 bit channel status and residual byte count in SW 2 */
stwd2 = ((uint32)chp->chan_status << 16) | ((uint32)chp->ccw_count);
if ((FIFO_Put(chsa, stwd1) == -1) || (FIFO_Put(chsa, stwd2) == -1)) {
fprintf(stderr, "FIFO Overflow ERROR on chsa %x\r\n", chsa);
fprintf(stderr, "FIFO Overflow ERROR on chsa %04x\r\n", chsa);
}
sim_debug(DEBUG_CMD, &cpu_dev, "store_csw on chsa %x sw1 %x sw2 %x\r\n", chsa, stwd1, stwd2);
sim_debug(DEBUG_CMD, &cpu_dev, "store_csw on chsa %04x sw1 %08x sw2 %08x\r\n", chsa, stwd1, stwd2);
chp->chan_status = 0; /* no status anymore */
irq_pend = 1; /* wakeup controller */
}
@ -809,37 +815,38 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio 1 chsa %x chan %x loc 0 %x\n", chsa, chan, M[0]);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio 1 chsa %04x chan %04x loc 0 %08x\n", chsa, chan, M[0]);
if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */
*status = CC3BIT; /* not found, so CC3 */
return SCPE_OK; /* not found, CC3 */
}
sim_debug(DEBUG_CMD, &cpu_dev, "startxio 2 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio 2 chsa %04x chan %04x\n", chsa, chan);
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
fprintf(stderr, "startxio chsa %x is not attached, error return\r\n", chsa);
fprintf(stderr, "startxio chsa %04x is not attached, error return\r\n", chsa);
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
/* see if interrupt is setup in SPAD and determine IVL for channel */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio dev spad %.8x chsa %x chan %x\n", spadent, chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio dev spad %08x chsa %04x chan %04x\n", spadent, chsa, chan);
inta = ((spadent & 0x007f0000) >> 16); /* 1's complement of chan int level */
inta = 127 - inta; /* get positive int level */
spadent = SPAD[inta + 0x80]; /* get interrupt spad entry */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio int spad %.8x inta %x chan %x\n", spadent, inta, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio int spad %08x inta %04x chan %04x\n", spadent, inta, chan);
/* get the address of the interrupt IVL in main memory */
chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */
chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio busy test chsa %0x chan %x cmd %x iocla %x flags %x IOCD1 %x IOCD2 %x\n",
sim_debug(DEBUG_CMD, &cpu_dev,
"startxio busy test chsa %04x chan %04x cmd %02x iocla %08x flags %04x IOCD1 %08x IOCD2 %08x\n",
chsa, chan, chp->ccw_cmd, iocla, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO %x %x cmd %x flags %x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO %04x %04x cmd %02x flags %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags);
/* check for a Command or data chain operation in progresss */
if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
sim_debug(DEBUG_CMD, &cpu_dev, "startxio busy return CC4 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
*status = CC4BIT; /* busy, so CC4 */
return SCPE_OK; /* just busy CC4 */
}
@ -850,7 +857,7 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
tempa = dibp->pre_io(uptr, chan); /* get status from device */
if (tempa != 0) { /* see if sub channel status is ready */
/* The device must be busy or something, but it is not ready. Return busy */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio start_io call return busy chan %x cstat %08x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "startxio start_io call return busy chan %04x cstat %08x\n",
chan, tempa);
chp->chan_status = 0; /* no status anymore */
*status = CC3BIT|CC4BIT; /* sub channel busy, so CC3|CC4 */
@ -872,16 +879,17 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
}
#endif
sim_debug(DEBUG_CMD, &cpu_dev, "@ startxio 4 chsa %x chan %x iocla %x tempa %x loc 0=%x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "@ startxio 4 chsa %04x chan %04x iocla %08x tempa %08x loc 0=%08x\n",
chsa, chan, iocla, tempa, M[0]);
sim_debug(DEBUG_CMD, &cpu_dev, "$$ SIO starting IOCL processing chsa %02x iocla %x\n", chsa, iocla);
sim_debug(DEBUG_CMD, &cpu_dev, "$$ SIO starting IOCL processing chsa %04x iocla %08x\n", chsa, iocla);
/* start processing the IOCL */
if (load_ccw(chp, 0) || (chp->chan_status & STATUS_PCI)) {
/* we have an error or user requested interrupt, return status */
store_csw(chp); /* store the status in the inch status dw */
sim_debug(DEBUG_CMD, &cpu_dev, "startxio store csw CC1 chan %02x status %08x\n", chan, chp->chan_status);
sim_debug(DEBUG_CMD, &cpu_dev, "startxio store csw CC1 chan %04x status %08x\n",
chan, chp->chan_status);
chp->chan_status &= ~STATUS_PCI; /* remove PCI status bit */
dev_status[chsa] = 0; /* no device status */
*status = CC1BIT; /* status stored, so CC1 */
@ -889,7 +897,7 @@ t_stat startxio(uint16 lchsa, uint32 *status) {
}
*status = CC1BIT; /* CCs = 1, SIO accepted & queued, will not echo status */
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO done chsa %x status %08x iocla %x M[0] %x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ SIO done chsa %04x status %08x iocla %08x M[0] %08x\n",
chsa, chp->chan_status, iocla, M[0]);
return SCPE_OK; /* No CC's all OK */
}
@ -917,38 +925,40 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
pchp = find_chanp_ptr(chsa & 0x7f00); /* find the channel chanp pointer */
sim_debug(DEBUG_CMD, &cpu_dev, "testxio 1 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio 1 chsa %04x chan %04x\n", chsa, chan);
if ((dibp == 0) || (uptr == 0)) { /* if non found, CC3 on return */
*status = CC3BIT; /* not found, so CC3 */
goto tioret; /* not found, CC3 */
}
sim_debug(DEBUG_CMD, &cpu_dev, "testxio 2 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio 2 chsa %04x chan %04x\n", chsa, chan);
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
*status = CC3BIT; /* not attached, so error CC3 */
goto tioret; /* not found, CC3 */
}
/* see if interrupt is setup in SPAD and determine IVL for channel */
sim_debug(DEBUG_CMD, &cpu_dev, "testxio dev spad %.8x chsa %x chan %x\n", spadent, chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio dev spad %08x chsa %04x chan %04x\n", spadent, chsa, chan);
/* the startio opcode processing software has already checked for F class */
inta = ((spadent & 0x007f0000) >> 16); /* 1's complement of chan int level */
inta = 127 - inta; /* get positive int level */
spadent = SPAD[inta + 0x80]; /* get interrupt spad entry */
sim_debug(DEBUG_CMD, &cpu_dev, "testxio int spad %.8x inta %x chan %x\n", spadent, inta, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio int spad %08x inta %04x chan %04x\n", spadent, inta, chan);
/* get the address of the interrupt IVL in main memory */
chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */
chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */
sim_debug(DEBUG_CMD, &cpu_dev, "testxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x IOCLA %x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2], iocla);
sim_debug(DEBUG_CMD, &cpu_dev,
"testxio busy test chsa %04x chan %04x cmd %02x flags %04x IOCD1 %08x IOCD2 %08x IOCLA %08x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2], iocla);
sim_debug(DEBUG_CMD, &cpu_dev, "$$ TIO chsa %x chan %x cmd %x flags %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags);
sim_debug(DEBUG_CMD, &cpu_dev, "$$ TIO chsa %04x chan %04x cmd %02x flags %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags);
/* check for a Command or data chain operation in progresss */
if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
sim_debug(DEBUG_CMD, &cpu_dev, "testxio busy return CC4 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
*status = CC4BIT; /* busy, so CC4 */
goto tioret; /* just busy CC4 */
}
@ -956,7 +966,7 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
if ((FIFO_Get(chsa, &sw1) == 0) && (FIFO_Get(chsa, &sw2) == 0)) {
uint32 chan_icb = find_int_icb(chsa); /* get icb address */
sim_debug(DEBUG_CMD, &cpu_dev, "testxio status stored OK, sw1 %x sw2 %x\n", sw1, sw2);
sim_debug(DEBUG_CMD, &cpu_dev, "testxio status stored OK, sw1 %08x sw2 %08x\n", sw1, sw2);
/* we have status to return, do it now */
tempa = pchp->chan_inch_addr; /* get inch status buffer address */
M[tempa >> 2] = sw1; /* save sa & IOCD address in status WD 1 loc */
@ -970,9 +980,10 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */
/* nothing going on, so say all OK */
*status = CC1BIT; /* request accepted, no status, so CC1 */
tioret:
// fprintf(stderr, "$$$ TIO END chsa %x chan %x cmd %x flags %x chan_stat %x CCs %x\n",
// fprintf(stderr, "$$$ TIO END chsa %04x chan %04x cmd %02x flags %04x chan_stat %04x CCs %08x\n",
// chsa, chan, chp->ccw_cmd, chp->ccw_flags, chp->chan_status, *status);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ TIO END chsa %x chan %x cmd %x flags %x chan_stat %x CCs %x\n",
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ TIO END chsa %04x chan %04x cmd %02x flags %04x chan_stat %04x CCs %08x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, chp->chan_status, *status);
return SCPE_OK; /* No CC's all OK */
}
@ -996,37 +1007,39 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio 1 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio 1 chsa %04x chan %04x\n", chsa, chan);
if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */
*status = CC3BIT; /* not found, so CC3 */
return SCPE_OK; /* not found, CC3 */
}
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio 2 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio 2 chsa %04x chan %04x\n", chsa, chan);
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
/* see if interrupt is setup in SPAD and determine IVL for channel */
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio dev spad %.8x chsa %x chan %x\n", spadent, chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio dev spad %08x chsa %04x chan %04x\n", spadent, chsa, chan);
/* the startio opcode processing software has already checked for F class */
inta = ((spadent & 0x007f0000) >> 16); /* 1's complement of chan int level */
inta = 127 - inta; /* get positive int level */
spadent = SPAD[inta + 0x80]; /* get interrupt spad entry */
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio int spad %.8x inta %x chan %x\n", spadent, inta, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio int spad %08x inta %08x chan %04x\n", spadent, inta, chan);
/* get the address of the interrupt IVL in main memory */
chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */
chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x\n",
sim_debug(DEBUG_CMD, &cpu_dev,
"stopxio busy test chsa %04x chan %04x cmd %02x flags %04x IOCD1 %08x IOCD2 %08x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ STOPIO %x %x %x %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ STOPIO %04x %04x %02x %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags);
/* check for a Command or data chain operation in progresss */
if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio busy return CC4 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "stopxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
/* reset the DC or CC bits to force completion after current IOCD */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
dev_status[chsa] |= STATUS_ECHO; /* show we stopped the cmd */
@ -1035,7 +1048,8 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */
}
/* the channel is not busy, so return OK */
*status = 0; /* CCs = 0, accepted */
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ STOPIO good return chsa %x chan %x cmd %x flags %x status %x\n",
sim_debug(DEBUG_CMD, &cpu_dev,
"$$$ STOPIO good return chsa %04x chan %04x cmd %02x flags %04x status %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, *status);
return SCPE_OK; /* No CC's all OK */
}
@ -1058,12 +1072,12 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio 1 chan %x SPAD %x\n", chsa, spadent);
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio 1 chan %04x SPAD %08x\n", chsa, spadent);
if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */
*status = CC3BIT; /* not found, so CC3 */
return SCPE_OK; /* not found, CC3 */
}
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio 2 chan %x, spad %x\r\n", chsa, spadent);
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio 2 chan %04x, spad %08x\r\n", chsa, spadent);
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
@ -1099,7 +1113,7 @@ t_stat rschnlxio(uint16 lchsa, uint32 *status) { /* reset channel XIO */
chp->ccw_flags = 0; /* clear flags */
chp->ccw_cmd = 0; /* read command */
}
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio return CC1 chan %x lev %x\n", chan, lev);
sim_debug(DEBUG_CMD, &cpu_dev, "rschnlxio return CC1 chan %04x lev %04x\n", chan, lev);
*status = CC1BIT; /* request accepted, no status, so CC1 TRY THIS */
return SCPE_OK; /* All OK */
}
@ -1123,37 +1137,39 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
uptr = find_unit_ptr(chsa); /* find pointer to unit on channel */
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio 1 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio 1 chsa %04x chan %04x\n", chsa, chan);
if (dibp == 0 || uptr == 0) { /* if no dib or unit ptr, CC3 on return */
*status = CC3BIT; /* not found, so CC3 */
return SCPE_OK; /* not found, CC3 */
}
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio 2 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio 2 chsa %04x chan %04x\n", chsa, chan);
if ((uptr->flags & UNIT_ATTABLE) && ((uptr->flags & UNIT_ATT) == 0)) { /* is unit attached? */
*status = CC3BIT; /* not attached, so error CC3 */
return SCPE_OK; /* not found, CC3 */
}
/* see if interrupt is setup in SPAD and determine IVL for channel */
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio dev spad %.8x chsa %x chan %x\n", spadent, chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio dev spad %08x chsa %04x chan %04x\n", spadent, chsa, chan);
/* the startio opcode processing software has already checked for F class */
inta = ((spadent & 0x007f0000) >> 16); /* 1's complement of chan int level */
inta = 127 - inta; /* get positive int level */
spadent = SPAD[inta + 0x80]; /* get interrupt spad entry */
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio int spad %.8x inta %x chan %x\n", spadent, inta, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio int spad %08x inta %08x chan %04x\n", spadent, inta, chan);
/* get the address of the interrupt IVL in main memory */
chan_ivl = SPAD[0xf1] + (inta<<2); /* contents of spad f1 points to chan ivl in mem */
chan_ivl = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
iocla = M[(chan_ivl+16)>>2]; /* iocla is in wd 4 of ICB */
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio busy test chsa %0x chan %x cmd %x flags %x IOCD1 %x IOCD2 %x\n",
sim_debug(DEBUG_CMD, &cpu_dev,
"haltxio busy test chsa %04x chan %04x cmd %02x flags %04x IOCD1 %8x IOCD2 %08x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ HIO %x %x %x %x\n", chsa, chan, chp->ccw_cmd, chp->ccw_flags);
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ HIO %04x %04x %02x %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags);
/* check for a Command or data chain operation in progresss */
if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio busy return CC4 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "haltxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
/* reset the DC or CC bits to force completion after current IOCD */
chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */
dev_status[chsa] |= STATUS_ECHO; /* show we stopped the cmd */
@ -1163,7 +1179,7 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */
/* the channel is not busy, so return OK */
*status = CC2BIT; /* INCH status stored, so CC2 TRY */
hioret:
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ HIO END chsa %x chan %x cmd %x flags %x status %x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "$$$ HIO END chsa %04x chan %04x cmd %02x flags %04x status %04x\n",
chsa, chan, chp->ccw_cmd, chp->ccw_flags, *status);
return SCPE_OK; /* No CC's all OK */
}
@ -1184,12 +1200,12 @@ t_stat grabxio(uint16 lchsa, uint32 *status) { /* grab controller XIO n/u
/* check for a Command or data chain operation in progresss */
if (chp->ccw_cmd != 0 || (chp->ccw_flags & (FLAG_DC|FLAG_CC)) != 0) {
sim_debug(DEBUG_CMD, &cpu_dev, "grabxio busy return CC4 chsa %x chan %x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "grabxio busy return CC4 chsa %04x chan %04x\n", chsa, chan);
*status = CC4BIT; /* busy, so CC4 */
return SCPE_OK; /* CC4 all OK */
}
*status = 0; /* not busy, no CC */
sim_debug(DEBUG_CMD, &cpu_dev, "grabxio chsa %x chan %08x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "grabxio chsa %04x chan %04x\n", chsa, chan);
return 0;
}
@ -1207,7 +1223,7 @@ t_stat rsctlxio(uint16 lchsa, uint32 *status) { /* reset controller XIO */
chp = find_chanp_ptr(chsa); /* find the chanp pointer */
*status = 0; /* not busy, no CC */
sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio chsa %x chan %08x\n", chsa, chan);
sim_debug(DEBUG_CMD, &cpu_dev, "rsctlxio chsa %04x chan %04x\n", chsa, chan);
return 0;
}
@ -1218,7 +1234,7 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr) {
DIB *dibp = dev_unit[chsa];
CHANP *chp = dibp->chan_prg;
sim_debug(DEBUG_EXP, &cpu_dev, "Channel Boot chan/device addr %x\n", chsa);
sim_debug(DEBUG_EXP, &cpu_dev, "Channel Boot chan/device addr %04x\n", chsa);
if (dibp == 0) /* if no channel or device, error */
return SCPE_IOERR; /* error */
if (dibp->chan_prg == NULL) /* must have channel information for each device */
@ -1236,18 +1252,18 @@ t_stat chan_boot(uint16 chsa, DEVICE *dptr) {
chp->ccw_flags = 0; /* Command chain and supress incorrect length */
chp->ccw_cmd = 0; /* read command */
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot calling load_ccw chan %02x status %08x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot calling load_ccw chan %04x status %08x\n",
chan, chp->chan_status);
/* start processing the boot IOCL at loc 0 */
if (load_ccw(chp, 0)) { /* load IOCL starting from location 0 */
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot Error return from load_ccw chan %02x status %08x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot Error return from load_ccw chan %04x status %08x\n",
chan, chp->chan_status);
dev_status[chsa] = 0; /* no device status */
chp->ccw_flags = 0; /* clear the command flags */
return SCPE_IOERR; /* return error */
}
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot OK return from load_ccw chsa %02x status %08x\n",
sim_debug(DEBUG_CMD, &cpu_dev, "Channel Boot OK return from load_ccw chsa %04x status %04x\n",
chsa, chp->chan_status);
loading = chsa; /* show we are loading from the boot device */
return SCPE_OK; /* all OK */
@ -1303,8 +1319,9 @@ uint32 scan_chan(void) {
/* now store the status dw address into word 5 of the ICB for the channel */
M[(chan_icba + 20) >> 2] = tempa | BIT1; /* post sw addr in ICB+5w & set CC2 in SW */
INTS[i] |= INTS_REQ; /* turn on channel interrupt request */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan %x FIFO read, set INTS REQ irq %x inch %x chan_icba %x sw1 %x sw2 %x\n",
chan, i, tempa, chan_icba, sw1, sw2);
sim_debug(DEBUG_EXP, &cpu_dev,
"scan_chan %04x FIFO read, set INTS REQ irq %04x inch %08x chan_icba %08x sw1 %08x sw2 %08x\n",
chan, i, tempa, chan_icba, sw1, sw2);
}
}
}
@ -1323,7 +1340,7 @@ uint32 scan_chan(void) {
/* get the address of the interrupt IVL table in main memory */
chan_ivl = SPAD[0xf1] + (i<<2); /* contents of spad f1 points to chan ivl in mem */
chan_icba = M[chan_ivl >> 2]; /* get the interrupt context block addr in memory */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan INTS REQ irq %x found chan_icba %x INTS %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan INTS REQ irq %04x found chan_icba %8x INTS %0x\n",
i, chan_icba, INTS[i]);
return(chan_icba); /* return ICB address */
}
@ -1336,7 +1353,7 @@ uint32 scan_chan(void) {
/* loop through all the channels/units for channel with pending I/O completion */
for (i = 0; sim_devices[i] != NULL; i++) {
DEVICE *dptr = sim_devices[i]; /* get pointer to configured device */
DIB *dibp = (DIB *)dptr->ctxt; /* get pointer to Device Information Block for this device */
DIB *dibp = (DIB *)dptr->ctxt; /* get pointer to DIB for this device */
UNIT *uptr = dptr->units; /* get pointer to units defined for this device */
if (dibp == NULL) /* If no DIB, not channel device */
@ -1352,14 +1369,17 @@ uint32 scan_chan(void) {
/* If channel end, check if we should continue */
if (chp->chan_status & STATUS_CEND) { /* do we have channel end */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end chsa %x flags %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"scan_chan loading %02x chan end chsa %04x flags %04x status %04x\n",
loading, chsa, chp->ccw_flags, chp->chan_status);
if (chp->ccw_flags & FLAG_CC) { /* command chain flag */
/* we have channel end and CC flag, continue channel prog */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & CC chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"scan_chan loading %02x chan end & CC chsa %04x status %04x\n",
loading, chsa, chp->chan_status);
if (chp->chan_status & STATUS_DEND) { /* device end? */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x dev end & CC chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"scan_chan loading %02x dev end & CC chsa %04x status %04x\n",
loading, chsa, chp->chan_status);
(void)load_ccw(chp, 1); /* go load the next IOCB */
} else
@ -1367,7 +1387,8 @@ uint32 scan_chan(void) {
} else {
/* we have channel end and no CC flag, end command */
chsa = chp->chan_dev; /* get the chan/sa */
sim_debug(DEBUG_EXP, &cpu_dev, "scan_chan loading %x chan end & no CC chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"scan_chan loading %02x chan end & no CC chsa %04x status %04x\n",
loading, chsa, chp->chan_status);
dev_status[chsa] = 0; /* no device status anymore */
/* handle case where we are loading the O/S on boot */
@ -1505,14 +1526,14 @@ t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc) {
dev_unit[devaddr] = dibp;
uptr->u3 &= ~UNIT_ADDR(0x7ff);
uptr->u3 |= UNIT_ADDR(devaddr);
fprintf(stderr, "Set dev %x\r\n", GET_UADDR(uptr->u3));
fprintf(stderr, "Set dev %04x\r\n", GET_UADDR(uptr->u3));
} else {
for (i = 0; i < dibp->numunits; i++) {
dev_unit[devaddr + i] = dibp;
uptr = &((dibp->units)[i]);
uptr->u3 &= ~UNIT_ADDR(0x7ff);
uptr->u3 |= UNIT_ADDR(devaddr + i);
fprintf(stderr, "Set dev %x\r\n", GET_UADDR(uptr->u3));
fprintf(stderr, "Set dev %04x\r\n", GET_UADDR(uptr->u3));
}
}
return r;

89
SEL32/sel32_com.c
View File

@ -394,12 +394,12 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
return SNS_BSY; /* yes, return busy */
}
sim_debug(DEBUG_CMD, &com_dev, "CMD unit %x chan %x cmd %x", unit, chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "CMD unit %04x chan %04x cmd %02x", unit, chan, cmd);
/* process the commands */
switch (cmd & 0xFF) {
case COM_INCH: /* 00 */ /* INCH command */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: CMD INCH\n", chan);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: CMD INCH\n", chan);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (0x7f & COM_MSK); /* save 0x7f as INCH cmd command */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
@ -411,7 +411,7 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case COM_WR: /* 0x01 */ /* Write command */
case COM_WRSCM: /* 0x05 */ /* Write w/sub channel monitor */
case COM_WRHFC: /* 0x0D */ /* Write w/hardware flow control */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd WRITE %x\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd WRITE %02x\n", chan, cmd);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & COM_MSK); /* save command */
@ -433,19 +433,19 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
/* if bit 0 set for COM_RDFC, use DTR for flow, else use RTS for flow control */
case COM_RDFC: /* 0x0A */ /* Read command w/flow control */
case COM_RDHFC: /* 0x8E */ /* Read command w/hardware flow control only */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd read\n", chan);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd read\n", chan);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & COM_MSK); /* save command */
if ((cmd & 0x06) == COM_RDECHO) /* echo command? */
uptr->u3 |= COM_EKO; /* save echo status */
uptr->u3 |= COM_READ; /* show read mode */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: input cnt = %x\n", chan, coml_chp[unit].ccw_count);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: input cnt = %04x\n", chan, coml_chp[unit].ccw_count);
return 0;
break;
case COM_NOP: /* 0x03 */ /* NOP has do nothing */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x NOP\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x NOP\n", chan, cmd);
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & COM_MSK); /* save command */
@ -458,7 +458,7 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
com_lstat[unit][1] = 0; /* Clear status wd 1 */
/* value 4 is Data Set Ready */
/* value 5 is Data carrier detected n/u */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: unit %x Cmd Sense %02x\n", chan, unit, uptr->u5);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: unit %04x Cmd Sense %02x\n", chan, unit, uptr->u5);
/* Sense byte 0 */
//#define SNS_CMDREJ 0x80000000 /* Command reject */
//#define SNS_INTVENT 0x40000000 /* Unit intervention required (N/U) */
@ -522,50 +522,50 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
ch = (com_lstat[unit][1] >> 0) & 0xff;
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
sim_debug(DEBUG_CMD, &com_dev,
"com_startcmd Cmd SENSE return chan %x u5-status %x ls0 %x ls1 %x\n",
"com_startcmd Cmd SENSE return chan %04x u5-status %04x ls0 %08x ls1 %08x\n",
chan, uptr->u5, com_lstat[unit][0], com_lstat[unit][1]);
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_DEFSC: /* 0x0B */ /* Define special char */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x DEFSC\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x DEFSC\n", chan, cmd);
chan_read_byte(GET_UADDR(uptr->u3), &ch); /* read char */
uptr->u5 = ~SNS_RTS; /* Request to send not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_RRTS: /* 0x1B */ /* Reset RTS */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x RRTS\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x RRTS\n", chan, cmd);
uptr->u5 &= ~SNS_RTS; /* Request to send not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_SRTS: /* 0x1F */ /* Set RTS */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x SRTS\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x SRTS\n", chan, cmd);
uptr->u5 |= SNS_RTS; /* Requestd to send ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_RBRK: /* 0x33 */ /* Reset BREAK */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x RBRK\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x RBRK\n", chan, cmd);
uptr->u5 &= ~SNS_BREAK; /* Request to send not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_SBRK: /* 0x37 */ /* Set BREAK */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x SBRK\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x SBRK\n", chan, cmd);
uptr->u5 |= SNS_BREAK; /* Requestd to send ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_RDTR: /* 0x13 */ /* Reset DTR (ADVR) */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x DTR\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x DTR\n", chan, cmd);
uptr->u5 &= ~SNS_DTR; /* Data terminal not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case COM_SDTR: /* 0x17 */ /* Set DTR (ADVF) */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x NOP\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x NOP\n", chan, cmd);
uptr->u5 |= SNS_DTR; /* Data terminal ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
@ -610,20 +610,22 @@ uint8 com_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
#endif
case COM_SACE: /* 0xff */ /* Set ACE parameters (3 chars) */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x SACE\n", chan, cmd);
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x SACE\n", chan, cmd);
chan_read_byte(GET_UADDR(uptr->u3), &ch); /* read char 0 */
uptr->u4 = ((uint32)ch)<<24; /* byte 0 of ACE data */
chan_read_byte(GET_UADDR(uptr->u3), &ch); /* read char 1 */
uptr->u4 |= ((uint32)ch)<<16; /* byte 1 of ACE data */
chan_read_byte(GET_UADDR(uptr->u3), &ch); /* read char 2 */
uptr->u4 |= ((uint32)ch)<<8; /* byte 2 of ACE data */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd %x SACE bytes %x\n", chan, cmd, uptr->u4);
return SNS_CHNEND|SNS_DEVEND; /* good return */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd %02x ACE bytes %08x\n",
chan, cmd, uptr->u4);
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
default: /* invalid command */
uptr->u5 |= SNS_CMDREJ; /* command rejected */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %x: Cmd Invald %x status %02x\n", chan, cmd, uptr->u5);
default: /* invalid command */
uptr->u5 |= SNS_CMDREJ; /* command rejected */
sim_debug(DEBUG_CMD, &com_dev, "com_startcmd %04x: Cmd Invald %02x status %02x\n",
chan, cmd, uptr->u5);
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
break;
}
@ -646,12 +648,13 @@ t_stat comi_srv(UNIT *uptr)
uint32 cln = (uptr - coml_unit) & 0x7; /* use line # 0-7 for 8-15 */
ln = uptr - com_unit; /* line # */
sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %04x line %04x cmd %02x\n", chsa, ln, cmd);
/* handle NOP and INCH cmds */
sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "comi_srv entry chsa %04x line %04x cmd %02x\n", chsa, ln, cmd);
if (cmd == COM_NOP || cmd == 0x7f) { /* check for NOP or INCH */
uptr->u3 &= LMASK; /* leave only chsa */
sim_debug(DEBUG_CMD, &com_dev, "comi_srv NOP or INCH done chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "comi_srv NOP or INCH done chsa %04x line %04x cmd %02x\n",
chsa, ln, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
return SCPE_OK; /* return */
}
@ -666,13 +669,13 @@ t_stat comi_srv(UNIT *uptr)
int chan = ((chsa >> 8) & 0x7f); /* get the channel number */
UNIT *comlp = coml_unit+ln; /* get uptr for coml line */
int cmd = comlp->u3 & 0xff; /* get the active cmd */
//fprintf(stderr, "comi_srv poll chsa %x new line %x\r\n", chsa, newln);
//fprintf(stderr, "comi_srv poll chsa %04x new line %04x\r\n", chsa, newln);
com_ldsc[newln].rcve = 1; /* enable rcv */
com_ldsc[newln+8].xmte = 1; /* enable xmt for output line */
com_sta[newln] &= ~COML_REP; /* clr pending */
/* send attention to OS here for this channel */
/* need to get chsa here for the channel */
//fprintf(stderr, "comi_srv chsa %x chan %x\r\n", chsa, chan);
//fprintf(stderr, "comi_srv chsa %04x chan %04x\r\n", chsa, chan);
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
}
/* poll all devices for input */
@ -683,7 +686,7 @@ t_stat comi_srv(UNIT *uptr)
uint16 chsa = GET_UADDR(comlp->u3); /* get channel/sub-addr */
if (com_ldsc[ln].conn) { /* connected? */
if ((c = tmxr_getc_ln(&com_ldsc[ln]))) { /* get char */
//fprintf(stderr, "comi_srv chsa %x input %x cmd %x\r\n", chsa, c, cmd);
//fprintf(stderr, "comi_srv chsa %04x input %02x cmd %02x\r\n", chsa, c, cmd);
ch = c; /* just the char */
/* echo the char out */
tmxr_putc_ln(&com_ldsc[ln], ch); /* output char */
@ -701,12 +704,12 @@ t_stat comi_srv(UNIT *uptr)
/* write byte to memory */
if (chan_write_byte(chsa, &ch)) {
/* done, reading chars */
//fprintf(stderr, "comi_srv chsa %x input %x complete cmd %x\r\n", chsa, c, cmd);
//fprintf(stderr, "comi_srv chsa %04x input %02x complete cmd %02x\r\n", chsa, c, cmd);
comlp->u3 &= LMASK; /* nothing left, clear cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
} else {
/* more to go, continue */
//fprintf(stderr, "comi_srv chsa %x input %x cnt %x cmd %x\r\n", chsa, c, cmd);
//fprintf(stderr, "comi_srv chsa %04x input %02x cmd %02x\r\n", chsa, c, cmd);
if (ch == '\r') { /* see if done */
comlp->u3 &= LMASK; /* nothing left, clear cmd */
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
@ -718,7 +721,8 @@ t_stat comi_srv(UNIT *uptr)
if (((comlp->u4 & ACE_WAKE) >> 8) == ch) {
/* send attention to OS here for this channel */
/* need to get chsa here for the channel */
// fprintf(stderr, "comi_srv WAKEUP chsa %x ch %x wake %x\r\n", chsa, ch, (comlp->u4 & ACE_WAKE)>>8);
// fprintf(stderr, "comi_srv WAKEUP chsa %04x ch %02x wake %04x\r\n",
// chsa, ch, (comlp->u4 & ACE_WAKE)>>8);
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
}
}
@ -741,15 +745,16 @@ t_stat como_srv(UNIT *uptr)
uint8 ch;
/* handle NOP and INCH cmds */
sim_debug(DEBUG_CMD, &com_dev, "como_srv entry chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "como_srv entry chsa %04x line %04x cmd %02x\n", chsa, ln, cmd);
if (cmd == COM_NOP || cmd == 0x7f) { /* check for NOP or INCH */
uptr->u3 &= LMASK; /* leave only chsa */
sim_debug(DEBUG_CMD, &com_dev, "como_srv NOP or INCH done chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "como_srv NOP or INCH done chsa %04x line %04x cmd %02x\n",
chsa, ln, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
return SCPE_OK; /* return */
}
sim_debug(DEBUG_CMD, &com_dev, "como_srv entry 1 chsa %x line %x cmd %x\n", chsa, ln, cmd);
sim_debug(DEBUG_CMD, &com_dev, "como_srv entry 1 chsa %04x line %04x cmd %02x\n", chsa, ln, cmd);
if (cmd) {
/* get a user byte from memory */
done = chan_read_byte(chsa, &ch); /* get byte from memory */
@ -759,27 +764,28 @@ t_stat como_srv(UNIT *uptr)
return SCPE_OK;
if (com_dev.flags & DEV_DIS) { /* disabled */
sim_debug(DEBUG_CMD, &com_dev, "como_srv chsa %x line %x DEV_DIS set\n", chsa, ln);
sim_debug(DEBUG_CMD, &com_dev, "como_srv chsa %04x line %04x DEV_DIS set\n", chsa, ln);
if (done) {
sim_debug(DEBUG_CMD, &com_dev, "como_srv Write DONE %d status %x\n", ln, SNS_CHNEND|SNS_DEVEND);
sim_debug(DEBUG_CMD, &com_dev, "como_srv Write DONE %04x status %04x\n",
ln, SNS_CHNEND|SNS_DEVEND);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
}
return SCPE_OK; /* return */
}
sim_debug(DEBUG_CMD, &com_dev, "como_srv poll chsa %x line %x DEV_DIS set\n", chsa, ln);
sim_debug(DEBUG_CMD, &com_dev, "como_srv poll chsa %04x line %04x DEV_DIS set\n", chsa, ln);
if (com_ldsc[ln].conn) { /* connected? */
if (com_ldsc[ln].xmte) { /* xmt enabled? */
if (done) { /* are we done writing */
endit:
uptr->u3 &= LMASK; /* nothing left, command complete */
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write %d: chnend|devend\n", ln);
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write %04x: chnend|devend\n", ln);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
return SCPE_OK;
}
/* send the next char out */
tmxr_putc_ln(&com_ldsc[ln], ch); /* output char */
sim_debug(DEBUG_CMD, &com_dev, "com_srvo writing char %c to ln %d\n", ch, ln);
sim_debug(DEBUG_CMD, &com_dev, "com_srvo writing char %c to ln %04x\n", ch, ln);
tmxr_poll_tx(&com_desc); /* poll xmt */
sim_activate(uptr, uptr->wait); /* wait */
return SCPE_OK;
@ -788,7 +794,7 @@ endit:
goto endit; /* done */
/* just dump the char */
// /* xmt disabled, just wait around */
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write dumping char %c on line %d\n", ch, ln);
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write dumping char %c on line %04\n", ch, ln);
tmxr_poll_tx(&com_desc); /* poll xmt */
//?? sim_activate(uptr, coml_unit[ln].wait); /* wait */
sim_activate(uptr, uptr->wait); /* wait */
@ -797,7 +803,8 @@ endit:
} else {
/* not connected, so dump char on ground */
if (done) {
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write dump DONE line %d status %x\n", ln, SNS_CHNEND|SNS_DEVEND);
sim_debug(DEBUG_CMD, &com_dev, "com_srvo write dump DONE line %04x status %04x\n",
ln, SNS_CHNEND|SNS_DEVEND);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
uptr->u3 &= LMASK; /* nothing left, command complete */
}
@ -835,7 +842,7 @@ t_stat com_attach(UNIT *uptr, CONST char *cptr)
r = tmxr_attach(&com_desc, uptr, cptr); /* attach */
if (r != SCPE_OK) /* error? */
return r; /* return error */
sim_debug(DEBUG_CMD, &com_dev, "com_srv com is now attached chsa %x\n", chsa);
sim_debug(DEBUG_CMD, &com_dev, "com_srv com is now attached chsa %04x\n", chsa);
sim_activate(uptr, 0); /* start poll at once */
return SCPE_OK;
}

26
SEL32/sel32_con.c
View File

@ -167,11 +167,11 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
if ((uptr->u3 & CON_MSK) != 0) /* is unit busy */
return SNS_BSY; /* yes, return busy */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd chan %x cmd %x enter\n", chan, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd chan %04x cmd %02x enter\n", chan, cmd);
/* process the commands */
switch (cmd & 0xFF) {
case CON_INCH: /* 0x00 */ /* INCH command */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd INCH\n", chan);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd INCH\n", chan);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= CON_MSK; /* save INCH command as 0xff */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
@ -221,19 +221,19 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
break;
case CON_CON: /* 0x1f */ /* Connect, return Data Set ready */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x CON\n", chan, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd %02x CON\n", chan, cmd);
uptr->u5 |= (SNS_DSR|SNS_DCD); /* Data set ready, Data Carrier detected */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case CON_DIS: /* 0x23 */ /* Disconnect has do nothing */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x DIS\n", chan, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd %02x DIS\n", chan, cmd);
uptr->u5 &= ~(SNS_DSR|SNS_DCD); /* Data set not ready */
return SNS_CHNEND|SNS_DEVEND; /* good return */
break;
case CON_SNS: /* 0x04 */ /* Sense */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd Sense %02x\n", chan, uptr->u5);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Cmd Sense %02x\n", chan, uptr->u5);
/* value 4 is Data Set Ready */
/* value 5 is Data carrier detected n/u */
ch = uptr->u5; /* status */
@ -243,7 +243,7 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
default: /* invalid command */
uptr->u5 |= SNS_CMDREJ; /* command rejected */
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Invalid command Sense %02x\n", chan, uptr->u5);
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %04x: Invalid command Sense %02x\n", chan, uptr->u5);
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
break;
}
@ -260,14 +260,14 @@ t_stat con_srvo(UNIT *uptr) {
int cmd = uptr->u3 & CON_MSK;
uint8 ch;
sim_debug(DEBUG_CMD, &con_dev, "con_srvo enter chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvo enter chsa %04x cmd = %02x\n", chsa, cmd);
if ((cmd == CON_NOP) || (cmd == CON_MSK)) { /* NOP has to do nothing */
uptr->u3 &= LMASK; /* nothing left, command complete */
if (cmd == CON_MSK) { /* Channel end only for INCH */
sim_debug(DEBUG_CMD, &con_dev, "con_srvo INCH chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvo INCH chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND); /* done */
} else {
sim_debug(DEBUG_CMD, &con_dev, "con_srvo NOP chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvo NOP chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
}
return SCPE_OK;
@ -295,15 +295,15 @@ t_stat con_srvi(UNIT *uptr) {
uint8 ch;
t_stat r;
sim_debug(DEBUG_DATA, &con_dev, "con_srvi enter chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_DATA, &con_dev, "con_srvi enter chsa %04x cmd = %02x\n", chsa, cmd);
if ((cmd == CON_NOP) || (cmd == CON_MSK)) { /* NOP has do nothing */
uptr->u3 &= LMASK; /* nothing left, command complete */
if (cmd == CON_MSK) { /* Channel end only for INCH */
sim_debug(DEBUG_CMD, &con_dev, "con_srvi INCH chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvi INCH chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND); /* done */
} else {
sim_debug(DEBUG_CMD, &con_dev, "con_srvi NOP chsa %x cmd = %x\n", chsa, cmd);
sim_debug(DEBUG_CMD, &con_dev, "con_srvi NOP chsa %04x cmd = %02x\n", chsa, cmd);
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
// chan_end(chsa, SNS_CHNEND); /* done */
}
@ -316,7 +316,7 @@ t_stat con_srvi(UNIT *uptr) {
case CON_ECHO: /* 0x0a */ /* read from device w/ECHO */
if (uptr->u3 & CON_INPUT) { /* input waiting? */
ch = con_data[unit].ibuff[uptr->u4++]; /* get char from read buffer */
sim_debug(DEBUG_CMD, &con_dev, "con_srvi %d: read %02x\n", unit, ch);
sim_debug(DEBUG_CMD, &con_dev, "con_srvi %04x: read %02x\n", unit, ch);
if (chan_write_byte(chsa, &ch)) { /* write byte to memory */
con_data[unit].incnt = 0; /* buffer empty */
cmd = 0; /* no cmd either */

176
SEL32/sel32_cpu.c
View File

@ -960,7 +960,7 @@ t_stat RealAddr(uint32 addr, uint32 *realaddr, uint32 *prot)
t = SPAD[0xf3]; /* get mpl from spad address */
if ((M[(t+4)>>2] & MASK24) >= (MEMSIZE*4)) { /* check OS midl */
// fprintf(stderr, "RealAddr MPL %x MPL[1] %x\r\n", t, M[(t+4)>>2]);
return MACHINECHK_TRAP; /* no, machine check error */
return MACHINECHK_TRAP; /* no, diags want machine check error */
// return NPMEM; /* no, none present memory error */
}
/* we are mapped, so calculate real address from map information */
@ -1015,7 +1015,7 @@ t_stat RealAddr(uint32 addr, uint32 *realaddr, uint32 *prot)
/* diag wants the mpl entries checked to make sure valid */
if ((M[(t+4)>>2] & MASK24) >= (MEMSIZE*4)) { /* check OS midl */
// fprintf(stderr, "RealAddr MPL %x MPL[1] %x\r\n", t, M[(t+4)>>2]);
return MACHINECHK_TRAP; /* no, machine check error */
return MACHINECHK_TRAP; /* diags want machine check error */
// return NPMEM; /* no, none present memory error */
}
/* we are mapped, so calculate real address from map information */
@ -1062,7 +1062,7 @@ t_stat read_instruction(uint32 thepsd[2], uint32 *instr)
*instr |= 0x80000000; /* set instruction fetch paging error */
pfault = *instr; /* save page number */
}
sim_debug(DEBUG_DETAIL, &cpu_dev, "read_instr status = %x\n", status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "read_instr status = %02x\n", status);
return status; /* return ALLOK or ERROR */
}
@ -1076,7 +1076,7 @@ t_stat Mem_read(uint32 addr, uint32 *data)
uint32 status, realaddr, prot, raddr, page;
status = RealAddr(addr, &realaddr, &prot); /* convert address to real physical address */
sim_debug(DEBUG_DETAIL, &cpu_dev, "Mem_read status = %x\n", status);
sim_debug(DEBUG_DETAIL, &cpu_dev, "Mem_read status = %02x\n", status);
if (status == ALLOK) {
*data = M[realaddr >> 2]; /* valid address, get physical address contents */
if ((CPU_MODEL >= MODEL_V6) && (modes & MAPMODE)) {
@ -1245,7 +1245,8 @@ redo:
if (civl == int_icb)
break;
}
sim_debug(DEBUG_EXP, &cpu_dev, "Normal int scan return icb %x irq_pend %x wait4int %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"Normal int scan return icb %08x irq_pend %02x wait4int %02x\n",
int_icb, irq_pend, wait4int);
/* take interrupt, store the PSD, fetch new PSD */
@ -1284,7 +1285,7 @@ redo:
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
SPAD[0xf5] = PSD2; /* save the current PSD2 */
sim_debug(DEBUG_IRQ, &cpu_dev,
"Interrupt %x OPSD1 %.8x OPSD2 %.8x NPSD1 %.8x NPSD2 %.8x ICBA %x\n",
"Interrupt %04x OPSD1 %08x OPSD2 %08x NPSD1 %08x NPSD2 %08x ICBA %08x\n",
il, M[int_icb>>2], M[(int_icb>>2)+1], PSD1, PSD2, int_icb);
wait4int = 0; /* wait is over for int */
skipinstr = 1; /* skip next inter test after this instr */
@ -1327,7 +1328,7 @@ redo:
if (!skipinstr && attention_trap) {
TRAPME = attention_trap; /* get trap number */
attention_trap = 0; /* do only once */
sim_debug(DEBUG_DETAIL, &cpu_dev, "Attention TRAP %x\n", TRAPME);
sim_debug(DEBUG_DETAIL, &cpu_dev, "Attention TRAP %04x\n", TRAPME);
skipinstr = 1; /* skip next interrupt test only once */
goto newpsd; /* got process trap */
}
@ -1341,7 +1342,7 @@ skipi:
/* fill IR from logical memory address */
if ((TRAPME = read_instruction(PSD, &IR))) {
sim_debug(DEBUG_DATA, &cpu_dev, "read_instr TRAPME %x PSD %x %x\n",
sim_debug(DEBUG_DATA, &cpu_dev, "read_instr TRAPME %04x PSD %08x %08x\n",
TRAPME, PSD1, PSD2);
if ((TRAPME == MAPFLT) || (TRAPME == NPMEM))
i_flags |= BT; /* do not update pc if MF or NPM */
@ -1407,7 +1408,8 @@ exec:
/* Split instruction into pieces */
PC = PSD1 & 0xfffffe; /* get 24 bit addr from PSD1 */
sim_debug(DEBUG_DATA, &cpu_dev, "-----Instr @ PC %x PSD1 %.8x PSD2 %.8x IR %.8x\n", PC, PSD1, PSD2, IR);
sim_debug(DEBUG_DATA, &cpu_dev, "-----Instr @ PC %08x PSD1 %08x PSD2 %08x IR %08x\n",
PC, PSD1, PSD2, IR);
opr = (IR >> 16) & MASK16; /* use upper half of instruction */
OP = (opr >> 8) & 0xFC; /* Get opcode (bits 0-5) left justified */
FC = ((IR & F_BIT) ? 0x4 : 0) | (IR & 3); /* get F & C bits for addressing */
@ -1425,7 +1427,7 @@ exec:
if (modes & BASEBIT) {
i_flags = base_mode[OP>>2]; /* set the instruction processing flags */
addr = IR & RMASK; /* get address offset from instruction */
sim_debug(DEBUG_DATA, &cpu_dev, "Base OP %x i_flags %x addr %.8x\n", OP, i_flags, addr);
sim_debug(DEBUG_DATA, &cpu_dev, "Base OP %04x i_flags %04x addr %08x\n", OP, i_flags, addr);
switch(i_flags & 0xf) {
case HLF:
source = GPR[sreg]; /* get the src reg from instruction */
@ -1466,7 +1468,7 @@ exec:
goto newpsd; /* handle trap */
}
sim_debug(DEBUG_DATA, &cpu_dev, "Non Based i_flags %x addr %.8x\n", i_flags, addr);
sim_debug(DEBUG_DATA, &cpu_dev, "Non Based i_flags %04x addr %08x\n", i_flags, addr);
/* non base mode instructions have bit 0 of the instruction set */
/* for word length instructions and zero for halfword instructions */
/* the LA (op=0x34) is the only exception. So test for PC on a halfword */
@ -1661,7 +1663,8 @@ exec:
}
}
sim_debug(DEBUG_DETAIL, &cpu_dev, "PSD %x %x SW OP %x IR %x addr %.8x\n", PSD1, PSD2, OP, IR, addr);
sim_debug(DEBUG_DETAIL, &cpu_dev, "PSD %08x %08x SW OP %04x IR %08x addr %08x\n",
PSD1, PSD2, OP, IR, addr);
switch (OP>>2) {
/*
* For op-codes=00,04,08,0c,10,14,28,2c,38,3c,40,44,60,64,68
@ -1708,7 +1711,7 @@ exec:
}
if (wait4int == 0) {
time_t result = time(NULL);
sim_debug(DEBUG_CMD, &cpu_dev, "Starting WAIT mode %x\n", (uint32)result);
sim_debug(DEBUG_CMD, &cpu_dev, "Starting WAIT mode %08x\n", (uint32)result);
}
wait4int = 1; /* show we are waiting for interrupt */
/* tell simh we will be waiting */
@ -1851,23 +1854,44 @@ exec:
break;
case 0xA: /* CMC */ /* Cache Memory Control - Diag use only */
/* Cache memory control bit assignments for reg */
/* 0-22 reserved, must be zero */
/* 23 - Initialize Instruction Cache Bank 0 On = 1 Off = 0 */
/* 24 - Initialize Instruction Cache Bank 1 On = 1 Off = 0 */
/* 25 - Initialize Operand Cache Bank 0 On = 1 Off = 0 */
/* 26 - Initialize Operand Cache Bank 1 On = 1 Off = 0 */
/* 27 - Enable Instruction Cache Bank 0 On = 1 Off = 0 */
/* 28 - Enable Instruction Cache Bank 1 On = 1 Off = 0 */
/* 29 - Enable Operand Cache Bank 0 On = 1 Off = 0 */
/* 30 - Enable Operand Cache Bank 1 On = 1 Off = 0 */
/* 31 - Bypass Instruction Cache Bank 1 On = 1 Off = 0 */
// fprintf(stderr, "CMC GPR[%x] = %x CMCR %x\n", reg, GPR[reg], CMCR);
CMCR = GPR[reg]; /* write reg bits 23-31 to cache memory controller */
i_flags &= ~SD; /* turn off store dest for this instruction */
if (CPU_MODEL < MODEL_V6) {
TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
goto newpsd; /* handle trap */
}
#ifndef DO_DYNAMIC_DEBUG
/* start debugging */
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP);
#endif
if (CPU_MODEL == MODEL_V6) {
/* Cache memory control bit assignments for reg */
/* 0-22 reserved, must be zero */
/* 23 - Initialize Instruction Cache Bank 0 On = 1 Off = 0 */
/* 24 - Initialize Instruction Cache Bank 1 On = 1 Off = 0 */
/* 25 - Initialize Operand Cache Bank 0 On = 1 Off = 0 */
/* 26 - Initialize Operand Cache Bank 1 On = 1 Off = 0 */
/* 27 - Enable Instruction Cache Bank 0 On = 1 Off = 0 */
/* 28 - Enable Instruction Cache Bank 1 On = 1 Off = 0 */
/* 29 - Enable Operand Cache Bank 0 On = 1 Off = 0 */
/* 30 - Enable Operand Cache Bank 1 On = 1 Off = 0 */
/* 31 - Bypass Instruction Cache Bank 1 On = 1 Off = 0 */
fprintf(sim_deb, "CMC V6 GPR[%02x] = %04x CMCR = %08x CPU STATUS SPAD[f9] = %08x\r\n",
reg, GPR[reg], CMCR, SPAD[0xf9]);
CMCR = GPR[reg]; /* write reg bits 23-31 to cache memory controller */
i_flags &= ~SD; /* turn off store dest for this instruction */
} else
if (CPU_MODEL == MODEL_V9) {
fprintf(sim_deb, "CMC V9 GPR[%02x] = %08x CMCR = %08x CPU STATUS SPAD[f9] = %08x\r\n",
reg, GPR[reg], CMCR, SPAD[0xf9]);
CMCR = GPR[reg]; /* write reg bits 23-31 to cache memory controller */
i_flags &= ~SD; /* turn off store dest for this instruction */
}
break;
case 0x7: /* SMC */ /* Shared Memory Control - Diag use only */
if (CPU_MODEL != MODEL_V6) {
TRAPME = UNDEFINSTR_TRAP; /* Undefined Instruction Trap */
goto newpsd; /* handle trap */
}
/* Shared memory control bit assignments for reg */
/* 0 - Reserved */
/* 1 - Shared Memory Enabled (=1)/Disabled (=0) */
@ -1875,7 +1899,8 @@ exec:
/* 7 - Read & Lock Enabled (=1)/Disabled (=0) */
/* 8-12 - Lower Bound of Shared Memory */
/* 3-31 - Reserved and must be zero */
// fprintf(stderr, "SMC GPR[%x] = %x SMCR %x\n", reg, GPR[reg], SMCR);
fprintf(sim_deb, "SMC V6 GPR[%02x] = %08x SMCR = %08x CPU STATUS SPAD[f9] = %08x\r\n",
reg, GPR[reg], SMCR, SPAD[0xf9]);
SMCR = GPR[reg]; /* write reg bits 0-12 to shared memory controller */
i_flags &= ~SD; /* turn off store dest for this instruction */
break;
@ -4688,7 +4713,7 @@ doovr2:
// fprintf(stderr, "LPSDCM MAPS LOADED TRAPME = %x PSD1 %x PSD2 %x CPUSTATUS %x\r\n",
// TRAPME, PSD1, PSD2, CPUSTATUS);
sim_debug(DEBUG_EXP, &cpu_dev,
"LPSDCM MAPS LOADED TRAPME = %x PSD1 %x PSD2 %x CPUSTATUS %x\n",
"LPSDCM MAPS LOADED TRAPME = %02x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
TRAPME, PSD1, PSD2, CPUSTATUS);
}
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
@ -4778,11 +4803,11 @@ doovr2:
unsigned int nx;
for (nx=0; nx<112; nx++) {
if (INTS[nx] & INTS_ACT)
fprintf(stderr, "EI %x Interrupt level %x active\n", prior, nx);
fprintf(stderr, "EI %04x Interrupt level %04x active\n", prior, nx);
if (INTS[nx] & INTS_REQ)
fprintf(stderr, "EI %x Interrupt level %x requesting\n", prior, nx);
fprintf(stderr, "EI %04x Interrupt level %04x requesting\n", prior, nx);
if (INTS[nx] & INTS_ENAB)
fprintf(stderr, "EI %x Interrupt level %x enabled\n", prior, nx);
fprintf(stderr, "EI %04x Interrupt level %04x enabled\n", prior, nx);
}
}
#endif
@ -4816,11 +4841,11 @@ doovr2:
unsigned int nx;
for (nx=0; nx<112; nx++) {
if (INTS[nx] & INTS_ACT)
fprintf(stderr, "DI %x Interrupt level %x active\n", prior, nx);
fprintf(stderr, "DI %04x Interrupt level %04x active\n", prior, nx);
if (INTS[nx] & INTS_REQ)
fprintf(stderr, "DI %x Interrupt level %x requesting\n", prior, nx);
fprintf(stderr, "DI %04x Interrupt level %04x requesting\n", prior, nx);
if (INTS[nx] & INTS_ENAB)
fprintf(stderr, "DI %x Interrupt level %x enabled\n", prior, nx);
fprintf(stderr, "DI %04x Interrupt level %04x enabled\n", prior, nx);
}
}
#endif
@ -4845,11 +4870,11 @@ doovr2:
unsigned int nx;
for (nx=0; nx<112; nx++) {
if (INTS[nx] & INTS_ACT)
fprintf(stderr, "RI %x Interrupt level %x active\n", prior, nx);
fprintf(stderr, "RI %04x Interrupt level %04x active\n", prior, nx);
if (INTS[nx] & INTS_REQ)
fprintf(stderr, "RI %x Interrupt level %x requesting\n", prior, nx);
fprintf(stderr, "RI %04x Interrupt level %04x requesting\n", prior, nx);
if (INTS[nx] & INTS_ENAB)
fprintf(stderr, "RI %x Interrupt level %x enabled\n", prior, nx);
fprintf(stderr, "RI %04x Interrupt level %04x enabled\n", prior, nx);
}
}
#endif
@ -4875,11 +4900,11 @@ doovr2:
unsigned int nx;
for (nx=0; nx<112; nx++) {
if (INTS[nx] & INTS_ACT)
fprintf(stderr, "AI %x Interrupt level %x active\n", prior, nx);
fprintf(stderr, "AI %04x Interrupt level %04x active\n", prior, nx);
if (INTS[nx] & INTS_REQ)
fprintf(stderr, "AI %x Interrupt level %x requesting\n", prior, nx);
fprintf(stderr, "AI %04x Interrupt level %04x requesting\n", prior, nx);
if (INTS[nx] & INTS_ENAB)
fprintf(stderr, "AI %x Interrupt level %x enabled\n", prior, nx);
fprintf(stderr, "AI %04x Interrupt level %04x enabled\n", prior, nx);
}
}
#endif
@ -4909,11 +4934,11 @@ doovr2:
unsigned int nx;
for (nx=0; nx<112; nx++) {
if (INTS[nx] & INTS_ACT)
fprintf(stderr, "DAI %x Interrupt level %x active\n", prior, nx);
fprintf(stderr, "DAI %04x Interrupt level %04x active\n", prior, nx);
if (INTS[nx] & INTS_REQ)
fprintf(stderr, "DAI %x Interrupt level %x requesting\n", prior, nx);
fprintf(stderr, "DAI %04x Interrupt level %04x requesting\n", prior, nx);
if (INTS[nx] & INTS_ENAB)
fprintf(stderr, "DAI %x Interrupt level %x enabled\n", prior, nx);
fprintf(stderr, "DAI %04x Interrupt level %04x enabled\n", prior, nx);
}
}
#endif
@ -4988,7 +5013,7 @@ syscheckf:
TRAPSTATUS &= ~BIT1; /* I/O processing error */
goto newpsd; /* undefined instruction trap */
}
/* sim_debug(DEBUG_EXP, &cpu_dev, "$$ XIO lchan %x sa %x spad %.8x\n", lchan, suba, t); */
/* sim_debug(DEBUG_EXP, &cpu_dev, "$$ XIO lchan %04x sa %04x spad %08x\n", lchan, suba, t); */
/* get real channel from spad device entry */
chan = (t & 0x7f00) >> 8; /* real channel */
/* get the 1's comp of interrupt address from bits 9-15 SPAD entry */
@ -5019,7 +5044,7 @@ mcheck:
}
sim_debug(DEBUG_EXP, &cpu_dev,
"XIO ready chan %x intr %x icb %x iocla %x iocd1 %.8x iocd2 %.8x\n",
"XIO ready chan %04x intr %04x icb %08x iocla %08x iocd1 %08x iocd2 %08x\n",
chan, ix, addr, addr+16, M[temp>>2], M[(temp+4)>>2]);
/* at this point, the channel has a valid SPAD channel entry */
/* t is SPAD entry contents for chan device */
@ -5031,7 +5056,7 @@ mcheck:
/* addr - ICB for specified interrupt level, points to 6 wd block */
/* temp - First IOCD address */
sim_debug(DEBUG_EXP, &cpu_dev,
"XIO switch %x lchan %x, chan %x intr %x chsa %x IOCDa %.8x\n",
"XIO switch %02x lchan %04x, chan %04x intr %04x chsa %04x IOCDa %08x\n",
((opr>>3)&0x0f), lchan, chan, ix, (chan<<8)|suba, temp);
switch((opr >> 3) & 0xf) { /* use bits 9-12 to determine I/O instruction */
@ -5050,7 +5075,8 @@ mcheck:
/* TODO, provide support code */
/* for now or maybe forever, return unsupported transaction */
PSD1 = ((PSD1 & 0x87fffffe) | (CC2BIT|CC4BIT)); /* insert status 5 */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO unsupported WCS chan %x chsa %x status %x M[0] %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"XIO unsupported WCS chan %04x chsa %04x status %08x M[0] %08x\n",
chan, (chan<<8)|suba, status, M[0]);
/* just give unsupported transaction */
TRAPME = SYSTEMCHK_TRAP; /* trap condition if F class */
@ -5064,7 +5090,8 @@ mcheck:
if ((TRAPME = startxio(chsa, &status)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO SIO ret chan %x chsa %x status %x M[0] %x\n",
sim_debug(DEBUG_EXP, &cpu_dev,
"XIO SIO ret chan %04x chsa %04x status %08x M[0] %08x\n",
chan, (chan<<8)|suba, status, M[0]);
break;
@ -5075,7 +5102,7 @@ mcheck:
goto newpsd; /* error returned, trap cpu */
}
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO TIO ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "XIO TIO ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
@ -5084,7 +5111,7 @@ mcheck:
if ((TRAPME = stopxio(chsa, &status)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO STPIO ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "XIO STPIO ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
@ -5100,7 +5127,7 @@ mcheck:
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
//fprintf(stderr, "XIO RSCHNL ret chan %x chsa %x status %x\n", chan, (chan<<8)|suba, status);
sim_debug(DEBUG_EXP, &cpu_dev, "XIO RSCHNL ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "XIO RSCHNL ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
@ -5109,7 +5136,7 @@ mcheck:
if ((TRAPME = haltxio(chsa, &status)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "HIO HALTXIO ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "HIO HALTXIO ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
@ -5118,7 +5145,7 @@ mcheck:
if ((TRAPME = grabxio(chsa, &status)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO GRIO ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "XIO GRIO ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
@ -5127,14 +5154,15 @@ mcheck:
if ((TRAPME = stopxio(chsa, &status)))
goto newpsd; /* error returned, trap cpu */
PSD1 = ((PSD1 & 0x87fffffe) | (status & 0x78000000)); /* insert status */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO RSCTL ret chan %x chsa %x status %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "XIO RSCTL ret chan %04x chsa %04x status %08x\n",
chan, (chan<<8)|suba, status);
break;
/* TODO Finish XIO interrupts */
case 0x0C: /* Enable channel interrupt ECI */
chsa = temp2 & 0x7FFF; /* get logical device address */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO ECI chan %x sa %x spad %.8x\n", chan, suba, t);
sim_debug(DEBUG_EXP, &cpu_dev, "XIO ECI chan %04x sa %04x spad %08x\n",
chan, suba, t);
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] |= INTS_ENAB; /* enable specified int level */
SPAD[ix+0x80] |= SINT_ENAB; /* enable in SPAD too */
@ -5151,7 +5179,8 @@ if (chan == 0x7e)
cpu_dev.dctrl |= (DEBUG_INST | DEBUG_CMD | DEBUG_EXP);
#endif
chsa = temp2 & 0x7FFF; /* get logical device address */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO DCI chan %x sa %x spad %.8x\n", chan, suba, t);
sim_debug(DEBUG_EXP, &cpu_dev, "XIO DCI chan %04x sa %04x spad %08x\n",
chan, suba, t);
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] &= ~INTS_ENAB; /* disable specified int level */
SPAD[ix+0x80] &= ~SINT_ENAB; /* disable in SPAD too */
@ -5159,7 +5188,8 @@ if (chan == 0x7e)
case 0x0E: /* Activate channel interrupt ACI */
chsa = temp2 & 0x7FFF; /* get logical device address */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO ACI chan %x sa %x spad %.8x\n", chan, suba, t);
sim_debug(DEBUG_EXP, &cpu_dev, "XIO ACI chan %04x sa %04x spad %08x\n",
chan, suba, t);
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] |= INTS_ACT; /* activate specified int level */
SPAD[ix+0x80] |= SINT_ACT; /* enable in SPAD too */
@ -5169,7 +5199,8 @@ if (chan == 0x7e)
case 0x0F: /* Deactivate channel interrupt DACI */
/* Note, instruction following DACI is not interruptable */
chsa = temp2 & 0x7FFF; /* get logical device address */
sim_debug(DEBUG_EXP, &cpu_dev, "XIO DACI chan %x sa %x spad %.8x\n", chan, suba, t);
sim_debug(DEBUG_EXP, &cpu_dev, "XIO DACI chan %04x sa %04x spad %08x\n",
chan, suba, t);
/* SPAD entries for interrupts begin at 0x80 */
INTS[ix] &= ~INTS_ACT; /* deactivate specified int level */
SPAD[ix+0x80] &= ~SINT_ACT; /* deactivate in SPAD too */
@ -5400,7 +5431,7 @@ newpsd:
/* drop through */
default:
sim_debug(DEBUG_EXP, &cpu_dev,
"##TRAPME %x page# %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x\r\n",
"##TRAPME %04x page# %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
TRAPME, pfault, PSD1, PSD2, CPUSTATUS);
/* adjust PSD1 to next instruction */
/* Update instruction pointer to next instruction */
@ -5430,16 +5461,17 @@ newpsd:
/* Set map number */
/* pfault will have 11 bit page number and bit 0 set if op fetch */
sim_debug(DEBUG_EXP, &cpu_dev,
"##PAGEFAULT TRAPS %x page# %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x\r\n",
"##PAGEFAULT TRAPS %04x page# %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
TRAPME, pfault, PSD1, PSD2, CPUSTATUS);
}
sim_debug(DEBUG_EXP, &cpu_dev, "TRAPME %x PSD1 %x PSD2 %x CPUSTATUS %x drop_nop %x\n",
TRAPME, PSD1, PSD2, CPUSTATUS, drop_nop);
sim_debug(DEBUG_EXP, &cpu_dev,
"At TRAP %x IR %x PSD1 %x PSD2 %x CPUSTATUS %x ovr %d drop_nop %x\r\n",
"TRAPME %04x PSD1 %08x PSD2 %08x CPUSTATUS %08x drop_nop %02x\n",
TRAPME, PSD1, PSD2, CPUSTATUS, drop_nop);
sim_debug(DEBUG_EXP, &cpu_dev,
"At TRAP %04x IR %08x PSD1 %08x PSD2 %08x CPUSTATUS %08x ovr %02x drop_nop %02x\n",
TRAPME, IR, PSD1, PSD2, CPUSTATUS, ovr, drop_nop);
sim_debug(DEBUG_EXP, &cpu_dev,
"tvl %.8x, tta %.8x status %.8x\r\n", tvl, tta, CPUSTATUS);
"tvl %08x, tta %08x status %08x\n", tvl, tta, CPUSTATUS);
tta = tta + (TRAPME - 0x80); /* tta has mem addr of trap vector */
if (modes & BASEBIT)
@ -5451,7 +5483,7 @@ newpsd:
/* execute a trap halt */
/* set the PSD to trap vector location */
fprintf(stderr, "[][][][][][][][][][] HALT TRAP [][][][][][][][][][]\r\n");
fprintf(stderr, "PSD1 %.8x PSD2 %.8x TRAPME %.4x\r\n", PSD1, PSD2, TRAPME);
fprintf(stderr, "PSD1 %08x PSD2 %08x TRAPME %04x\r\n", PSD1, PSD2, TRAPME);
PSD1 = 0x80000000 + TRAPME; /* just priv and PC to trap vector */
PSD2 = 0x00004000; /* unmapped, blocked interrupts mode */
M[0x680>>2] = PSD1; /* store PSD 1 */
@ -5459,12 +5491,12 @@ newpsd:
M[0x688>>2] = TRAPSTATUS; /* store trap status */
M[0x68C>>2] = 0; /* This will be device table entry later TODO */
for (ix=0; ix<8; ix+=2) {
fprintf(stderr, "GPR[%d] %.8x GPR[%d] %.8x\r\n", ix, GPR[ix], ix+1, GPR[ix+1]);
fprintf(stderr, "GPR[%d] %08x GPR[%d] %08x\r\n", ix, GPR[ix], ix+1, GPR[ix+1]);
}
if (modes & BASEBIT) {
for (ix=0; ix<8; ix+=2) {
fprintf(stderr, "BR[%d] %.8x BR[%d] %.8x\r\n", ix, BR[ix], ix+1, BR[ix+1]);
}
for (ix=0; ix<8; ix+=2) {
fprintf(stderr, "BR[%d] %08x BR[%d] %08x\r\n", ix, BR[ix], ix+1, BR[ix+1]);
}
}
fprintf(stderr, "[][][][][][][][][][] HALT TRAP [][][][][][][][][][]\r\n");
return STOP_HALT; /* exit to simh for halt */
@ -5505,14 +5537,14 @@ newpsd:
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
SPAD[0xf5] = PSD2; /* save the current PSD2 */
sim_debug(DEBUG_EXP, &cpu_dev, "Process TRAPME %x PSD1 %x PSD2 %x CPUSTATUS %x\n",
sim_debug(DEBUG_EXP, &cpu_dev, "Process TRAPME %04x PSD1 %08x PSD2 %08x CPUSTATUS %08x\n",
TRAPME, PSD1, PSD2, CPUSTATUS);
/* TODO provide page fault data to word 6 */
if (TRAPME == DEMANDPG_TRAP) { /* 0xC4 Demand Page Fault Trap (V6&V9 Only) */
/* Set map number */
/* pfault will have 11 bit page number and bit 0 set if op fetch */
sim_debug(DEBUG_EXP, &cpu_dev,
"PAGE TRAP %x TSTATUS %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x pfault %x\r\n",
"PAGE TRAP %04x TSTATUS %08x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x pfault %08x\n",
TRAPME, TRAPSTATUS, PSD1, PSD2, CPUSTATUS, pfault);
}
break; /* Go execute the trap */

15
SEL32/sel32_iop.c
View File

@ -1,6 +1,6 @@
/* sel32_iop.c: SEL 32 Class F IOP processor channel.
Copyright (c) 2018, James C. Bevier
Copyright (c) 2018-2019, James C. Bevier
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -139,7 +139,7 @@ void iop_ini(UNIT *uptr, t_bool f)
int unit = (uptr - iop_unit); /* unit 0 */
DEVICE *dptr = &iop_dev; /* one and only dummy device */
sim_debug(DEBUG_CMD, &iop_dev, "IOP init device %s controller/device %x\n", dptr->name, GET_UADDR(uptr->u3));
sim_debug(DEBUG_CMD, &iop_dev, "IOP init device %s controller/device %04x\n", dptr->name, GET_UADDR(uptr->u3));
iop_data[unit].incnt = 0; /* no input data */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
}
@ -155,14 +155,14 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
case IOP_INCH: /* INCH command */
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd INCH\n", chan);
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %04x: Cmd INCH\n", chan);
uptr->u3 |= IOP_MSK; /* save INCH command as 0xff */
sim_activate(uptr, 20); /* TRY 07-13-19 */
return 0; /* no status change */
break;
case IOP_NOP: /* NOP command */
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd NOP\n", chan);
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %04x: Cmd NOP\n", chan);
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save NOP command */
@ -172,7 +172,8 @@ uint8 iop_startcmd(UNIT *uptr, uint16 chan, uint8 cmd)
default: /* invalid command */
uptr->u5 |= SNS_CMDREJ; /* command rejected */
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %x: Cmd Invald %x status %02x\n", chan, cmd, uptr->u5);
sim_debug(DEBUG_CMD, &iop_dev, "iop_startcmd %04x: Cmd Invald %02x status %02x\n",
chan, cmd, uptr->u5);
uptr->u3 &= LMASK; /* leave only chsa */
uptr->u3 |= (cmd & IOP_MSK); /* save command */
sim_activate(uptr, 20); /* force interrupt */
@ -207,7 +208,7 @@ t_stat iop_srvo(UNIT *uptr)
uint16 chsa = GET_UADDR(uptr->u3);
int cmd = uptr->u3 & IOP_MSK;
sim_debug(DEBUG_CMD, &iop_dev, "iop_srvo start %x: cmd %x \n", chsa, cmd);
sim_debug(DEBUG_CMD, &iop_dev, "iop_srvo start %04x: cmd %02x \n", chsa, cmd);
return SCPE_OK;
}
@ -217,7 +218,7 @@ t_stat iop_srvi(UNIT *uptr)
uint16 chsa = GET_UADDR(uptr->u3);
int cmd = uptr->u3 & IOP_MSK;
sim_debug(DEBUG_CMD, &iop_dev, "iop_srv start %x: cmd %x \n", chsa, cmd);
sim_debug(DEBUG_CMD, &iop_dev, "iop_srv start %04x: cmd %02x \n", chsa, cmd);
return SCPE_OK;
}