diff --git a/B5500/b5500_cpu.c b/B5500/b5500_cpu.c
index adccb01..2e3f4a5 100644
--- a/B5500/b5500_cpu.c
+++ b/B5500/b5500_cpu.c
@@ -269,8 +269,6 @@ t_stat              cpu_reset(DEVICE * dptr);
 t_stat              cpu_msize(UNIT *up, int32 v, CONST char *cp, void *dp);
 t_stat              cpu_set_size(UNIT * uptr, int32 val, CONST char *cptr,
                                  void *desc);
-t_stat              cpu_show_size(FILE * st, UNIT * uptr, int32 val,
-                                  CONST void *desc);
 t_stat              cpu_show_hist(FILE * st, UNIT * uptr, int32 val,
                                   CONST void *desc);
 t_stat              cpu_set_hist(UNIT * uptr, int32 val, CONST char *cptr,
@@ -291,7 +289,7 @@ int32               rtc_tps = 60 ;
 */
 
 UNIT                cpu_unit[] =
-    {{ UDATA(rtc_srv, MEMAMOUNT(7)|UNIT_IDLE, MAXMEMSIZE ), 16667 },
+    {{ UDATA(rtc_srv, MEMAMOUNT(7)|UNIT_IDLE|UNIT_FIX, MAXMEMSIZE ), 16667 },
     { UDATA(0, UNIT_DISABLE|UNIT_DIS, 0 ), 0 }};
 
 REG                 cpu_reg[] = {
@@ -339,7 +337,6 @@ MTAB                cpu_mod[] = {
     {UNIT_MSIZE|MTAB_VDV, MEMAMOUNT(5), NULL, "24K", &cpu_set_size},
     {UNIT_MSIZE|MTAB_VDV, MEMAMOUNT(6), NULL, "28K", &cpu_set_size},
     {UNIT_MSIZE|MTAB_VDV, MEMAMOUNT(7), NULL, "32K", &cpu_set_size},
-    {MTAB_VDV, 0, "MEMORY", NULL, NULL, &cpu_show_size},
     {MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
     {MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
     {MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_SHP, 0, "HISTORY", "HISTORY",
@@ -3876,13 +3873,6 @@ cpu_dep(t_value val, t_addr addr, UNIT * uptr, int32 sw)
     return SCPE_OK;
 }
 
-t_stat
-cpu_show_size(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
-{
-    fprintf(st, "%dK", MEMSIZE/1024);
-    return SCPE_OK;
-}
-
 t_stat
 cpu_msize(UNIT *uptr, int32 v, CONST char *cptr, void *dptr)
 {
@@ -4035,6 +4025,7 @@ t_stat              cpu_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, con
     fprintf(st, "       sim> SET CPU1 ENABLE                enable second CPU\n");
     fprintf(st, "The primary CPU can't be disabled. Memory is shared between the two\n");
     fprintf(st, "CPU's. Memory can be configured in 4K increments up to 32K total.\n");
+    fprint_reg_help (st, dptr);
     fprint_set_help(st, dptr);
     fprint_show_help(st, dptr);
     return SCPE_OK;
diff --git a/B5500/b5500_dtc.c b/B5500/b5500_dtc.c
index 5a971bd..958bf57 100644
--- a/B5500/b5500_dtc.c
+++ b/B5500/b5500_dtc.c
@@ -195,11 +195,15 @@ MTAB                dtc_mod[] = {
 REG                 dtc_reg[] = {
     {ORDATAD(BUFSIZE, dtc_bufsize, 8, "Buffer size"), REG_HRO},
     {ORDATAD(NLINES, dtc_desc.lines, 8, "Buffer size"), REG_HRO},
+    {BRDATA(BUF, dtc_buf, 16, 8, sizeof(dtc_buf)), REG_HRO},
+    {BRDATA(LSTAT, dtc_lstatus, 16, 8, sizeof(dtc_lstatus)), REG_HRO},
+    {BRDATA(BUFPTR, dtc_bufptr, 16, 16, sizeof(dtc_bufptr)), REG_HRO},
+    {BRDATA(BUFSIZ, dtc_bsize, 16, 16, sizeof(dtc_bsize)), REG_HRO},
+    {BRDATA(BUFLIM, dtc_blimit, 16, 16, sizeof(dtc_blimit)), REG_HRO},
     {0}
 };
 
 
-
 UNIT                dtc_unit[] = {
     {UDATA(&dtc_srv, UNIT_DTC, 0)},                   /* DTC */
     {UDATA(&dtco_srv, UNIT_DIS, 0)},                  /* DTC server process */