mirror of
https://github.com/rcornwell/sims.git
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KA10: More Floating Point fixes, WAITS DMP Loader.
This commit is contained in:
Richard Cornwell
parent
24c71602e0
commit
cd8f6509c3
@ -60,7 +60,7 @@
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static int pia = 0;
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static int status = 0;
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static t_stat auxcpu_devio(uint32 dev, uint64 *data);
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static t_stat auxcpu_devio(uint32 dev, t_uint64 *data);
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static t_stat auxcpu_svc (UNIT *uptr);
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static t_stat auxcpu_reset (DEVICE *dptr);
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static t_stat auxcpu_attach (UNIT *uptr, CONST char *ptr);
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@ -246,7 +246,7 @@ static int transaction (unsigned char *request, unsigned char *response)
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return 0;
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}
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int auxcpu_read (int addr, uint64 *data)
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int auxcpu_read (int addr, t_uint64 *data)
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{
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unsigned char request[12];
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unsigned char response[12];
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@ -271,11 +271,11 @@ int auxcpu_read (int addr, uint64 *data)
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switch (response[0])
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{
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case ACK:
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*data = (uint64)response[1];
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*data |= (uint64)response[2] << 8;
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*data |= (uint64)response[3] << 16;
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*data |= (uint64)response[4] << 24;
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*data |= (uint64)response[5] << 32;
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*data = (t_uint64)response[1];
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*data |= (t_uint64)response[2] << 8;
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*data |= (t_uint64)response[3] << 16;
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*data |= (t_uint64)response[4] << 24;
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*data |= (t_uint64)response[5] << 32;
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break;
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case ERR:
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fprintf (stderr, "AUXCPU: Read error %06o\r\n", addr);
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@ -292,7 +292,7 @@ int auxcpu_read (int addr, uint64 *data)
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return 0;
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}
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int auxcpu_write (int addr, uint64 data)
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int auxcpu_write (int addr, t_uint64 data)
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{
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unsigned char request[12];
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unsigned char response[12];
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@ -362,7 +362,7 @@ static int auxcpu_interrupt (void)
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return 0;
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}
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t_stat auxcpu_devio(uint32 dev, uint64 *data)
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t_stat auxcpu_devio(uint32 dev, t_uint64 *data)
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{
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DEVICE *dptr = &auxcpu_dev;
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@ -387,15 +387,15 @@ t_stat ch10_devio(uint32 dev, uint64 *data)
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int i = 512-rx_count;
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ch10_status &= ~RXD;
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if (ch10_status & SWAP) {
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*data = ((t_uint64)(rx_buffer[i]) & 0xff) << 20;
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*data |= ((t_uint64)(rx_buffer[i+1]) & 0xff) << 28;
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*data |= ((t_uint64)(rx_buffer[i+2]) & 0xff) << 4;
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*data |= ((t_uint64)(rx_buffer[i+3]) & 0xff) << 12;
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*data = ((uint64)(rx_buffer[i]) & 0xff) << 20;
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*data |= ((uint64)(rx_buffer[i+1]) & 0xff) << 28;
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*data |= ((uint64)(rx_buffer[i+2]) & 0xff) << 4;
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*data |= ((uint64)(rx_buffer[i+3]) & 0xff) << 12;
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} else {
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*data = ((t_uint64)(rx_buffer[i]) & 0xff) << 28;
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*data |= ((t_uint64)(rx_buffer[i+1]) & 0xff) << 20;
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*data |= ((t_uint64)(rx_buffer[i+2]) & 0xff) << 12;
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*data |= ((t_uint64)(rx_buffer[i+3]) & 0xff) << 4;
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*data = ((uint64)(rx_buffer[i]) & 0xff) << 28;
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*data |= ((uint64)(rx_buffer[i+1]) & 0xff) << 20;
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*data |= ((uint64)(rx_buffer[i+2]) & 0xff) << 12;
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*data |= ((uint64)(rx_buffer[i+3]) & 0xff) << 4;
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}
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rx_count-=4;
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sim_debug (DBG_DAT, &ch10_dev, "Read buffer word %d:%02x %02x %02x %02x %012llo %012llo\n",
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397
PDP10/ka10_cpu.c
397
PDP10/ka10_cpu.c
@ -541,7 +541,7 @@ int opflags[] = {
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0, 0, 0, 0,
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/* UFA */ /* DFN */ /* FSC */ /* IBP */
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P10(FCE|FBR), P10(FCE|FAC|SAC), FAC|SAC, 0,
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P10(FCE|FBR), P10(FCE|FAC), FAC|SAC, 0,
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/* ILDB */ /* LDB */ /* IDPB */ /* DPB */
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0, 0, 0, 0,
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/* Floating point */
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@ -1320,6 +1320,7 @@ t_stat dev_apr(uint32 dev, uint64 *data) {
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Ph = ((0377 & (*data >> 19)) << 10) + 01777;
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Pl = ((0377 & (*data >> 28)) << 10) + 01777;
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sim_debug(DEBUG_DATAIO, &cpu_dev, "DATAO APR %012llo\n", *data);
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sim_debug(DEBUG_DATAIO, &cpu_dev, "Rl=%06o Pl=%06o, Rh=%06o, Ph=%06o\n", Rl, Pl, Rh, Ph);
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break;
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case DATAI:
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@ -1545,6 +1546,8 @@ read:
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('R')))
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watch_stop = 1;
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MB = M[addr];
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}
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return 0;
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@ -1582,6 +1585,8 @@ write:
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('W')))
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watch_stop = 1;
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M[addr] = MB;
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}
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return 0;
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@ -1798,6 +1803,8 @@ int Mem_read_its(int flag, int cur_context, int fetch) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('R')))
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watch_stop = 1;
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MB = M[addr];
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}
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return 0;
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@ -1843,6 +1850,8 @@ int Mem_write_its(int flag, int cur_context) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('W')))
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watch_stop = 1;
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M[addr] = MB;
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}
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return 0;
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@ -2110,6 +2119,8 @@ int Mem_read_bbn(int flag, int cur_context, int fetch) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('R')))
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watch_stop = 1;
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MB = M[addr];
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}
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return 0;
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@ -2137,6 +2148,8 @@ int Mem_write_bbn(int flag, int cur_context) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('W')))
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watch_stop = 1;
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M[addr] = MB;
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}
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return 0;
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@ -2159,7 +2172,7 @@ int page_lookup_ka(int addr, int flag, int *loc, int wr, int cur_context, int fe
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mem_prot = 1;
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return 0;
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} else {
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*loc = addr;
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*loc = addr;
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}
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return 1;
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}
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@ -2177,6 +2190,8 @@ int Mem_read_ka(int flag, int cur_context, int fetch) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('R')))
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watch_stop = 1;
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MB = M[addr];
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}
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return 0;
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@ -2201,6 +2216,8 @@ int Mem_write_ka(int flag, int cur_context) {
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nxm_flag = 1;
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return 1;
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}
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if (sim_brk_summ && sim_brk_test(AB, SWMASK('W')))
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watch_stop = 1;
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M[addr] = MB;
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}
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return 0;
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@ -2508,7 +2525,7 @@ no_fetch:
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#if KI | KL
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/* Handle page fault and traps */
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if (page_enable && trap_flag == 0 && (FLAGS & (TRP1|TRP2))) {
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if (pi_enable && page_enable && trap_flag == 0 && (FLAGS & (TRP1|TRP2))) {
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AB = 0420 + ((FLAGS & (TRP1|TRP2)) >> 2);
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trap_flag = FLAGS & (TRP1|TRP2);
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FLAGS &= ~(TRP1|TRP2);
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@ -2712,7 +2729,7 @@ unasign:
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if ((FLAGS & USER) != 0 && (AB & 4) != 0) {
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FLAGS |= USERIO;
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if (AB & 2)
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FLAGS |= OVR;
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FLAGS |= PRV_PUB;
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}
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PC = MB & RMASK;
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f_pc_inh = 1;
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@ -2774,83 +2791,107 @@ unasign:
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AB = (AB + 1) & RMASK;
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if (Mem_read(0, 0, 0))
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goto last;
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/* Make into 64 bit numbers */
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SC = GET_EXPO(BR);
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SMEAR_SIGN(BR);
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BR <<= 35;
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BR |= MB & CMASK;
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BR |= (MB & CMASK);
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FE = GET_EXPO(AR);
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SMEAR_SIGN(AR);
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AR <<= 35;
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AR |= (MQ & CMASK);
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if (IR & 01) {
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BR = (DFMASK ^ BR) + 1;
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BR = (FPFMASK ^ BR) + 1;
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}
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SCAD = SC - FE;
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if (SCAD < 0) {
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SCAD = (SC - 200) + (FE - 200);
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if (FE > SC) { /* Swap if BR larger */
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AD = AR;
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AR = BR;
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BR = AD;
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SCAD = FE;
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FE = SC;
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SC = SCAD;
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SCAD = SC - FE;
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}
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if (SCAD > 0) {
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while (SCAD > 0) {
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AR = (AR & (DSMASK|DNMASK)) | (AR >> 1);
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SCAD--;
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SCAD = SC - FE;
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flag3 = 0;
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MQ = 0;
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if (SCAD > 0) { /* Align numbers */
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if (SCAD > 64) /* Outside range */
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AR = 0;
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else {
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while (SCAD > 0) {
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MQ >>= 1;
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if (AR & 1)
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MQ |= SMASK;
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AR = (AR & (FPHBIT|FPSBIT)) | (AR >> 1);
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SCAD--;
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}
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}
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}
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AD = (AR + BR);
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flag1 = 0;
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if ((AR & DSMASK) ^ (BR & DSMASK)) {
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if (AD & DSMASK) {
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AD = (DCMASK ^ AD) + 1;
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flag1 = 1;
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AR = AR + BR + flag3;
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/* Set flag1 to sign */
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flag1 = (AR & FPHBIT) != 0;
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dpnorm:
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/* Make sure High bit and sign bit same */
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while (((AR & FPHBIT) != 0) != ((AR & FPSBIT) != 0)) {
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SC += 1;
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MQ >>= 1;
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if (AR & 1)
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MQ |= SMASK;
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AR = (AR & FPHBIT) | (AR >> 1);
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}
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/* Check for potiential underflow */
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if (((SC & 0400) != 0) ^ ((SC & 0200) != 0))
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fxu_hold_set = 1;
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if (AR != 0) {
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while (AR != 0 &&
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(((AR & (FPSBIT|FPNBIT)) == (FPSBIT|FPNBIT)) ||
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((AR & (FPSBIT|FPNBIT)) == 0))) {
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SC --;
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AR <<= 1;
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if (MQ & SMASK)
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AR |= 1;
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MQ <<= 1;
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}
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/* Handle special minus case */
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if (AR == (FPHBIT|FPSBIT)) {
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SC += 1;
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AR = (AR & FPHBIT) | (AR >> 1);
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}
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} else {
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if (AR & DSMASK) {
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AD = (DCMASK ^ AD) + 1;
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flag1 = 1;
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}
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if (AD & DNMASK) {
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AD ++;
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AD = (AD & DSMASK) | (AD >> 1);
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SC++;
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}
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AR = MQ = 0;
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SC = 0;
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}
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AR = AD;
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while (AR != 0 && ((AR & DXMASK) == 0)) {
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AR <<= 1;
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SC--;
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fxu_hold_set = 1;
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/* Check if we need to round */
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if (!nrf && ((MQ & SMASK) != 0) && (((AR & FPSBIT) == 0) ||
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((AR & FPSBIT) != 0) && (MQ & 0377700000000LL) != 0)) {
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AR++;
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nrf = 1;
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/* Clean things up if we overflowed */
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if ((AR & FPHBIT) == 0)
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goto dpnorm;
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}
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dpnorm:
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if (AR == 0)
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flag1 = 0;
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ARX = AR & CMASK;
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/* Extract result */
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MQ = (AR & CMASK);
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AR >>= 35;
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AR &= MMASK;
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if (flag1) {
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ARX = (ARX ^ CMASK) + 1;
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AR = (AR ^ MMASK) + ((ARX & SMASK) != 0);
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ARX &= CMASK;
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AR &= MMASK;
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AR |= SMASK;
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}
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if (flag1) /* Append sign */
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AR |= SMASK;
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/* Check for over/under flow */
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if (((SC & 0400) != 0) && !pi_cycle) {
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FLAGS |= OVR|FLTOVR|TRP1;
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if (fxu_hold_set) {
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if (!fxu_hold_set) {
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FLAGS |= FLTUND;
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}
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}
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/* Add exponent */
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SCAD = SC ^ ((AR & SMASK) ? 0377 : 0);
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AR &= SMASK|MMASK;
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if (AR != 0)
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if (AR != 0 || MQ != 0)
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AR |= ((uint64)(SCAD & 0377)) << 27;
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MQ = ARX;
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set_reg(AC, AR);
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set_reg(AC+1, MQ);
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break;
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@ -2868,6 +2909,7 @@ dpnorm:
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AB = (AB + 1) & RMASK;
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if (Mem_read(0, 0, 0))
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goto last;
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/* Make into 64 bit numbers */
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SC = GET_EXPO(AR);
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SMEAR_SIGN(AR);
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AR <<= 35;
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@ -2877,26 +2919,97 @@ dpnorm:
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BR <<= 35;
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BR |= MB & CMASK;
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flag1 = 0;
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if (AR & DSMASK) {
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AR = (DFMASK ^ AR) + 1;
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/* Make both numbers positive */
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if (AR & FPSBIT) {
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AR = (FPFMASK ^ AR) + 1;
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flag1 = 1;
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}
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if (BR & DSMASK) {
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BR = (DFMASK ^ BR) + 1;
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if (BR & FPSBIT) {
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BR = (FPFMASK ^ BR) + 1;
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flag1 = !flag1;
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}
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SC = SC + FE - 0201;
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if (SC < 0)
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fxu_hold_set = 1;
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AD = (AR >> 30) * (BR >> 30);
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AD += ((AR >> 30) * (BR & PMASK)) >> 30;
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AD += ((AR & PMASK) * (BR >> 30)) >> 30;
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AR = AD >> 1;
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if (AR & DNMASK) {
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AR >>= 1;
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SC++;
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/* Compute exponent */
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SC = SC + FE - 0200;
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ARX = 0;
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/* Do multiply */
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for (FE = 0; FE < 62; FE++) {
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if (FE == 35) /* Clear MQ so it has correct lower product digits */
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MQ = 0;
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if (BR & 1)
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ARX += AR;
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MQ >>= 1;
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if (ARX & 1)
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MQ |= BIT1;
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ARX >>= 1;
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BR >>= 1;
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}
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goto dpnorm;
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AR = ARX;
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/* Make result negative if needed */
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if (flag1) {
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MQ = (MQ ^ CMASK) + 0400;
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AR = (AR ^ FPFMASK);
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if (MQ & SMASK) {
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AR ++;
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MQ &= FMASK;
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}
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/* Check for overflow */
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if ((AR & (FPHBIT|FPSBIT)) == (FPHBIT)) {
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SC += 1;
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MQ >>= 1;
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if (AR & 1)
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MQ |= BIT1;
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AR = (AR >> 1) | (FPHBIT & AR);
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}
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}
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/* Check if we need to normalize */
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if (AR != 0) {
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/* Check for fast shift */
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if ((AR & ~MMASK) == 0 || ((AR & ~MMASK) + BIT8) == 0) {
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SC -= 35;
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AR <<= 35;
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AR |= MQ & CMASK;
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MQ = 0;
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if ((AR & 0777) == 0777)
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AR &= (FPFMASK << 8);
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}
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if (((AR & (FPSBIT|FPNBIT)) == (FPSBIT|FPNBIT)) ||
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((AR & (FPSBIT|FPNBIT)) == 0)) {
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SC --;
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AR <<= 1;
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if (MQ & BIT1)
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AR |= 1;
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MQ <<= 1;
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MQ &= FMASK;
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nrf = 1;
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}
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} else {
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AR = MQ = 0;
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SC = 0;
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flag1 = 0;
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}
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/* Round if needed */
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if (MQ & BIT1)
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AR++;
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/* Build results */
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MQ = (AR & CMASK);
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AR >>= 35;
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AR &= MMASK;
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if (flag1)
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||||
AR |= SMASK;
|
||||
if (((SC & 0400) != 0) && !pi_cycle) {
|
||||
FLAGS |= OVR|FLTOVR|TRP1;
|
||||
if (SC < 0) {
|
||||
FLAGS |= FLTUND;
|
||||
}
|
||||
}
|
||||
SCAD = SC ^ ((AR & SMASK) ? 0377 : 0);
|
||||
AR &= SMASK|MMASK;
|
||||
if (AR != 0 || MQ != 0)
|
||||
AR |= ((uint64)(SCAD & 0377)) << 27;
|
||||
|
||||
set_reg(AC, AR);
|
||||
set_reg(AC+1, MQ);
|
||||
break;
|
||||
|
||||
case 0113: /* DFDV */
|
||||
/* On Load AR,MQ has memory operand */
|
||||
@ -2911,6 +3024,7 @@ dpnorm:
|
||||
AB = (AB + 1) & RMASK;
|
||||
if (Mem_read(0, 0, 0))
|
||||
goto last;
|
||||
/* Make into 64 bit numbers */
|
||||
SC = GET_EXPO(AR);
|
||||
SMEAR_SIGN(AR);
|
||||
AR <<= 35;
|
||||
@ -2919,15 +3033,17 @@ dpnorm:
|
||||
SMEAR_SIGN(BR);
|
||||
BR <<= 35;
|
||||
BR |= MB & CMASK;
|
||||
/* Make both positive */
|
||||
flag1 = 0;
|
||||
if (AR & DSMASK) {
|
||||
AR = (DFMASK ^ AR) + 1;
|
||||
if (AR & FPSBIT) {
|
||||
AR = (FPFMASK ^ AR) + 1;
|
||||
flag1 = 1;
|
||||
}
|
||||
if (BR & DSMASK) {
|
||||
BR = (DFMASK ^ BR) + 1;
|
||||
if (BR & FPSBIT) {
|
||||
BR = (FPFMASK ^ BR) + 1;
|
||||
flag1 = !flag1;
|
||||
}
|
||||
/* Precheck if divide ok */
|
||||
if (AR >= (BR << 1)) {
|
||||
if (!pi_cycle)
|
||||
FLAGS |= OVR|FLTOVR|NODIV|TRP1;
|
||||
@ -2935,18 +3051,21 @@ dpnorm:
|
||||
sac_inh = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Divide by zero */
|
||||
if (AR == 0) {
|
||||
sac_inh = 1;
|
||||
break;
|
||||
}
|
||||
/* Compute exponents */
|
||||
SC = SC - FE + 0201;
|
||||
/* Precheck divider */
|
||||
if (AR < BR) {
|
||||
AR <<= 1;
|
||||
SC--;
|
||||
}
|
||||
if (SC < 0)
|
||||
fxu_hold_set = 1;
|
||||
if (SC < 0 && !pi_cycle)
|
||||
FLAGS |= FLTUND|OVR|FLTOVR|TRP1;
|
||||
/* Do divide */
|
||||
AD = 0;
|
||||
for (FE = 0; FE < 62; FE++) {
|
||||
AD <<= 1;
|
||||
@ -2957,7 +3076,34 @@ dpnorm:
|
||||
AR <<= 1;
|
||||
}
|
||||
AR = AD;
|
||||
goto dpnorm;
|
||||
if (flag1) {
|
||||
AR = (AR ^ FPFMASK) + 1;
|
||||
}
|
||||
if (((SC & 0400) != 0) ^ ((SC & 0200) != 0) || SC == 0600)
|
||||
fxu_hold_set = 1;
|
||||
while (((AR & FPHBIT) != 0) != ((AR & FPSBIT) != 0)) {
|
||||
SC += 1;
|
||||
AR = (AR & FPHBIT) | (AR >> 1);
|
||||
}
|
||||
MQ = (AR & CMASK);
|
||||
AR >>= 35;
|
||||
AR &= MMASK;
|
||||
if (flag1)
|
||||
AR |= SMASK;
|
||||
if (((SC & 0400) != 0) && !pi_cycle) {
|
||||
FLAGS |= OVR|FLTOVR|TRP1;
|
||||
if (!fxu_hold_set) {
|
||||
FLAGS |= FLTUND;
|
||||
}
|
||||
}
|
||||
SCAD = SC ^ ((AR & SMASK) ? 0377 : 0);
|
||||
AR &= SMASK|MMASK;
|
||||
if (AR != 0 | MQ != 0)
|
||||
AR |= ((uint64)(SCAD & 0377)) << 27;
|
||||
|
||||
set_reg(AC, AR);
|
||||
set_reg(AC+1, MQ);
|
||||
break;
|
||||
|
||||
case 0114: /* DADD */
|
||||
case 0115: /* DSUB */
|
||||
@ -3046,15 +3192,7 @@ dpnorm:
|
||||
MQ = 0;
|
||||
SC = ((((AR & SMASK) ? 0377 : 0 )
|
||||
^ ((AR >> 27) & 0377)) + 0600) & 0777;
|
||||
flag1 = 0;
|
||||
if ((AR & SMASK) != 0) {
|
||||
AR ^= MMASK;
|
||||
AR++;
|
||||
AR &= MMASK;
|
||||
flag1 = 1;
|
||||
} else {
|
||||
AR &= MMASK;
|
||||
}
|
||||
SMEAR_SIGN(AR);
|
||||
SC -= 27;
|
||||
SC &= 0777;
|
||||
if (SC < 9) {
|
||||
@ -3063,17 +3201,21 @@ dpnorm:
|
||||
} else if ((SC & 0400) != 0) {
|
||||
/* -27 < N < 0 */
|
||||
SC = 01000 - SC;
|
||||
MQ = (AR << (36 - SC)) - flag1 ;
|
||||
AR = (AR >> SC);
|
||||
if ((IR & 04) && (MQ & SMASK) != 0)
|
||||
if (SC > 27) {
|
||||
AR = MQ = 0;
|
||||
} else {
|
||||
MQ = (AR << (36 - SC)) & FMASK /*- flag1*/ ;
|
||||
AR = (AR >> SC) | FMASK & (((AR & SMASK)? FMASK << (27 - SC): 0));
|
||||
}
|
||||
if (((IR & 04) != 0 && (MQ & SMASK) != 0) ||
|
||||
((IR & 04) == 0 && (AR & SMASK) != 0 &&
|
||||
((MQ & CMASK) != 0 || (MQ & SMASK) != 0)))
|
||||
AR ++;
|
||||
} else {
|
||||
if (!pi_cycle)
|
||||
FLAGS |= OVR|TRP1; /* OV & T1 */
|
||||
sac_inh = 1;
|
||||
}
|
||||
if (flag1)
|
||||
AR = (CM(AR) + 1) & FMASK;
|
||||
if (!sac_inh)
|
||||
set_reg(AC, AR);
|
||||
break;
|
||||
@ -3429,6 +3571,7 @@ ldb_ptr:
|
||||
BR = AR;
|
||||
AR = AD;
|
||||
MB = BR;
|
||||
set_reg(AC, AR);
|
||||
if (Mem_write(0, 0))
|
||||
goto last;
|
||||
#endif
|
||||
@ -3667,7 +3810,7 @@ fnormx:
|
||||
flag1 = 0;
|
||||
flag3 = 0;
|
||||
if (AR & SMASK) {
|
||||
if ((AR & EXPO) != 0 && (AR & MMASK) == 0) {
|
||||
if ((AR & MMASK) == 0) {
|
||||
AR = BIT9;
|
||||
SC++;
|
||||
} else
|
||||
@ -3676,6 +3819,10 @@ fnormx:
|
||||
flag3 = 1;
|
||||
}
|
||||
if (BR & SMASK) {
|
||||
if ((BR & MMASK) == 0) {
|
||||
BR = BIT9;
|
||||
SC++;
|
||||
} else
|
||||
BR = CM(BR) + 1;
|
||||
flag1 = !flag1;
|
||||
}
|
||||
@ -3710,12 +3857,12 @@ fnormx:
|
||||
flag1 = 1;
|
||||
flag3 = 1;
|
||||
}
|
||||
if ((BR & MMASK) == 0) {
|
||||
AR = 0;
|
||||
if ((BR & (MMASK)) == 0) {
|
||||
AR = BR;
|
||||
break;
|
||||
}
|
||||
if (AR & SMASK) {
|
||||
if ((AR & EXPO) != 0 && (AR & MMASK) == 0) {
|
||||
if ((AR & MMASK) == 0) {
|
||||
AR = BIT9;
|
||||
SC--;
|
||||
} else
|
||||
@ -3744,6 +3891,8 @@ fnormx:
|
||||
} else {
|
||||
SC--;
|
||||
}
|
||||
if (((SC & 0400) != 0) ^ ((SC & 0200) != 0) || SC == 0600)
|
||||
fxu_hold_set = 1;
|
||||
if (IR & 04) {
|
||||
AR++;
|
||||
}
|
||||
@ -3776,10 +3925,6 @@ fnormx:
|
||||
SC--;
|
||||
}
|
||||
AR &= MMASK;
|
||||
#endif
|
||||
if (((SC & 0400) != 0) ^ ((SC & 0200) != 0) || SC == 0600)
|
||||
fxu_hold_set = 1;
|
||||
#if PDP6
|
||||
if (flag1) {
|
||||
AR |= SMASK;
|
||||
}
|
||||
@ -3868,7 +4013,7 @@ fnormx:
|
||||
MQ = BR;
|
||||
if (flag1)
|
||||
AR = ((AR ^ FMASK) + 1) & FMASK;
|
||||
|
||||
|
||||
/* FDT1 */
|
||||
if (AR != 0) {
|
||||
MQ = (MQ >> 1) & (CMASK >> 1);
|
||||
@ -3985,11 +4130,10 @@ left:
|
||||
AR |= SMASK;
|
||||
}
|
||||
} else if (flag1) {
|
||||
AR = SMASK | BIT9;
|
||||
SC++;
|
||||
FE = SC = 0;
|
||||
} else {
|
||||
AR = 0;
|
||||
SC = 0;
|
||||
AR = 0;
|
||||
SC = 0;
|
||||
}
|
||||
if (((SC & 0400) != 0) && !pi_cycle) {
|
||||
FLAGS |= OVR|FLTOVR|TRP1;
|
||||
@ -4008,7 +4152,7 @@ left:
|
||||
MQ = (MQ ^ MMASK) + 1;
|
||||
MQ |= SMASK;
|
||||
}
|
||||
if (FE & 0400) {
|
||||
if (FE < 0 /*FE & 0400*/) {
|
||||
MQ = 0;
|
||||
FE = 0;
|
||||
} else
|
||||
@ -4128,6 +4272,10 @@ left:
|
||||
}
|
||||
AR &= FMASK;
|
||||
MQ = (MQ & ~SMASK) | (AR & SMASK);
|
||||
#if KA
|
||||
if (BR == SMASK && (AR & SMASK)) /* Handle special case */
|
||||
FLAGS |= OVR;
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 0230: /* IDIV */
|
||||
@ -4148,6 +4296,21 @@ left:
|
||||
break; /* Done */
|
||||
}
|
||||
|
||||
#if !PDP6
|
||||
if (AR == SMASK && BR == 1) {
|
||||
FLAGS |= OVR|NODIV; /* Overflow and No Divide */
|
||||
sac_inh=1; /* Don't touch AC */
|
||||
check_apr_irq();
|
||||
break; /* Done */
|
||||
}
|
||||
#else
|
||||
if (AR == SMASK && BR == 1) {
|
||||
MQ = 0;
|
||||
AR = 0;
|
||||
break; /* Done */
|
||||
}
|
||||
#endif
|
||||
|
||||
if (AR & SMASK) {
|
||||
AR = (CM(AR) + 1) & FMASK;
|
||||
flag1 = !flag1;
|
||||
@ -4187,7 +4350,8 @@ left:
|
||||
MQ |= (AD & SMASK) != 0;
|
||||
SC = 35;
|
||||
if ((AD & SMASK) == 0) {
|
||||
FLAGS |= OVR|NODIV; /* Overflow and No Divide */
|
||||
FLAGS |= OVR|NODIV|TRP1; /* Overflow and No Divide */
|
||||
i_flags = 0;
|
||||
sac_inh=1;
|
||||
check_apr_irq();
|
||||
break; /* Done */
|
||||
@ -4420,7 +4584,12 @@ left:
|
||||
AR = AOB(AR) & FMASK;
|
||||
#endif
|
||||
f_pc_inh = 1;
|
||||
#if KA & ITS
|
||||
if (QITS)
|
||||
set_reg(AC, AR);
|
||||
#else
|
||||
set_reg(AC, AR);
|
||||
#endif
|
||||
goto last;
|
||||
}
|
||||
AB = (AR & RMASK);
|
||||
@ -4435,7 +4604,12 @@ left:
|
||||
AR = AOB(AR) & FMASK;
|
||||
#endif
|
||||
f_pc_inh = 1;
|
||||
#if KA & ITS
|
||||
if (QITS)
|
||||
set_reg(AC, AR);
|
||||
#else
|
||||
set_reg(AC, AR);
|
||||
#endif
|
||||
goto last;
|
||||
}
|
||||
AD = (AR & RMASK) + CM(BR) + 1;
|
||||
@ -4530,6 +4704,9 @@ left:
|
||||
#endif
|
||||
FLAGS |= AR & (OVR|NODIV|FLTUND|BYTI|FLTOVR|CRY1|CRY0|\
|
||||
TRP1|TRP2|PUBLIC|PCHNG);
|
||||
#if KI
|
||||
FLAGS |= (FLAGS & OVR) ? PRV_PUB : 0;
|
||||
#endif
|
||||
#if ITS
|
||||
if (QITS)
|
||||
FLAGS |= AR & (PURE|ONEP);
|
||||
@ -4539,7 +4716,7 @@ left:
|
||||
|
||||
if (AC & 01) { /* Enter User Mode */
|
||||
#if KI | KL
|
||||
FLAGS &= ~PUBLIC;
|
||||
FLAGS &= ~(PUBLIC|PRV_PUB);
|
||||
#else
|
||||
FLAGS |= USER;
|
||||
#endif
|
||||
@ -4667,6 +4844,12 @@ left:
|
||||
/* Stack, JUMP */
|
||||
case 0260: /* PUSHJ */ /* AR Frm PC */
|
||||
MB = ((uint64)(FLAGS) << 23) | ((PC + !pi_cycle) & RMASK);
|
||||
#if KI
|
||||
if ((FLAGS & USER) == 0) {
|
||||
MB &= ~SMASK;
|
||||
MB |= (FLAGS & PRV_PUB) ? SMASK : 0;
|
||||
}
|
||||
#endif
|
||||
BR = AB;
|
||||
AR = AOB(AR);
|
||||
AB = AR & RMASK;
|
||||
@ -4765,6 +4948,12 @@ left:
|
||||
|
||||
case 0264: /* JSR */ /* AR Frm PC */
|
||||
MB = ((uint64)(FLAGS) << 23) | ((PC + !pi_cycle) & RMASK);
|
||||
#if KI
|
||||
if ((FLAGS & USER) == 0) {
|
||||
MB &= ~SMASK;
|
||||
MB |= (FLAGS & PRV_PUB) ? SMASK : 0;
|
||||
}
|
||||
#endif
|
||||
#if PDP6
|
||||
if (ill_op | uuo_cycle | pi_cycle | ex_uuo_sync) {
|
||||
ill_op = 0;
|
||||
@ -4791,6 +4980,12 @@ left:
|
||||
AD = ((uint64)(FLAGS) << 23) |
|
||||
((PC + !pi_cycle) & RMASK);
|
||||
FLAGS &= ~ (BYTI|ADRFLT|TRP1|TRP2);
|
||||
#if KI
|
||||
if ((FLAGS & USER) == 0) {
|
||||
AD &= ~SMASK;
|
||||
AD |= (FLAGS & PRV_PUB) ? SMASK : 0;
|
||||
}
|
||||
#endif
|
||||
#if !PDP6
|
||||
if (uuo_cycle | pi_cycle) {
|
||||
FLAGS &= ~(USER|PUBLIC); /* Clear USER */
|
||||
@ -5385,7 +5580,7 @@ fetch_opr:
|
||||
AR = AOB(AR);
|
||||
if (AR & C1) {
|
||||
pi_ov = 1;
|
||||
}
|
||||
}
|
||||
else if (!pi_cycle)
|
||||
PC = (PC + 1) & RMASK;
|
||||
AR &= FMASK;
|
||||
|
||||
@ -70,7 +70,7 @@ MTAB cty_mod[] = {
|
||||
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
|
||||
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
|
||||
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
|
||||
{ TT_MODE, TT_MODE_7P, "7b", "7P", &tty_set_mode },
|
||||
{ TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
||||
@ -68,7 +68,7 @@
|
||||
#define OFF_HOOK 0000100 /* Off Hook (CD) */
|
||||
#define CAUSE_PI 0000200 /* Cause PI */
|
||||
|
||||
t_uint64 dc_l_status; /* Line status */
|
||||
uint64 dc_l_status; /* Line status */
|
||||
int dc_l_count = 0; /* Scan counter */
|
||||
int dc_modem = DC10_MLINES; /* Modem base address */
|
||||
uint8 dcix_buf[DC10_MLINES] = { 0 }; /* Input buffers */
|
||||
|
||||
@ -121,6 +121,8 @@
|
||||
Code = 0 stops execution for an interrupt check
|
||||
*/
|
||||
|
||||
typedef t_uint64 uint64;
|
||||
|
||||
#define STOP_HALT 1 /* halted */
|
||||
#define STOP_IBKPT 2 /* breakpoint */
|
||||
|
||||
@ -161,11 +163,6 @@ extern DEBTAB crd_debug[];
|
||||
#define BIT10_35 00000377777777LL
|
||||
#define MANT 00000777777777LL
|
||||
#define EXPO 00377000000000LL
|
||||
#define DFMASK 01777777777777777777777LL
|
||||
#define DSMASK 01000000000000000000000LL
|
||||
#define DCMASK 00777777777777777777777LL
|
||||
#define DNMASK 00400000000000000000000LL
|
||||
#define DXMASK 00200000000000000000000LL
|
||||
#define FPHBIT 01000000000000000000000LL
|
||||
#define FPSBIT 00400000000000000000000LL
|
||||
#define FPNBIT 00200000000000000000000LL
|
||||
@ -234,6 +231,11 @@ extern DEBTAB crd_debug[];
|
||||
#define CRY1 002000 /* 100000 */
|
||||
#define CRY0 004000 /* 200000 */
|
||||
#define OVR 010000 /* 400000 */
|
||||
#if KI|KL
|
||||
#define PRV_PUB 020000 /* Overflow in excutive mode */
|
||||
#else
|
||||
#define PRV_PUB 000000 /* Not on KA or PDP6 */
|
||||
#endif
|
||||
#ifdef ITS
|
||||
#ifdef PURE
|
||||
#undef PURE
|
||||
@ -308,8 +310,6 @@ extern DEBTAB crd_debug[];
|
||||
#define UNIT_MPX (1 << UNIT_V_MPX) /* MPX Device for ITS */
|
||||
#define UNIT_M_MPX (1 << UNIT_V_MPX)
|
||||
|
||||
typedef unsigned long long int uint64;
|
||||
|
||||
|
||||
#if MPX_DEV
|
||||
extern void set_interrupt_mpx(int dev, int lvl, int mpx);
|
||||
@ -366,7 +366,7 @@ extern DEVICE dtc_dev;
|
||||
extern DEVICE mtc_dev;
|
||||
extern DEVICE dsk_dev;
|
||||
|
||||
extern t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
|
||||
extern t_stat (*dev_tab[128])(uint32 dev, t_uint64 *data);
|
||||
|
||||
#define VEC_DEVMAX 8 /* max device vec */
|
||||
|
||||
@ -374,7 +374,7 @@ extern t_stat (*dev_tab[128])(uint32 dev, uint64 *data);
|
||||
struct pdp_dib {
|
||||
uint32 dev_num; /* device address */
|
||||
uint32 num_devs; /* length */
|
||||
t_stat (*io)(uint32 dev, uint64 *data);
|
||||
t_stat (*io)(uint32 dev, t_uint64 *data);
|
||||
int (*irq)(uint32 dev, int addr);
|
||||
};
|
||||
|
||||
@ -396,7 +396,7 @@ struct df10 {
|
||||
uint32 wcr;
|
||||
uint32 cda;
|
||||
uint32 devnum;
|
||||
uint64 buf;
|
||||
t_uint64 buf;
|
||||
uint8 nxmerr;
|
||||
uint8 ccw_comp;
|
||||
} ;
|
||||
@ -415,17 +415,17 @@ int dct_write(int u, t_uint64 *data, int c);
|
||||
int dct_is_connect(int u);
|
||||
#endif
|
||||
|
||||
int ten11_read (int addr, uint64 *data);
|
||||
int ten11_write (int addr, uint64 data);
|
||||
int ten11_read (int addr, t_uint64 *data);
|
||||
int ten11_write (int addr, t_uint64 data);
|
||||
|
||||
/* Console lights. */
|
||||
extern void ka10_lights_init (void);
|
||||
extern void ka10_lights_main (uint64);
|
||||
extern void ka10_lights_main (t_uint64);
|
||||
extern void ka10_lights_set_aux (int);
|
||||
extern void ka10_lights_clear_aux (int);
|
||||
|
||||
int auxcpu_read (int addr, uint64 *);
|
||||
int auxcpu_write (int addr, uint64);
|
||||
int auxcpu_read (int addr, t_uint64 *);
|
||||
int auxcpu_write (int addr, t_uint64);
|
||||
|
||||
/* I/O system parameters */
|
||||
#define NUM_DEVS_LP 1
|
||||
@ -466,8 +466,8 @@ int auxcpu_write (int addr, uint64);
|
||||
|
||||
extern t_bool sim_idle_enab;
|
||||
extern struct rh_dev rh[];
|
||||
extern uint64 M[];
|
||||
extern uint64 FM[];
|
||||
extern t_uint64 M[];
|
||||
extern t_uint64 FM[];
|
||||
extern uint32 PC;
|
||||
extern uint32 FLAGS;
|
||||
|
||||
|
||||
@ -253,8 +253,8 @@
|
||||
#define DT_WRDTIM 15000
|
||||
|
||||
int32 dtsa = 0; /* status A */
|
||||
t_uint64 dtsb = 0; /* status B */
|
||||
t_uint64 dtdb = 0; /* data buffer */
|
||||
uint64 dtsb = 0; /* status B */
|
||||
uint64 dtdb = 0; /* data buffer */
|
||||
int dt_mpx_lvl;
|
||||
|
||||
t_stat dt_devio(uint32 dev, uint64 *data);
|
||||
@ -525,7 +525,7 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
void dt_getword(t_uint64 *data, int req) {
|
||||
void dt_getword(uint64 *data, int req) {
|
||||
int dev = dt_dib.dev_num;
|
||||
clr_interrupt(dev|4);
|
||||
if (dtsb & DTB_DATREQ) {
|
||||
@ -539,7 +539,7 @@ void dt_getword(t_uint64 *data, int req) {
|
||||
}
|
||||
}
|
||||
|
||||
void dt_putword(t_uint64 *data) {
|
||||
void dt_putword(uint64 *data) {
|
||||
int dev = dt_dib.dev_num;
|
||||
clr_interrupt(dev|4);
|
||||
if (dtsb & DTB_DATREQ) {
|
||||
@ -559,7 +559,7 @@ void dt_putword(t_uint64 *data) {
|
||||
t_stat dt_svc (UNIT *uptr)
|
||||
{
|
||||
int word;
|
||||
t_uint64 data = 0;
|
||||
uint64 data = 0;
|
||||
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
||||
int u = uptr-dt_unit;
|
||||
int blk;
|
||||
@ -710,8 +710,8 @@ if (uptr->DSTATE & DTC_MOT) {
|
||||
break;
|
||||
case FNC_RALL:
|
||||
case FNC_READ:
|
||||
data = ((t_uint64)fbuf[off]) << 18;
|
||||
data |= ((t_uint64)fbuf[off+1]);
|
||||
data = ((uint64)fbuf[off]) << 18;
|
||||
data |= ((uint64)fbuf[off+1]);
|
||||
if ((dtsb & DTB_STOP) == 0)
|
||||
dt_putword(&data);
|
||||
break;
|
||||
@ -779,7 +779,7 @@ if (uptr->DSTATE & DTC_MOT) {
|
||||
case DTC_RBLK: /* In reverse block number */
|
||||
sim_activate(uptr,DT_WRDTIM*2);
|
||||
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
||||
data = (t_uint64)word;
|
||||
data = (uint64)word;
|
||||
uptr->DSTATE = DTC_RCHK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) | (DTC_MOTMASK & uptr->DSTATE);
|
||||
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev reverse block %04o\n", u, word);
|
||||
dtsb &= ~DTB_END;
|
||||
@ -837,7 +837,7 @@ if (uptr->DSTATE & DTC_MOT) {
|
||||
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
||||
uptr->DSTATE = DTC_FCHK|(word << DTC_V_BLK) | (DTC_MOTMASK & uptr->DSTATE);
|
||||
sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o forward block %04o\n", u, word);
|
||||
data = (t_uint64)word;
|
||||
data = (uint64)word;
|
||||
if (DTC_GETUNI(dtsa) == u) {
|
||||
uptr->u3 &= 077077;
|
||||
uptr->u3 |= dtsa & 0700; /* Copy command */
|
||||
@ -926,8 +926,8 @@ if (uptr->DSTATE & DTC_MOT) {
|
||||
break;
|
||||
case FNC_RALL:
|
||||
case FNC_READ:
|
||||
data = ((t_uint64)fbuf[off]) << 18;
|
||||
data |= (t_uint64)fbuf[off+1];
|
||||
data = ((uint64)fbuf[off]) << 18;
|
||||
data |= (uint64)fbuf[off+1];
|
||||
if ((dtsb & DTB_STOP) == 0)
|
||||
dt_putword(&data);
|
||||
else
|
||||
@ -1059,8 +1059,8 @@ dt_boot(int32 unit_num, DEVICE * dptr)
|
||||
while (wc != 0) {
|
||||
wc = (wc + 1) & RMASK;
|
||||
addr = (addr + 1) & RMASK;
|
||||
word = ((t_uint64)fbuf[off++]) << 18;
|
||||
word |= (t_uint64)fbuf[off++];
|
||||
word = ((uint64)fbuf[off++]) << 18;
|
||||
word |= (uint64)fbuf[off++];
|
||||
if (addr < 020)
|
||||
FM[addr] = word;
|
||||
else
|
||||
|
||||
@ -610,28 +610,28 @@ t_stat rp_devio(uint32 dev, uint64 *data) {
|
||||
return SCPE_OK;
|
||||
}
|
||||
if (rp_reg[ctlr] == 040) {
|
||||
*data = (t_uint64)(rp_read(ctlr, rp_drive[ctlr], 0) & 077);
|
||||
*data |= ((t_uint64)(df10->cia)) << 6;
|
||||
*data |= ((t_uint64)(rp_xfer_drive[ctlr])) << 18;
|
||||
*data = (uint64)(rp_read(ctlr, rp_drive[ctlr], 0) & 077);
|
||||
*data |= ((uint64)(df10->cia)) << 6;
|
||||
*data |= ((uint64)(rp_xfer_drive[ctlr])) << 18;
|
||||
} else if (rp_reg[ctlr] == 044) {
|
||||
*data = (t_uint64)rp_ivect[ctlr];
|
||||
*data = (uint64)rp_ivect[ctlr];
|
||||
if (rp_imode[ctlr])
|
||||
*data |= IRQ_KI10;
|
||||
else
|
||||
*data |= IRQ_KA10;
|
||||
} else if (rp_reg[ctlr] == 054) {
|
||||
*data = (t_uint64)(rp_rae[ctlr]);
|
||||
*data = (uint64)(rp_rae[ctlr]);
|
||||
} else if ((rp_reg[ctlr] & 040) == 0) {
|
||||
int parity;
|
||||
*data = (t_uint64)(rp_read(ctlr, rp_drive[ctlr], rp_reg[ctlr]) & 0177777);
|
||||
*data = (uint64)(rp_read(ctlr, rp_drive[ctlr], rp_reg[ctlr]) & 0177777);
|
||||
parity = (int)((*data >> 8) ^ *data);
|
||||
parity = (parity >> 4) ^ parity;
|
||||
parity = (parity >> 2) ^ parity;
|
||||
parity = ((parity >> 1) ^ parity) & 1;
|
||||
*data |= ((t_uint64)(parity ^ 1)) << 17;
|
||||
*data |= ((t_uint64)(rp_drive[ctlr])) << 18;
|
||||
*data |= ((uint64)(parity ^ 1)) << 17;
|
||||
*data |= ((uint64)(rp_drive[ctlr])) << 18;
|
||||
}
|
||||
*data |= ((t_uint64)(rp_reg[ctlr])) << 30;
|
||||
*data |= ((uint64)(rp_reg[ctlr])) << 30;
|
||||
sim_debug(DEBUG_DATAIO, dptr, "RP %03o DATI %012llo, %d %d PC=%06o\n",
|
||||
dev, *data, ctlr, rp_drive[ctlr], PC);
|
||||
return SCPE_OK;
|
||||
|
||||
@ -389,29 +389,29 @@ t_stat rs_devio(uint32 dev, uint64 *data) {
|
||||
return SCPE_OK;
|
||||
}
|
||||
if (rs_reg[ctlr] == 040) {
|
||||
*data = (t_uint64)(rs_read(ctlr, rs_drive[ctlr], 0) & 077);
|
||||
*data |= ((t_uint64)(df10->cia)) << 6;
|
||||
*data |= ((t_uint64)(rs_xfer_drive[ctlr])) << 18;
|
||||
*data = (uint64)(rs_read(ctlr, rs_drive[ctlr], 0) & 077);
|
||||
*data |= ((uint64)(df10->cia)) << 6;
|
||||
*data |= ((uint64)(rs_xfer_drive[ctlr])) << 18;
|
||||
} else if (rs_reg[ctlr] == 044) {
|
||||
*data = (t_uint64)rs_ivect[ctlr];
|
||||
*data = (uint64)rs_ivect[ctlr];
|
||||
if (rs_imode[ctlr])
|
||||
*data |= IRQ_KI10;
|
||||
else
|
||||
*data |= IRQ_KA10;
|
||||
} else if (rs_reg[ctlr] == 054) {
|
||||
*data = (t_uint64)(rs_rae[ctlr]);
|
||||
*data = (uint64)(rs_rae[ctlr]);
|
||||
} else if ((rs_reg[ctlr] & 040) == 0) {
|
||||
int parity;
|
||||
|
||||
*data = (t_uint64)(rs_read(ctlr, rs_drive[ctlr], rs_reg[ctlr]) & 0177777);
|
||||
*data = (uint64)(rs_read(ctlr, rs_drive[ctlr], rs_reg[ctlr]) & 0177777);
|
||||
parity = (int)((*data >> 8) ^ *data);
|
||||
parity = (parity >> 4) ^ parity;
|
||||
parity = (parity >> 2) ^ parity;
|
||||
parity = ((parity >> 1) ^ parity) & 1;
|
||||
*data |= ((t_uint64)(parity ^ 1)) << 17;
|
||||
*data |= ((t_uint64)(rs_drive[ctlr])) << 18;
|
||||
*data |= ((uint64)(parity ^ 1)) << 17;
|
||||
*data |= ((uint64)(rs_drive[ctlr])) << 18;
|
||||
}
|
||||
*data |= ((t_uint64)(rs_reg[ctlr])) << 30;
|
||||
*data |= ((uint64)(rs_reg[ctlr])) << 30;
|
||||
sim_debug(DEBUG_DATAIO, dptr, "RS %03o DATI %012llo, %d %d PC=%06o\n",
|
||||
dev, *data, ctlr, rs_drive[ctlr], PC);
|
||||
return SCPE_OK;
|
||||
|
||||
@ -218,12 +218,42 @@ DEBTAB crd_debug[] = {
|
||||
#define FMT_R 1 /* RIM10 */
|
||||
#define FMT_S 2 /* SAV */
|
||||
#define FMT_E 3 /* EXE */
|
||||
#define FMT_D 4 /* WAITS DMP */
|
||||
|
||||
#define EXE_DIR 01776 /* EXE directory */
|
||||
#define EXE_VEC 01775 /* EXE entry vec */
|
||||
#define EXE_PDV 01774 /* EXE ignored */
|
||||
#define EXE_END 01777 /* EXE end */
|
||||
|
||||
/* WAITS Octal dump loader.
|
||||
|
||||
Simple octal ASCII file, one word per line. All lines which don't
|
||||
start with 0-7 are ignored. Everything after the octal constant is
|
||||
also ignored.
|
||||
|
||||
*/
|
||||
t_stat load_dmp (FILE *fileref)
|
||||
{
|
||||
char buffer[100];
|
||||
char *p;
|
||||
uint32 addr = 075;
|
||||
uint64 data;
|
||||
|
||||
while (fgets((char *)buffer, 80, fileref) != 0) {
|
||||
p = (char *)buffer;
|
||||
if (*p >= '0' && *p <= '7') {
|
||||
data = 0;
|
||||
while (*p >= '0' && *p <= '7') {
|
||||
data = (data << 3) + *p - '0';
|
||||
p++;
|
||||
}
|
||||
M[addr++] = data;
|
||||
}
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* RIM10 loader
|
||||
|
||||
RIM10 format is a binary paper tape format (all data frames
|
||||
@ -493,12 +523,16 @@ else if (sim_switches & SWMASK ('S')) /* -s? */
|
||||
fmt = FMT_S;
|
||||
else if (sim_switches & SWMASK ('E')) /* -e? */
|
||||
fmt = FMT_E;
|
||||
else if (sim_switches & SWMASK ('D')) /* -d? */
|
||||
fmt = FMT_D;
|
||||
else if (match_ext (fnam, "RIM")) /* .RIM? */
|
||||
fmt = FMT_R;
|
||||
else if (match_ext (fnam, "SAV")) /* .SAV? */
|
||||
fmt = FMT_S;
|
||||
else if (match_ext (fnam, "EXE")) /* .EXE? */
|
||||
fmt = FMT_E;
|
||||
else if (match_ext (fnam, "DMP")) /* .DMP? */
|
||||
fmt = FMT_D;
|
||||
else {
|
||||
wc = sim_fread (&data, sizeof (uint64), 1, fileref);/* read hdr */
|
||||
if (wc == 0) /* error? */
|
||||
@ -520,6 +554,9 @@ switch (fmt) { /* case fmt */
|
||||
|
||||
case FMT_E: /* EXE */
|
||||
return load_exe (fileref);
|
||||
|
||||
case FMT_D: /* DMP */
|
||||
return load_dmp (fileref);
|
||||
}
|
||||
|
||||
printf ("Can't determine load file format\n");
|
||||
|
||||
@ -368,22 +368,22 @@ t_stat tu_devio(uint32 dev, uint64 *data) {
|
||||
return SCPE_OK;
|
||||
}
|
||||
if (tu_reg[ctlr] == 040) {
|
||||
*data = (t_uint64)(tu_read(ctlr, tu_drive[ctlr], 0) & 077);
|
||||
*data |= ((t_uint64)(df10->cia)) << 6;
|
||||
*data |= ((t_uint64)(tu_xfer_drive[ctlr])) << 18;
|
||||
*data = (uint64)(tu_read(ctlr, tu_drive[ctlr], 0) & 077);
|
||||
*data |= ((uint64)(df10->cia)) << 6;
|
||||
*data |= ((uint64)(tu_xfer_drive[ctlr])) << 18;
|
||||
} else if (tu_reg[ctlr] == 044) {
|
||||
*data = (t_uint64)tu_ivect[ctlr];
|
||||
*data = (uint64)tu_ivect[ctlr];
|
||||
if (tu_imode[ctlr])
|
||||
*data |= IRQ_KI10;
|
||||
else
|
||||
*data |= IRQ_KA10;
|
||||
} else if (tu_reg[ctlr] == 054) {
|
||||
*data = (t_uint64)(tu_rae[ctlr]);
|
||||
*data = (uint64)(tu_rae[ctlr]);
|
||||
} else if ((tu_reg[ctlr] & 040) == 0) {
|
||||
*data = (t_uint64)(tu_read(ctlr, tu_drive[ctlr], tu_reg[ctlr]) & 0177777);
|
||||
*data |= ((t_uint64)(tu_drive[ctlr])) << 18;
|
||||
*data = (uint64)(tu_read(ctlr, tu_drive[ctlr], tu_reg[ctlr]) & 0177777);
|
||||
*data |= ((uint64)(tu_drive[ctlr])) << 18;
|
||||
}
|
||||
*data |= ((t_uint64)(tu_reg[ctlr])) << 30;
|
||||
*data |= ((uint64)(tu_reg[ctlr])) << 30;
|
||||
sim_debug(DEBUG_DATAIO, dptr, "TU %03o DATI %012llo, %d %d PC=%06o\n",
|
||||
dev, *data, ctlr, tu_drive[ctlr], PC);
|
||||
return SCPE_OK;
|
||||
|
||||
@ -44,8 +44,8 @@
|
||||
#define MISS 0000000010000LL
|
||||
#define NUM_CHARS 0000000160000LL
|
||||
|
||||
t_uint64 dct_buf[NUM_DEVS_DCT];
|
||||
t_uint64 dct_acc[NUM_DEVS_DCT];
|
||||
uint64 dct_buf[NUM_DEVS_DCT];
|
||||
uint64 dct_acc[NUM_DEVS_DCT];
|
||||
|
||||
t_stat dct_devio(uint32 dev, uint64 *data);
|
||||
t_stat dct_svc(UNIT *);
|
||||
@ -189,7 +189,7 @@ dct_is_connect (int dev)
|
||||
|
||||
/* Read data from memory */
|
||||
int
|
||||
dct_read (int dev, t_uint64 *data, int cnt)
|
||||
dct_read (int dev, uint64 *data, int cnt)
|
||||
{
|
||||
int d = dev & 07;
|
||||
int u = (dev >> 3) & 07;
|
||||
@ -224,7 +224,7 @@ dct_read (int dev, t_uint64 *data, int cnt)
|
||||
|
||||
/* Write data to memory */
|
||||
int
|
||||
dct_write (int dev, t_uint64 *data, int cnt)
|
||||
dct_write (int dev, uint64 *data, int cnt)
|
||||
{
|
||||
int d = dev & 07;
|
||||
int u = (dev >> 3) & 07;
|
||||
|
||||
@ -188,7 +188,7 @@ DEVICE dsk_dev = {
|
||||
t_stat
|
||||
dsk_devio(uint32 dev, uint64 *data) {
|
||||
UNIT *uptr = &dsk_unit[(dsk_addr >> 16) & 03];
|
||||
t_uint64 res;
|
||||
uint64 res;
|
||||
int unit;
|
||||
int tmp;
|
||||
int drv;
|
||||
@ -197,9 +197,9 @@ dsk_devio(uint32 dev, uint64 *data) {
|
||||
|
||||
switch(dev & 3) {
|
||||
case CONI:
|
||||
res = ((t_uint64)(dsk_cmd) << 18);
|
||||
res |= ((t_uint64)(dsk_octflp)) << 10;
|
||||
res |= ((t_uint64)(dsk_status & RMASK));
|
||||
res = ((uint64)(dsk_cmd) << 18);
|
||||
res |= ((uint64)(dsk_octflp)) << 10;
|
||||
res |= ((uint64)(dsk_status & RMASK));
|
||||
if ((uptr->flags & UNIT_ATT) == 0)
|
||||
res |= OPR;
|
||||
if (uptr->flags & UNIT_WLK)
|
||||
@ -267,7 +267,7 @@ dsk_svc (UNIT *uptr)
|
||||
int cyl;
|
||||
int sec;
|
||||
int tmp, wc;
|
||||
t_uint64 data;
|
||||
uint64 data;
|
||||
DEVICE *dptr;
|
||||
t_stat err, r;
|
||||
|
||||
|
||||
@ -406,7 +406,7 @@ t_stat
|
||||
dtc_svc (UNIT *uptr)
|
||||
{
|
||||
int word;
|
||||
t_uint64 data = 0;
|
||||
uint64 data = 0;
|
||||
uint32 *fbuf = (uint32 *) uptr->filebuf; /* file buffer */
|
||||
int u = uptr-dtc_unit;
|
||||
int blk;
|
||||
@ -604,8 +604,8 @@ dtc_svc (UNIT *uptr)
|
||||
break;
|
||||
case FNC_RALL:
|
||||
case FNC_READ:
|
||||
data = ((t_uint64)fbuf[off]) << 18;
|
||||
data |= ((t_uint64)fbuf[off+1]);
|
||||
data = ((uint64)fbuf[off]) << 18;
|
||||
data |= ((uint64)fbuf[off+1]);
|
||||
if (dct_write(dtc_dct, &data, 6) == 0) {
|
||||
dtc_dtsb &= ~DTB_ACT;
|
||||
dtc_dtsb |= DTB_INCBLK|DTB_DONE;
|
||||
@ -670,7 +670,7 @@ dtc_svc (UNIT *uptr)
|
||||
sim_activate(uptr,DT_WRDTIM*2);
|
||||
uptr->DELAY -= 2;
|
||||
word = (uptr->DSTATE >> DTC_V_BLK) & DTC_M_BLK;
|
||||
data = (t_uint64)word;
|
||||
data = (uint64)word;
|
||||
uptr->DSTATE = DTC_RCHK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD) |
|
||||
(uptr->DSTATE & DTC_MOTMASK);
|
||||
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o rev reverse block %04o\n", u, word);
|
||||
@ -744,7 +744,7 @@ dtc_svc (UNIT *uptr)
|
||||
uptr->DSTATE = DTC_FCHK|(word << DTC_V_BLK) | (uptr->DSTATE & DTC_MOTMASK);
|
||||
sim_debug(DEBUG_DETAIL, &dtc_dev, "DTC %o forward block %04o %06o\n",
|
||||
u, word, dtc_dtsb);
|
||||
data = (t_uint64)word;
|
||||
data = (uint64)word;
|
||||
if ((dtc_dtsb & DTB_DLY) != 0) {
|
||||
if (uptr->DELAY < 0) {
|
||||
if (uptr->CMD & DTC_TIME)
|
||||
@ -861,8 +861,8 @@ dtc_svc (UNIT *uptr)
|
||||
break;
|
||||
case FNC_RALL:
|
||||
case FNC_READ:
|
||||
data = ((t_uint64)fbuf[off]) << 18;
|
||||
data |= (t_uint64)fbuf[off+1];
|
||||
data = ((uint64)fbuf[off]) << 18;
|
||||
data |= (uint64)fbuf[off+1];
|
||||
if (dct_write(dtc_dct, &data, 6) == 0)
|
||||
dtc_dtsb |= DTB_DONE;
|
||||
break;
|
||||
@ -1053,8 +1053,8 @@ dtc_boot(int32 unit_num, DEVICE * dptr)
|
||||
while (wc != 0777777) {
|
||||
wc = (wc + 1) & RMASK;
|
||||
addr = (addr + 1) & RMASK;
|
||||
word = ((t_uint64)fbuf[off++]) << 18;
|
||||
word |= (t_uint64)fbuf[off++];
|
||||
word = ((uint64)fbuf[off++]) << 18;
|
||||
word |= (uint64)fbuf[off++];
|
||||
if (addr < 020)
|
||||
FM[addr] = word;
|
||||
else
|
||||
|
||||
@ -279,7 +279,7 @@ mtc_devio(uint32 dev, uint64 *data) {
|
||||
switch(dev & 03) {
|
||||
case CONI:
|
||||
uptr = &mtc_unit[mtc_sel_unit];
|
||||
res = mtc_status | (t_uint64)(uptr->STATUS);
|
||||
res = mtc_status | (uint64)(uptr->STATUS);
|
||||
if ((uptr->flags & MTUF_WLK) != 0)
|
||||
res |= WRITE_LOCK;
|
||||
if (sim_tape_bot(uptr))
|
||||
@ -384,7 +384,7 @@ mtc_srv(UNIT * uptr)
|
||||
t_stat r = SCPE_ARG; /* Force error if not set */
|
||||
uint8 ch;
|
||||
int cc;
|
||||
t_uint64 hold_reg;
|
||||
uint64 hold_reg;
|
||||
int cc_max;
|
||||
int i;
|
||||
|
||||
@ -782,10 +782,10 @@ mtc_srv(UNIT * uptr)
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_uint64
|
||||
uint64
|
||||
mtc_read_word(UNIT *uptr) {
|
||||
int i, cc, ch;
|
||||
t_uint64 hold_reg = 0;
|
||||
int i, cc, ch;
|
||||
uint64 hold_reg = 0;
|
||||
|
||||
for(i = 0; i <= 4; i++) {
|
||||
cc = (8 * (3 - i)) + 4;
|
||||
@ -806,7 +806,7 @@ mtc_boot(int32 unit_num, DEVICE * dptr)
|
||||
UNIT *uptr = &dptr->units[unit_num];
|
||||
t_mtrlnt reclen;
|
||||
t_stat r;
|
||||
t_uint64 hold_reg;
|
||||
uint64 hold_reg;
|
||||
int wc, addr;
|
||||
|
||||
if ((uptr->flags & UNIT_ATT) == 0)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user