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KA10: Fixed bugs with Dectape that effected stand alone operation.
This commit is contained in:
Richard Cornwell
parent
9e48a862b4
commit
cf34c5a4dd
@ -339,6 +339,8 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
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break;
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case CONO:
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clr_interrupt(dev);
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clr_interrupt(dev|4);
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/* Copy over command and priority */
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dtsa &= ~0777;
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dtsa |= (*data & 0777);
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@ -352,6 +354,8 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
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for (i = 0; i < DT_NUMDR; i++) {
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dt_unit[i].u3 &= ~0700;
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}
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if ((*data & DTC_SEL) == 0)
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break;
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}
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if (*data & DTC_SEL) {
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dtsa |= *data & 07000;
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@ -393,6 +397,7 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
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if ((dt_unit[i].u4 & (DTC_MOT)) != 0) {
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dt_unit[i].u3 |= DTC_FNC_STOP;
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}
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dtsa &=~ (DTC_FWDRV|DTC_RVDRV);
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} else {
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/* Start the unit if not already running */
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dt_unit[i].u3 &= ~DTC_FNC_STOP;
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@ -402,23 +407,32 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
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if (!sim_is_active(&dt_unit[i]))
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sim_activate(&dt_unit[i], 10000);
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}
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dtsa &=~ (DTC_FWDRV|DTC_RVDRV);
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switch(*data & (DTC_FWDRV|DTC_RVDRV)) {
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case DTC_FWDRV:
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if (dt_unit[i].u4 & DTC_REV)
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dt_unit[i].u3 |= DTC_FNC_REV;
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if (dt_unit[i].u4 & DTC_REV) {
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dt_unit[i].u3 |= DTC_FNC_REV;
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dtsa |= (DTC_RVDRV);
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} else
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dtsa |= (DTC_FWDRV);
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break;
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case DTC_RVDRV:
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if ((dt_unit[i].u4 & DTC_REV) == 0)
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dt_unit[i].u3 |= DTC_FNC_REV;
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if ((dt_unit[i].u4 & DTC_REV) == 0) {
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dt_unit[i].u3 |= DTC_FNC_REV;
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dtsa |= (DTC_RVDRV);
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} else
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dtsa |= (DTC_FWDRV);
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break;
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case DTC_FWDRV|DTC_RVDRV:
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dt_unit[i].u3 |= DTC_FNC_REV;
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if ((dt_unit[i].u4 & DTC_REV) == 0)
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dtsa |= (DTC_RVDRV);
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else
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dtsa |= (DTC_FWDRV);
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break;
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}
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}
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}
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clr_interrupt(dev);
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clr_interrupt(dev|4);
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break;
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case DATAI:
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@ -456,13 +470,13 @@ t_stat dt_devio(uint32 dev, uint64 *data) {
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dt_unit[i].u3 |= DTC_FNC_STOP;
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}
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}
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if (*data & DTS_FUNC_STOP)
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dtsb |= DTB_STOP;
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dtsb = (uint64)((*data & (DTS_PAR_ERR|DTS_DATA_MISS|DTS_JOB_DONE| \
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DTS_ILL_OP|DTS_END_ZONE|DTS_BLK_MISS)) << 18);
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if (*data & DTS_FUNC_STOP)
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dtsb |= DTB_STOP;
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sim_debug(DEBUG_CONO, &dt_dev, "DTB %03o CONO %06o PC=%o\n",
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dev, (uint32)*data, PC);
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sim_debug(DEBUG_CONO, &dt_dev, "DTB %03o CONO %06o PC=%o DTSB=%012llo\n",
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dev, (uint32)*data, PC, dtsb);
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break;
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case DATAI|4:
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@ -586,6 +600,8 @@ if (uptr->u4 & DTC_MOT) {
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uptr->u5 = DTC_RBLK|(word << DTC_V_BLK);
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dtsb &= ~(DTB_CHK);
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dtsb |= DTB_IDL;
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if (dtsb & DTB_STOP)
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dtsa &= ~0700; /* Clear command */
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev forward block\n", u);
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switch (DTC_GETFNC(uptr->u3)) {
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case FNC_MOVE:
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@ -659,7 +675,7 @@ if (uptr->u4 & DTC_MOT) {
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if ((dtsb & DTB_STOP) == 0)
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dt_putword(&data);
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break;
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case FNC_WRIT:
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case FNC_WALL:
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if ((dtsb & DTB_STOP) == 0)
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@ -675,7 +691,7 @@ if (uptr->u4 & DTC_MOT) {
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dtsb &= ~DTB_DAT;
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dtsb |= DTB_FIN;
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}
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sim_debug(DEBUG_DETAIL, &dt_dev,
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sim_debug(DEBUG_DETAIL, &dt_dev,
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"DTA %o rev data word %o:%o %012llo %d %06o %06o\n",
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u, blk, word, data, off, fbuf[off], fbuf[off+1]);
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break;
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@ -685,6 +701,8 @@ if (uptr->u4 & DTC_MOT) {
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o rev reverse check\n", u);
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word = (uptr->u5 >> DTC_V_BLK) & DTC_M_BLK;
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uptr->u5 = DTC_BLOCK|(word << DTC_V_BLK)|(DTC_M_WORD << DTC_V_WORD);
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if (dtsb & DTB_STOP)
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dtsa &= ~0700; /* Clear command */
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if (DTC_GETUNI(dtsa) == u) {
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uptr->u3 &= 077077;
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uptr->u3 |= dtsa & 0700; /* Copy command */
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@ -807,6 +825,8 @@ if (uptr->u4 & DTC_MOT) {
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dtsb &= ~DTB_BLKRD;
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uptr->u5 &= ~7;
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uptr->u5 |= DTC_BLOCK; /* Move to datablock */
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if (dtsb & DTB_STOP)
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dtsa &= ~0700; /* Clear command */
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if (DTC_GETUNI(dtsa) == u) {
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uptr->u3 &= 077077;
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uptr->u3 |= dtsa & 0700; /* Copy command */
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@ -864,12 +884,16 @@ if (uptr->u4 & DTC_MOT) {
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data |= (t_uint64)fbuf[off+1];
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if ((dtsb & DTB_STOP) == 0)
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dt_putword(&data);
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else
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uptr->u3 &= 077077;
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break;
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case FNC_WRIT:
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if ((dtsb & DTB_STOP) == 0)
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dt_getword(&data, (word != DTC_M_WORD));
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else
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else {
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uptr->u3 &= 077077;
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data = dtdb;
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}
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fbuf[off] = (data >> 18) & RMASK;
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fbuf[off+1] = data & RMASK;
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uptr->hwmark = uptr->capac;
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@ -888,7 +912,7 @@ if (uptr->u4 & DTC_MOT) {
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case DTC_RCHK: /* In reverse checksum */
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sim_activate(uptr,30000);
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse check\n", u);
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse check\n", u);
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uptr->u5 &= ~(DTC_M_WORD << DTC_V_WORD) | 7;
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uptr->u5 |= DTC_RBLK; /* Move to end of block */
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dtsb &= ~(DTB_DAT|DTB_FIN);
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@ -910,7 +934,9 @@ if (uptr->u4 & DTC_MOT) {
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} else {
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uptr->u5 = DTC_FBLK|(word << DTC_V_BLK);
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}
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse block %o\n", u, word);
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if (dtsb & DTB_STOP)
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dtsa &= ~0700; /* Clear command */
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sim_debug(DEBUG_DETAIL, &dt_dev, "DTA %o reverse block %o\n", u, word);
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switch (DTC_GETFNC(uptr->u3)) {
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case FNC_MOVE:
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case FNC_WBLK:
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@ -921,11 +947,11 @@ if (uptr->u4 & DTC_MOT) {
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case FNC_WRIT:
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case FNC_READ:
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case FNC_WMRK:
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uptr->u3 &= 077077;
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dtsb |= DTB_DONE;
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if (dtsb & DTB_JOBENB)
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set_interrupt(DT_DEVNUM, dtsa);
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dtsb &= ~DTB_STOP;
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uptr->u3 &= 077077;
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dtsb |= DTB_DONE;
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if (dtsb & DTB_JOBENB)
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set_interrupt(DT_DEVNUM, dtsa);
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dtsb &= ~DTB_STOP;
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break;
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}
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if (dtsb & (DTB_PAR|DTB_MIS|DTB_ILL|DTB_END|DTB_INCBLK|DTB_MRKERR)) {
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@ -994,7 +1020,7 @@ dt_boot(int32 unit_num, DEVICE * dptr)
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else
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M[addr] = word;
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uptr->u5 = (1 << DTC_V_BLK) | DTC_BLOCK;
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uptr->u4 = DTC_MOT;
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uptr->u4 = DTC_MOT;
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sim_activate(uptr,30000);
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PC = word & RMASK;
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return SCPE_OK;
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@ -1005,7 +1031,13 @@ dt_boot(int32 unit_num, DEVICE * dptr)
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t_stat dt_reset (DEVICE *dptr)
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{
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int i;
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dtsb = dtsa = 0; /* clear status */
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for (i = 0; i < DT_NUMDR; i++) {
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if ((dt_unit[i].u4 & DTC_MOT) != 0)
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dt_unit[i].u3 |= DTC_FNC_STOP;
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}
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clr_interrupt(DT_DEVNUM);
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clr_interrupt(DT_DEVNUM|4);
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return SCPE_OK;
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