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SEL32: Correct mapping code to fix sysgen error.
Fix BU *1,1 condition code error Fix EXM to correct l/r h/w detection code
This commit is contained in:
James C. Bevier
Richard Cornwell
parent
869f56dcf3
commit
d5899f1dd5
@ -161,7 +161,7 @@
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/* CPU registers, map cache, spad, and other variables */
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int traceme = 0; /* dynamic trace function */
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int trstart = 9981910; /* count of when to start tracing */
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int trstart = 8000000; /* count of when to start tracing */
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//int trstart = 37; /* count of when to start tracing */
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int cpu_index; /* Current CPU running */
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uint32 PSD[2]; /* the PC for the instruction */
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@ -722,16 +722,19 @@ t_stat load_maps(uint32 thepsd[2])
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}
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/* num should be even at this point, so zero 32 bit word for remaining maps */
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if ((num/2) > HIWM) /* largerst number of maps loaded so far* */
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HIWM = num/2; /* yes, set new high watter mark */
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HIWM = num/2; /* yes, set new high water mark */
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// for (i = num/2; i < 32/2; i++) /* zero any remaining entries */
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for (i = num/2; i < HIWM; i++) /* zero any remaining entries */
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MAPC[i] = 0; /* clear the map entry to make not valid */
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HIWM = num/2; /* set new high water mark */
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return ALLOK; /* all cache is loaded, return OK */
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}
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else
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{
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#if 0 /* set to 1 for traceme to work */
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char n[9];
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uint32 dqe;
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#endif
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/* 32/27, 32/67, 32/87, 32/97 2KW maps */
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/* Concept/32 machine, 2KW maps */
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if ((modes & MAPMODE) == 0) { /* mapped mode? */
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@ -744,7 +747,11 @@ t_stat load_maps(uint32 thepsd[2])
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/* master process list is in 0xf3 of spad for concept */
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mpl = SPAD[0xf3] >> 2; /* get mpl from spad address */
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midl = M[mpl+cpix]; /* get mpl entry wd 0 for given cpix */
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msdl = M[mpl+cpix+1]; /* get mpl entry wd 0 for given cpix */
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msdl = M[mpl+cpix+1]; /* get mpl entry wd 1 for given cpix */
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#if 0 /* set to 1 for traceme to work */
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//traceme = trstart;
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if (traceme >= trstart) {
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dqe = M[0x8e8>>2];
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for (j=0; j<8; j++) {
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n[j] = (M[((dqe+0x18)>>2)+(j/4)] >> ((3-(j&7))*8)) & 0xff;
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@ -752,16 +759,27 @@ t_stat load_maps(uint32 thepsd[2])
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n[j] = 0x20;
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}
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n[8] = 0;
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// fprintf(stderr, "mapping SPAD PSD2 %.8x PSD2 %x mpl %x osmidl %x umidl %x C.CURR %x LMN %s\r\n",
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// SPAD[0xf5], PSD2, mpl, M[mpl], midl, dqe, n);
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/* if bit zero of mpl entry is set, use msd entry 0 first to load maps */
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if (midl & BIT0)
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{
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/* TODO do not load O/S if already loaded. Bit zero of O/S midl will be set by swapper */
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fprintf(stderr, "\r\nmapping SPAD[0xf3] %x mpl %x mpl0 %x mpl1 %x midl %x msdl %x cpix %x\r\n",
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SPAD[0xf3], mpl<<2, M[mpl], M[mpl+1], midl, msdl, cpix<<2);
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fprintf(stderr, "mapping SPAD PSD2 %.8x PSD2 %x mpl %x osmidl %x osmidl2 %x umidl %x C.CURR %x LMN %s\r\n",
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SPAD[0xf5], PSD2, mpl<<2, M[mpl], M[mpl+1], midl, dqe, n);
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}
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#endif
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/* load msd 0 maps first (O/S) */
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osmidl = M[mpl]; /* get midl 0 word address */
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/* if bit zero of cpix mpl entry is set, use msd entry 0 first to load maps */
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// if (((osmidl & BIT0) == 0) || (midl & BIT0)) {
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/* This test must be made (cpix == bpix) to allow sysgen to run without using a valid cpix */
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/* the cpix is zero indicating only load MSD 0 for the target system */
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/* bit 0 of msd 0 will be zero saying load the maps */
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if ((osmidl == midl) || (midl & BIT0)) {
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/* Do not load O/S if already loaded. Bit zero of O/S midl will be set by swapper on startup */
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/* load msd 0 maps first (O/S) */
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osmidl = M[mpl]; /* get midl 0 word address */
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spc = osmidl & MASK16; /* get 16 bit segment description count */
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if (osmidl & BIT0) { /* see f O/S already loaded */
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#if 0 /* set to 1 for traceme to work */
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fprintf(stderr, "mapping osmidl %x spc %x osmsdl %x usermidl %x\r\n", osmidl, spc, M[mpl+1], midl);
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#endif
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if (osmidl & BIT0) { /* see if O/S already loaded */
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num = spc; /* set the number of o/s maps loaded */
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goto skipos; /* skip load */
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}
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@ -781,8 +799,12 @@ t_stat load_maps(uint32 thepsd[2])
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if (num & 1) {
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/* entry going to rt hw, clean it first */
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map = (MAPC[num/2] & LMASK) | map; /* map is in rt hw */
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// fprintf(stderr, "mapping 0x%x O/S num 0x%x midl %x MAPC[%d] %x\r\n",
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// spc, num-1, (midl+(j/2))<<2, num/2, map);
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#if 0 /* set to 1 for traceme to work */
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if (traceme >= trstart) {
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fprintf(stderr, "mapping 0x%x O/S num 0x%x midl %x MAPC[%d] %x\r\n",
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spc, num-1, (midl+(j/2))<<2, num/2, map);
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}
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#endif
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}
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else {
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/* entry going to left hw, clean it first */
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@ -792,17 +814,28 @@ t_stat load_maps(uint32 thepsd[2])
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if (++num >= 2048)
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return MAPFLT; /* map loading overflow, map fault error */
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}
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#if 0
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#if 0 /* set to 1 for traceme to work */
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if (traceme >= trstart) {
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if (num & 1)
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fprintf(stderr, "mapping 0x%x O/S num 0x%x midl %x MAPC[%d] %x\r\n",
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spc, num-1, (midl+((spc-1)/2))<<2, num/2, map);
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}
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#endif
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}
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skipos:
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/* sysgen in mpx does not have a valid cpix MPL entry, only a bpix entry */
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/* that entry uses 64 map entries to map between target/host systems */
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/* When cpix in instruction is zero, just load the O/S specified by MSD 0 */
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if (cpix == 0)
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goto skipcpix; /* only load maps specified by msd 0 */
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/* now load cpix maps */
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midl = M[mpl+cpix]; /* get cpix midl word address */
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msdl = M[mpl+cpix+1]; /* get 24 bit real word address of midl */
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spc = midl & RMASK; /* get segment page count from msdl */
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#if 0 /* set to 1 for traceme to work */
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fprintf(stderr, "mapping usmidl %x spc %x msdl %x\r\n", midl, spc, msdl);
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#endif
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midl = M[mpl+cpix+1] & MASK24; /* get 24 bit real word address of midl */
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midl = midl>>2; /* get word address of midl */
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for (j = 0; j < spc; j++)
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@ -819,8 +852,12 @@ skipos:
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if (num & 1) {
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/* entry going to rt hw, clean it first */
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map = (MAPC[num/2] & LMASK) | map; /* map is in rt hw */
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// fprintf(stderr, "mapping 0x%x USER num 0x%x midl %x MAPC[%d] %x\r\n",
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// spc, num-1, (midl+(j/2))<<2, num/2, map);
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#if 0 /* set to 1 for traceme to work */
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if (traceme >= trstart) {
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fprintf(stderr, "mapping 0x%x USER num 0x%x midl %x MAPC[%d] %x\r\n",
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spc, num-1, (midl+(j/2))<<2, num/2, map);
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}
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#endif
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}
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else {
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/* entry going to left hw, clean it first */
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@ -834,20 +871,26 @@ skipos:
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/* we got here without map block found, return map fault error */
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if (num == 0)
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return MAPFLT; /* map fault error */
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skipcpix:
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if (num & 1) {
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/* left hw of map is good, zero right */
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map = (MAPC[num/2] & LMASK); /* clean rt hw */
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// if (spc != 0)
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// fprintf(stderr, "mapping 0x%x USER num 0x%x midl %x MAPC[%d] %x\r\n",
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// spc, num-1, (midl+((spc-1)/2))<<2, num/2, map);
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#if 0 /* set to 1 for traceme to work */
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if (traceme >= trstart) {
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if (spc != 0)
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fprintf(stderr, "mapping 0x%x USER num 0x%x midl %x MAPC[%d] %x\r\n",
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spc, num-1, (midl+((spc-1)/2))<<2, num/2, map);
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}
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#endif
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MAPC[num++/2] = map; /* store the map reg contents into cache */
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}
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/* num should be even at this point, so zero 32 bit words for remaining maps */
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if ((num/2) > HIWM) /* largerst number of maps loaded so far* */
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HIWM = num/2; /* yes, set new high watter mark */
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if ((num/2) > HIWM) /* largest number of maps loaded so far* */
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HIWM = num/2; /* yes, set new high water mark */
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// for (i = num/2; i < 2048/2; i++) /* zero any remaining entries */
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for (i = num/2; i < HIWM; i++) /* zero any remaining entries */
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MAPC[i] = 0; /* clear the map entry to make not valid */
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HIWM = num/2; /* set new high water mark */
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return ALLOK; /* all cache is loaded, retun OK */
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}
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}
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@ -1331,7 +1374,7 @@ exec:
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t &= ~IND; /* turn off IND bit to stop while loop */
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} else {
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/* non-extended mode, process new X, I, ADDR fields */
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// fprintf(stderr, "Indirect NE before addr %x contents %x\n", addr, temp);
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// fprintf(stderr, "Indirect NE before addr %x contents %x\n", addr, temp);
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addr = temp & MASK19; /* get just the addr */
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ix = (temp >> 21) & 3; /* get the index reg from indirect word */
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if (ix != 0)
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@ -1339,7 +1382,7 @@ exec:
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/* if no F or C bits set, use original, else new */
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if ((temp & F_BIT) || (addr & 3))
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FC = ((temp & F_BIT) ? 0x4 : 0) | (addr & 3);
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// fprintf(stderr, "Indirect NE after addr %x temp %x\n", addr, temp);
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// fprintf(stderr, "Indirect NE after addr %x temp %x\n", addr, temp);
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t = temp; /* go process next indirect location */
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}
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}
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@ -1465,7 +1508,9 @@ exec:
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TRAPME = PRIVHALT_TRAP; /* set the trap to take */
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goto newpsd; /* Privlege mode halt trap */
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}
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/*FIXME*/ reason = STOP_HALT; /* do halt for now */
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/*FIXME*/
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reason = STOP_HALT; /* do halt for now */
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return STOP_HALT; /* exit to simh for halt */
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break;
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case 0x1: /* WAIT */
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if (modes & PRIVBIT == 0) { /* must be privileged to wait */
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@ -2629,7 +2674,8 @@ src:
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goto newpsd; /* memory read error or map fault */
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IR = temp; /* get instruction from memory */
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if (FC == 2) /* see if right halfword specified */
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// if (FC == 2) /* see if right halfword specified */
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if (FC == 3) /* see if right halfword specified */
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IR <<= 16; /* move over the HW instruction */
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if ((IR & 0xFC7F0000) == 0xC8070000 ||
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(IR & 0xFF800000) == 0xA8000000 ||
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@ -2865,8 +2911,8 @@ doovr2:
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/* |-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------| */
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/* */
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case 0x6: /* SVC none - none */ /* Supervisor Call Trap */
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{
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#if 0
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{
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#if 0 /* set to 1 for traceme to work */
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int j;
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char n[9];
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uint32 dqe = M[0x8e8>>2];
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@ -2904,7 +2950,7 @@ doovr2:
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PSD1 = M[(t>>2)+2]; /* get new PSD 1 */
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PSD2 = (M[(t>>2)+3] & ~0x3ffc) | bc; /* get new PSD 2 w/old cpix */
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M[(t>>2)+4] = IR&0xFFF; /* store call number */
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#if 0
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#if 0 /* set to 1 for traceme to work */
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fprintf(stderr, "SVC @ %.8x SVC %x,%x PSD1 %.8x PSD2 %.8x SPAD PSD@ %x C.CURR %x LMN %s\r\n", OPSD1, temp2>>2, IR&0xFFF, PSD1, PSD2, SPAD[0xf5], dqe, n);
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fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
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fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
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@ -2937,7 +2983,7 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
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SPAD[0xf5] = PSD2; /* save the current PSD2 */
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goto newpsd; /* new psd loaded */
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}
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}
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break;
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case 0x7: /* EXR */
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@ -3082,6 +3128,7 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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TRAPME = ADDRSPEC_TRAP; /* bad address, error */
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goto newpsd; /* go execute the trap now */
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}
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temp2 = CC; /* save the old CC's */
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CC = PSD1 & 0x78000000; /* get CC's if any */
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switch(reg) {
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case 0: t = 1; break;
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@ -3097,7 +3144,8 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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if (t) { /* see if we are going to branch */
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/* we are taking the branch, set CC's if indirect, else leave'm */
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if (IR & IND) /* see if CCs from last indirect location are wanted */
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PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */
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// PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */
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PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last CCs */
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/* update the PSD with new address */
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PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */
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i_flags |= BT; /* we branched, so no PC update */
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@ -3114,6 +3162,7 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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TRAPME = ADDRSPEC_TRAP; /* bad address, error */
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goto newpsd; /* go execute the trap now */
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}
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temp2 = CC; /* save the old CC's */
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CC = PSD1 & 0x78000000; /* get CC's if any */
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switch(reg) {
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case 0: t = (GPR[4] & (0x8000 >> ((CC >> 27) & 0xf))) != 0; break;
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@ -3132,7 +3181,8 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe); /* set new PC */
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i_flags |= BT; /* we branched, so no PC update */
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if (IR & IND) /* see if CCs from last indirect location are wanted */
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PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */
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// PSD1 = (PSD1 & 0x87fffffe) | CC; /* insert last CCs */
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PSD1 = (PSD1 & 0x87fffffe) | temp2; /* insert last CCs */
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//fprintf(stderr, "BR t %.8x addr %.8x PSD1 %.8x\r\n", t, addr, PSD1);
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}
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break;
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@ -3142,7 +3192,7 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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if (dest != 0) { /* if reg is not 0, take the branch */
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/* we are taking the branch, set CC's if indirect, else leave'm */
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/* update the PSD with new address */
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#if 1
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#if 1 /* set to 1 to stop branch to self, for now */
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/* FIXME */ if (PC == (addr & 0x7FFFC)) { /* BIB to current PC, bump branch addr */
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addr += 4;
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// fprintf(stderr, "BI? stopping BIB $ addr %x PC %x\r\n", addr, PC);
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@ -3164,8 +3214,8 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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case 0x1: /* BL F880 */
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/* copy CC's from instruction and PC incremented by 4 */
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GPR[0] = ((PSD1 & 0x78000000) | (PSD1 & 0x7fffe)) + 4;
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if (IR & IND) /* see if CC from last indirect loacation are wanted */
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GPR[0] = (CC | (PSD1 & 0x7fffe)) + 4; /* set CC's and incremented PC */
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if (IR & IND) /* see if CC from last indirect loacation are wanted */
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GPR[0] = (GPR[0] & 0x87fffffe) | CC; /* insert last CCs */
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/* update the PSD with new address */
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PSD1 = (PSD1 & 0xff000000) | (addr & 0xfffffe);
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i_flags |= BT; /* we branched, so no PC update */
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@ -3174,11 +3224,12 @@ fprintf(stderr, "SVC %x,%x GPR[6] %x GPR[6] %x\r\n", temp2>>2, IR&0xfff, GPR[6],
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case 0x3: /* LPSD F980 */
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/* fall through */;
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case 0x5: /* LPSDCM FA80 */
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{
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#if 0
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{
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#if 0 /* set to 1 for traceme to work */
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int j;
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char n[9];
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uint32 dqe = M[0x8e8>>2];
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/* get task name blank filled */
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for (j=0; j<8; j++) {
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n[j] = (M[((dqe+0x18)>>2)+(j/4)] >> ((3-(j&7))*8)) & 0xff;
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if (n[j] == 0)
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@ -3217,16 +3268,14 @@ n[8] = 0;
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if (CPUSTATUS & 0x80) /* see if old mode is blocked */
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PSD2 |= 0x00004000; /* set to blocked state */
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/* TRY if cpix is zero, copy cpix from PSD2 in SPAD[0xf5] */
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if ((PSD2 & 0x3fff) == 0)
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PSD2 |= (SPAD[0xf5] & 0x3fff); /* use new cpix */
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if (opr & 0x0200) { /* Was it LPSDCM? */
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/* map bit must be on to load maps */
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if (PSD2 & MAPBIT) {
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#if 0
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#if 0 /* set to 1 for traceme to work */
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// FIXME DEBUG EDIT
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// if (n[0] == 'E' && n[1] == 'D' && n[2] == 'I' && n[3] == 'T')
|
||||
// FIXME DEBUG SYSGEN
|
||||
//if (n[0] == 'S' && n[1] == 'Y' && n[2] == 'S' && n[3] == 'G')
|
||||
// traceme = trstart; /* start tracing */
|
||||
traceme++; /* start trace */
|
||||
//if (traceme >= trstart) {
|
||||
@ -3250,17 +3299,23 @@ fprintf(stderr, "\r\n");
|
||||
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
|
||||
} else {
|
||||
/* LPSD */
|
||||
//traceme++; /* start trace */
|
||||
#if 0
|
||||
/* if cpix is zero, copy cpix from PSD2 in SPAD[0xf5] */
|
||||
if ((PSD2 & 0x3fff) == 0) {
|
||||
// fprintf(stderr, "LPSD using SPAD PSD2 %x instead of user PSD2 %x\r\n", SPAD[0xf5], PSD2);
|
||||
PSD2 |= (SPAD[0xf5] & 0x3fff); /* use new cpix */
|
||||
}
|
||||
#if 0 /* set to 1 for traceme to work */
|
||||
sim_debug(DEBUG_EXP, &cpu_dev, "LPSD PSD1 %x PSD2 %x CPUSTATUS %x\n", PSD1, PSD2, CPUSTATUS);
|
||||
if (traceme >= trstart) {
|
||||
fprintf(stderr, "LPSD PSD1 %x PSD2 %x SPAD PSD2 %x CPUSTATUS %x C.CURR %x LMN %s\r\n",
|
||||
PSD1, PSD2, SPAD[0xf5], CPUSTATUS, dqe, n);
|
||||
fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
|
||||
fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
|
||||
fprintf(stderr, "\r\n");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
/* TRAPME can be error from LPSDCM or OK here */
|
||||
skipinstr = 1; /* skip next interrupt test only once */
|
||||
goto newpsd; /* load the new psd */
|
||||
@ -3753,11 +3808,8 @@ sim_debug(DEBUG_EXP, &cpu_dev, "XIO DACI chan %x sa %x spad %.8x\n", chan, suba,
|
||||
TRAPME = AEXPCEPT_TRAP; /* trap the system now */
|
||||
goto newpsd; /* process the trap */
|
||||
}
|
||||
#if 0
|
||||
#if 0 /* set to 1 for traceme to work */
|
||||
/* no trap, so continue with next instruction */
|
||||
//PC = PSD1 & 0xfffffe; /* get 24 bit addr from PSD1 */
|
||||
// Get CCs from PSD1 and PC from original instruction */
|
||||
//if (traceme >= 4) {
|
||||
if (traceme >= trstart) {
|
||||
OPSD1 &= 0x87FFFFFE; /* clear the old CC's */
|
||||
OPSD1 |= PSD1 & 0x78000000; /* update the CC's in the PSD */
|
||||
@ -3856,8 +3908,9 @@ fprintf(stderr, "[][][][][][][][][][][] HALT TRAP [][][][][][][][][][][][]\r\n")
|
||||
|
||||
PSD2 &= ~RETMBIT; /* turn off retain bit in PSD2 */
|
||||
SPAD[0xf5] = PSD2; /* save the current PSD2 */
|
||||
#if 0
|
||||
if (TRAPME == UNDEFINSTR_TRAP) {
|
||||
#if 0 /* set to 1 for traceme to work */
|
||||
//if (TRAPME == UNDEFINSTR_TRAP || TRAPME == MAPFAULT_TRAP) {
|
||||
if (TRAPME == MAPFAULT_TRAP) {
|
||||
sim_debug(DEBUG_EXP, &cpu_dev, "TRAP PSD1 %x PSD2 %x CPUSTATUS %x\n", PSD1, PSD2, CPUSTATUS);
|
||||
fprintf(stderr, "TRAPS %x LOAD MAPS PSD1 %x PSD2 %x CPUSTATUS %x\r\n", TRAPME, PSD1, PSD2, CPUSTATUS);
|
||||
goto dumpi;
|
||||
@ -3872,7 +3925,7 @@ goto dumpi;
|
||||
/* we have a new PSD loaded via a LPSD or LPSDCM */
|
||||
/* TODO finish instruction history, then continue */
|
||||
/* update cpu status word too */
|
||||
#if 0
|
||||
#if 0 /* set to 1 for traceme to work */
|
||||
if (traceme >= trstart) {
|
||||
dumpi:
|
||||
OPSD1 &= 0x87FFFFFE; /* clear the old CC's */
|
||||
@ -3885,6 +3938,14 @@ fprint_inst(stderr, OIR, 0); /* display instruction */
|
||||
fprintf(stderr, " R0=%x R1=%x R2=%x R3=%x", GPR[0], GPR[1], GPR[2], GPR[3]);
|
||||
fprintf(stderr, " R4=%x R5=%x R6=%x R7=%x", GPR[4], GPR[5], GPR[6], GPR[7]);
|
||||
fprintf(stderr, "\r\n");
|
||||
fprintf(stderr, "Current MAPC\r\n");
|
||||
for (ix=0; ix<16; ix++) {
|
||||
fprintf(stderr, "MAP %x MPC %x\r\n", ix/2, MAPC[ix]);
|
||||
}
|
||||
fflush(stderr);
|
||||
//if (TRAPME == UNDEFINSTR_TRAP || TRAPME == MAPFAULT_TRAP)
|
||||
if (TRAPME == MAPFAULT_TRAP)
|
||||
return STOP_HALT; /* exit to simh for halt */
|
||||
}
|
||||
#endif
|
||||
sim_debug(DEBUG_DATA, &cpu_dev, "R0=%08x R1=%08x R2=%08x R3=%08x\n", GPR[0], GPR[1], GPR[2], GPR[3]);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user