mirror of
https://github.com/rcornwell/sims.git
synced 2026-01-13 23:35:30 +00:00
SEL32: Reformat files to use DOS format and no tabbing
This commit is contained in:
James C. Bevier
Richard Cornwell
parent
d3d4e808cc
commit
d9283178d9
2240
SEL32/sel32_chan.c
2240
SEL32/sel32_chan.c
File diff suppressed because it is too large
Load Diff
@ -50,14 +50,14 @@ t_stat rtc_reset (DEVICE *dptr);
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t_stat rtc_set_freq (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat rtc_show_freq (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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extern int irq_pend; /* go scan for pending int or I/O */
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extern uint32 INTS[]; /* interrupt control flags */
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extern uint32 SPAD[]; /* computer SPAD */
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extern uint32 M[]; /* system memory */
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extern int irq_pend; /* go scan for pending int or I/O */
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extern uint32 INTS[]; /* interrupt control flags */
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extern uint32 SPAD[]; /* computer SPAD */
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extern uint32 M[]; /* system memory */
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int32 rtc_pie = 0; /* rtc pulse ie */
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int32 rtc_tps = 60; /* rtc ticks/sec */
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int32 rtc_lvl = 0x18; /* rtc interrupt level */
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int32 rtc_pie = 0; /* rtc pulse ie */
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int32 rtc_tps = 60; /* rtc ticks/sec */
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int32 rtc_lvl = 0x18; /* rtc interrupt level */
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/* Clock data structures
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@ -106,14 +106,14 @@ DEVICE rtc_dev = {
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/* service clock signal from simulator */
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t_stat rtc_srv (UNIT *uptr)
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{
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if (rtc_pie) { /* set pulse intr */
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INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
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irq_pend = 1; /* make sure we scan for int */
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}
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// rtc_unit.wait = sim_rtcn_calb (rtc_tps, TMR_RTC); /* calibrate */
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// sim_activate (&rtc_unit, rtc_unit.wait); /* reactivate */
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sim_activate (&rtc_unit, 16667); /* reactivate */
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return SCPE_OK;
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if (rtc_pie) { /* set pulse intr */
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INTS[rtc_lvl] |= INTS_REQ; /* request the interrupt */
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irq_pend = 1; /* make sure we scan for int */
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}
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// rtc_unit.wait = sim_rtcn_calb (rtc_tps, TMR_RTC); /* calibrate */
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// sim_activate (&rtc_unit, rtc_unit.wait); /* reactivate */
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sim_activate (&rtc_unit, 16667); /* reactivate */
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return SCPE_OK;
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}
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/* Clock interrupt start/stop */
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@ -122,64 +122,64 @@ t_stat rtc_srv (UNIT *uptr)
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/* level = interrupt level */
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void rtc_setup(uint ss, uint32 level)
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{
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uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */
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rtc_lvl = level; /* save the interrupt level */
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uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */
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addr = M[addr>>2]; /* get the interrupt context block addr */
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uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */
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rtc_lvl = level; /* save the interrupt level */
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uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */
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addr = M[addr>>2]; /* get the interrupt context block addr */
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//fprintf(stderr, "rtc_setup called ss %x level %x SPAD %x icba %x\r\n", ss, level, val, addr);
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if (ss == 1) { /* starting? */
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INTS[level] |= INTS_ENAB; /* make sure enabled */
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SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
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INTS[level] |= INTS_REQ; /* request the interrupt */
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sim_activate(&rtc_unit, 20); /* start us off */
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} else {
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INTS[level] &= ~INTS_ENAB; /* make sure disabled */
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SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
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}
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rtc_pie = ss; /* set new state */
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if (ss == 1) { /* starting? */
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INTS[level] |= INTS_ENAB; /* make sure enabled */
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SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
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INTS[level] |= INTS_REQ; /* request the interrupt */
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sim_activate(&rtc_unit, 20); /* start us off */
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} else {
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INTS[level] &= ~INTS_ENAB; /* make sure disabled */
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SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
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}
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rtc_pie = ss; /* set new state */
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}
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/* Clock reset */
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t_stat rtc_reset(DEVICE *dptr)
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{
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rtc_pie = 0; /* disable pulse */
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rtc_unit.wait = sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* initialize clock calibration */
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sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */
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return SCPE_OK;
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rtc_pie = 0; /* disable pulse */
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rtc_unit.wait = sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* initialize clock calibration */
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sim_activate (&rtc_unit, rtc_unit.wait); /* activate unit */
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return SCPE_OK;
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}
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/* Set frequency */
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t_stat rtc_set_freq(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (cptr) /* if chars, bad */
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return SCPE_ARG; /* ARG error */
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if ((val != 50) && (val != 60) && (val != 100) && (val != 120))
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return SCPE_IERR; /* scope error */
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rtc_tps = val; /* set the new frequency */
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return SCPE_OK; /* we done */
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if (cptr) /* if chars, bad */
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return SCPE_ARG; /* ARG error */
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if ((val != 50) && (val != 60) && (val != 100) && (val != 120))
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return SCPE_IERR; /* scope error */
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rtc_tps = val; /* set the new frequency */
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return SCPE_OK; /* we done */
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}
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/* Show frequency */
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t_stat rtc_show_freq (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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/* print the cirrent frequency setting */
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if (rtc_tps < 100)
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fprintf (st, (rtc_tps == 50)? "50Hz": "60Hz");
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else
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fprintf (st, (rtc_tps == 100)? "100Hz": "120Hz");
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return SCPE_OK;
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/* print the cirrent frequency setting */
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if (rtc_tps < 100)
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fprintf (st, (rtc_tps == 50)? "50Hz": "60Hz");
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else
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fprintf (st, (rtc_tps == 100)? "100Hz": "120Hz");
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return SCPE_OK;
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}
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/************************************************************************/
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/* Interval Timer support */
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int32 itm_pie = 0; /* itm pulse enable */
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//int32 itm_tps = 38; /* itm 26041 ticks/sec = 38.4 us per tic */
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///int32 itm_tps = 48; /* itm 26041 ticks/sec = 38.4 us per tic */
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int32 itm_tps = 64; /* itm 26041 ticks/sec = 38.4 us per tic */
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int32 itm_lvl = 0x5f; /* itm interrupt level */
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int32 itm_cnt = 26041; /* value that we are downcounting */
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int32 itm_run = 0; /* set when timer running */
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int32 itm_pie = 0; /* itm pulse enable */
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//int32 itm_tps = 38; /* itm 26041 ticks/sec = 38.4 us per tic */
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///int32 itm_tps = 48; /* itm 26041 ticks/sec = 38.4 us per tic */
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int32 itm_tps = 64; /* itm 26041 ticks/sec = 38.4 us per tic */
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int32 itm_lvl = 0x5f; /* itm interrupt level */
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int32 itm_cnt = 26041; /* value that we are downcounting */
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int32 itm_run = 0; /* set when timer running */
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t_stat itm_srv (UNIT *uptr);
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t_stat itm_set_freq (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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t_stat itm_reset (DEVICE *dptr);
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@ -236,33 +236,33 @@ DEVICE itm_dev = {
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/* downcount the loaded value until zero and then cause interrupt */
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t_stat itm_srv (UNIT *uptr)
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{
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// uint32 val = SPAD[itm_lvl+0x80]; /* get SPAD value for interrupt vector */
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// uint32 addr = SPAD[0xf1] + (itm_lvl<<2); /* vector address in SPAD */
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// addr = M[addr>>2]; /* get the interrupt context block addr */
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// uint32 val = SPAD[itm_lvl+0x80]; /* get SPAD value for interrupt vector */
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// uint32 addr = SPAD[0xf1] + (itm_lvl<<2); /* vector address in SPAD */
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// addr = M[addr>>2]; /* get the interrupt context block addr */
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//fprintf(stderr, "itm_srv level %x itm_pie %x wait %x spad %x icba %x\r\n",
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// itm_lvl, itm_pie, itm_unit.wait, val, addr);
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// itm_lvl, itm_pie, itm_unit.wait, val, addr);
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/* count down about 48 instructions per tick ~38.4 us */
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/* we will be called once for each instructon */
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itm_unit.wait -= 1; /* subtract 1 from wait count */
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if (itm_unit.wait > 0)
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return SCPE_OK; /* not time yet */
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itm_unit.wait = itm_tps; /* reset wait count */
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/* count down about 48 instructions per tick ~38.4 us */
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/* we will be called once for each instructon */
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itm_unit.wait -= 1; /* subtract 1 from wait count */
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if (itm_unit.wait > 0)
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return SCPE_OK; /* not time yet */
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itm_unit.wait = itm_tps; /* reset wait count */
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if (itm_run) { /* see if timer running */
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itm_cnt--; /* down count by one */
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if ((itm_cnt == 0) && itm_pie) { /* see if reached 0 yet */
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// if (itm_cnt == 0) { /* see if reached 0 yet */
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if (itm_run) { /* see if timer running */
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itm_cnt--; /* down count by one */
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if ((itm_cnt == 0) && itm_pie) { /* see if reached 0 yet */
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// if (itm_cnt == 0) { /* see if reached 0 yet */
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//fprintf(stderr, "itm_srv REQ itm_pie %x wait %x itm_cnt %x\r\n", itm_pie, itm_unit.wait, itm_cnt);
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INTS[itm_lvl] |= INTS_REQ; /* request the interrupt on zero value */
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irq_pend = 1; /* make sure we scan for int */
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}
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}
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INTS[itm_lvl] |= INTS_REQ; /* request the interrupt on zero value */
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irq_pend = 1; /* make sure we scan for int */
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}
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}
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#if 0
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itm_unit.wait = sim_rtcn_calb (itm_tps, TMR_ITM); /* calibrate */
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sim_activate (&itm_unit, itm_unit.wait); /* reactivate */
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itm_unit.wait = sim_rtcn_calb (itm_tps, TMR_ITM); /* calibrate */
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sim_activate (&itm_unit, itm_unit.wait); /* reactivate */
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#endif
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return SCPE_OK;
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return SCPE_OK;
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}
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/* ITM read/load function called from CD command processing */
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@ -275,37 +275,37 @@ t_stat itm_srv (UNIT *uptr)
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/* ret = return value read from timer */
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int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
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{
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uint32 temp;
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// uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */
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uint32 temp;
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// uint32 val = SPAD[level+0x80]; /* get SPAD value for interrupt vector */
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// itm_lvl = level; /* save the interrupt level */
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// uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */
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// addr = M[addr>>2]; /* get the interrupt context block addr */
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// itm_lvl = level; /* save the interrupt level */
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// uint32 addr = SPAD[0xf1] + (level<<2); /* vector address in SPAD */
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// addr = M[addr>>2]; /* get the interrupt context block addr */
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//fprintf(stderr, "itm_rdwr called ss %x level %x SPAD %x icba %x\r\n", ss, level, val, addr);
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//fprintf(stderr, "itm_rdwr called cmd %x count %x (%d) level %x return cnt %x (%d)\r\n",
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// cmd, cnt, cnt, level, itm_cnt, itm_cnt);
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switch (cmd) {
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case 0x39: /* load timer with new value and start*/
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if (cnt < 0)
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cnt = 26042; /* TRY ??*/
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itm_cnt = cnt; /* load timer with value from user to down count */
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itm_run = 1; /* start timer */
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return 0; /* does not matter, no value returned */
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case 0x60: /* read and stop timer */
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temp = itm_cnt; /* get timer value and stop timer */
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itm_run = 0; /* stop timer */
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// itm_cnt = 0; /* reset with timer value from user to down count */
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return temp; /* return current count value */
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case 0x79: /* read the current timer value */
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temp = itm_cnt; /* get timer value, load new value and start timer */
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itm_cnt = cnt; /* load timer with value from user to down count */
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itm_run = 1; /* start timer */
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return temp; /* return current count value */
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case 0x40: /* read the current timer value */
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return itm_cnt; /* return current count value */
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break;
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}
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return 0; /* does not matter, no value returned */
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// cmd, cnt, cnt, level, itm_cnt, itm_cnt);
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switch (cmd) {
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case 0x39: /* load timer with new value and start*/
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if (cnt < 0)
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cnt = 26042; /* TRY ??*/
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itm_cnt = cnt; /* load timer with value from user to down count */
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itm_run = 1; /* start timer */
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return 0; /* does not matter, no value returned */
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case 0x60: /* read and stop timer */
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temp = itm_cnt; /* get timer value and stop timer */
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itm_run = 0; /* stop timer */
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// itm_cnt = 0; /* reset with timer value from user to down count */
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return temp; /* return current count value */
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case 0x79: /* read the current timer value */
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temp = itm_cnt; /* get timer value, load new value and start timer */
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itm_cnt = cnt; /* load timer with value from user to down count */
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itm_run = 1; /* start timer */
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return temp; /* return current count value */
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case 0x40: /* read the current timer value */
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return itm_cnt; /* return current count value */
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break;
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}
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return 0; /* does not matter, no value returned */
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}
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/* Clock interrupt start/stop */
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@ -314,54 +314,54 @@ int32 itm_rdwr(uint32 cmd, int32 cnt, uint32 level)
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/* level = interrupt level */
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void itm_setup(uint ss, uint32 level)
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{
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itm_lvl = level; /* save the interrupt level */
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itm_lvl = level; /* save the interrupt level */
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// fprintf(stderr, "itm_setup called ss %x level %x\r\n", ss, level);
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if (ss == 1) { /* starting? */
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INTS[level] |= INTS_ENAB; /* make sure enabled */
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SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
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INTS[level] |= INTS_REQ; /* request the interrupt */
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itm_cnt = 26042; /* start with 1 sec */
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itm_run = 0; /* not running yet */
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/// sim_activate(&itm_unit, 48); /* start us off */
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} else {
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INTS[level] &= ~INTS_ENAB; /* make sure disabled */
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SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
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}
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itm_pie = ss; /* set new state */
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if (ss == 1) { /* starting? */
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INTS[level] |= INTS_ENAB; /* make sure enabled */
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SPAD[level+0x80] |= SINT_ENAB; /* in spad too */
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INTS[level] |= INTS_REQ; /* request the interrupt */
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itm_cnt = 26042; /* start with 1 sec */
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itm_run = 0; /* not running yet */
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/// sim_activate(&itm_unit, 48); /* start us off */
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} else {
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INTS[level] &= ~INTS_ENAB; /* make sure disabled */
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SPAD[level+0x80] &= ~SINT_ENAB; /* in spad too */
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}
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itm_pie = ss; /* set new state */
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}
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/* Clock reset */
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t_stat itm_reset (DEVICE *dptr)
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{
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// int intlev = 0x5f; /* interrupt level for itm */
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// int intlev = 0x5f; /* interrupt level for itm */
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//fprintf(stderr, "itm_reset called\r\n");
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itm_pie = 0; /* disable pulse */
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itm_cnt = 26042; /* start with 1 sec */
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itm_run = 0; /* not running yet */
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itm_pie = 0; /* disable pulse */
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itm_cnt = 26042; /* start with 1 sec */
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itm_run = 0; /* not running yet */
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#if 0
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rtc_unit.wait = sim_rtcn_init (itm_unit.wait, TMR_ITM); /* initialize clock calibration */
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sim_activate (&itm_unit, itm_unit.wait); /* activate unit */
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rtc_unit.wait = sim_rtcn_init (itm_unit.wait, TMR_ITM); /* initialize clock calibration */
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sim_activate (&itm_unit, itm_unit.wait); /* activate unit */
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#endif
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return SCPE_OK;
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return SCPE_OK;
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}
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/* Set frequency */
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t_stat itm_set_freq (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
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{
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if (cptr) /* if chars, bad */
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return SCPE_ARG; /* ARG error */
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if ((val != 384) && (val != 768))
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return SCPE_IERR; /* scope error */
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itm_tps = val/10; /* set the new frequency */
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return SCPE_OK; /* we done */
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if (cptr) /* if chars, bad */
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return SCPE_ARG; /* ARG error */
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if ((val != 384) && (val != 768))
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return SCPE_IERR; /* scope error */
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itm_tps = val/10; /* set the new frequency */
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return SCPE_OK; /* we done */
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}
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/* Show frequency */
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t_stat itm_show_freq (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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{
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/* print the cirrent frequency setting */
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fprintf (st, (itm_tps == 38)? "38.4us": "76.8us");
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return SCPE_OK;
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/* print the cirrent frequency setting */
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fprintf (st, (itm_tps == 38)? "38.4us": "76.8us");
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return SCPE_OK;
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}
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#endif
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1102
SEL32/sel32_com.c
1102
SEL32/sel32_com.c
File diff suppressed because it is too large
Load Diff
@ -35,112 +35,112 @@
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#ifdef NUM_DEVS_CON
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extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat show_dev_addr(FILE *st, UNIT * uptr, int32 v, CONST void *desc);
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extern void chan_end(uint16 chan, uint8 flags);
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extern int chan_read_byte(uint16 chan, uint8 *data);
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extern int chan_write_byte(uint16 chan, uint8 *data);
|
||||
extern void set_devattn(uint16 addr, uint8 flags);
|
||||
extern void post_extirq(void);
|
||||
extern uint32 attention_trap; /* set when trap is requested */
|
||||
extern void set_devwake(uint16 addr, uint8 flags);
|
||||
extern t_stat set_dev_addr(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
|
||||
extern t_stat show_dev_addr(FILE *st, UNIT * uptr, int32 v, CONST void *desc);
|
||||
extern void chan_end(uint16 chan, uint8 flags);
|
||||
extern int chan_read_byte(uint16 chan, uint8 *data);
|
||||
extern int chan_write_byte(uint16 chan, uint8 *data);
|
||||
extern void set_devattn(uint16 addr, uint8 flags);
|
||||
extern void post_extirq(void);
|
||||
extern uint32 attention_trap; /* set when trap is requested */
|
||||
extern void set_devwake(uint16 addr, uint8 flags);
|
||||
|
||||
/* Held in u3 is the device command and status */
|
||||
#define CON_INCH 0x00 /* Initialize channel command */
|
||||
#define CON_WR 0x01 /* Write console */
|
||||
#define CON_RD 0x02 /* Read console */
|
||||
#define CON_NOP 0x03 /* No op command */
|
||||
#define CON_SNS 0x04 /* Sense command */
|
||||
#define CON_ECHO 0x0a /* Read with Echo */
|
||||
#define CON_CON 0x1f /* connect line */
|
||||
#define CON_DIS 0x23 /* disconnect line */
|
||||
#define CON_RWD 0x37 /* TOF and write line */
|
||||
#define CON_INCH 0x00 /* Initialize channel command */
|
||||
#define CON_WR 0x01 /* Write console */
|
||||
#define CON_RD 0x02 /* Read console */
|
||||
#define CON_NOP 0x03 /* No op command */
|
||||
#define CON_SNS 0x04 /* Sense command */
|
||||
#define CON_ECHO 0x0a /* Read with Echo */
|
||||
#define CON_CON 0x1f /* connect line */
|
||||
#define CON_DIS 0x23 /* disconnect line */
|
||||
#define CON_RWD 0x37 /* TOF and write line */
|
||||
|
||||
#define CON_MSK 0xff /* Command mask */
|
||||
#define CON_MSK 0xff /* Command mask */
|
||||
|
||||
/* Status held in u3 */
|
||||
/* controller/unit address in upper 16 bits */
|
||||
#define CON_INPUT 0x100 /* Input ready for unit */
|
||||
#define CON_CR 0x200 /* Output at beginning of line */
|
||||
#define CON_REQ 0x400 /* Request key pressed */
|
||||
#define CON_EKO 0x800 /* Echo input character */
|
||||
#define CON_OUTPUT 0x1000 /* Output ready for unit */
|
||||
#define CON_READ 0x2000 /* Read mode selected */
|
||||
#define CON_INPUT 0x100 /* Input ready for unit */
|
||||
#define CON_CR 0x200 /* Output at beginning of line */
|
||||
#define CON_REQ 0x400 /* Request key pressed */
|
||||
#define CON_EKO 0x800 /* Echo input character */
|
||||
#define CON_OUTPUT 0x1000 /* Output ready for unit */
|
||||
#define CON_READ 0x2000 /* Read mode selected */
|
||||
|
||||
/* Input buffer pointer held in u4 */
|
||||
|
||||
/* in u5 packs sense byte 0,1 and 3 */
|
||||
/* Sense byte 0 */
|
||||
#define SNS_CMDREJ 0x80000000 /* Command reject */
|
||||
#define SNS_INTVENT 0x40000000 /* Unit intervention required */
|
||||
#define SNS_CMDREJ 0x80000000 /* Command reject */
|
||||
#define SNS_INTVENT 0x40000000 /* Unit intervention required */
|
||||
/* sense byte 3 */
|
||||
#define SNS_RDY 0x80 /* device ready */
|
||||
#define SNS_ONLN 0x40 /* device online */
|
||||
//#define SNS_DSR 0x04 /* data set ready */
|
||||
#define SNS_DSR 0x08 /* data set ready */
|
||||
#define SNS_DCD 0x04 /* data carrier detect */
|
||||
#define SNS_RDY 0x80 /* device ready */
|
||||
#define SNS_ONLN 0x40 /* device online */
|
||||
//#define SNS_DSR 0x04 /* data set ready */
|
||||
#define SNS_DSR 0x08 /* data set ready */
|
||||
#define SNS_DCD 0x04 /* data carrier detect */
|
||||
|
||||
/* std devices. data structures
|
||||
con_dev Console device descriptor
|
||||
con_unit Console unit descriptor
|
||||
con_reg Console register list
|
||||
con_mod Console modifiers list
|
||||
con_dev Console device descriptor
|
||||
con_unit Console unit descriptor
|
||||
con_reg Console register list
|
||||
con_mod Console modifiers list
|
||||
*/
|
||||
|
||||
struct _con_data
|
||||
{
|
||||
uint8 ibuff[145]; /* Input line buffer */
|
||||
uint8 incnt; /* char count */
|
||||
uint8 ibuff[145]; /* Input line buffer */
|
||||
uint8 incnt; /* char count */
|
||||
}
|
||||
con_data[NUM_UNITS_CON];
|
||||
|
||||
uint32 atbuf=0; /* attention buffer */
|
||||
uint32 atbuf=0; /* attention buffer */
|
||||
|
||||
/* forward definitions */
|
||||
uint8 con_startcmd(UNIT *, uint16, uint8);
|
||||
void con_ini(UNIT *, t_bool);
|
||||
t_stat con_srvi(UNIT *);
|
||||
t_stat con_srvo(UNIT *);
|
||||
t_stat con_reset(DEVICE *);
|
||||
t_stat con_attach(UNIT *, char *);
|
||||
t_stat con_detach(UNIT *);
|
||||
void con_ini(UNIT *, t_bool);
|
||||
t_stat con_srvi(UNIT *);
|
||||
t_stat con_srvo(UNIT *);
|
||||
t_stat con_reset(DEVICE *);
|
||||
t_stat con_attach(UNIT *, char *);
|
||||
t_stat con_detach(UNIT *);
|
||||
|
||||
/* channel program information */
|
||||
CHANP con_chp[NUM_UNITS_CON] = {0};
|
||||
CHANP con_chp[NUM_UNITS_CON] = {0};
|
||||
|
||||
MTAB con_mod[] = {
|
||||
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "DEV", "DEV", &set_dev_addr, &show_dev_addr, NULL},
|
||||
{0}
|
||||
MTAB con_mod[] = {
|
||||
{MTAB_XTD | MTAB_VUN | MTAB_VALR, 0, "DEV", "DEV", &set_dev_addr, &show_dev_addr, NULL},
|
||||
{0}
|
||||
};
|
||||
|
||||
UNIT con_unit[] = {
|
||||
{UDATA(con_srvi, UNIT_ATT, 0), 0, UNIT_ADDR(0x7EFC)}, /* Input */
|
||||
{UDATA(con_srvo, UNIT_ATT, 0), 0, UNIT_ADDR(0x7EFD)}, /* Output */
|
||||
UNIT con_unit[] = {
|
||||
{UDATA(con_srvi, UNIT_ATT, 0), 0, UNIT_ADDR(0x7EFC)}, /* Input */
|
||||
{UDATA(con_srvo, UNIT_ATT, 0), 0, UNIT_ADDR(0x7EFD)}, /* Output */
|
||||
};
|
||||
|
||||
//DIB con_dib = {NULL, con_startcmd, NULL, NULL, NULL, con_ini, con_unit, con_chp, NUM_UNITS_CON, 0xf, 0x7e00, 0, 0, 0};
|
||||
DIB con_dib = {
|
||||
NULL, /* uint8 (*pre_io)(UNIT *uptr, uint16 chan)*/ /* Start I/O */
|
||||
con_startcmd, /* uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd)*/ /* Start a command */
|
||||
NULL, /* uint8 (*halt_io)(UNIT *uptr) */ /* Stop I/O */
|
||||
NULL, /* uint8 (*test_io)(UNIT *uptr) */ /* Test I/O */
|
||||
NULL, /* uint8 (*post_io)(UNIT *uptr) */ /* Post I/O */
|
||||
con_ini, /* void (*dev_ini)(UNIT *, t_bool) */ /* init function */
|
||||
con_unit, /* UNIT* units */ /* Pointer to units structure */
|
||||
con_chp, /* CHANP* chan_prg */ /* Pointer to chan_prg structure */
|
||||
NUM_UNITS_CON, /* uint8 numunits */ /* number of units defined */
|
||||
0x0f, /* uint8 mask */ /* 2 devices - device mask */
|
||||
0x7e00, /* uint16 chan_addr */ /* parent channel address */
|
||||
0, /* uint32 chan_fifo_in */ /* fifo input index */
|
||||
0, /* uint32 chan_fifo_out */ /* fifo output index */
|
||||
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
|
||||
//DIB con_dib = {NULL, con_startcmd, NULL, NULL, NULL, con_ini, con_unit, con_chp, NUM_UNITS_CON, 0xf, 0x7e00, 0, 0, 0};
|
||||
DIB con_dib = {
|
||||
NULL, /* uint8 (*pre_io)(UNIT *uptr, uint16 chan)*/ /* Start I/O */
|
||||
con_startcmd, /* uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd)*/ /* Start a command */
|
||||
NULL, /* uint8 (*halt_io)(UNIT *uptr) */ /* Stop I/O */
|
||||
NULL, /* uint8 (*test_io)(UNIT *uptr) */ /* Test I/O */
|
||||
NULL, /* uint8 (*post_io)(UNIT *uptr) */ /* Post I/O */
|
||||
con_ini, /* void (*dev_ini)(UNIT *, t_bool) */ /* init function */
|
||||
con_unit, /* UNIT* units */ /* Pointer to units structure */
|
||||
con_chp, /* CHANP* chan_prg */ /* Pointer to chan_prg structure */
|
||||
NUM_UNITS_CON, /* uint8 numunits */ /* number of units defined */
|
||||
0x0f, /* uint8 mask */ /* 2 devices - device mask */
|
||||
0x7e00, /* uint16 chan_addr */ /* parent channel address */
|
||||
0, /* uint32 chan_fifo_in */ /* fifo input index */
|
||||
0, /* uint32 chan_fifo_out */ /* fifo output index */
|
||||
0, /* uint32 chan_fifo[FIFO_SIZE] */ /* interrupt status fifo for channel */
|
||||
};
|
||||
|
||||
DEVICE con_dev = {
|
||||
"CON", con_unit, NULL, con_mod,
|
||||
NUM_UNITS_CON, 8, 15, 1, 8, 8,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
&con_dib, DEV_UADDR|DEV_DISABLE|DEV_DEBUG, 0, dev_debug
|
||||
DEVICE con_dev = {
|
||||
"CON", con_unit, NULL, con_mod,
|
||||
NUM_UNITS_CON, 8, 15, 1, 8, 8,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
&con_dib, DEV_UADDR|DEV_DISABLE|DEV_DEBUG, 0, dev_debug
|
||||
};
|
||||
|
||||
/*
|
||||
@ -148,91 +148,91 @@ DEVICE con_dev = {
|
||||
*/
|
||||
/* initialize the console chan/unit */
|
||||
void con_ini(UNIT *uptr, t_bool f) {
|
||||
int unit = (uptr - con_unit); /* unit 0 */
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
int unit = (uptr - con_unit); /* unit 0 */
|
||||
DEVICE *dptr = find_dev_from_unit(uptr);
|
||||
|
||||
con_data[unit].incnt = 0; /* no input data */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
sim_activate(uptr, 1000); /* time increment */
|
||||
con_data[unit].incnt = 0; /* no input data */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
sim_activate(uptr, 1000); /* time increment */
|
||||
}
|
||||
|
||||
/* start an I/O operation */
|
||||
uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
|
||||
int unit = (uptr - con_unit); /* unit 0,1 */
|
||||
uint8 ch;
|
||||
int unit = (uptr - con_unit); /* unit 0,1 */
|
||||
uint8 ch;
|
||||
|
||||
if ((uptr->u3 & CON_MSK) != 0) /* is unit busy */
|
||||
return SNS_BSY; /* yes, return busy */
|
||||
if ((uptr->u3 & CON_MSK) != 0) /* is unit busy */
|
||||
return SNS_BSY; /* yes, return busy */
|
||||
|
||||
/* process the commands */
|
||||
switch (cmd & 0xFF) {
|
||||
case CON_INCH: /* 0x00 */ /* INCH command */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd INCH\n", chan);
|
||||
return SNS_CHNEND|SNS_DEVEND; /* all is well */
|
||||
break;
|
||||
/* process the commands */
|
||||
switch (cmd & 0xFF) {
|
||||
case CON_INCH: /* 0x00 */ /* INCH command */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd INCH\n", chan);
|
||||
return SNS_CHNEND|SNS_DEVEND; /* all is well */
|
||||
break;
|
||||
|
||||
case CON_RWD: /* 0x37 */ /* TOF and write line */
|
||||
case CON_WR: /* 0x01 */ /* Write command */
|
||||
/* if input requested for output device, give error */
|
||||
if (unit == 0) {
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
}
|
||||
uptr->u3 &= LMASK; /* leave only chsa */
|
||||
uptr->u3 |= (cmd & CON_MSK); /* save command */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
sim_activate(uptr, 20); /* TRY 06-09-18 */
|
||||
return 0; /* no status change */
|
||||
break;
|
||||
case CON_RWD: /* 0x37 */ /* TOF and write line */
|
||||
case CON_WR: /* 0x01 */ /* Write command */
|
||||
/* if input requested for output device, give error */
|
||||
if (unit == 0) {
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
}
|
||||
uptr->u3 &= LMASK; /* leave only chsa */
|
||||
uptr->u3 |= (cmd & CON_MSK); /* save command */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
sim_activate(uptr, 20); /* TRY 06-09-18 */
|
||||
return 0; /* no status change */
|
||||
break;
|
||||
|
||||
case CON_RD: /* Read command */
|
||||
case CON_ECHO: /* Read command w/ECHO */
|
||||
/* if output requested for input device, give error */
|
||||
if (unit == 1) {
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
}
|
||||
uptr->u3 &= LMASK; /* leave only chsa */
|
||||
uptr->u3 |= (cmd & CON_MSK); /* save command */
|
||||
if (cmd == CON_ECHO) /* echo command? */
|
||||
uptr->u3 |= CON_EKO; /* save echo status */
|
||||
uptr->u3 |= CON_READ; /* show read mode */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
uptr->u4 = 0; /* no I/O yet */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
return 0;
|
||||
break;
|
||||
case CON_RD: /* Read command */
|
||||
case CON_ECHO: /* Read command w/ECHO */
|
||||
/* if output requested for input device, give error */
|
||||
if (unit == 1) {
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
}
|
||||
uptr->u3 &= LMASK; /* leave only chsa */
|
||||
uptr->u3 |= (cmd & CON_MSK); /* save command */
|
||||
if (cmd == CON_ECHO) /* echo command? */
|
||||
uptr->u3 |= CON_EKO; /* save echo status */
|
||||
uptr->u3 |= CON_READ; /* show read mode */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
uptr->u4 = 0; /* no I/O yet */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case CON_NOP: /* NOP has do nothing */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
case CON_NOP: /* NOP has do nothing */
|
||||
uptr->u5 = SNS_RDY|SNS_ONLN; /* status is online & ready */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
|
||||
case CON_CON: /* Connect, return Data Set ready */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x NOP\n", chan, cmd);
|
||||
uptr->u5 |= (SNS_DSR|SNS_DCD); /* Data set ready, Data Carrier detected */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
case CON_CON: /* Connect, return Data Set ready */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x NOP\n", chan, cmd);
|
||||
uptr->u5 |= (SNS_DSR|SNS_DCD); /* Data set ready, Data Carrier detected */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
|
||||
case CON_DIS: /* NOP has do nothing */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x NOP\n", chan, cmd);
|
||||
uptr->u5 &= ~(SNS_DSR|SNS_DCD); /* Data set not ready */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
case CON_DIS: /* NOP has do nothing */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd %x NOP\n", chan, cmd);
|
||||
uptr->u5 &= ~(SNS_DSR|SNS_DCD); /* Data set not ready */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
|
||||
case CON_SNS: /* Sense */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd Sense %02x\n", chan, uptr->u5);
|
||||
/* value 4 is Data Set Ready */
|
||||
/* value 5 is Data carrier detected n/u */
|
||||
ch = uptr->u5; /* status */
|
||||
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
case CON_SNS: /* Sense */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_startcmd %x: Cmd Sense %02x\n", chan, uptr->u5);
|
||||
/* value 4 is Data Set Ready */
|
||||
/* value 5 is Data carrier detected n/u */
|
||||
ch = uptr->u5; /* status */
|
||||
chan_write_byte(GET_UADDR(uptr->u3), &ch); /* write status */
|
||||
return SNS_CHNEND|SNS_DEVEND; /* good return */
|
||||
break;
|
||||
|
||||
default: /* invalid command */
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
break;
|
||||
default: /* invalid command */
|
||||
uptr->u5 |= SNS_CMDREJ; /* command rejected */
|
||||
return SNS_CHNEND|SNS_DEVEND|SNS_UNITCHK; /* unit check */
|
||||
break;
|
||||
}
|
||||
|
||||
if (uptr->u5 & (~(SNS_RDY|SNS_ONLN|SNS_DSR)))
|
||||
@ -242,128 +242,128 @@ uint8 con_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) {
|
||||
|
||||
/* Handle output transfers for console */
|
||||
t_stat con_srvo(UNIT *uptr) {
|
||||
uint16 chsa = GET_UADDR(uptr->u3);
|
||||
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
|
||||
int cmd = uptr->u3 & CON_MSK;
|
||||
uint8 ch;
|
||||
uint16 chsa = GET_UADDR(uptr->u3);
|
||||
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
|
||||
int cmd = uptr->u3 & CON_MSK;
|
||||
uint8 ch;
|
||||
|
||||
if ((cmd == CON_WR) || (cmd == CON_RWD)) {
|
||||
/* Write to device */
|
||||
if (chan_read_byte(chsa, &ch)) { /* get byte from memory */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
|
||||
} else {
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_srvo write %d: putch %0.2x %c\n", unit, ch, ch);
|
||||
sim_putchar(ch); /* output next char to device */
|
||||
sim_activate(uptr, 20); /* TRY 07-18-18 */
|
||||
}
|
||||
}
|
||||
if ((cmd == CON_WR) || (cmd == CON_RWD)) {
|
||||
/* Write to device */
|
||||
if (chan_read_byte(chsa, &ch)) { /* get byte from memory */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* done */
|
||||
} else {
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_srvo write %d: putch %0.2x %c\n", unit, ch, ch);
|
||||
sim_putchar(ch); /* output next char to device */
|
||||
sim_activate(uptr, 20); /* TRY 07-18-18 */
|
||||
}
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Handle input transfers for console */
|
||||
t_stat con_srvi(UNIT *uptr) {
|
||||
uint16 chsa = GET_UADDR(uptr->u3);
|
||||
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
|
||||
int cmd = uptr->u3 & CON_MSK;
|
||||
t_stat r = SCPE_ARG; /* Force error if not set */
|
||||
uint8 ch;
|
||||
int i;
|
||||
uint16 chsa = GET_UADDR(uptr->u3);
|
||||
int unit = (uptr - con_unit); /* unit 0 is read, unit 1 is write */
|
||||
int cmd = uptr->u3 & CON_MSK;
|
||||
t_stat r = SCPE_ARG; /* Force error if not set */
|
||||
uint8 ch;
|
||||
int i;
|
||||
|
||||
switch (cmd) {
|
||||
switch (cmd) {
|
||||
|
||||
case CON_RD: /* read from device */
|
||||
case CON_ECHO: /* read from device w/ECHO */
|
||||
if (uptr->u3 & CON_INPUT) { /* input waiting? */
|
||||
ch = con_data[unit].ibuff[uptr->u4++]; /* get char from read buffer */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_srvi %d: read %02x\n", unit, ch);
|
||||
if (chan_write_byte(chsa, &ch)) { /* write byte to memory */
|
||||
con_data[unit].incnt = 0; /* buffer empty */
|
||||
cmd = 0; /* no cmd either */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
|
||||
} else {
|
||||
if (uptr->u4 == con_data[unit].incnt) { /* read completed */
|
||||
con_data[unit].incnt = 0; /* buffer is empty */
|
||||
cmd = 0; /* no cmd either */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case CON_RD: /* read from device */
|
||||
case CON_ECHO: /* read from device w/ECHO */
|
||||
if (uptr->u3 & CON_INPUT) { /* input waiting? */
|
||||
ch = con_data[unit].ibuff[uptr->u4++]; /* get char from read buffer */
|
||||
sim_debug(DEBUG_CMD, &con_dev, "con_srvi %d: read %02x\n", unit, ch);
|
||||
if (chan_write_byte(chsa, &ch)) { /* write byte to memory */
|
||||
con_data[unit].incnt = 0; /* buffer empty */
|
||||
cmd = 0; /* no cmd either */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
|
||||
} else {
|
||||
if (uptr->u4 == con_data[unit].incnt) { /* read completed */
|
||||
con_data[unit].incnt = 0; /* buffer is empty */
|
||||
cmd = 0; /* no cmd either */
|
||||
uptr->u3 &= LMASK; /* nothing left, command complete */
|
||||
chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* we done */
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* poll for next input if reading or @@A sequence */
|
||||
r = sim_poll_kbd(); /* poll for ready */
|
||||
if (r & SCPE_KFLAG) { /* got a char */
|
||||
ch = r & 0377; /* drop any extra bits */
|
||||
if ((cmd == CON_RD) || (cmd == CON_ECHO)) { /* looking for input */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
if (ch == '\n') /* convert newline */
|
||||
ch = '\r'; /* make newline into carriage return */
|
||||
/* Handle end of buffer */
|
||||
switch (ch) {
|
||||
/* poll for next input if reading or @@A sequence */
|
||||
r = sim_poll_kbd(); /* poll for ready */
|
||||
if (r & SCPE_KFLAG) { /* got a char */
|
||||
ch = r & 0377; /* drop any extra bits */
|
||||
if ((cmd == CON_RD) || (cmd == CON_ECHO)) { /* looking for input */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
if (ch == '\n') /* convert newline */
|
||||
ch = '\r'; /* make newline into carriage return */
|
||||
/* Handle end of buffer */
|
||||
switch (ch) {
|
||||
|
||||
case 0x7f: /* Delete */
|
||||
case '\b': /* backspace */
|
||||
if (con_data[unit].incnt != 0) {
|
||||
con_data[unit].incnt--;
|
||||
sim_putchar('\b');
|
||||
sim_putchar(' ');
|
||||
sim_putchar('\b');
|
||||
}
|
||||
break;
|
||||
case 03: /* ^C */
|
||||
case 025: /* ^U clear line */
|
||||
for (i = con_data[unit].incnt; i> 0; i--) {
|
||||
sim_putchar('\b');
|
||||
sim_putchar(' ');
|
||||
sim_putchar('\b');
|
||||
}
|
||||
con_data[unit].incnt = 0;
|
||||
break;
|
||||
case 0x7f: /* Delete */
|
||||
case '\b': /* backspace */
|
||||
if (con_data[unit].incnt != 0) {
|
||||
con_data[unit].incnt--;
|
||||
sim_putchar('\b');
|
||||
sim_putchar(' ');
|
||||
sim_putchar('\b');
|
||||
}
|
||||
break;
|
||||
case 03: /* ^C */
|
||||
case 025: /* ^U clear line */
|
||||
for (i = con_data[unit].incnt; i> 0; i--) {
|
||||
sim_putchar('\b');
|
||||
sim_putchar(' ');
|
||||
sim_putchar('\b');
|
||||
}
|
||||
con_data[unit].incnt = 0;
|
||||
break;
|
||||
|
||||
case '\r': /* return */
|
||||
case '\n': /* newline */
|
||||
uptr->u3 |= CON_CR; /* C/R received */
|
||||
/* fall through */
|
||||
default:
|
||||
if (con_data[unit].incnt < sizeof(con_data[unit].ibuff)) {
|
||||
if (uptr->u3 & CON_EKO) /* ECHO requested */
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
con_data[unit].ibuff[con_data[unit].incnt++] = ch;
|
||||
uptr->u3 |= CON_INPUT; /* we have a char available */
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* look for attention sequence '@@A' */
|
||||
if (ch == '@' || ch == 'A' || ch == 'a') {
|
||||
if (ch == 'a')
|
||||
ch = 'A';
|
||||
atbuf = (atbuf|ch)<<8;
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
if (atbuf == 0x40404100) {
|
||||
attention_trap = CONSOLEATN_TRAP; /* console attn (0xb4) */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
sim_putchar('\r'); /* return char */
|
||||
sim_putchar('\n'); /* line feed char */
|
||||
}
|
||||
} else {
|
||||
if (ch == '?') {
|
||||
int chan = ((chsa >> 8) & 0x7f); /* get the channel number */
|
||||
/* set ring bit? */
|
||||
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((cmd == CON_RD) || (cmd == CON_ECHO)) /* looking for input */
|
||||
sim_activate(uptr, 200); /* keep going */
|
||||
else
|
||||
sim_activate(uptr, 400); /* keep going */
|
||||
return SCPE_OK;
|
||||
case '\r': /* return */
|
||||
case '\n': /* newline */
|
||||
uptr->u3 |= CON_CR; /* C/R received */
|
||||
/* fall through */
|
||||
default:
|
||||
if (con_data[unit].incnt < sizeof(con_data[unit].ibuff)) {
|
||||
if (uptr->u3 & CON_EKO) /* ECHO requested */
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
con_data[unit].ibuff[con_data[unit].incnt++] = ch;
|
||||
uptr->u3 |= CON_INPUT; /* we have a char available */
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* look for attention sequence '@@A' */
|
||||
if (ch == '@' || ch == 'A' || ch == 'a') {
|
||||
if (ch == 'a')
|
||||
ch = 'A';
|
||||
atbuf = (atbuf|ch)<<8;
|
||||
sim_putchar(ch); /* ECHO the char */
|
||||
if (atbuf == 0x40404100) {
|
||||
attention_trap = CONSOLEATN_TRAP; /* console attn (0xb4) */
|
||||
atbuf = 0; /* reset attention buffer */
|
||||
sim_putchar('\r'); /* return char */
|
||||
sim_putchar('\n'); /* line feed char */
|
||||
}
|
||||
} else {
|
||||
if (ch == '?') {
|
||||
int chan = ((chsa >> 8) & 0x7f); /* get the channel number */
|
||||
/* set ring bit? */
|
||||
set_devwake(chsa, SNS_ATTN|SNS_DEVEND|SNS_CHNEND); /* tell user */
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((cmd == CON_RD) || (cmd == CON_ECHO)) /* looking for input */
|
||||
sim_activate(uptr, 200); /* keep going */
|
||||
else
|
||||
sim_activate(uptr, 400); /* keep going */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
8228
SEL32/sel32_cpu.c
8228
SEL32/sel32_cpu.c
File diff suppressed because it is too large
Load Diff
@ -22,24 +22,24 @@
|
||||
|
||||
*/
|
||||
|
||||
#include "sim_defs.h" /* simh simulator defns */
|
||||
#include "sim_defs.h" /* simh simulator defns */
|
||||
|
||||
/* Simulator stop codes */
|
||||
|
||||
#define STOP_IONRDY 1 /* I/O dev not ready */
|
||||
#define STOP_HALT 2 /* HALT */
|
||||
#define STOP_IBKPT 3 /* breakpoint */
|
||||
#define STOP_UUO 4 /* invalid opcode */
|
||||
#define STOP_INVINS 5 /* invalid instr */
|
||||
#define STOP_INVIOP 6 /* invalid I/O op */
|
||||
#define STOP_INDLIM 7 /* indirect limit */
|
||||
#define STOP_XECLIM 8 /* XEC limit */
|
||||
#define STOP_IOCHECK 9 /* IOCHECK */
|
||||
#define STOP_MMTRP 10 /* mm in trap */
|
||||
#define STOP_TRPINS 11 /* trap inst not BRM */
|
||||
#define STOP_RTCINS 12 /* rtc inst not MIN/SKR */
|
||||
#define STOP_ILLVEC 13 /* zero vector */
|
||||
#define STOP_CCT 14 /* runaway CCT */
|
||||
#define STOP_IONRDY 1 /* I/O dev not ready */
|
||||
#define STOP_HALT 2 /* HALT */
|
||||
#define STOP_IBKPT 3 /* breakpoint */
|
||||
#define STOP_UUO 4 /* invalid opcode */
|
||||
#define STOP_INVINS 5 /* invalid instr */
|
||||
#define STOP_INVIOP 6 /* invalid I/O op */
|
||||
#define STOP_INDLIM 7 /* indirect limit */
|
||||
#define STOP_XECLIM 8 /* XEC limit */
|
||||
#define STOP_IOCHECK 9 /* IOCHECK */
|
||||
#define STOP_MMTRP 10 /* mm in trap */
|
||||
#define STOP_TRPINS 11 /* trap inst not BRM */
|
||||
#define STOP_RTCINS 12 /* rtc inst not MIN/SKR */
|
||||
#define STOP_ILLVEC 13 /* zero vector */
|
||||
#define STOP_CCT 14 /* runaway CCT */
|
||||
|
||||
/* I/O equates */
|
||||
/* Channel sense bytes set by device */
|
||||
@ -96,36 +96,36 @@
|
||||
#define BUFF_NEWCMD 0x10 /* Channel ready for new command */
|
||||
#define BUFF_CHNEND 0x20 /* Channel end */
|
||||
|
||||
#define MAX_CHAN 128 /* max channels that can be defined */
|
||||
#define SUB_CHANS 256 /* max sub channels that can be defined */
|
||||
#define MAX_DEV (MAX_CHAN * SUB_CHANS) /* max possible */
|
||||
#define MAX_CHAN 128 /* max channels that can be defined */
|
||||
#define SUB_CHANS 256 /* max sub channels that can be defined */
|
||||
#define MAX_DEV (MAX_CHAN * SUB_CHANS) /* max possible */
|
||||
|
||||
/* simulator devices configuration */
|
||||
#define NUM_DEVS_IOP 1 /* 1 device IOP channel controller */
|
||||
#define NUM_UNITS_IOP 1 /* 1 master IOP channel device */
|
||||
#define NUM_DEVS_COM 2 /* 8-Line async controller */
|
||||
#define NUM_UNITS_COM 16 /* 8-Line async units */
|
||||
#define NUM_DEVS_CON 1 /* 1 I/O console controller */
|
||||
#define NUM_UNITS_CON 2 /* 2 console input & output */
|
||||
#define NUM_DEVS_MT 1 /* 1 mag tape controllers */
|
||||
#define NUM_UNITS_MT 4 /* 4 of 8 devices */
|
||||
#define NUM_DEVS_DISK 1 /* 1 DP02 disk drive controller */
|
||||
#define NUM_UNITS_DISK 4 /* 4 disk drive devices */
|
||||
#define NUM_DEVS_SCFI 2 /* 2 scfi (SCSI) disk drive units */
|
||||
#define NUM_UNITS_SCFI 2 /* 2 of 4 disk drive devices */
|
||||
#define NUM_DEVS_RTOM 1 /* 1 IOP RTOM channel */
|
||||
#define NUM_UNITS_RTOM 1 /* 1 IOP RTOM device (clock & interval timer) */
|
||||
#define NUM_DEVS_LPR 1 /* 1 IOP Line printer */
|
||||
#define NUM_UNITS_LPR 1 /* 1 IOP Line printer device */
|
||||
#define NUM_DEVS_IOP 1 /* 1 device IOP channel controller */
|
||||
#define NUM_UNITS_IOP 1 /* 1 master IOP channel device */
|
||||
#define NUM_DEVS_COM 2 /* 8-Line async controller */
|
||||
#define NUM_UNITS_COM 16 /* 8-Line async units */
|
||||
#define NUM_DEVS_CON 1 /* 1 I/O console controller */
|
||||
#define NUM_UNITS_CON 2 /* 2 console input & output */
|
||||
#define NUM_DEVS_MT 1 /* 1 mag tape controllers */
|
||||
#define NUM_UNITS_MT 4 /* 4 of 8 devices */
|
||||
#define NUM_DEVS_DISK 1 /* 1 DP02 disk drive controller */
|
||||
#define NUM_UNITS_DISK 4 /* 4 disk drive devices */
|
||||
#define NUM_DEVS_SCFI 2 /* 2 scfi (SCSI) disk drive units */
|
||||
#define NUM_UNITS_SCFI 2 /* 2 of 4 disk drive devices */
|
||||
#define NUM_DEVS_RTOM 1 /* 1 IOP RTOM channel */
|
||||
#define NUM_UNITS_RTOM 1 /* 1 IOP RTOM device (clock & interval timer) */
|
||||
#define NUM_DEVS_LPR 1 /* 1 IOP Line printer */
|
||||
#define NUM_UNITS_LPR 1 /* 1 IOP Line printer device */
|
||||
|
||||
extern DEVICE cpu_dev; /* cpu device */
|
||||
extern UNIT cpu_unit; /* the cpu unit */
|
||||
extern DEVICE cpu_dev; /* cpu device */
|
||||
extern UNIT cpu_unit; /* the cpu unit */
|
||||
#ifdef NUM_DEVS_IOP
|
||||
extern DEVICE iop_dev; /* IOP channel controller */
|
||||
extern DEVICE iop_dev; /* IOP channel controller */
|
||||
#endif
|
||||
#ifdef NUM_DEVS_RTOM
|
||||
extern DEVICE rtc_dev; /* RTOM rtc */
|
||||
extern DEVICE itm_dev; /* RTOM itm */
|
||||
extern DEVICE rtc_dev; /* RTOM rtc */
|
||||
extern DEVICE itm_dev; /* RTOM itm */
|
||||
#endif
|
||||
#ifdef NUM_DEVS_CON
|
||||
extern DEVICE con_dev;
|
||||
@ -158,49 +158,49 @@ extern DEVICE lpr_dev;
|
||||
|
||||
/* Memory */
|
||||
|
||||
#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size */
|
||||
#define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */
|
||||
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
|
||||
#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
|
||||
#define MAXMEMSIZE ((16*1024*1024)/4) /* max memory size */
|
||||
#define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */
|
||||
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
|
||||
#define MEM_ADDR_OK(x) (((x)) < MEMSIZE)
|
||||
|
||||
/* channel program data for a chan/sub-address */
|
||||
typedef struct chp {
|
||||
/* channel program values */
|
||||
uint32 chan_inch_addr; /* Channel status dw in memory */
|
||||
uint32 chan_caw; /* Channel command address word */
|
||||
uint32 ccw_addr; /* Channel address */
|
||||
uint16 ccw_count; /* Channel count */
|
||||
uint8 ccw_cmd; /* Channel command and flags */
|
||||
uint16 ccw_flags; /* Channel flags */
|
||||
uint16 chan_status; /* Channel status */
|
||||
uint16 chan_dev; /* Device on channel */
|
||||
uint32 chan_buf; /* Channel data buffer */
|
||||
uint8 chan_byte; /* Current byte, dirty/full */
|
||||
/* channel program values */
|
||||
uint32 chan_inch_addr; /* Channel status dw in memory */
|
||||
uint32 chan_caw; /* Channel command address word */
|
||||
uint32 ccw_addr; /* Channel address */
|
||||
uint16 ccw_count; /* Channel count */
|
||||
uint8 ccw_cmd; /* Channel command and flags */
|
||||
uint16 ccw_flags; /* Channel flags */
|
||||
uint16 chan_status; /* Channel status */
|
||||
uint16 chan_dev; /* Device on channel */
|
||||
uint32 chan_buf; /* Channel data buffer */
|
||||
uint8 chan_byte; /* Current byte, dirty/full */
|
||||
} CHANP;
|
||||
|
||||
/* Device information block */
|
||||
#define FIFO_SIZE 256 /* fifo to hold 128 double words of status */
|
||||
#define FIFO_SIZE 256 /* fifo to hold 128 double words of status */
|
||||
typedef struct dib {
|
||||
/* Pre start I/O operation */
|
||||
uint8 (*pre_io)(UNIT *uptr, uint16 chan);
|
||||
/* Start a channel command SIO */
|
||||
uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
|
||||
/* Halt I/O HIO */
|
||||
uint8 (*halt_io)(UNIT *uptr);
|
||||
/* Test I/O TESTIO */
|
||||
uint8 (*test_io)(UNIT *uptr);
|
||||
/* Post I/O processing */
|
||||
uint8 (*post_io)(UNIT *uptr);
|
||||
/* Controller init */
|
||||
void (*dev_ini)(UNIT *, t_bool); /* init function */
|
||||
UNIT *units; /* Pointer to units structure */
|
||||
CHANP *chan_prg; /* Pointer to channel program */
|
||||
uint8 numunits; /* number of units */
|
||||
uint8 mask; /* device mask */
|
||||
uint16 chan_addr; /* parent channel address */
|
||||
uint32 chan_fifo_in; /* fifo input index */
|
||||
uint32 chan_fifo_out; /* fifo output index */
|
||||
uint32 chan_fifo[FIFO_SIZE]; /* interrupt status fifo for each channel */
|
||||
/* Pre start I/O operation */
|
||||
uint8 (*pre_io)(UNIT *uptr, uint16 chan);
|
||||
/* Start a channel command SIO */
|
||||
uint8 (*start_cmd)(UNIT *uptr, uint16 chan, uint8 cmd);
|
||||
/* Halt I/O HIO */
|
||||
uint8 (*halt_io)(UNIT *uptr);
|
||||
/* Test I/O TESTIO */
|
||||
uint8 (*test_io)(UNIT *uptr);
|
||||
/* Post I/O processing */
|
||||
uint8 (*post_io)(UNIT *uptr);
|
||||
/* Controller init */
|
||||
void (*dev_ini)(UNIT *, t_bool); /* init function */
|
||||
UNIT *units; /* Pointer to units structure */
|
||||
CHANP *chan_prg; /* Pointer to channel program */
|
||||
uint8 numunits; /* number of units */
|
||||
uint8 mask; /* device mask */
|
||||
uint16 chan_addr; /* parent channel address */
|
||||
uint32 chan_fifo_in; /* fifo input index */
|
||||
uint32 chan_fifo_out; /* fifo output index */
|
||||
uint32 chan_fifo[FIFO_SIZE]; /* interrupt status fifo for each channel */
|
||||
} DIB;
|
||||
|
||||
/* DEV 0x7F000000 UNIT 0x00ff0000 */
|
||||
@ -234,22 +234,22 @@ typedef struct dib {
|
||||
extern DEBTAB dev_debug[];
|
||||
|
||||
/* defines for all programs */
|
||||
#define RMASK 0x0000FFFF /* right hw 16 bit mask */
|
||||
#define LMASK 0xFFFF0000 /* left hw 16 bit mask */
|
||||
#define FMASK 0xFFFFFFFF /* 32 bit mask */
|
||||
#define DMASK 0xFFFFFFFFFFFFFFFFLL /* 64 bit all bits mask */
|
||||
#define D48LMASK 0xFFFFFFFFFFFF0000LL /* 64 bit left 48 bits mask */
|
||||
#define D32LMASK 0xFFFFFFFF00000000LL /* 64 bit left 32 bits mask */
|
||||
#define D32RMASK 0x00000000FFFFFFFFLL /* 64 bit right 32 bits mask */
|
||||
#define MSIGN 0x80000000 /* 32 bit minus sign */
|
||||
#define DMSIGN 0x8000000000000000LL /* 64 bit minus sign */
|
||||
#define FSIGN 0x80000000 /* 32 bit minus sign */
|
||||
#define RMASK 0x0000FFFF /* right hw 16 bit mask */
|
||||
#define LMASK 0xFFFF0000 /* left hw 16 bit mask */
|
||||
#define FMASK 0xFFFFFFFF /* 32 bit mask */
|
||||
#define DMASK 0xFFFFFFFFFFFFFFFFLL /* 64 bit all bits mask */
|
||||
#define D48LMASK 0xFFFFFFFFFFFF0000LL /* 64 bit left 48 bits mask */
|
||||
#define D32LMASK 0xFFFFFFFF00000000LL /* 64 bit left 32 bits mask */
|
||||
#define D32RMASK 0x00000000FFFFFFFFLL /* 64 bit right 32 bits mask */
|
||||
#define MSIGN 0x80000000 /* 32 bit minus sign */
|
||||
#define DMSIGN 0x8000000000000000LL /* 64 bit minus sign */
|
||||
#define FSIGN 0x80000000 /* 32 bit minus sign */
|
||||
/* sign extend 16 bit value to uint32 */
|
||||
#define SEXT16(x) (x&0x8000?(uint32)(((uint32)x&RMASK)|LMASK):(uint32)x)
|
||||
#define SEXT16(x) (x&0x8000?(uint32)(((uint32)x&RMASK)|LMASK):(uint32)x)
|
||||
/* sign extend 16 bit value to uint64 */
|
||||
#define DSEXT16(x) (x&0x8000?(l_uint64)(((l_uint64)x&RMASK)|D48LMASK):(t_uint64)x)
|
||||
#define DSEXT16(x) (x&0x8000?(l_uint64)(((l_uint64)x&RMASK)|D48LMASK):(t_uint64)x)
|
||||
/* sign extend 32 bit value to uint64 */
|
||||
#define DSEXT32(x) (x&0x8000?(l_uint64)(((l_uint64)x&D32RMASK)|D32LMASK):(t_uint64)x)
|
||||
#define DSEXT32(x) (x&0x8000?(l_uint64)(((l_uint64)x&D32RMASK)|D32LMASK):(t_uint64)x)
|
||||
|
||||
#define UNIT_V_MODEL (UNIT_V_UF + 0)
|
||||
#define UNIT_MODEL (7 << UNIT_V_MODEL)
|
||||
@ -257,7 +257,7 @@ extern DEBTAB dev_debug[];
|
||||
#define UNIT_V_MSIZE (UNIT_V_MODEL + 3)
|
||||
#define UNIT_MSIZE (0x1F << UNIT_V_MSIZE)
|
||||
#define MEMAMOUNT(x) (x << UNIT_V_MSIZE)
|
||||
#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_MODEL) & 0x7) /* cpu model 0-7 */
|
||||
#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_MODEL) & 0x7) /* cpu model 0-7 */
|
||||
|
||||
#define MODEL_55 0 /* 512K Mode Only */
|
||||
#define MODEL_75 1 /* Extended */
|
||||
@ -275,75 +275,75 @@ extern DEBTAB dev_debug[];
|
||||
#define HIST_PC 0x80000000
|
||||
|
||||
/* CC defs Held in CC */
|
||||
#define CC1BIT 0x40000000 /* CC1 in PSD1 */
|
||||
#define CC2BIT 0x20000000 /* CC2 in PSD1 */
|
||||
#define CC3BIT 0x10000000 /* CC3 in PSD1 */
|
||||
#define CC4BIT 0x08000000 /* CC4 in PSD1 */
|
||||
#define CC1BIT 0x40000000 /* CC1 in PSD1 */
|
||||
#define CC2BIT 0x20000000 /* CC2 in PSD1 */
|
||||
#define CC3BIT 0x10000000 /* CC3 in PSD1 */
|
||||
#define CC4BIT 0x08000000 /* CC4 in PSD1 */
|
||||
|
||||
#define MAPMODE 0x40 /* Map mode, PSD 2 bit 0 */
|
||||
#define RETMODE 0x20 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define BLKMODE 0x10 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define RETBLKM 0x08 /* Set retain blocked mode, PSD 2 bit 16 */
|
||||
#define MAPMODE 0x40 /* Map mode, PSD 2 bit 0 */
|
||||
#define RETMODE 0x20 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define BLKMODE 0x10 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define RETBLKM 0x08 /* Set retain blocked mode, PSD 2 bit 16 */
|
||||
|
||||
/* PSD mode bits in PSD words 1&2 variable */
|
||||
#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
|
||||
#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
|
||||
#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
|
||||
#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
|
||||
#define PRIVBIT 0x80000000 /* Privileged mode PSD 1 bit 0 */
|
||||
#define EXTDBIT 0x04000000 /* Extended Addressing PSD 1 bit 5 */
|
||||
#define BASEBIT 0x02000000 /* Base Mode PSD 1 bit 6 */
|
||||
#define AEXPBIT 0x01000000 /* Arithmetic exception PSD 1 bit 7 */
|
||||
|
||||
#define BLKEDBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define RETBBIT 0x00008000 /* Retain current blocking state, PSD 2 bit 16 */
|
||||
#define RETMBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
|
||||
#define BLKEDBIT 0x00004000 /* Set blocked mode, PSD 2 bit 17 */
|
||||
#define RETBBIT 0x00008000 /* Retain current blocking state, PSD 2 bit 16 */
|
||||
#define RETMBIT 0x00010000 /* Retain current maps, PSD 2 bit 15 */
|
||||
#define MAPBIT 0x80000000 /* Map mode, PSD 2 bit 0 */
|
||||
|
||||
/* Trap Table Address in memory is pointed to by SPAD 0xF0 */
|
||||
#define POWERFAIL_TRAP 0x80 /* Power fail trap */
|
||||
#define POWERON_TRAP 0x84 /* Power-On trap */
|
||||
#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
|
||||
#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
|
||||
#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
|
||||
#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
|
||||
#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
|
||||
#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
|
||||
#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
|
||||
#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
|
||||
#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
|
||||
#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
|
||||
#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
|
||||
#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
|
||||
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
|
||||
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
|
||||
#define POWERFAIL_TRAP 0x80 /* Power fail trap */
|
||||
#define POWERON_TRAP 0x84 /* Power-On trap */
|
||||
#define MEMPARITY_TRAP 0x88 /* Memory Parity Error trap */
|
||||
#define NONPRESMEM_TRAP 0x8C /* Non Present Memory trap */
|
||||
#define UNDEFINSTR_TRAP 0x90 /* Undefined Instruction Trap */
|
||||
#define PRIVVIOL_TRAP 0x94 /* Privlege Violation Trap */
|
||||
#define SVCCALL_TRAP 0x98 /* Supervisor Call Trap */
|
||||
#define MACHINECHK_TRAP 0x9C /* Machine Check Trap */
|
||||
#define SYSTEMCHK_TRAP 0xA0 /* System Check Trap */
|
||||
#define MAPFAULT_TRAP 0xA4 /* Map Fault Trap */
|
||||
#define IPUUNDEFI_TRAP 0xA8 /* IPU Undefined Instruction Trap */
|
||||
#define SIGNALIPU_TRAP 0xAC /* Signal IPU/CPU Trap */
|
||||
#define ADDRSPEC_TRAP 0xB0 /* Address Specification Trap */
|
||||
#define CONSOLEATN_TRAP 0xB4 /* Console Attention Trap */
|
||||
#define PRIVHALT_TRAP 0xB8 /* Privlege Mode Halt Trap */
|
||||
#define AEXPCEPT_TRAP 0xBC /* Arithmetic Exception Trap */
|
||||
|
||||
/* Errors returned from various functions */
|
||||
#define ALLOK 0x0000 /* no error, all is OK */
|
||||
#define MAPFLT MAPFAULT_TRAP /* map fault error */
|
||||
#define NPMEM NONPRESMEM_TRAP /* non present memory */
|
||||
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
|
||||
#define ALLOK 0x0000 /* no error, all is OK */
|
||||
#define MAPFLT MAPFAULT_TRAP /* map fault error */
|
||||
#define NPMEM NONPRESMEM_TRAP /* non present memory */
|
||||
#define MPVIOL PRIVVIOL_TRAP /* memory protection violation */
|
||||
|
||||
/* general instruction decode equates */
|
||||
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
|
||||
#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
|
||||
#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 20 & 31 */
|
||||
#define BIT0 0x80000000 /* general use for bit 0 testing */
|
||||
#define BIT1 0x40000000 /* general use for bit 1 testing */
|
||||
#define MASK16 0x0000FFFF /* 16 bit address mask */
|
||||
#define MASK19 0x0007FFFF /* 19 bit address mask */
|
||||
#define MASK20 0x000FFFFF /* 20 bit address mask */
|
||||
#define MASK24 0x00FFFFFF /* 24 bit address mask */
|
||||
#define MASK32 0xFFFFFFFF /* 32 bit address mask */
|
||||
#define IND 0x00100000 /* indirect bit in instruction, bit 11 */
|
||||
#define F_BIT 0x00080000 /* byte flag addressing bit 11 in instruction */
|
||||
#define C_BITS 0x00000003 /* byte number or hw, dw, dw flags bits 20 & 31 */
|
||||
#define BIT0 0x80000000 /* general use for bit 0 testing */
|
||||
#define BIT1 0x40000000 /* general use for bit 1 testing */
|
||||
#define MASK16 0x0000FFFF /* 16 bit address mask */
|
||||
#define MASK19 0x0007FFFF /* 19 bit address mask */
|
||||
#define MASK20 0x000FFFFF /* 20 bit address mask */
|
||||
#define MASK24 0x00FFFFFF /* 24 bit address mask */
|
||||
#define MASK32 0xFFFFFFFF /* 32 bit address mask */
|
||||
|
||||
/* SPAD int entry equates, entries accessed by interrupt level number */
|
||||
#define SINT_RAML 0x80000000 /* ram loaded (n/u) */
|
||||
#define SINT_EWCS 0x40000000 /* Enabled channel WCS executed (XIO) */
|
||||
#define SINT_ACT 0x20000000 /* Interrupt active when set (copy is in INTS */
|
||||
#define SINT_ENAB 0x10000000 /* Interrupt enabled when set (copy is in INTS */
|
||||
#define SINT_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy in INTS) */
|
||||
#define SINT_RAML 0x80000000 /* ram loaded (n/u) */
|
||||
#define SINT_EWCS 0x40000000 /* Enabled channel WCS executed (XIO) */
|
||||
#define SINT_ACT 0x20000000 /* Interrupt active when set (copy is in INTS */
|
||||
#define SINT_ENAB 0x10000000 /* Interrupt enabled when set (copy is in INTS */
|
||||
#define SINT_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy in INTS) */
|
||||
|
||||
/* INTS int entry equates, entries accessed by interrupt level number */
|
||||
#define INTS_NU1 0x80000000 /* Not used */
|
||||
#define INTS_NU2 0x40000000 /* Not used */
|
||||
#define INTS_ACT 0x20000000 /* Interrupt active when set (copy is of SPAD */
|
||||
#define INTS_ENAB 0x10000000 /* Interrupt enabled when set (copy is of SPAD */
|
||||
#define INTS_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy of SPAD) */
|
||||
#define INTS_REQ 0x04000000 /* Interrupt is requesting */
|
||||
#define INTS_NU1 0x80000000 /* Not used */
|
||||
#define INTS_NU2 0x40000000 /* Not used */
|
||||
#define INTS_ACT 0x20000000 /* Interrupt active when set (copy is of SPAD */
|
||||
#define INTS_ENAB 0x10000000 /* Interrupt enabled when set (copy is of SPAD */
|
||||
#define INTS_EXTL 0x08000000 /* IOP/RTOM ext interrupt if set, I/O if not set (copy of SPAD) */
|
||||
#define INTS_REQ 0x04000000 /* Interrupt is requesting */
|
||||
|
||||
|
||||
1398
SEL32/sel32_disk.c
1398
SEL32/sel32_disk.c
File diff suppressed because it is too large
Load Diff
858
SEL32/sel32_mt.c
858
SEL32/sel32_mt.c
File diff suppressed because it is too large
Load Diff
1342
SEL32/sel32_scfi.c
1342
SEL32/sel32_scfi.c
File diff suppressed because it is too large
Load Diff
1956
SEL32/sel32_sys.c
1956
SEL32/sel32_sys.c
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user