From e300fe81bf2a62666a4442872ca29b1c4a6a07c9 Mon Sep 17 00:00:00 2001 From: "James C. Bevier" Date: Tue, 30 Nov 2021 09:37:04 -0700 Subject: [PATCH] SEL32: Update SIO, HIO, STPIO, TOI error processing and CC's returned SEL32: Continue code cleanup. --- SEL32/sel32_chan.c | 187 ++++++++++++++++++++++++++++++--------------- SEL32/sel32_con.c | 24 +++--- SEL32/sel32_cpu.c | 58 +------------- SEL32/sel32_disk.c | 60 +++++++++++---- SEL32/sel32_ec.c | 15 ++-- SEL32/sel32_hsdp.c | 42 ++++------ 6 files changed, 207 insertions(+), 179 deletions(-) diff --git a/SEL32/sel32_chan.c b/SEL32/sel32_chan.c index 36ec19c..40fc293 100644 --- a/SEL32/sel32_chan.c +++ b/SEL32/sel32_chan.c @@ -1155,13 +1155,24 @@ int16 post_csw(CHANP *chp, uint32 rstat) sw2 &= ~rstat; /* remove bits */ /* we have status to post, do it now */ /* save the status double word to memory */ - WMW(incha, sw1); /* save sa & IOCD address in status WD 1 loc */ - WMW(incha+4, sw2); /* save status and residual cnt in status WD 2 loc */ - /* now store the status dw address into word 5 of the ICB for the channel */ - WMW(chan_icb+20, incha|BIT1); /* post sw addr in ICB+5w & set CC2 in INCH addr */ - sim_debug(DEBUG_IRQ, &cpu_dev, - "post_csw %04x READ FIFO #%1x inch %06x chan_icb %06x sw1 %08x sw2 %08x\n", - chsa, FIFO_Num(chsa), incha, chan_icb, sw1, sw2); + /* if bit 0 of sw2 is set (STATUS_ECHO), post inch addr 0 with bit 0 set */ + if (sw2 & BIT0) { /* see if only not busy post */ + WMW(chan_icb+20, 0x80000000); /* post sw addr 0 in ICB+5w & reset CCs */ + sim_debug(DEBUG_IRQ, &cpu_dev, + "post_csw %04x READ0 FIFO #%1x inch 0x80000000 chan_icb %06x sw1 %08x sw2 %08x\n", + chsa, FIFO_Num(chsa), chan_icb, sw1, sw2); + } else { + sim_debug(DEBUG_IRQ, &cpu_dev, + "post_csw %04x B4READ1 icb+16 %08x icb+20 %08x inch %06x chan_icb %06x\n", + chsa, RMW(chan_icb+16), RMW(chan_icb+20), incha, chan_icb); + WMW(incha, sw1); /* save sa & IOCD address in status WD 1 loc */ + WMW(incha+4, sw2); /* save status and residual cnt in status WD 2 loc */ + /* now store the status dw address into word 5 of the ICB for the channel */ + WMW(chan_icb+20, incha|BIT1); /* post sw addr in ICB+5w & set CC2 in INCH addr */ + sim_debug(DEBUG_IRQ, &cpu_dev, + "post_csw %04x READ1 FIFO #%1x inch %06x chan_icb %06x sw1 %08x sw2 %08x\n", + chsa, FIFO_Num(chsa), incha, chan_icb, sw1, sw2); + } return 1; /* show we posted status */ } sim_debug(DEBUG_DETAIL, &cpu_dev, @@ -1190,7 +1201,8 @@ void store_csw(CHANP *chp) "store_csw FIFO #%1x write chsa %04x sw1 %08x sw2 %08x incha %08x cmd %02x\n", FIFO_Num(chsa), chsa, stwd1, stwd2, chp->chan_inch_addr, chp->ccw_cmd); /* added 011321 */ - INTS[chp->chan_int] |= INTS_REQ; /* request an interrupt for channel */ + /* removed 112421 */ +// INTS[chp->chan_int] |= INTS_REQ; /* request an interrupt for channel */ irq_pend = 1; /* wakeup controller */ } @@ -1215,7 +1227,8 @@ void push_csw(CHANP *chp) "push_csw FIFO #%1x write chsa %04x sw1 %08x sw2 %08x incha %08x cmd %02x\n", FIFO_Num(chsa), chsa, stwd1, stwd2, chp->chan_inch_addr, chp->ccw_cmd); /* added 011321 */ - INTS[chp->chan_int] |= INTS_REQ; /* request an interrupt for channel */ + /* removed 112421 */ +// INTS[chp->chan_int] |= INTS_REQ; /* request an interrupt for channel */ irq_pend = 1; /* wakeup controller */ } @@ -1347,6 +1360,7 @@ t_stat startxio(uint16 lchsa, uint32 *status) { } chan_icb = find_int_icb(lchsa); /* Interrupt level context block address */ incha = RMW(chan_icb+20); /* post inch addr in ICB+5w */ +// WMW(chan_icb+20,0); /* zero incha in IOCB */ /* check if we have a valid unit */ chp = find_chanp_ptr(chsa); /* find the chanp pointer */ @@ -1411,11 +1425,14 @@ missing: if (chp->chan_byte == BUFF_POST) { chp->chan_byte = BUFF_DONE; /* show done & not busy */ } + incha = chp->chan_inch_addr; /* get inch address */ sim_debug(DEBUG_XIO, &cpu_dev, "SIOT END status stored incha %06x chan_icba+20 %08x chsa %04x sw1 %08x sw2 %08x\n", incha, RMW(chan_icb+20), chsa, RMW(incha), RMW(incha+4)); - INTS[inta] &= ~INTS_REQ; /* clear any level request if no status */ + INTS[inta] &= ~INTS_REQ; /* clear level request for no status */ +// INTS[inta] |= INTS_REQ; /* set level request if no status */ *status = CC2BIT; /* status stored from SIO, so CC2 */ +//not work *status = CC1BIT; /* status stored from SIO, so CC2 */ return SCPE_OK; /* No CC's all OK */ } else { sim_debug(DEBUG_IRQ, &cpu_dev, @@ -1427,6 +1444,10 @@ missing: return SCPE_OK; /* No CC's all OK */ } } +//TRY WMW(chan_icb+20, 0); /* post sw addr 0 in ICB+5w & reset CCs */ + sim_debug(DEBUG_IRQ, &cpu_dev, + "SIOT chsa %04x Nothing to post FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", + chsa, FIFO_Num(chsa), inta, chp->chan_inch_addr, chan_icb, chp->chan_byte); #endif /* check for a Command or data chain operation in progresss */ @@ -1621,8 +1642,8 @@ missing: chsa, chp->chan_status, chp->chan_caw, chp->chan_byte); } sim_debug(DEBUG_XIO, &cpu_dev, - "SIO started chsa %04x iocla %06x IOCD1 %08x IOCD2 %08x\n", - chsa, iocla, RMW(iocla), RMW(iocla+4)); + "SIO started chsa %04x iocla %06x IOCD1 %08x IOCD2 %08x incha %06x icb+20 %08x\n", + chsa, iocla, RMW(iocla), RMW(iocla+4), incha, RMW(chan_icb+20)); *status = CC1BIT; /* CCs = 1, SIO accepted & queued, no echo status */ sim_debug(DEBUG_XIO, &cpu_dev, "SIO return chsa %04x status %08x iocla %08x CC's %08x byte %02x\n", @@ -1687,6 +1708,9 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */ sim_debug(DEBUG_IRQ, &cpu_dev, "TIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n", rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte); + if (chp->chan_byte == BUFF_DONE) { + chp->chan_byte = BUFF_POST; /* if done, show post for post_csw() */ + } if (post_csw(chp, 0)) { sim_debug(DEBUG_IRQ, &cpu_dev, "TIO rchsa %04x POST FIFO #%1x irq %02x inch %06x chan_icba+20 %08x chan_byte %02x\n", @@ -1715,9 +1739,16 @@ t_stat testxio(uint16 lchsa, uint32 *status) { /* test XIO */ } /* nothing going on, so say all OK */ - WMW(chan_icb+20, 0); /* post sw addr 0 in ICB+5w & reset CCs */ + /* now store the status dw address into word 5 of the ICB for the channel */ +#ifdef FIXES_DMDIAG_TEST_11C_TIO_BUT_BREAKS_UTX + WMW(chan_icb+20, 0x80000000); /* post CC1 & sw addr 0 in ICB+5w & reset CCs */ + *status = CC4BIT; /* FIX FOR DIAG */ /* request accepted, not busy, so CC4 */ +#else +/// WMW(chan_icb+20, 0x80000001); /* post sw addr 0 in ICB+5w & reset CCs */ + WMW(chan_icb+20, 0x80000000); /* post sw addr 0 in ICB+5w & reset CCs */ *status = CC1BIT; /* request accepted, no status, so CC1 */ - INTS[inta] &= ~INTS_REQ; /* clear any level request if no status */ +#endif +// INTS[inta] &= ~INTS_REQ; /* clear any level request if no status */ sim_debug(DEBUG_XIO, &cpu_dev, "TIO END rchsa %04x rchan %04x ccw_flags %04x chan_stat %04x CCs %08x\n", rchsa, rchan, chp->ccw_flags, chp->chan_status, *status); @@ -1770,29 +1801,22 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ itva = SPAD[0xf1] + (inta<<2); /* int vector address */ chan_icb = RMW(itva); /* Interrupt context block addr */ iocla = RMW(chan_icb+16); /* iocla is in wd 4 of ICB */ - /* reset the CC bit to force completion after current IOCD */ - chp->ccw_flags &= ~FLAG_CC; /* reset chaining bits */ sim_debug(DEBUG_CMD, &cpu_dev, "STPIO busy test rchsa %04x cmd %02x ccw_flags %04x IOCD1 %08x IOCD2 %08x\n", rchsa, chp->ccw_cmd, chp->ccw_flags, M[iocla>>2], M[(iocla+4)>>2]); + /* reset the CC bit to force completion after current IOCD */ + chp->ccw_flags &= ~FLAG_CC; /* reset chaining bits */ - if ((chp->chan_byte & BUFF_BUSY) == 0) { - /* the channel is not busy, so return OK */ - *status = CC1BIT; /* request accepted, post good status, so CC1 */ - sim_debug(DEBUG_CMD, &cpu_dev, - "STPIO not busy return rchsa %04x cmd %02x ccw_flags %04x status %04x byte %02x\n", - rchsa, chp->ccw_cmd, chp->ccw_flags, *status, chp->chan_byte); - return SCPE_OK; /* No CC's all OK */ - } - - /* the channel is busy, so process */ /* see if we have a stopio device entry */ if (dibp->stop_io != NULL) { /* NULL if no stop_io function */ /* call the device controller to get stop_io status */ int32 tempa = dibp->stop_io(uptr); /* get status from device */ /* test for SCPE_IOERR */ - if (tempa != 0) { /* sub channel has status ready */ + /* CC's are returned in byte 0, status in bytes 2-3 */ + /* SCPR_OK is 0 */ + /* SCPR_IOERR is 2 */ + if ((tempa & RMASK) != SCPE_OK) { /* sub channel has status ready */ /* The device I/O has been terminated and status stored. */ sim_debug(DEBUG_XIO, &cpu_dev, "STPIO stop_io call return ERROR FIFO #%1x rchan %04x retstat %08x cstat %08x\n", @@ -1801,7 +1825,7 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ /* chan_end is called in stop device service routine */ /* the device is no longer busy, post status */ /* remove PPCI status. Unit check should not be set */ - if (tempa == 1) { /* see if console HIO */ + if ((tempa & LMASK) == CC2BIT) { chp->ccw_count = 0; /* zero the count */ /* post status for UTX */ if (post_csw(chp, ((STATUS_PCI) << 16))) { @@ -1833,6 +1857,20 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ rchsa, chp->ccw_cmd, chp->ccw_flags, *status); return SCPE_OK; /* No CC's all OK */ } + if ((chp->chan_byte & BUFF_BUSY) == 0) { + /* the channel is not busy, so return OK */ + sim_debug(DEBUG_CMD, &cpu_dev, + "STPIO not busy return rchsa %04x cmd %02x ccw_flags %04x status %04x byte %02x\n", + rchsa, chp->ccw_cmd, chp->ccw_flags, *status, chp->chan_byte); + sim_debug(DEBUG_IRQ, &cpu_dev, + "STPIO rchsa %04x NOT POSTED FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", + rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chan_icb, chp->chan_byte); + /* now store the status dw address into word 5 of the ICB for the channel */ + WMW(chan_icb+20, 0x80000000); /* post sw addr 0 in ICB+5w & set CC 1*/ + *status = CC1BIT; /* show not busy, post no status with CC1 */ + return SCPE_OK; /* No CC's all OK */ + } + /* device does not have stop_io entry, so stop the I/O */ /* check for a Command or data chain operation in progresss */ /* set the return to CC3BIT & CC4BIT causes infinite loop in MPX1X */ @@ -1862,11 +1900,15 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ return SCPE_OK; /* No CC's all OK */ } else { sim_debug(DEBUG_IRQ, &cpu_dev, - "STPIO chsa %04x NOT POSTED FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", + "STPIOX chsa %04x NOT POSTED FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chan_icb, chp->chan_byte); /* now store the status dw address into word 5 of the ICB for the channel */ - WMW(chan_icb+20, 0); /* post sw addr 0 in ICB+5w & reset CCs */ - *status = 0; /* no status stored from STPIO, so no CC */ +// WMW(chan_icb+20, 0x80000003); /* post CC1 & sw addr 0 in ICB+5w & reset CCs */ + WMW(chan_icb+20, 0x80000000); /* post CC1 & sw addr 0 in ICB+5w & reset CCs */ +// WMW(chan_icb+20, 0); /* post sw addr 0 in ICB+5w & reset CCs */ +//XX *status = 0; /* no status stored from STPIO, so no CC */ + *status = CC1BIT; /* show not busy, post no status with CC1 */ +// *status = CC4BIT; /* BAD FOR DIAG *//* request accepted, busy, so CC4 */ return SCPE_OK; /* No CC's all OK */ } } @@ -1875,9 +1917,13 @@ t_stat stopxio(uint16 lchsa, uint32 *status) { /* stop XIO */ /* having it set to CC1 allows diags to work, but not MPX 3X boot! */ // This check allows DBUG2 and DIAGS to both work if (chp->chan_byte == BUFF_NEXT) - *status = CC1BIT; /* request accepted, no status, so CC1 */ +//BAD?? *status = CC1BIT; /* request accepted, no status, so CC1 */ + *status = CC4BIT; /* BAD FOR DIAG *//* request accepted, busy, so CC4 */ else *status = CC4BIT; /* BAD FOR DIAG *//* request accepted, busy, so CC4 */ + sim_debug(DEBUG_IRQ, &cpu_dev, + "STPIO2 chsa %04x NOT POSTED FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", + rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chan_icb, chp->chan_byte); } // /* reset the DC or CC bits to force completion after current IOCD */ // chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */ @@ -2034,8 +2080,10 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ /* call the device controller to get halt_io status */ tempa = dibp->halt_io(uptr); /* get status from device */ - /* test for SCPE_IOERR (=2) SCPE_OK (=0)*/ - if (tempa != SCPE_OK) { /* sub channel has status ready */ + /* CC's are returned in bits 1-4. Bits 16-31 has SCPE code */ + /* SCPE_IOERR is 2 */ + /* SCPE_OK is 0 */ + if ((tempa & RMASK) != SCPE_OK) { /* sub channel has status ready */ /* The device I/O has been terminated and status stored. */ sim_debug(DEBUG_EXP, &cpu_dev, "HIO halt_io call return ERROR FIFO #%1x rchsa %04x retstat %08x cstat %08x\n", @@ -2048,13 +2096,17 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ sim_debug(DEBUG_EXP, &cpu_dev, "HIO END2X ECHO rchsa %04x cmd %02x ccw_flags %04x status %04x\n", rchsa, chp->ccw_cmd, chp->ccw_flags, *status); - irq_pend = 1; /* flag to test for int condition */ +// irq_pend = 1; /* flag to test for int condition */ + sim_debug(DEBUG_IRQ, &cpu_dev, + "HIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n", + rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte); - /* see if any status ready to post */ - if ((FIFO_Num(rchsa)) && (CPUSTATUS & BIT24)) { /* interrupts blocked? */ + /* see if user wants to have status posted and setting CC2 in return value */ + if ((tempa & LMASK) == CC2BIT) { sim_debug(DEBUG_IRQ, &cpu_dev, "HIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n", rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte); + /* post any status */ if (post_csw(chp, 0)) { uint32 incha = chp->chan_inch_addr; /* get inch address */ sim_debug(DEBUG_IRQ, &cpu_dev, @@ -2073,24 +2125,36 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ INTS[inta] &= ~INTS_REQ; /* clear any level request */ *status = CC2BIT; /* status stored from SIO, so CC2 */ return SCPE_OK; /* No CC's all OK */ - } else { - sim_debug(DEBUG_IRQ, &cpu_dev, - "HIO rchsa %04x NOT POSTED FIFO #%1x irq %02x inch %06x chan_icba %06x chan_byte %02x\n", - rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chan_icb, chp->chan_byte); - /* now store the status dw address into word 5 of the ICB for the channel */ - WMW(chan_icb+20, 0); /* post sw addr 0 in ICB+5w & reset CCs */ - *status = 0; /* no status stored from HIO, so no CC */ - return SCPE_OK; /* No CC's all OK */ } } - if ((CPUSTATUS & BIT24) == 0) { /* interrupts blocked? */ - sim_debug(DEBUG_DETAIL, &cpu_dev, "HIO after END2 INTS not blocked!\n"); + /* see if user wants to have status posted by setting CC4 in return value */ + if ((tempa & LMASK) == CC4BIT) { + sim_debug(DEBUG_IRQ, &cpu_dev, + "HIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n", + rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte); } + sim_debug(DEBUG_EXP, &cpu_dev, + "HIO END2Y rchsa %04x cmd %02x ccw_flags %04x status %04x\n", + rchsa, chp->ccw_cmd, chp->ccw_flags, *status); return SCPE_OK; /* CC1 & all OK */ } /* the device is not busy, so cmd is completed */ sim_debug(DEBUG_EXP, &cpu_dev, - "HIO BUFF_DONE2 chp %p chan_byte %04x\n", chp, chp->chan_byte); + "HIO BUFF_DONE1 chp %p chan_byte %04x\n", chp, chp->chan_byte); +#ifdef BADWAY + /* see if user wants to have status posted by setting CC4 in return value */ + if ((tempa & LMASK) == CC4BIT) { + sim_debug(DEBUG_IRQ, &cpu_dev, + "HIO rchsa %04x LOOK FIFO #%1x irq %02x inch %06x chp %p icba %06x chan_byte %02x\n", + rchsa, FIFO_Num(rchsa), inta, chp->chan_inch_addr, chp, chan_icb, chp->chan_byte); + /* now store the status dw address into word 5 of the ICB for the channel */ +// WMW(chan_icb+20, 0x80000000); /* post sw addr 0 in ICB+5w & reset CCs */ + /* maybe this should be CC4 returned */ + *status = 0; /* no status stored from HIO, so no CC */ +// *status = CC2BIT; /* no status stored from HIO, so no CC */ + return SCPE_OK; /* No CC's all OK */ + } +#endif /* the channel is not busy, so return OK */ *status = CC1BIT; /* request accepted, post good status, so CC1 */ sim_debug(DEBUG_EXP, &cpu_dev, @@ -2101,7 +2165,14 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ chp->chan_byte = BUFF_DONE; /* we are done */ sim_debug(DEBUG_EXP, &cpu_dev, "haltxio BUFF_DONE2 chp %p chan_byte %04x\n", chp, chp->chan_byte); - chp->chan_status = (STATUS_DEND|STATUS_CEND); + if ((dptr != NULL) && + (DEV_TYPE(dptr) == DEV_ETHER)) { /* see if this is ethernet */ + /* Ethernet does not want SNS_UNITEXP */ + chp->chan_status = (STATUS_DEND|STATUS_CEND); + } else { +// chp->chan_status = (STATUS_DEND|STATUS_CEND|STATUS_ECHO); + chp->chan_status = (STATUS_DEND|STATUS_CEND|STATUS_EXPT); + } push_csw(chp); /* store the status 1st in FIFO */ /* change chan_byte to BUFF_POST */ chp->chan_byte = BUFF_POST; /* show done with data */ @@ -2133,7 +2204,9 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ /* device does not have a HIO entry, so terminate the I/O */ /* a haltxio entry should be provided for a device so busy can be cleared */ /* check for a Command or data chain operation in progresss */ +#ifdef XXX if (chp->chan_byte & BUFF_BUSY) { +#endif sim_debug(DEBUG_EXP, &cpu_dev, "HIO device busy lchsa %04x rchsa %04x\n", lchsa, rchsa); @@ -2159,10 +2232,12 @@ t_stat haltxio(uint16 lchsa, uint32 *status) { /* halt XIO */ } return SCPE_OK; /* CC2 & all OK */ } +#ifdef XXX } chp->chan_byte = BUFF_DONE; /* chan prog done */ /* the channel is not busy, so return OK */ *status = CC1BIT; /* request accepted, no status, so CC1 */ +#endif sim_debug(DEBUG_EXP, &cpu_dev, "HIO END5 rchsa %04x cmd %02x ccw_flags %04x status %04x\n", rchsa, chp->ccw_cmd, chp->ccw_flags, *status); @@ -2564,11 +2639,7 @@ uint32 scan_chan(uint32 *ilev) { for (i=0; i<112; i++) { if (SPAD[i+0x80] == 0) /* not initialize? */ continue; /* skip this one */ -#ifdef FIX3X - if (SPAD[i+0x80] == 0xffffffff) /* not initialize? */ -#else if ((SPAD[i+0x80]&MASK24) == MASK24) /* not initialize? */ -#endif continue; /* skip this one */ if (INTS[i] & INTS_REQ) /* if already requesting, skip */ continue; /* skip this one */ @@ -2604,18 +2675,8 @@ uint32 scan_chan(uint32 *ilev) { for (i=0; i<112; i++) { if (SPAD[i+0x80] == 0) /* not initialize? */ continue; /* skip this one */ -#ifdef FIX3X - if (SPAD[i+0x80] == 0xffffffff) /* not initialize? */ -#else - if ((SPAD[i+0x80]&MASK24) == MASK24) /* not initialize? */ -#endif - continue; /* skip this one */ /* this is a bug fix for MPX 1.x restart command */ -#ifdef FIX3X - if (SPAD[i+0x80] == 0xefffffff) /* not initialize? */ -#else if ((SPAD[i+0x80]&MASK24) == MASK24) /* not initialize? */ -#endif continue; /* skip this one */ if ((INTS[i]&INTS_ACT) || (SPAD[i+0x80]&SINT_ACT)) { /* look for level active */ sim_debug(DEBUG_DETAIL, &cpu_dev, diff --git a/SEL32/sel32_con.c b/SEL32/sel32_con.c index 63a3152..804ac4b 100644 --- a/SEL32/sel32_con.c +++ b/SEL32/sel32_con.c @@ -649,22 +649,24 @@ t_stat con_haltio(UNIT *uptr) { "con_haltio HIO chsa %04x cmd = %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count); sim_cancel(uptr); /* stop timer */ - } else { + /* stop any I/O and post status and return error status */ + chp->ccw_count = 0; /* zero the count */ + chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */ + uptr->CMD &= LMASK; /* make non-busy */ + uptr->u4 = 0; /* no I/O yet */ + con_data[unit].incnt = 0; /* no input data */ + uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */ sim_debug(DEBUG_CMD, &con_dev, - "con_haltio HIO not busy chsa %04x cmd = %02x ccw_count %02x\n", - chsa, cmd, chp->ccw_count); + "con_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd); + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ + return CC2BIT | SCPE_IOERR; /* tell chan code to post status */ } - /* stop any I/O and post status and return error status */ - chp->ccw_count = 0; /* zero the count */ - chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* reset chaining bits */ uptr->CMD &= LMASK; /* make non-busy */ - uptr->u4 = 0; /* no I/O yet */ - con_data[unit].incnt = 0; /* no input data */ uptr->SNS = SNS_RDY|SNS_ONLN; /* status is online & ready */ sim_debug(DEBUG_CMD, &con_dev, - "con_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd); - chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ - return SCPE_IOERR; /* tell chan code to post status */ + "con_haltio HIO not busy chsa %04x cmd = %02x ccw_count %02x\n", + chsa, cmd, chp->ccw_count); + return CC1BIT | SCPE_OK; /* not busy */ } #endif diff --git a/SEL32/sel32_cpu.c b/SEL32/sel32_cpu.c index de75eae..adeaed0 100644 --- a/SEL32/sel32_cpu.c +++ b/SEL32/sel32_cpu.c @@ -3665,9 +3665,6 @@ tbr: /* handle basemode TBR too * t = (GPR[reg] >> 16) & 0xff; /* get SPAD address from Rd (6-8) */ temp2 = SPAD[t]; /* get old SPAD data */ SPAD[t] = GPR[sreg]; /* store Rs into SPAD */ -sim_debug(DEBUG_XIO, &cpu_dev, - "TRSC B4 spad[%d] %08x R[%d] %08x R[%d] %08x at PSD1 %08x\n", - t, temp2, sreg, GPR[sreg], reg, GPR[reg], PSD1); break; case 0xF: /* TSCR */ /* Transfer scratchpad to register */ @@ -3705,21 +3702,13 @@ skipit: if ((PSD1 & 2) != 0) /* is it lf hw instruction */ goto inv; /* invalid instr if in rt hw */ addr = SPAD[0xf0]; /* get trap table memory address from SPAD (def 80) */ -#ifdef FIX3X - if ((addr == 0) || (addr == 0xffffffff)) { /* see if secondary vector table set up */ -#else if ((addr == 0) || ((addr&MASK24) == MASK24)) { /* see if secondary vector table set up */ -#endif TRAPME = ADDRSPEC_TRAP; /* Not setup, error */ goto newpsd; /* program error */ } addr = addr + (0x0A << 2); /* addr has mem addr of CALM trap vector (def A8) */ t = M[addr >> 2]; /* get the ICB address from memory */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) { /* see if ICB set up */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) { /* see if ICB set up */ -#endif TRAPME = ADDRSPEC_TRAP; /* Not setup, error */ goto newpsd; /* program error */ } @@ -5347,31 +5336,19 @@ skipdqe2: int32c = CPUSTATUS; /* keep for retain blocking state */ addr = SPAD[0xf0]; /* get trap table memory address from SPAD (def 80) */ int32a = addr; -#ifdef FIX3X - if (addr == 0 || addr == 0xffffffff) { /* see if secondary vector table set up */ -#else if (addr == 0 || ((addr&MASK24) == MASK24)) { /* see if secondary vector table set up */ -#endif TRAPME = ADDRSPEC_TRAP; /* Not setup, error */ goto newpsd; /* program error */ } addr = addr + (0x06 << 2); /* addr has mem addr of SVC trap vector (def 98) */ temp = M[addr >> 2]; /* get the secondary trap table address from memory */ -#ifdef FIX3X - if (temp == 0 || temp == 0xffffffff) { /* see if ICB set up */ -#else if (temp == 0 || ((temp&MASK24) == MASK24)) { /* see if ICB set up */ -#endif TRAPME = ADDRSPEC_TRAP; /* Not setup, error */ goto newpsd; /* program error */ } temp2 = ((IR>>12) & 0x0f) << 2; /* get SVC index from IR */ t = M[(temp+temp2)>>2]; /* get secondary trap vector address ICB address */ -#ifdef FIX3X - if (t == 0 || t == 0xffffffff) { /* see if ICB set up */ -#else if (temp == 0 || ((temp&MASK24) == MASK24)) { /* see if ICB set up */ -#endif TRAPME = ADDRSPEC_TRAP; /* Not setup, error */ goto newpsd; /* program error */ } @@ -6006,9 +5983,7 @@ skipdqe2: case 0x3: /* LPSD F980 */ /* fall through */; case 0x5: /* LPSDCM FA80 */ -#ifdef MAYBE_NO irq_pend = 1; /* start scanning interrupts again */ -#endif if ((MODES & PRIVBIT) == 0) { /* must be privileged */ TRAPME = PRIVVIOL_TRAP; /* set the trap to take */ if ((CPU_MODEL == MODEL_97) || (CPU_MODEL == MODEL_V9)) @@ -6216,7 +6191,6 @@ skipdqe: /* if this code is not present, MPX3X will not boot correctly */ if (spc != CPIXPL) { PSD2 &= ~RETMBIT; /* no, turn off retain bit in PSD2 */ -// cpu_dev.dctrl |= DEBUG_INST; /* start instruction trace */ } /* if this code is not present MPX3X will abort */ /* when trying to mount a secondary disk */ @@ -6352,11 +6326,7 @@ skipdqe: break; /* ignore */ /* SPAD entries for interrupts begin at 0x80 */ t = SPAD[prior+0x80]; /* get spad entry for interrupt */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) /* if unused, ignore instruction */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) /* if unused, ignore instruction */ -#endif break; /* ignore */ if ((t & 0x0f800000) == 0x0f000000) /* if class F ignore instruction */ @@ -6390,11 +6360,7 @@ skipdqe: /* SPAD entries for interrupts begin at 0x80 */ t = SPAD[prior+0x80]; /* get spad entry for interrupt */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) /* if unused, ignore instruction */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) /* if unused, ignore instruction */ -#endif break; /* ignore */ if ((t & 0x0f800000) == 0x0f000000) /* if class F ignore instruction */ @@ -6428,11 +6394,7 @@ skipdqe: break; /* ignore */ /* SPAD entries for interrupts begin at 0x80 */ t = SPAD[prior+0x80]; /* get spad entry for interrupt */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) /* if unused, ignore instruction */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) /* if unused, ignore instruction */ -#endif break; /* ignore */ if ((t & 0x0f800000) == 0x0f000000) /* if class F ignore instruction */ @@ -6447,11 +6409,7 @@ skipdqe: break; /* ignore */ /* SPAD entries for interrupts begin at 0x80 */ t = SPAD[prior+0x80]; /* get spad entry for interrupt */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) /* if unused, ignore instruction */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) /* if unused, ignore instruction */ -#endif break; /* ignore */ if ((t & 0x0f800000) == 0x0f000000) /* if class F ignore instruction */ @@ -6467,11 +6425,7 @@ skipdqe: break; /* ignore */ /* SPAD entries for interrupts begin at 0x80 */ t = SPAD[prior+0x80]; /* get spad entry for interrupt */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff)) /* if unused, ignore instruction */ -#else if ((t == 0) || ((t&MASK24) == MASK24)) /* if unused, ignore instruction */ -#endif break; /* ignore */ if ((t & 0x0f800000) == 0x0f000000) /* if class F ignore instruction */ @@ -6577,11 +6531,7 @@ skipdqe: /* the channel must be defined as a class F I/O channel in SPAD */ /* if not class F, the system will generate a system check trap */ t = SPAD[lchan]; /* get spad entry for channel */ -#ifdef FIX3X - if ((t == 0) || (t == 0xffffffff) || /* if not set up, system check */ -#else if ((t == 0) || ((t&MASK24) == MASK24) || /* if not set up, system check */ -#endif ((t & 0x0f800000) != 0x0f000000)) { /* class in bits 4-7 */ TRAPME = SYSTEMCHK_TRAP; /* trap condition if F class */ TRAPSTATUS |= BIT0; /* class F error bit */ @@ -7036,11 +6986,7 @@ newpsd: /* SPAD location 0xf0 has trap vector base address */ uint32 tta = SPAD[0xf0]; /* get trap table address in memory */ uint32 tvl; /* trap vector location */ -#ifdef FIX3X - if ((tta == 0) || (tta == 0xffffffff) -#else if ((tta == 0) || ((tta&MASK24) == MASK24)) -#endif tta = 0x80; /* if not set, assume 0x80 FIXME */ /* Trap Table Address in memory is pointed to by SPAD 0xF0 */ /* TODO update cpu status and trap status words with reason too */ @@ -7111,7 +7057,7 @@ newpsd: "##PAGEFAULT TRAPS %02x page# %04x LOAD MAPS PSD1 %08x PSD2 %08x CPUSTATUS %08x\n", TRAPME, pfault, PSD1, PSD2, CPUSTATUS); } - /* Moved here 05/28/2021 so PC does not get incremeneted incorrectly */ + /* Moved here 05/28/2021 so PC gets incremented incorrectly */ /* This caused the 2nd instruction of an int service routine to be skipped */ /* The attn trap had to be on 2nd instruction */ case CONSOLEATN_TRAP: /* 0xB4 PL0D Console Attention Trap */ @@ -7362,8 +7308,8 @@ t_stat cpu_reset(DEVICE *dptr) SPAD[0xf9] = CPUSTATUS; /* set default cpu type in cpu status word */ SPAD[0xff] = 0x00ffffff; /* interrupt level 7f 1's complament */ } - /* set low memory bootstrap code */ #if 0 + /* set low memory bootstrap code */ /* moved to boot code in sel32_chan.c so we can reset system and not destroy memory */ M[0] = 0x02000000; /* 0x00 IOCD 1 read into address 0 */ M[1] = 0x60000078; /* 0x04 IOCD 1 CMD Chain, Suppress incor len, 120 bytes */ diff --git a/SEL32/sel32_disk.c b/SEL32/sel32_disk.c index dae2cec..52e1fdd 100644 --- a/SEL32/sel32_disk.c +++ b/SEL32/sel32_disk.c @@ -294,6 +294,10 @@ bits 24-31 - FHD head count (number of heads on FHD or number head on FHD option /* us9 */ /* us9 holds bytes 4 & 5 of the status for the drive */ +#define LASTCNT us10 +/* us10 */ +/* us10 holds original read/write byte count from iocd */ + /* Sense byte 4 */ #define SNS_SEND 0x8000 /* Seek End */ #define SNS_USEL 0x4000 /* Unit Selected */ @@ -1029,9 +1033,10 @@ t_stat disk_startcmd(UNIT *uptr, uint16 chan, uint8 cmd) uptr->SNS2 = (SNS_UNR|SNS_ONC|SNS_USEL);/* reset status to on cyl & ready */ case DSK_SNS: /* Sense 0x04 */ uptr->CMD |= cmd; /* save cmd */ + uptr->LASTCNT = chp->ccw_count; /* save cmd count for diags */ sim_debug(DEBUG_CMD, dptr, - "disk_startcmd starting disk cmd %02x chsa %04x\n", - cmd, chsa); + "disk_startcmd starting disk cmd %02x chsa %04x cnt %04x \n", + cmd, chsa, chp->ccw_count); #ifdef FAST_FOR_UTX /* when value was 50, UTX would get a spontainous interrupt */ /* when value was 30, UTX would get a spontainous interrupt */ @@ -1068,24 +1073,30 @@ t_stat disk_haltio(UNIT *uptr) { /* status must not have an error bit set */ /* otherwise, UTX will panic with "bad status" */ /* stop any I/O and post status and return error status */ - chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* stop any chaining */ - uptr->CMD &= LMASK; /* make non-busy */ - uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ + sim_debug(DEBUG_EXP, dptr, + "disk_haltio HIO I/O stop chsa %04x cmd = %02x CHS %08x STAR %08x\n", + chsa, cmd, uptr->CHS, uptr->STAR); if ((uptr->CMD & DSK_CMDMSK) != 0) { /* is unit busy */ sim_debug(DEBUG_EXP, dptr, "disk_haltio HIO chsa %04x cmd = %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count); sim_cancel(uptr); /* clear the input timer */ + chp->ccw_count = 0; /* zero the count */ + chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* stop any chaining */ + uptr->CMD &= LMASK; /* make non-busy */ +// chp->chan_caw = 0; /* zero iocd address for diags */ + uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ chan_end(chsa, SNS_CHNEND|SNS_DEVEND|SNS_UNITEXP); /* force end */ - } else { - sim_debug(DEBUG_DETAIL, dptr, - "disk_haltio HIO I/O not busy chsa %04x cmd = %02x\n", chsa, cmd); - chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ +// return CC2BIT | SCPE_IOERR; + return CC1BIT | SCPE_IOERR; /* DIAGS want just an interrupt */ } - sim_debug(DEBUG_EXP, dptr, - "disk_haltio HIO I/O stop chsa %04x cmd = %02x CHS %08x STAR %08x\n", - chsa, cmd, uptr->CHS, uptr->STAR); - return SCPE_IOERR; + sim_debug(DEBUG_DETAIL, dptr, + "disk_haltio HIO I/O not busy chsa %04x cmd = %02x\n", chsa, cmd); + uptr->CMD &= LMASK; /* make non-busy */ + uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ +// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_ECHO); /* post 0x80000000 to ICB */ +// return CC4BIT | SCPE_OK; /* not busy return */ + return CC1BIT | SCPE_OK; /* not busy return */ } /* Handle processing of disk requests. */ @@ -1824,11 +1835,19 @@ iha_error: /* convert sector number back to chs value to sync disk for diags */ uptr->CHS = disksec2star(tstart, type); + sim_debug(DEBUG_CMD, dptr, + "DISK B4READ reading CMD %08x chsa %04x tstart %04x buffer %06x count %04x\n", + uptr->CMD, chsa, tstart, chp->ccw_addr, chp->ccw_count); + /* get alternate track if this one is defective */ tempt = get_dmatrk(uptr, uptr->CHS, lbuf); /* file offset in bytes to std or alt track */ tstart = STAR2SEC(tempt, SPT(type), SPC(type)) * SSB(type); + sim_debug(DEBUG_CMD, dptr, + "DISK FTRREAD reading CMD %08x chsa %04x tstart %04x buffer %06x count %04x\n", + uptr->CMD, chsa, tstart, chp->ccw_addr, chp->ccw_count); + if ((tempt == 0) && (uptr->STAR != 0)) { /* we have error */ sim_debug(DEBUG_EXP, dptr, @@ -1846,7 +1865,10 @@ iha_error: uptr->SNS |= SNS_DADE; /* disk addr error */ uptr->CMD &= LMASK; /* remove old status bits & cmd */ sim_debug(DEBUG_EXP, dptr, - "disk_srv READ2 get_dmatrk return spare tempt %06x tstart %06x\n", tempt, tstart); + "disk_srv READ2 get_dmatrk return spare tempt %06x tstart %06x LASTCNT %04x\n", + tempt, tstart, uptr->LASTCNT); + /* restore original transfer count */ + chp->ccw_count = uptr->LASTCNT; /* restore original transfer count */ chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK); break; } @@ -1856,6 +1878,11 @@ iha_error: uptr->SNS |= SNS_MOCK; /* mode check error */ uptr->SNS |= SNS_RTAE; /* reserved track access error */ uptr->CMD &= LMASK; /* remove old status bits & cmd */ + sim_debug(DEBUG_EXP, dptr, + "disk_srv READ3 get_dmatrk return spare tempt %06x tstart %06x LASTCNT %04x\n", + tempt, tstart, uptr->LASTCNT); + /* restore original transfer count */ + chp->ccw_count = uptr->LASTCNT; /* restore original transfer count */ chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_PCHK); break; } @@ -1921,7 +1948,7 @@ if ((chp->ccw_addr == 0x3cde0) && (buf[0] == 0x4a)) { if (chp->chan_status & STATUS_PCHK) /* test for memory error */ uptr->SNS |= SNS_INAD; /* invalid address */ sim_debug(DEBUG_EXP, dptr, - "DISK Read %04x bytes leaving %04x from diskfile %04x/%02x/%02x\n", + "DISK READ4 %04x bytes leaving %04x from diskfile %04x/%02x/%02x\n", i, chp->ccw_count, ((uptr->CHS)>>16)&0xffff, ((uptr->CHS)>>8)&0xff, (uptr->CHS)&0xff); uptr->CMD &= LMASK; /* remove old status bits & cmd */ @@ -2032,6 +2059,9 @@ if ((chp->ccw_addr == 0x3cde0) && (buf[0] == 0x4a)) { ((uptr->CHS)>>16)&0xffff, ((uptr->CHS)>>8)&0xff, (uptr->CHS)&0xff); if (uptr->SNS & 0xf0000000) { /* see if any mode bit 0-3 is set */ + sim_debug(DEBUG_CMD, dptr, + "DISK WRITE2 starting CMD %08x chsa %04x buffer %06x count %04x\n", + uptr->CMD, chsa, chp->ccw_addr, chp->ccw_count); uptr->SNS |= SNS_MOCK; /* mode check error */ chp->chan_status |= STATUS_PCHK; /* channel prog check */ uptr->CMD &= LMASK; /* remove old status bits & cmd */ diff --git a/SEL32/sel32_ec.c b/SEL32/sel32_ec.c index cb03fcc..4629881 100644 --- a/SEL32/sel32_ec.c +++ b/SEL32/sel32_ec.c @@ -1472,25 +1472,24 @@ t_stat ec_haltio(UNIT *uptr) { sim_debug(DEBUG_CMD, dptr, "ec_haltio HIO chsa %04x cmd = %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count); // stop any I/O and post status and return error status */ + if (chsa & 0x0f) /* no cancel for 0 */ + sim_cancel(uptr); /* clear the output timer */ chp->ccw_count = 0; /* zero the count */ +//? chp->chan_caw = 0; /* zero iocd address for diags */ chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* stop any chaining */ uptr->CMD &= LMASK; /* make non-busy */ uptr->SNS = SNS_RCV_RDY; /* status is online & ready */ - if (chsa & 0x0f) /* no cancel for 0 */ - sim_cancel(uptr); /* clear the output timer */ sim_debug(DEBUG_CMD, dptr, "ec_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd); /* No unit exception status for ethernet */ chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ -// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_LENGTH|STATUS_PCHK); -// chan_end(chsa, SNS_CHNEND|SNS_DEVEND|STATUS_LENGTH); - return SCPE_IOERR; + return CC1BIT | SCPE_IOERR; } - uptr->CMD &= LMASK; /* make non-busy */ - uptr->SNS = SNS_RCV_RDY; /* status is online & ready */ sim_debug(DEBUG_CMD, dptr, "ec_haltio HIO I/O not busy chsa %04x cmd = %02x\n", chsa, cmd); - return SCPE_OK; /* not busy */ + uptr->CMD &= LMASK; /* make non-busy */ + uptr->SNS = SNS_RCV_RDY; /* status is online & ready */ + return CC1BIT | SCPE_OK; /* not busy */ } /* initialize the ethernet */ diff --git a/SEL32/sel32_hsdp.c b/SEL32/sel32_hsdp.c index 0e0ad59..2e4f155 100644 --- a/SEL32/sel32_hsdp.c +++ b/SEL32/sel32_hsdp.c @@ -571,9 +571,7 @@ MTAB hsdp_mod[] = { }; UNIT dpa_unit[] = { -/* SET_TYPE(3) DM300 */ /* SET_TYPE(10) 8887 */ -/* SET_TYPE(11) 8887 */ {UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x800)}, /* 0 */ {UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x802)}, /* 1 */ {UDATA(&hsdp_srv, UNIT_HSDP|SET_TYPE(10), 0), 0, UNIT_ADDR(0x804)}, /* 2 */ @@ -858,7 +856,6 @@ t_stat hsdp_iocl(CHANP *chp, int32 tic_ok) uint32 word1 = 0; uint32 word2 = 0; int32 docmd = 0; -// DIB *dibp = dib_unit[chp->chan_dev];/* get the DIB pointer */ UNIT *uptr = chp->unitptr; /* get the unit ptr */ uint16 chan = get_chan(chp->chan_dev); /* our channel */ uint16 chsa = chp->chan_dev; /* our chan/sa */ @@ -910,9 +907,6 @@ loop: chp->chan_caw, chan, word1, word2, uptr->SNS); chp->chan_caw = (chp->chan_caw & 0xfffffc) + 8; /* point to next IOCD */ -#ifdef BAD_05142021 - chp->ccw_cmd = (word1 >> 24) & 0xff; /* set command from IOCD wd 1 */ -#endif /* Check if we had data chaining in previous iocd */ /* if we did, use previous cmd value */ @@ -941,8 +935,6 @@ loop: case DSK_IHA: case DSK_WTL: case DSK_RTL: case DSK_RAP: case DSK_WTF: case DSK_FMT: case DSK_RE: case DSK_RENO: case DSK_REL: case DSK_RES: case DSK_RVL: case DSK_POR: case DSK_REC: case DSK_TIC: - /* reset status to on cyl & ready */ -// uptr->SNS2 = (SNS_UNR|SNS_ONC|SNS_USEL); case DSK_SNS: break; default: @@ -998,14 +990,9 @@ loop: } /* Check if we had data chaining in previous iocd */ -#ifdef BAD_05152021 - if ((chp->chan_info & INFO_SIOCD) || /* see if 1st IOCD in channel prog */ - ((chp->ccw_flags & FLAG_DC) == 0)) { /* last IOCD have DC set? */ -#else if ((chp->chan_info & INFO_SIOCD) || /* see if 1st IOCD in channel prog */ (((chp->chan_info & INFO_SIOCD) == 0) && /* see if 1st IOCD in channel prog */ ((chp->ccw_flags & FLAG_DC) == 0))) { /* last IOCD have DC set? */ -#endif sim_debug(DEBUG_CMD, dptr, "hsdp_iocl @%06x DO CMD No DC, ccw_flags %04x cmd %02x\n", chp->chan_caw, chp->ccw_flags, chp->ccw_cmd); @@ -1211,24 +1198,27 @@ t_stat hsdp_haltio(UNIT *uptr) { /* UTX wants SLI bit, but no unit exception */ /* status must not have an error bit set */ /* otherwise, UTX will panic with "bad status" */ - if ((uptr->CMD & DSK_CMDMSK) != 0) { /* is unit busy */ + /* stop any I/O and post status and return error status */ + sim_debug(DEBUG_CMD, dptr, + "hsdp_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd); + if ((uptr->CMD & DSK_CMDMSK) != 0) { /* is unit busy */ sim_debug(DEBUG_CMD, dptr, "hsdp_haltio HIO chsa %04x cmd = %02x ccw_count %02x\n", chsa, cmd, chp->ccw_count); - sim_cancel(uptr); /* clear the input timer */ + sim_cancel(uptr); /* clear the input timer */ + chp->ccw_count = 0; /* zero the count */ + chp->chan_caw = 0; /* zero iocd address for diags */ + chp->ccw_flags &= ~(FLAG_DC|FLAG_CC); /* stop any chaining */ + uptr->CMD &= LMASK; /* make non-busy */ + uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ + chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ + return CC2BIT | SCPE_IOERR; /* busy return */ } else { sim_debug(DEBUG_CMD, dptr, "hsdp_haltio HIO I/O not busy chsa %04x cmd = %02x\n", chsa, cmd); + uptr->CMD &= LMASK; /* make non-busy */ + uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ + return CC1BIT | SCPE_OK; /* not busy */ } - /* stop any I/O and post status and return error status */ - chp->ccw_count = 0; /* zero the count */ - chp->chan_caw = 0; /* zero iocd address for diags */ - chp->ccw_flags &= ~(FLAG_DC|FLAG_CC);/* stop any chaining */ - uptr->CMD &= LMASK; /* make non-busy */ - uptr->SNS2 |= (SNS_ONC|SNS_UNR); /* on cylinder & ready */ - sim_debug(DEBUG_CMD, dptr, - "hsdp_haltio HIO I/O stop chsa %04x cmd = %02x\n", chsa, cmd); - chan_end(chsa, SNS_CHNEND|SNS_DEVEND); /* force end */ - return SCPE_IOERR; } /* Handle rsctl command for disk */ @@ -1838,7 +1828,7 @@ iha_error: uptr->LSC, (tstar>>16)&0xffff, (tstar>>8)&0xff, tstar&0xff); //#define DO_DYNAMIC_DEBUG #ifdef DO_DYNAMIC_DEBUG -// cpu_dev.dctrl |= DEBUG_INST|DEBUG_TRAP|DEBUG_CMD|DEBUG_DETAIL; /* start instruction trace */ +// cpu_dev.dctrl |= DEBUG_INST|DEBUG_TRAP|DEBUG_CMD|DEBUG_DETAIL; /* start instruction trace */ #endif }