diff --git a/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common b/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
index 1a0d113..de49547 160000
--- a/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
+++ b/sbus-to-ztex-gateware-migen/VintageBusFPGA_Common
@@ -1 +1 @@
-Subproject commit 1a0d113e8bd9126625e55d5572d00569d47a88ac
+Subproject commit de495473a94e0aabb9f498bdc996bdeab15195f7
diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
index ee5f350..5955065 100644
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
@@ -560,7 +560,7 @@ class SBusFPGA(SoCCore):
                 self.bus.add_slave("goblin_accel", self.goblin_accel.bus, SoCRegion(origin=self.mem_map.get("jareth", None), size=0x1000, cached=False))
                 self.bus.add_master(name="goblin_accel_r5_i", master=self.goblin_accel.ibus)
                 self.bus.add_master(name="goblin_accel_r5_d", master=self.goblin_accel.dbus)
-                goblin_rom_file = "blit_goblin.raw"
+                goblin_rom_file = "VintageBusFPGA_Common/blit_goblin_sbus.raw"
                 goblin_rom_data = soc_core.get_mem_data(filename_or_regions=goblin_rom_file, endianness="little")
                 goblin_rom_len = 4*len(goblin_rom_data);
                 rounded_goblin_rom_len = 2**log2_int(goblin_rom_len, False)