From 04a01f564c0d4d588b23aefcc493d00dbfff60bb Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Mon, 14 Dec 2020 12:57:00 +0100 Subject: [PATCH] Update README.md --- README.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 7ecea39..7a05686 100644 --- a/README.md +++ b/README.md @@ -8,15 +8,15 @@ So unless you're a retrocomputing enthusiast with such a machine, this is useles I'm a software guy and know next to nothing about hardware design, so this is very much a work-in-progress and is likely full of rookie mistakes. -To save on PCB cost, the board is smaller than a 'true' SBus board; the directory includes an OpenSCAD 3D-printable extension to make the board compliant to the form factor (visible in the pictures in 'Pictures'). +To save on PCB cost, the board is smaller than a 'true' SBus board; the hardware directory includes an OpenSCAD 3D-printable extension to make the board compliant to the form factor (visible in the pictures in 'Pictures'). ## The hardware Directory 'sbus-to-ztex' -The board is a SBus-compliant (I hope...) board, designed to receive a [ZTex USB-FPGA Module 2.13](https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html) as a daughterboard. The ZTex module contains the actual FPGA (Artix-7), some RAM, programming hardware, etc. The SBus board contains level-shifters ICs to interface between the SBus signals and the FPGA, some Leds, a JTAG header, and a micro-sd card slot. +The custom board is a SBus-compliant (I hope...) board, designed to receive a [ZTex USB-FPGA Module 2.13](https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html) as a daughterboard. The ZTex module contains the actual FPGA (Artix-7), some RAM, programming hardware, etc. The SBus board contains level-shifters ICs to interface between the SBus signals and the FPGA, a serial header, some Leds, a JTAG header, and a micro-sd card slot. -This was designed with Kicad 5.0. +The PCB was designed with Kicad 5.0 ## The gateware @@ -24,6 +24,8 @@ Directory 'sbus-to-ztex-gateware' The function embedded in the FPGA currently includes the PROM, lighting Led to display a 32-bits value, and a GHASH MAC (128 polynomial accumulator, used for the AES-GCM encryption scheme). The device is a fairly basic scale, but should be able to read from the PROM and read/write from the GCM space with any kind of SBus burst (1, 2, 4, 8 or 16 words). +The gateware is currently synthesized with Vivado 2020.1 + ## The software Directory 'NetBSD'