From 119862f57f951705d10513b957f2c7fcd37949b0 Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Sat, 16 Jan 2021 03:17:47 -0500 Subject: [PATCH] switch to different sdcard controller, still not working --- sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd | 373 +++++++++++++++++++ sbus-to-ztex-gateware/sbus_fsm.vhd | 64 +++- 2 files changed, 420 insertions(+), 17 deletions(-) create mode 100644 sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd diff --git a/sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd b/sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd new file mode 100644 index 0000000..8830526 --- /dev/null +++ b/sbus-to-ztex-gateware/SimpleSDHC_wrapper.vhd @@ -0,0 +1,373 @@ +library ieee; +USE ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity SimpleSDHC_wrapper is + port ( + SimpleSDHC_wrapper_rst : in std_logic; + SimpleSDHC_wrapper_clk : in std_logic; + output_fifo_in : out std_logic_vector(160 downto 0); --1+ 32 +128 + output_fifo_full : in std_logic; + output_fifo_wr_en : out std_logic; + input_fifo_out : in std_logic_vector(127 downto 0); + input_fifo_empty : in std_logic; + input_fifo_rd_en : out std_logic; + out_sd_rd : in std_logic; + out_sd_addr : in std_logic_vector(31 downto 0); + out_sd_rd_addr_req : in std_logic; + out_sd_rd_addr_ack : out std_logic; + -- pins + cs_bo : out std_logic; + sclk_o : out std_logic; + mosi_o : out std_logic; + miso_i : in std_logic; + -- LEDs + leds : out std_logic_vector(7 downto 0) + ); +end SimpleSDHC_wrapper; + + +architecture RTL of SimpleSDHC_wrapper is + + component sd_controller is + generic ( + clockRate : integer := 50000000; -- Incoming clock is 25MHz (can change this to 2000 to test Write Timeout) + slowClockDivider : integer := 128; -- For a 50MHz clock, slow clock for startup is 50/128 = 390kHz + R1_TIMEOUT : integer := 64; -- Number of bytes to wait before giving up on receiving R1 response + WRITE_TIMEOUT : integer range 0 to 999 := 500; -- Number of ms to wait before giving up on write completing + RESET_TICKS : integer := 64; -- Number of half clock cycles being pulsed before lowing sd_busy in IDLE2 + ACTION_RETRIES : integer := 200; -- Number of retries when SEND_CMD_5 fails + READ_TOKEN_TIMEOUT : integer := 1000 -- Number of retries to receive the read start token "FE" + ); + port ( + cs : out std_logic; -- To SD card + mosi : out std_logic; -- To SD card + miso : in std_logic; -- From SD card + sclk : out std_logic; -- To SD card + card_present : in std_logic; -- From socket - can be fixed to '1' if no switch is present + card_write_prot : in std_logic; -- From socket - can be fixed to '0' if no switch is present, or '1' to make a Read-Only interface + + rd : in std_logic; -- Trigger single block read + rd_multiple : in std_logic; -- Trigger multiple block read + dout : out std_logic_vector(7 downto 0); -- Data from SD card + dout_avail : out std_logic; -- Set when dout is valid + dout_taken : in std_logic; -- Acknowledgement for dout + + wr : in std_logic; -- Trigger single block write + wr_multiple : in std_logic; -- Trigger multiple block write + din : in std_logic_vector(7 downto 0); -- Data to SD card + din_valid : in std_logic; -- Set when din is valid + din_taken : out std_logic; -- Ackowledgement for din + + addr : in std_logic_vector(31 downto 0); -- Block address + erase_count : in std_logic_vector(7 downto 0); -- For wr_multiple only + + sd_error : out std_logic; -- '1' if an error occurs, reset on next RD or WR + sd_busy : out std_logic; -- '0' if a RD or WR can be accepted + sd_error_code : out std_logic_vector(7 downto 0); -- See above, 000=No error + + + reset : in std_logic; -- System reset + clk : in std_logic; -- twice the SPI clk (max 50MHz) + + -- Optional debug outputs + sd_type : out std_logic_vector(1 downto 0); -- Card status (see above) + sd_fsm : out std_logic_vector(7 downto 0) := "11111111" -- FSM state (see block at end of file) + ); + end component; + + signal sd_reset : std_logic; + signal sd_rd : std_logic; + signal sd_wr : std_logic; + signal sd_continue : std_logic; + signal sd_addr : std_logic_vector(31 downto 0); + signal sd_data_i : std_logic_vector(7 downto 0); + signal sd_data_o : std_logic_vector(7 downto 0); + signal sd_busy : std_logic; + signal sd_dout_avail : std_logic; + signal sd_dout_taken : std_logic; + signal sd_din_valid : std_logic; + signal sd_din_taken : std_logic; + signal sd_error : std_logic; + signal sd_error_code : std_logic_vector(7 downto 0); + signal sd_type : std_logic_vector(1 downto 0); + + constant BLOCK_SIZE_G : natural := 512; + + TYPE SIMPLESDHC_States IS ( + SIMPLESDHC_IDLE, + SIMPLESDHC_INIT, + SIMPLESDHC_READ_WAIT_BUSY, + SIMPLESDHC_READ_WAIT_READ, + SIMPLESDHC_READ_WAIT_READ2, + SIMPLESDHC_WAIT_NOTBUSY, + SIMPLESDHC_WRITE_WAIT_BUSY, + SIMPLESDHC_WRITE_WAIT_WRITE, + SIMPLESDHC_WRITE_WAIT_WRITE2); + SIGNAL SIMPLESDHC_State : SIMPLESDHC_States := SIMPLESDHC_INIT; + +begin + + label_sd_controller: sd_controller + generic map ( + clockRate => 50000000, + slowClockDivider => 128, + R1_TIMEOUT => 10, + WRITE_TIMEOUT => 500 + ) + port map ( + -- pins + cs => cs_bo, + mosi => mosi_o, + miso => miso_i, + sclk => sclk_o, + card_present => '1', + card_write_prot => '0', + -- internal + rd => sd_rd, + rd_multiple => '0', + dout => sd_data_o, + dout_avail => sd_dout_avail, + dout_taken => sd_dout_taken, + + wr => sd_wr, + wr_multiple => '0', + din => sd_data_i, + din_valid => sd_din_valid, + din_taken => sd_din_taken, + + addr => sd_addr, + erase_count => (others => '0'), + + sd_error => sd_error, + sd_busy => sd_busy, + sd_error_code => sd_error_code, + + + reset => sd_reset, + clk => SimpleSDHC_wrapper_clk, + + -- Optional debug outputs + sd_type => sd_type, + sd_fsm => leds + ); + + SimpleSDHC_wrapper: process (SimpleSDHC_wrapper_rst, SimpleSDHC_wrapper_clk) + variable init_done : boolean := false; + constant TIMEOUT_MAX : integer := 5000000; + variable timeout_counter : natural range 0 to TIMEOUT_MAX := TIMEOUT_MAX; + variable timedout : std_logic_vector(15 downto 0) := x"0000"; + variable byte_counter : natural range 0 to BLOCK_SIZE_G := 0; -- fixme, wasteful + variable databuf : std_logic_vector(127 downto 0); + variable buf_counter : natural range 0 to 65535 := 0; + variable last_addr : std_logic_vector(31 downto 0); + + begin -- process SimpleSDHC_wrapper + IF (SimpleSDHC_wrapper_rst = '0') THEN +-- if (RISING_EDGE(SimpleSDHC_wrapper_clk)) THEN + sd_reset <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_INIT; + timedout := x"0000"; + byte_counter := 0; + timeout_counter := TIMEOUT_MAX; + init_done := false; + buf_counter := 0; + -- end if; + + ELSIF RISING_EDGE(SimpleSDHC_wrapper_clk) then + sd_reset <= '0'; + output_fifo_wr_en <= '0'; + input_fifo_rd_en <= '0'; + if (out_sd_rd_addr_req = '0') THEN + out_sd_rd_addr_ack <= '0'; + END IF; + -- out_sd_rd_addr_ack <= '0'; + case SIMPLESDHC_State IS + when SIMPLESDHC_IDLE => + sd_rd <= '0'; + sd_wr <= '0'; + if ((sd_busy = '0') and (out_sd_rd_addr_req ='1')) THEN -- handshake +--output_fifo_in <= '1' & x"7000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +--output_fifo_wr_en <= '1'; + out_sd_rd_addr_ack <= '1'; + sd_addr <= out_sd_addr; + last_addr := out_sd_addr; + byte_counter := 0; + buf_counter := 0; + timeout_counter := TIMEOUT_MAX; + IF (out_sd_rd = '1') THEN +--output_fifo_in <= '1' & x"6000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +--output_fifo_wr_en <= '1'; + sd_rd <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_READ_WAIT_BUSY; + ELSE + sd_wr <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_WRITE_WAIT_BUSY; + END IF; + END IF; +-- if (timeout_counter = 0) then +-- output_fifo_in <= (NOT timedout) & sd_error; +-- output_fifo_wr_en <= '1'; +-- timedout := conv_std_logic_vector(conv_integer(timedout)+1,16); +-- timeout_counter := TIMEOUT_MAX; +-- else +-- timeout_counter := timeout_counter - 1; +-- end if; + + when SIMPLESDHC_INIT => + sd_rd <= '0'; + sd_wr <= '0'; + sd_continue <= '0'; + sd_addr <= (others => '0'); + sd_data_i <= (others => '0'); + sd_din_valid <= '0'; + sd_dout_taken <= '0'; + out_sd_rd_addr_ack <= '0'; + IF (sd_busy = '0') THEN + SIMPLESDHC_State <= SIMPLESDHC_IDLE; +output_fifo_in <= '1' & x"8000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + elsif (init_done = false) THEN +output_fifo_in <= '1' & x"0F0F0F0F" & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + init_done := true; + elsif (timeout_counter = 0) then +output_fifo_in <= '1' & x"F" & timedout(11 downto 0) & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + timedout := conv_std_logic_vector(conv_integer(timedout)+1,16); + timeout_counter := TIMEOUT_MAX; + else + timeout_counter := timeout_counter - 1; + end IF; + + when SIMPLESDHC_READ_WAIT_BUSY => + IF (sd_busy = '1') THEN +output_fifo_in <= '1' & x"5000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + --sd_addr <= (others => '0'); + SIMPLESDHC_State <= SIMPLESDHC_READ_WAIT_READ; + timeout_counter := TIMEOUT_MAX; + elsif (timeout_counter = 0) then +output_fifo_in <= '1' & x"E" & timedout(11 downto 0) & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + timedout := conv_std_logic_vector(conv_integer(timedout)+1,16); + timeout_counter := TIMEOUT_MAX; + else + timeout_counter := timeout_counter - 1; + END IF; + + when SIMPLESDHC_READ_WAIT_READ => + --only read byte if we'll have some space to output the buffer + IF ((output_fifo_full = '0') AND (sd_dout_avail = '1')) THEN +output_fifo_in <= '1' & x"40" & sd_data_o & conv_std_logic_vector(byte_counter,16) & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + databuf(((15 - (byte_counter mod 16))*8 + 7) downto ((15 - (byte_counter mod 16))*8)) := sd_data_o; + sd_dout_taken <= '1'; + byte_counter := byte_counter + 1; + SIMPLESDHC_State <= SIMPLESDHC_READ_WAIT_READ2; + ELSIF ((output_fifo_full = '0') AND (timeout_counter = 0)) THEN +output_fifo_in <= '1' & x"1100" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_IDLE; + ELSIF (output_fifo_full = '0') THEN + timeout_counter := timeout_counter - 1; + ELSIF (sd_busy = '0') THEN +output_fifo_in <= '1' & x"1000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_IDLE; + END IF; + + when SIMPLESDHC_READ_WAIT_READ2 => + IF (sd_dout_avail = '0') THEN +output_fifo_in <= '1' & x"3000" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + sd_dout_taken <= '0'; + timeout_counter := TIMEOUT_MAX; + IF ((byte_counter mod 16) = 0) THEN + output_fifo_in <= '0' & last_addr(15 downto 0) & conv_std_logic_vector(buf_counter,16) & databuf; + output_fifo_wr_en <= '1'; + buf_counter := buf_counter + 1; + END IF; + IF (byte_counter = BLOCK_SIZE_G) THEN + sd_rd <= '0'; + SIMPLESDHC_State <= SIMPLESDHC_WAIT_NOTBUSY; + ELSE + SIMPLESDHC_State <= SIMPLESDHC_READ_WAIT_READ; + END IF; + END IF; + + when SIMPLESDHC_WAIT_NOTBUSY => + IF (sd_busy = '0') THEN + SIMPLESDHC_State <= SIMPLESDHC_IDLE; + elsif (timeout_counter = 0) then +output_fifo_in <= '1' & x"D" & timedout(11 downto 0) & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + timedout := conv_std_logic_vector(conv_integer(timedout)+1,16); + timeout_counter := TIMEOUT_MAX; + else + timeout_counter := timeout_counter - 1; + END IF; + + + when SIMPLESDHC_WRITE_WAIT_BUSY => + IF (sd_busy = '1') THEN +--output_fifo_in <= '1' & x"5001" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +--output_fifo_wr_en <= '1'; + --sd_addr <= (others => '0'); + SIMPLESDHC_State <= SIMPLESDHC_WRITE_WAIT_WRITE; + timeout_counter := TIMEOUT_MAX; + elsif (timeout_counter = 0) then +output_fifo_in <= '1' & x"C" & timedout(11 downto 0) & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + timedout := conv_std_logic_vector(conv_integer(timedout)+1,16); + timeout_counter := TIMEOUT_MAX; + else + timeout_counter := timeout_counter - 1; + END IF; + + when SIMPLESDHC_WRITE_WAIT_WRITE => + --only write byte if we have some space to output the buffer + IF ((input_fifo_empty = '0') OR ((byte_counter mod 16) /= 0)) THEN +--output_fifo_in <= '1' & x"40" & sd_data_o & conv_std_logic_vector(byte_counter,16) & x"00000000000000000000000000000000"; +--output_fifo_wr_en <= '1'; + IF ((byte_counter mod 16) = 0) THEN + databuf := input_fifo_out; + input_fifo_rd_en <= '1'; + END IF; + sd_data_i <= databuf(((15 - (byte_counter mod 16))*8 + 7) downto ((15 - (byte_counter mod 16))*8)); + sd_din_valid <= '1'; + byte_counter := byte_counter + 1; + SIMPLESDHC_State <= SIMPLESDHC_WRITE_WAIT_WRITE2; + ELSIF ((input_fifo_empty = '0') AND (timeout_counter = 0)) THEN +output_fifo_in <= '1' & x"1101" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_IDLE; + ELSIF (input_fifo_empty = '0') THEN + timeout_counter := timeout_counter - 1; + ELSIF (sd_busy = '0') THEN +output_fifo_in <= '1' & x"1001" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +output_fifo_wr_en <= '1'; + SIMPLESDHC_State <= SIMPLESDHC_IDLE; + END IF; + + when SIMPLESDHC_WRITE_WAIT_WRITE2 => + IF (sd_din_taken = '1') THEN +--output_fifo_in <= '1' & x"3001" & x"0" & sd_type & '0' & sd_error & sd_error_code & x"00000000000000000000000000000000"; +--output_fifo_wr_en <= '1'; + sd_din_valid <= '0'; + timeout_counter := TIMEOUT_MAX; + IF (byte_counter = BLOCK_SIZE_G) THEN + sd_wr <= '0'; + SIMPLESDHC_State <= SIMPLESDHC_WAIT_NOTBUSY; + ELSE + SIMPLESDHC_State <= SIMPLESDHC_WRITE_WAIT_WRITE; + END IF; + END IF; + + end case; + end IF; + + end process SimpleSDHC_wrapper; + +end RTL; diff --git a/sbus-to-ztex-gateware/sbus_fsm.vhd b/sbus-to-ztex-gateware/sbus_fsm.vhd index 37d2e0f..994c5ca 100644 --- a/sbus-to-ztex-gateware/sbus_fsm.vhd +++ b/sbus-to-ztex-gateware/sbus_fsm.vhd @@ -16,8 +16,6 @@ USE work.LedHandlerPkg.all; USE work.PromPkg.all; use work.mastrovito_V2_multiplier_parameters.all; -library XESS; - ENTITY SBusFSM is PORT ( fxclk_in: IN std_logic; -- 48 MHz FX2 clock @@ -353,6 +351,9 @@ ARCHITECTURE RTL OF SBusFSM IS signal fifo_fromsdcard_full : STD_LOGIC; signal fifo_fromsdcard_empty : STD_LOGIC; + signal mid_clk_rst_n : std_logic := '0'; + signal mid_50m_clk_out : std_logic; + signal mid_50m_rst_fromsbus_n : std_logic; signal fifo_tosdcard_din : STD_LOGIC_VECTOR ( 127 downto 0 ); signal fifo_tosdcard_wr_en : STD_LOGIC; signal fifo_tosdcard_rd_en : STD_LOGIC; @@ -376,6 +377,7 @@ ARCHITECTURE RTL OF SBusFSM IS SIGNAL AES_RST_COUNTER : natural range 0 to 31 := 5; SIGNAL AES_TIMEOUT_COUNTER : natural range 0 to 63 := 63; + SIGNAL SD_RST_COUNTER : natural range 0 to 31 := 5; -- bank of registers (256 bytes) for cryptoengine (and led) -- 0-64: 16 for controls (8 used) 16 registers for GCM (12 used), 16 unused, 16 for AES @@ -692,6 +694,7 @@ ARCHITECTURE RTL OF SBusFSM IS component clk_wiz_aes is port(clk_out1 : out std_logic; -- 100 MHz 'fast' clock clk_out2 : out std_logic; -- 5 MHz timer clock + clk_out3 : out std_logic; -- 50 MHz sd clock clk_in1 : in std_logic); end component clk_wiz_aes; @@ -730,10 +733,10 @@ ARCHITECTURE RTL OF SBusFSM IS ); end component trivium_wrapper; - component xess_sdcard_wrapper is + component SimpleSDHC_wrapper is port ( - xess_sdcard_wrapper_rst : in std_logic; - xess_sdcard_wrapper_clk : in std_logic; + SimpleSDHC_wrapper_rst : in std_logic; + SimpleSDHC_wrapper_clk : in std_logic; output_fifo_in : out std_logic_vector(160 downto 0); output_fifo_full : in std_logic; output_fifo_wr_en : out std_logic; @@ -752,7 +755,7 @@ ARCHITECTURE RTL OF SBusFSM IS -- leds leds : out std_logic_vector(7 downto 0) ); - end component xess_sdcard_wrapper; + end component SimpleSDHC_wrapper; PROCEDURE SBus_Set_Default( -- signal SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0); @@ -835,14 +838,14 @@ BEGIN din => fifo_fromstrng_din, wr_en => fifo_fromstrng_wr_en, rd_en => fifo_fromstrng_rd_en, dout => fifo_fromstrng_dout, full => fifo_fromstrng_full, empty => fifo_fromstrng_empty); label_fifo_fromsdcard: fifo_generator_from_sdcard port map(rst => fifo_rst, - wr_clk => fast_100m_clk_out, + wr_clk => mid_50m_clk_out, rd_clk => SBUS_3V3_CLK, din => fifo_fromsdcard_din, wr_en => fifo_fromsdcard_wr_en, rd_en => fifo_fromsdcard_rd_en, dout => fifo_fromsdcard_dout, full => fifo_fromsdcard_full, empty => fifo_fromsdcard_empty, wr_rst_busy => open, rd_rst_busy => open); label_fifo_tosdcard: fifo_generator_to_sdcard port map(rst => fifo_rst, wr_clk => SBUS_3V3_CLK, - rd_clk => fast_100m_clk_out, + rd_clk => mid_50m_clk_out, din => fifo_tosdcard_din, wr_en => fifo_tosdcard_wr_en, rd_en => fifo_tosdcard_rd_en, dout => fifo_tosdcard_dout, full => fifo_tosdcard_full, empty => fifo_tosdcard_empty, wr_rst_busy => open, rd_rst_busy => open); @@ -872,9 +875,9 @@ BEGIN output_fifo_wr_en => fifo_fromstrng_wr_en ); - label_xess_sdcard_wrapper: xess_sdcard_wrapper port map ( - xess_sdcard_wrapper_rst => fast_clk_rst_n, - xess_sdcard_wrapper_clk => fast_100m_clk_out, + label_SimpleSDHC_wrapper: SimpleSDHC_wrapper port map ( + SimpleSDHC_wrapper_rst => mid_clk_rst_n, + SimpleSDHC_wrapper_clk => mid_50m_clk_out, output_fifo_in => fifo_fromsdcard_din, output_fifo_full => fifo_fromsdcard_full, output_fifo_wr_en => fifo_fromsdcard_wr_en, @@ -895,7 +898,10 @@ BEGIN ); -- label_clk_wiz: clk_wiz_0 port map(clk_out1 => uart_clk, clk_in1 => fxclk_in); - label_aes_clk_wiz: clk_wiz_aes port map(clk_out1 => fast_100m_clk_out, clk_out2 => timer_5m_clk_out, clk_in1 => fxclk_in); + label_aes_clk_wiz: clk_wiz_aes port map(clk_out1 => fast_100m_clk_out, + clk_out2 => timer_5m_clk_out, + clk_out3 => mid_50m_clk_out, + clk_in1 => fxclk_in); label_uart : uart_tx generic map ( @@ -918,6 +924,14 @@ BEGIN dest_clk => fast_100m_clk_out, dest_out => fast_100m_rst_fromsbus_n); + xpm_cdc_single_reset2_n :xpm_cdc_single generic map( + DEST_SYNC_FF=>2) + port map ( + src_clk => SBUS_3V3_CLK, + src_in => SBUS_3V3_RSTs, + dest_clk => mid_50m_clk_out, + dest_out => mid_50m_rst_fromsbus_n); + xpm_cdc_gray_timer : xpm_cdc_gray generic map( DEST_SYNC_FF => 2, INIT_SYNC_FF => 0, @@ -940,7 +954,7 @@ BEGIN src_in => out_sd_rd_addr, src_send => out_sd_rd_addr_send, src_rcv => out_sd_rd_addr_rcv, - dest_clk => fast_100m_clk_out, + dest_clk => mid_50m_clk_out, dest_req => out_sd_rd_addr_req, dest_ack => out_sd_rd_addr_ack, dest_out => out_sd_rd_addr_fast @@ -1871,6 +1885,22 @@ BEGIN fast_clk_rst_n <= '0'; AES_RST_COUNTER <= 1; ELSIF RISING_EDGE(fast_100m_clk_out) THEN + if (AES_RST_COUNTER = 0) THEN + fast_clk_rst_n <= '1'; + else + AES_RST_COUNTER <= (AES_RST_COUNTER - 1); + fast_clk_rst_n <= '0'; + end if; + END IF; + END PROCESS; + + -- process to enable SDcard block + process (mid_50m_clk_out, mid_50m_rst_fromsbus_n) + BEGIN + if (mid_50m_rst_fromsbus_n = '0') THEN + mid_clk_rst_n <= '0'; + SD_RST_COUNTER <= 1; + ELSIF RISING_EDGE(mid_50m_clk_out) THEN LED0 <= sd_LEDs(0); LED1 <= sd_LEDs(1); LED2 <= sd_LEDs(2); @@ -1880,11 +1910,11 @@ BEGIN LED6 <= sd_LEDs(6); LED7 <= sd_LEDs(7); - if (AES_RST_COUNTER = 0) THEN - fast_clk_rst_n <= '1'; + if (SD_RST_COUNTER = 0) THEN + mid_clk_rst_n <= '1'; else - AES_RST_COUNTER <= (AES_RST_COUNTER - 1); - fast_clk_rst_n <= '0'; + SD_RST_COUNTER <= (SD_RST_COUNTER - 1); + mid_clk_rst_n <= '0'; end if; END IF; END PROCESS;