github.com/rdolbeau.SBusFPGA
1
0
Fork 0
mirror of synced 2026-04-25 12:01:26 +00:00
Code Issues Projects Releases Wiki Activity

split AES DMA in two control registers (for future pipelining?)

Browse Source
This commit is contained in:
Romain Dolbeau
2021-01-09 07:22:13 -05:00
parent 58bcaeec5a
commit 140fb92032
3 changed files with 88 additions and 43 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.c
View File

@@ -104,6 +104,16 @@ static int rdfpga_wait_dma_ready(struct rdfpga_softc *sc, const int count) {
ctr ++;
}
if (ctrl)
return EBUSY;
ctr = 0;
while (((ctrl = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_DMAW_CTRL)) != 0) &&
(ctr < count)) {
delay(1);
ctr ++;
}
if (ctrl)
return EBUSY;
@@ -1074,6 +1084,10 @@ rdfpga_encdec_aes128cbc(struct rdfpga_softc *sw, const u_int8_t thesid, struct c
memcpy(kvap, idat, tocopy);
bus_dmamap_sync(sw->sc_dmatag, sw->sc_dmamap, 0, tocopy, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
/* prepare write w/o start */
ctrl = ((uint64_t)(RDFPGA_MASK_DMA_CTRL_AES | ((tocopy/16)-1))) | ((uint64_t)(uint32_t)(sw->sc_dmamap->dm_segs[0].ds_addr)) << 32;
bus_space_write_8(sw->sc_bustag, sw->sc_bhregs, (RDFPGA_REG_DMAW_ADDR), ctrl);
/* start read */
ctrl = ((uint64_t)(RDFPGA_MASK_DMA_CTRL_START | RDFPGA_MASK_DMA_CTRL_AES | ((tocopy/16)-1))) | ((uint64_t)(uint32_t)(sw->sc_dmamap->dm_segs[0].ds_addr)) << 32;
bus_space_write_8(sw->sc_bustag, sw->sc_bhregs, (RDFPGA_REG_DMA_ADDR), ctrl);
rdfpga_wait_dma_ready(sw, 50000);

2
NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h
View File

@@ -63,6 +63,8 @@ struct rdfpga_softc {
#define RDFPGA_REG_AES128_CTRL (RDFPGA_REG_CTRL_BASE + 0x04)
#define RDFPGA_REG_DMA_ADDR (RDFPGA_REG_CTRL_BASE + 0x08)
#define RDFPGA_REG_DMA_CTRL (RDFPGA_REG_CTRL_BASE + 0x0C)
#define RDFPGA_REG_DMAW_ADDR (RDFPGA_REG_CTRL_BASE + 0x10)
#define RDFPGA_REG_DMAW_CTRL (RDFPGA_REG_CTRL_BASE + 0x14)
/* gcm stuff */
#define RDFPGA_REG_GCM_BASE 0x40