diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_curve25519engine.c b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_curve25519engine.c index 5875bae..bfbcc19 100644 --- a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_curve25519engine.c +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_curve25519engine.c @@ -596,6 +596,7 @@ sbusfpga_curve25519engine_attach(device_t parent, device_t self, void *aux) //#define CSR_CURVE25519ENGINE_BASE #define CSR_DDRPHY_BASE #define CSR_EXCHANGE_WITH_MEM_BASE +#define CSR_SBUS_BUS_STAT_BASE #define CSR_SDRAM_BASE #define CSR_SDBLOCK2MEM_BASE #define CSR_SDCORE_BASE @@ -608,6 +609,7 @@ sbusfpga_curve25519engine_attach(device_t parent, device_t self, void *aux) //#undef CSR_CURVE25519ENGINE_BASE #undef CSR_DDRPHY_BASE #undef CSR_EXCHANGE_WITH_MEM_BASE +#undef CSR_SBUS_BUS_STAT_BASE #undef CSR_SDRAM_BASE #undef CSR_SDBLOCK2MEM_BASE #undef CSR_SDCORE_BASE diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c index a44c77d..3aa313c 100644 --- a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c @@ -547,6 +547,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp) //#define CSR_DDRPHY_BASE //#define CSR_SDRAM_BASE //#define CSR_EXCHANGE_WITH_MEM_BASE +#define CSR_SBUS_BUS_STAT_BASE #define CSR_SDBLOCK2MEM_BASE #define CSR_SDCORE_BASE #define CSR_SDIRQ_BASE @@ -564,6 +565,7 @@ sbusfpga_sdram_diskstart(device_t self, struct buf *bp) //#undef CSR_DDRPHY_BASE //#undef CSR_SDRAM_BASE //#undef CSR_EXCHANGE_WITH_MEM_BASE +#undef CSR_SBUS_BUS_STAT_BASE #undef CSR_SDBLOCK2MEM_BASE #undef CSR_SDCORE_BASE #undef CSR_SDIRQ_BASE diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_trng.c b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_trng.c index 6218781..96b7c85 100644 --- a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_trng.c +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_trng.c @@ -112,6 +112,7 @@ sbusfpga_trng_match(device_t parent, cfdata_t cf, void *aux) #define CSR_CURVE25519ENGINE_BASE #define CSR_DDRPHY_BASE #define CSR_EXCHANGE_WITH_MEM_BASE +#define CSR_SBUS_BUS_STAT_BASE #define CSR_SDRAM_BASE #define CSR_SDBLOCK2MEM_BASE #define CSR_SDCORE_BASE @@ -124,6 +125,7 @@ sbusfpga_trng_match(device_t parent, cfdata_t cf, void *aux) #undef CSR_CURVE25519ENGINE_BASE #undef CSR_DDRPHY_BASE #undef CSR_EXCHANGE_WITH_MEM_BASE +#undef CSR_SBUS_BUS_STAT_BASE #undef CSR_SDRAM_BASE #undef CSR_SDBLOCK2MEM_BASE #undef CSR_SDCORE_BASE @@ -145,7 +147,7 @@ sbusfpga_trng_getentropy(size_t nbytes, void *cookie) { } else { failure ++; if (failure > (1+(dbytes/4))) { // something going on - aprint_normal_dev(sc->sc_dev, "out of entropy after %zd / %zd bytes\n", dbytes, nbytes); + device_printf(sc->sc_dev, "out of entropy after %zd / %zd bytes\n", dbytes, nbytes); return; } delay(1); @@ -153,7 +155,7 @@ sbusfpga_trng_getentropy(size_t nbytes, void *cookie) { if (((dbytes%32)==0) && (nbytes > dbytes)) delay(1); // let the hardware breathes if the OS needs a lof of bytes } - aprint_normal_dev(sc->sc_dev, "gathered %zd bytes [%d]\n", dbytes, failure); + device_printf(sc->sc_dev, "gathered %zd bytes [%d]\n", dbytes, failure); } /* diff --git a/sbus-to-ztex-gateware-migen/netbsd_csr.h b/sbus-to-ztex-gateware-migen/netbsd_csr.h index 06a181f..f6fd470 100644 --- a/sbus-to-ztex-gateware-migen/netbsd_csr.h +++ b/sbus-to-ztex-gateware-migen/netbsd_csr.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-08-20 12:28:27 +// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-08-21 07:21:33 //-------------------------------------------------------------------------------- #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H @@ -738,9 +738,91 @@ static inline uint32_t exchange_with_mem_sbus_master_error_virtual_read(struct s #define CSR_EXCHANGE_WITH_MEM_CHECKSUM_SIZE 8 #endif // CSR_EXCHANGE_WITH_MEM_BASE +/* sbus_bus_stat */ +#ifndef CSR_SBUS_BUS_STAT_BASE +#define CSR_SBUS_BUS_STAT_BASE (CSR_BASE + 0x4000L) +#define CSR_SBUS_BUS_STAT_STAT_CTRL_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x0L) +#define CSR_SBUS_BUS_STAT_STAT_CTRL_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_ctrl_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x0L); +} +static inline void sbus_bus_stat_stat_ctrl_write(struct sbusfpga_sbus_bus_stat_softc *sc, uint32_t v) { + bus_space_write_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x0L, v); +} +#define CSR_SBUS_BUS_STAT_STAT_CTRL_UPDATE_OFFSET 0 +#define CSR_SBUS_BUS_STAT_STAT_CTRL_UPDATE_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_ctrl_update_extract(struct sbusfpga_sbus_bus_stat_softc *sc, uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t sbus_bus_stat_stat_ctrl_update_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + uint32_t word = sbus_bus_stat_stat_ctrl_read(sc); + return sbus_bus_stat_stat_ctrl_update_extract(sc, word); +} +static inline uint32_t sbus_bus_stat_stat_ctrl_update_replace(struct sbusfpga_sbus_bus_stat_softc *sc, uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void sbus_bus_stat_stat_ctrl_update_write(struct sbusfpga_sbus_bus_stat_softc *sc, uint32_t plain_value) { + uint32_t oldword = sbus_bus_stat_stat_ctrl_read(sc); + uint32_t newword = sbus_bus_stat_stat_ctrl_update_replace(sc, oldword, plain_value); + sbus_bus_stat_stat_ctrl_write(sc, newword); +} +#define CSR_SBUS_BUS_STAT_LIVE_STAT_CYCLE_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x4L) +#define CSR_SBUS_BUS_STAT_LIVE_STAT_CYCLE_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_live_stat_cycle_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x4L); +} +#define CSR_SBUS_BUS_STAT_STAT_CYCLE_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x8L) +#define CSR_SBUS_BUS_STAT_STAT_CYCLE_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_cycle_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x8L); +} +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_START_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0xcL) +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_START_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_slave_start_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0xcL); +} +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_DONE_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x10L) +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_DONE_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_slave_done_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x10L); +} +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_ERROR_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x14L) +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_ERROR_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_slave_error_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x14L); +} +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_EARLY_ERROR_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x18L) +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_EARLY_ERROR_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_slave_early_error_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x18L); +} +#define CSR_SBUS_BUS_STAT_STAT_MASTER_START_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x1cL) +#define CSR_SBUS_BUS_STAT_STAT_MASTER_START_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_master_start_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x1cL); +} +#define CSR_SBUS_BUS_STAT_STAT_MASTER_DONE_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x20L) +#define CSR_SBUS_BUS_STAT_STAT_MASTER_DONE_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_master_done_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x20L); +} +#define CSR_SBUS_BUS_STAT_STAT_MASTER_ERROR_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x24L) +#define CSR_SBUS_BUS_STAT_STAT_MASTER_ERROR_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_master_error_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x24L); +} +#define CSR_SBUS_BUS_STAT_STAT_MASTER_RERUN_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x28L) +#define CSR_SBUS_BUS_STAT_STAT_MASTER_RERUN_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_master_rerun_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x28L); +} +#endif // CSR_SBUS_BUS_STAT_BASE + /* sdram */ #ifndef CSR_SDRAM_BASE -#define CSR_SDRAM_BASE (CSR_BASE + 0x4000L) +#define CSR_SDRAM_BASE (CSR_BASE + 0x5000L) #define CSR_SDRAM_DFII_CONTROL_ADDR (CSR_SDRAM_BASE + 0x0L) #define CSR_SDRAM_DFII_CONTROL_SIZE 1 static inline uint32_t sdram_dfii_control_read(struct sbusfpga_sdram_softc *sc) { @@ -1009,7 +1091,7 @@ static inline uint32_t sdram_dfii_pi3_rddata_read(struct sbusfpga_sdram_softc *s /* trng */ #ifndef CSR_TRNG_BASE -#define CSR_TRNG_BASE (CSR_BASE + 0x5000L) +#define CSR_TRNG_BASE (CSR_BASE + 0x6000L) #define CSR_TRNG_CTRL_ADDR (CSR_TRNG_BASE + 0x0L) #define CSR_TRNG_CTRL_SIZE 1 static inline uint32_t trng_ctrl_read(struct sbusfpga_trng_softc *sc) { diff --git a/sbus-to-ztex-gateware-migen/prom_csr.fth b/sbus-to-ztex-gateware-migen/prom_csr.fth index 56f4196..39cc271 100644 --- a/sbus-to-ztex-gateware-migen/prom_csr.fth +++ b/sbus-to-ztex-gateware-migen/prom_csr.fth @@ -3,8 +3,9 @@ h# 40000 constant sbusfpga_csraddr_leds h# 41000 constant sbusfpga_csraddr_curve25519engine h# 42000 constant sbusfpga_csraddr_ddrphy h# 43000 constant sbusfpga_csraddr_exchange_with_mem -h# 44000 constant sbusfpga_csraddr_sdram -h# 45000 constant sbusfpga_csraddr_trng +h# 44000 constant sbusfpga_csraddr_sbus_bus_stat +h# 45000 constant sbusfpga_csraddr_sdram +h# 46000 constant sbusfpga_csraddr_trng h# 80000 constant sbusfpga_regionaddr_usb_host_ctrl h# 0 constant sbusfpga_regionaddr_prom h# 80000000 constant sbusfpga_regionaddr_main_ram diff --git a/sbus-to-ztex-gateware-migen/prom_migen.fth b/sbus-to-ztex-gateware-migen/prom_migen.fth index e76ac67..a85283b 100644 --- a/sbus-to-ztex-gateware-migen/prom_migen.fth +++ b/sbus-to-ztex-gateware-migen/prom_migen.fth @@ -217,4 +217,31 @@ my-space constant my-sbus-space curve25519engine-regfile-virt h# 10000 map-out ; +\ OpenBIOS tokenizer won't accept finish-device without new-device +\ Cheat by using the tokenizer so we can do OpenBoot 2.x siblings +\ tokenizer[ 01 emit-byte h# 27 emit-byte h# 01 emit-byte h# 1f emit-byte ]tokenizer +\ The OpenFirmware tokenizer does accept the 'clean' syntax +finish-device +\ \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ STAT +new-device + +\ Absolute minimal stuff; name & registers def. +" RDOL,sbusstat" device-name + +my-address sbusfpga_csraddr_sbus_bus_stat + my-space h# 100 reg +\ we don't support ET or HWORD +h# 7d xdrint " slave-burst-sizes" attribute +h# 7d xdrint " burst-sizes" attribute + +headers +-1 instance value sbus_bus_stat-virt +my-address constant my-sbus-address +my-space constant my-sbus-space + +: map-in ( adr space size -- virt ) " map-in" $call-parent ; +: map-out ( virt size -- ) " map-out" $call-parent ; + +: map-in-sbus_bus_stat ( -- ) my-sbus-address sbusfpga_csraddr_sbus_bus_stat + my-sbus-space h# 100 map-in is sbus_bus_stat-virt ; +: map-out-sbus_bus_stat ( -- ) sbus_bus_stat-virt h# 100 map-out ; + end0 diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py index df1d9ff..e2b29c7 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py @@ -1,6 +1,6 @@ from migen import * from migen.genlib.fifo import * -from migen.genlib.cdc import PulseSynchronizer +from migen.genlib.cdc import BusSynchronizer from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone @@ -91,13 +91,14 @@ class ExchangeWithMem(Module, AutoCSR): self.comb += self.dma_status.fields.has_wr_data.eq(self.fromsbus_fifo.readable) # Some data available to write to memory # The next two status bits reflect stats in the SBus clock domain - self.submodules.fromsbus_req_fifo_readable_sync = PulseSynchronizer("sbus", "sys") + self.submodules.fromsbus_req_fifo_readable_sync = BusSynchronizer(width = 1, idomain = "sbus", odomain = "sys") fromsbus_req_fifo_readable_in_sys = Signal() self.comb += self.fromsbus_req_fifo_readable_sync.i.eq(self.fromsbus_req_fifo.readable) self.comb += fromsbus_req_fifo_readable_in_sys.eq(self.fromsbus_req_fifo_readable_sync.o) # w/o this extra delay, the driver sees an outdated checksum for some reason... # there's probably a more fundamental issue :-( + # note: replaced PulseSynchronizer with BusSynchronizer, should I retry w/o this ? fromsbus_req_fifo_readable_in_sys_cnt = Signal(5) self.sync += If(fromsbus_req_fifo_readable_in_sys, fromsbus_req_fifo_readable_in_sys_cnt.eq(0x1F) @@ -109,7 +110,7 @@ class ExchangeWithMem(Module, AutoCSR): #self.comb += self.dma_status.fields.has_requests.eq(fromsbus_req_fifo_readable_in_sys) # we still have outstanding requests self.comb += self.dma_status.fields.has_requests.eq(fromsbus_req_fifo_readable_in_sys | (fromsbus_req_fifo_readable_in_sys_cnt != 0)) # we still have outstanding requests, or had recently - self.submodules.tosbus_fifo_readable_sync = PulseSynchronizer("sbus", "sys") + self.submodules.tosbus_fifo_readable_sync = BusSynchronizer(width = 1, idomain = "sbus", odomain = "sys") tosbus_fifo_readable_in_sys = Signal() self.comb += self.tosbus_fifo_readable_sync.i.eq(self.tosbus_fifo.readable) self.comb += tosbus_fifo_readable_in_sys.eq(self.tosbus_fifo_readable_sync.o) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index 8d5a274..793c452 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -291,9 +291,9 @@ class SBusFPGABus(Module): sbus_wishbone_le = Signal() - wishbone_master_timeout = Signal(6) - wishbone_slave_timeout = Signal(6) - sbus_slave_timeout = Signal(6) + wishbone_master_timeout = Signal(log2_int(wishbone_default_timeout, False)) + wishbone_slave_timeout = Signal(log2_int(wishbone_default_timeout, False)) + sbus_slave_timeout = Signal(log2_int(sbus_default_timeout, False)) sbus_master_throttle = Signal(2) @@ -400,6 +400,16 @@ class SBusFPGABus(Module): #self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle")) #self.sync += platform.request("user_led", 6).eq(master_data_src_tosbus_fifo) #self.sync += platform.request("user_led", 7).eq(master_data_src_fromsbus_fifo) + + stat_slave_start_counter = Signal(32) + stat_slave_done_counter = Signal(32) + stat_slave_rerun_counter = Signal(32) + stat_slave_early_error_counter = Signal(32) + + stat_master_start_counter = Signal(32) + stat_master_done_counter = Signal(32) + stat_master_error_counter = Signal(32) + stat_master_rerun_counter = Signal(32) slave_fsm.act("Reset", #NextValue(self.led_display.value, 0x0000000000), @@ -443,6 +453,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_PARITY), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) | (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) | @@ -453,6 +464,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet NextValue(SBUS_3V3_ERRs_o, 1), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(self.wishbone_master.cyc == 0, NextValue(self.wishbone_master.cyc, 1), NextValue(self.wishbone_master.stb, 1), @@ -472,6 +484,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(((SBUS_3V3_SELs_i == 0) & @@ -485,6 +498,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet NextValue(SBUS_3V3_ERRs_o, 1), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(self.wishbone_master.cyc == 0, NextValue(self.wishbone_master.cyc, 1), NextValue(self.wishbone_master.stb, 1), @@ -504,6 +518,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(((SBUS_3V3_SELs_i == 0) & @@ -516,12 +531,14 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_PARITY), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) | (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet NextValue(SBUS_3V3_ERRs_o, 1), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(self.wishbone_master.cyc == 0, NextValue(self.wishbone_master.cyc, 1), NextValue(self.wishbone_master.stb, 1), @@ -541,6 +558,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(((SBUS_3V3_SELs_i == 0) & @@ -561,6 +579,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_PARITY), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) | (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == USBOHCI_ADDR_PFX) | @@ -568,6 +587,7 @@ class SBusFPGABus(Module): (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXA) | (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXB)), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(~self.wishbone_master.cyc, NextValue(SBUS_3V3_ACKs_o, ACK_WORD), NextValue(SBUS_3V3_ERRs_o, 1), @@ -584,6 +604,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(((SBUS_3V3_SELs_i == 0) & @@ -594,6 +615,7 @@ class SBusFPGABus(Module): NextValue(sbus_last_pa, SBUS_3V3_PA_i), If(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(~self.wishbone_master.cyc, NextValue(SBUS_3V3_ACKs_o, ACK_BYTE), NextValue(SBUS_3V3_ERRs_o, 1), @@ -610,6 +632,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(((SBUS_3V3_SELs_i == 0) & @@ -622,9 +645,11 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_PARITY), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), NextValue(sbus_wishbone_le, (SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX)), + NextValue(stat_slave_start_counter, stat_slave_start_counter + 1), If(~self.wishbone_master.cyc, NextValue(SBUS_3V3_ACKs_o, ACK_HWORD), NextValue(SBUS_3V3_ERRs_o, 1), @@ -641,6 +666,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_ERR), NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(led0123, led0123 | LED_ADDRESS), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ) ).Elif(self.wishbone_slave.cyc & @@ -736,7 +762,8 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_PPRD_o, 0), NextValue(master_we, 1), #NextValue(self.led_display.value, 0x0000000010 | Cat(Signal(8, reset = 0x00), self.wishbone_slave.adr)), - #NextValue(self.led_display.value, Cat(Signal(8, reset = LED_M_WRITE), Signal(2, reset = 0), self.wishbone_slave.adr)), + #NextValue(self.led_display.value, Cat(Signal(8, reset = LED_M_WRITE), Signal(2, reset = 0), self.wishbone_slave.adr)), + NextValue(stat_master_start_counter, stat_master_start_counter + 1), NextState("Master_Translation") ).Elif(SBUS_3V3_BGs_i & self.master_read_buffer_start & @@ -759,6 +786,7 @@ class SBusFPGABus(Module): NextValue(master_we, 0), #NextValue(self.led_display.value, 0x0000000000 | Cat(Signal(8, reset = 0x00), self.wishbone_slave.adr)), #NextValue(self.led_display.value, Cat(Signal(8, reset = LED_M_READ), Signal(2, reset = 0), self.master_read_buffer_addr)), + NextValue(stat_master_start_counter, stat_master_start_counter + 1), NextState("Master_Translation") ).Elif(SBUS_3V3_BGs_i & self.tosbus_fifo.readable & @@ -792,6 +820,7 @@ class SBusFPGABus(Module): }), NextValue(SBUS_3V3_PPRD_o, 0), NextValue(master_we, 1), + NextValue(stat_master_start_counter, stat_master_start_counter + 1), NextState("Master_Translation") ).Elif(SBUS_3V3_BGs_i & self.fromsbus_req_fifo.readable & @@ -825,6 +854,7 @@ class SBusFPGABus(Module): }), NextValue(SBUS_3V3_PPRD_o, 1), NextValue(master_we, 0), + NextValue(stat_master_start_counter, stat_master_start_counter + 1), NextState("Master_Translation") ).Elif(((SBUS_3V3_SELs_i == 0) & (SBUS_3V3_ASs_i == 0)), @@ -833,6 +863,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ERRs_o, 1), #NextValue(self.led_display.value, 0x000000000F | Cat(Signal(8, reset = 0x00), SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, SBUS_3V3_PPRD_i)), #NextValue(led0123, led0123 | LED_UNKNOWNREQ), + NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1), NextState("Slave_Error") ).Elif(~SBUS_3V3_BGs_i, ### ouch we got the bus but nothing more to do ?!? @@ -849,6 +880,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), If(((SBUS_3V3_ASs_i == 1) | ((SBUS_3V3_ASs_i == 0) & (SBUS_3V3_SELs_i == 1))), + NextValue(stat_slave_done_counter, stat_slave_done_counter + 1), NextState("Idle") ) ) @@ -897,6 +929,7 @@ class SBusFPGABus(Module): NextValue(wishbone_master_timeout, 0), NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_WORD | LED_RERUN_LATE), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -915,6 +948,7 @@ class SBusFPGABus(Module): ).Elif(sbus_slave_timeout == 0, ### this is taking too long NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_WORD), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -957,6 +991,7 @@ class SBusFPGABus(Module): NextValue(wishbone_master_timeout, 0), NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_LATE), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -975,6 +1010,7 @@ class SBusFPGABus(Module): ).Elif(sbus_slave_timeout == 0, ### this is taking too long NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1015,6 +1051,7 @@ class SBusFPGABus(Module): NextValue(wishbone_master_timeout, 0), NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_LATE), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1033,6 +1070,7 @@ class SBusFPGABus(Module): ).Elif(sbus_slave_timeout == 0, ### this is taking too long NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1070,6 +1108,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), If(((SBUS_3V3_ASs_i == 1) | ((SBUS_3V3_ASs_i == 0) & (SBUS_3V3_SELs_i == 1))), + NextValue(stat_slave_done_counter, stat_slave_done_counter + 1), NextState("Idle") ) ) @@ -1083,6 +1122,7 @@ class SBusFPGABus(Module): NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(self.led_display.value, Cat(Signal(8, reset = LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD), sbus_last_pa, Signal(4, reset = 0))), #NextValue(led0123, LED_RERUN | LED_RERUN_WRITE | LED_RERUN_WORD), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1125,6 +1165,7 @@ class SBusFPGABus(Module): ).Elif(sbus_slave_timeout == 0, ### this is taking too long NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_WRITE), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1167,6 +1208,7 @@ class SBusFPGABus(Module): ).Elif(sbus_slave_timeout == 0, ### this is taking too long NextValue(SBUS_3V3_ACKs_o, ACK_RERUN), #NextValue(led0123, LED_RERUN | LED_RERUN_WRITE), + NextValue(stat_slave_rerun_counter, stat_slave_rerun_counter + 1), NextState("Slave_Error") ) ) @@ -1233,6 +1275,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), NextValue(master_error_seen, 1), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextState("Idle")], ACK_RERUN: ### dunno how to handle that yet, [If(~master_data_src_tosbus_fifo & ~master_data_src_fromsbus_fifo, @@ -1242,6 +1285,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle")], ACK_IDLE: [If(master_we, @@ -1278,6 +1322,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle") ], ACK_ERR: ## ### burst not handled @@ -1290,6 +1335,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_master_in, 0), NextValue(master_error_seen, 8), NextValue(master_error_details, burst_counter), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextValue(self.sbus_master_error_virtual, self.sbus_master_last_virtual), NextState("Idle") ], @@ -1302,6 +1348,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), NextValue(master_error_seen, 4), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextValue(master_error_details, Cat(SBUS_3V3_ACKs_i, Signal(1, reset = 0))), NextState("Idle") ], @@ -1346,6 +1393,7 @@ class SBusFPGABus(Module): [NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle") ], "default": @@ -1353,6 +1401,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), NextValue(master_error_seen, 1), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextState("Idle") ], }), @@ -1368,6 +1417,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_done_counter, stat_master_done_counter + 1), NextState("Idle") ) slave_fsm.act("Master_Write", @@ -1417,6 +1467,7 @@ class SBusFPGABus(Module): [NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle") ], "default": ## ACK_ERRS or other @@ -1424,6 +1475,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), NextValue(master_error_seen, 1), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextState("Idle"), ], }) @@ -1434,6 +1486,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), NextValue(sbus_master_throttle, 3), + NextValue(stat_master_done_counter, stat_master_done_counter + 1), NextState("Idle") ) # ##### FINISHED ##### @@ -1652,3 +1705,52 @@ class SBusFPGABus(Module): # NextState("Idle"), # ) #) + + + self.stat_cycle_counter = Signal(32) + self.buf_stat_cycle_counter = Signal(32) + self.buf_stat_slave_start_counter = Signal(32) + self.buf_stat_slave_done_counter = Signal(32) + self.buf_stat_slave_rerun_counter = Signal(32) + self.buf_stat_slave_early_error_counter = Signal(32) + self.buf_stat_master_start_counter = Signal(32) + self.buf_stat_master_done_counter = Signal(32) + self.buf_stat_master_error_counter = Signal(32) + self.buf_stat_master_rerun_counter = Signal(32) + self.stat_update = Signal() + stat_update_prev = Signal() + + self.sync += stat_update_prev.eq(self.stat_update) + + self.sync += self.stat_cycle_counter.eq(self.stat_cycle_counter + 1) + self.sync += If(~stat_update_prev & self.stat_update, ## raising edge: copy to buffer and reset active + self.buf_stat_cycle_counter.eq(self.stat_cycle_counter), + self.buf_stat_slave_start_counter.eq(stat_slave_start_counter), + self.buf_stat_slave_done_counter.eq(stat_slave_done_counter), + self.buf_stat_slave_rerun_counter.eq(stat_slave_rerun_counter), + self.buf_stat_slave_early_error_counter.eq(stat_slave_early_error_counter), + self.buf_stat_master_start_counter.eq(stat_master_start_counter), + self.buf_stat_master_done_counter.eq(stat_master_done_counter), + self.buf_stat_master_error_counter.eq(stat_master_error_counter), + self.buf_stat_master_rerun_counter.eq(stat_master_rerun_counter), + self.stat_cycle_counter.eq(0), + stat_slave_start_counter.eq(0), + stat_slave_done_counter.eq(0), + stat_slave_rerun_counter.eq(0), + stat_slave_early_error_counter.eq(0), + stat_master_start_counter.eq(0), + stat_master_done_counter.eq(0), + stat_master_error_counter.eq(0), + stat_master_rerun_counter.eq(0), + ) + self.sync += If(stat_update_prev & ~self.stat_update, ## falling edge: reset buffer + self.buf_stat_cycle_counter.eq(0), + self.buf_stat_slave_start_counter.eq(0), + self.buf_stat_slave_done_counter.eq(0), + self.buf_stat_slave_rerun_counter.eq(0), + self.buf_stat_slave_early_error_counter.eq(0), + self.buf_stat_master_start_counter.eq(0), + self.buf_stat_master_done_counter.eq(0), + self.buf_stat_master_error_counter.eq(0), + self.buf_stat_master_rerun_counter.eq(0), + ) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index afe5324..e3cb722 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -17,13 +17,14 @@ from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy from sbus_to_fpga_fsm import * +from sbus_to_fpga_fsmstat import * from sbus_to_fpga_blk_dma import * from sbus_to_fpga_trng import * from litedram.frontend.dma import * from engine import Engine; -from migen.genlib.cdc import PulseSynchronizer, BusSynchronizer +from migen.genlib.cdc import BusSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer; import sbus_to_fpga_export; @@ -268,6 +269,7 @@ class SBusFPGA(SoCCore): burst_size=burst_size) #self.submodules.sbus_bus = _sbus_bus self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus) + self.submodules.sbus_bus_stat = SBusFPGABusStat(sbus_bus = self.sbus_bus) self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys) self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False)) @@ -289,7 +291,7 @@ class SBusFPGA(SoCCore): self.submodules.curve25519engine_wishbone_cdc = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=self.curve25519engine.bus, cd_master="sys", cd_slave="clk100") self.bus.add_slave("curve25519engine", self.curve25519engine_wishbone_cdc, SoCRegion(origin=self.mem_map.get("curve25519engine", None), size=0x20000, cached=False)) #self.bus.add_slave("curve25519engine", self.curve25519engine.bus, SoCRegion(origin=self.mem_map.get("curve25519engine", None), size=0x20000, cached=False)) - self.submodules.curve25519_on_sync = PulseSynchronizer("clk100", "sys") + self.submodules.curve25519_on_sync = BusSynchronizer(width = 1, idomain = "clk100", odomain = "sys") self.comb += self.curve25519_on_sync.i.eq(self.curve25519engine.power.fields.on) self.comb += self.crg.curve25519_on.eq(self.curve25519_on_sync.o)