diff --git a/sbus-to-ztex-gateware-migen/blit.sh b/sbus-to-ztex-gateware-migen/blit.sh index d351da7..65b8245 100755 --- a/sbus-to-ztex-gateware-migen/blit.sh +++ b/sbus-to-ztex-gateware-migen/blit.sh @@ -2,7 +2,7 @@ HRES=${1:-1280} VRES=${2:-1024} -BASE_FB=0x8FE00000 +BASE_FB=${3:-0x8FE00000} GCCDIR=~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14 GCCPFX=riscv64-unknown-elf- diff --git a/sbus-to-ztex-gateware-migen/cg6_accel.py b/sbus-to-ztex-gateware-migen/cg6_accel.py index b7cc0b0..f066f5b 100644 --- a/sbus-to-ztex-gateware-migen/cg6_accel.py +++ b/sbus-to-ztex-gateware-migen/cg6_accel.py @@ -5,20 +5,24 @@ from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone -class CG6Accel(Module): # AutoCSR ? - def __init__(self, platform): +#from cg6_blit import CG6Blit +class CG6Accel(Module): # AutoCSR ? + def __init__(self, soc, base_fb, hres, vres): + platform = soc.platform + # for FBC and TEC - where we just ignore TEC self.bus = bus = wishbone.Interface() - COORD_BITS=12 + self.COORD_BITS = COORD_BITS = 12 + fbc_config = Signal(32, reset = (0x60000000)) # bit 11-12 are for resolution, see the GX manual fbc_mode = Signal(32) fbc_clip = Signal(32) fbc_s = Signal(32) #fbc_font = Signal(32) - fbc_x = Array(Signal(COORD_BITS) for a in range(0, 4)) - fbc_y = Array(Signal(COORD_BITS) for a in range(0, 4)) + self.fbc_x = fbc_x = Array(Signal(COORD_BITS) for a in range(0, 4)) + self.fbc_y = fbc_y = Array(Signal(COORD_BITS) for a in range(0, 4)) fbc_offx = Signal(COORD_BITS) fbc_offy = Signal(COORD_BITS) fbc_incx = Signal(COORD_BITS) @@ -29,21 +33,23 @@ class CG6Accel(Module): # AutoCSR ? fbc_clipmaxy = Signal(COORD_BITS+1) # need the 13th bit as X11 uses 4096 for clipmaxx (console uses 4095) fbc_fg = Signal(8) fbc_bg = Signal(8) - fbc_alu = Signal(32) - fbc_pm = Signal(8) + self.fbc_alu = fbc_alu = Signal(32) + self.fbc_pm = fbc_pm = Signal(8) fbc_arectx = Signal(COORD_BITS) fbc_arecty = Signal(COORD_BITS) # extra stuff for the Vex core fbc_arectx_prev = Signal(COORD_BITS) # after fbc_arecty (600) - R/O fbc_arecty_prev = Signal(COORD_BITS) # after fbc_arectx_prev (601) - R/O - fbc_r5_cmd = Signal(32) # to communicate with Vex (602) + self.fbc_r5_cmd = fbc_r5_cmd = Signal(32) # to communicate with Vex (602) fbc_r5_status = Array(Signal(32) for a in range(0, 4)) fbc_next_font = Signal(32) fbc_next_x0 = Signal(COORD_BITS) fbc_next_x1 = Signal(COORD_BITS) fbc_next_y0 = Signal(COORD_BITS) + #self.submodules.cg6_blit = CG6Blit(accel = self, soc = soc, base_fb = base_fb, hres = hres, vres = vres) + # do-some-work flags fbc_do_draw = Signal() fbc_do_blit = Signal() @@ -256,8 +262,8 @@ class CG6Accel(Module): # AutoCSR ? #timeout_rst = 0xFFFFFFF #timeout = Signal(28, reset = timeout_rst) - #pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED") - #self.comb += pad_SBUS_DATA_OE_LED.eq(~local_reset) + pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED") + self.comb += pad_SBUS_DATA_OE_LED.eq(~local_reset) #self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_r5_cmd[1]) # blitting #self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_pm != 0) # planemasking #self.comb += pad_SBUS_DATA_OE_LED.eq(fifo_overflow) @@ -267,11 +273,11 @@ class CG6Accel(Module): # AutoCSR ? #self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_draw & fbc_s[GX_INPROGRESS_BIT]) #self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_blit & fbc_s[GX_INPROGRESS_BIT]) - self.sync += fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable) - self.sync += fbc_s[27].eq(fbc_do_draw) - self.sync += fbc_s[26].eq(fbc_do_blit) - self.sync += fbc_s[25].eq(self.fbc_fifo_font.readable) - self.sync += fbc_s[24].eq(~local_reset) + #self.sync += fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable) + #self.sync += fbc_s[27].eq(fbc_do_draw) + #self.sync += fbc_s[26].eq(fbc_do_blit) + #self.sync += fbc_s[25].eq(self.fbc_fifo_font.readable) + #self.sync += fbc_s[24].eq(~local_reset) #self.sync += fbc_s[0].eq(draw_blit_overflow) #fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable) @@ -324,6 +330,8 @@ class CG6Accel(Module): # AutoCSR ? #fbc_s[GX_FULL_BIT].eq(1), local_reset.eq(0), #timeout.eq(timeout_rst), + + ##self.cg6_blit.go.eq(1), ) #).Elif((timeout == 0) & fbc_s[GX_INPROGRESS_BIT], # OUPS # fbc_r5_cmd.eq(0), @@ -353,9 +361,9 @@ class CG6Accel(Module): # AutoCSR ? i_iBusWishbone_DAT_MISO = ibus.dat_r, o_iBusWishbone_DAT_MOSI = ibus.dat_w, o_iBusWishbone_SEL = ibus.sel, - #i_iBusWishbone_ERR = ibus.err, - #o_iBusWishbone_CTI = ibus.cti, - #o_iBusWishbone_BTE = ibus.bte, + i_iBusWishbone_ERR = ibus.err, + o_iBusWishbone_CTI = ibus.cti, + o_iBusWishbone_BTE = ibus.bte, o_dBusWishbone_CYC = dbus.cyc, o_dBusWishbone_STB = dbus.stb, i_dBusWishbone_ACK = dbus.ack, diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index f5d6aef..d99a755 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -219,7 +219,7 @@ class SBusFPGABus(Module): ADDR_BIGPFX_LOW = CG3_KEPT_UPPER_BIT ## x MiB per bigprefix ADDR_BIGPFX_LENGTH = (1 + ADDR_BIGPFX_HIGH - ADDR_BIGPFX_LOW) - CG3_REMAPPED_BASE=cg3_base >> CG3_KEPT_UPPER_BIT # we always remapped to the appropriate range (e.g. the 2 MiB is mapped four times consecutively) + CG3_REMAPPED_BASE=cg3_base >> CG3_KEPT_UPPER_BIT print(f"CG3 remapping: {cg3_fb_size//1048576} Mib starting at prefix {CG3_REMAPPED_BASE:x} ({(CG3_REMAPPED_BASE<= cg3_fb_size): avail_sdram = avail_sdram - cg3_fb_size + base_fb = self.wb_mem_map["main_ram"] + avail_sdram else: print("***** ERROR ***** Can't have a FrameBuffer without main ram\n") assert(False) @@ -411,7 +412,7 @@ class SBusFPGA(SoCCore): version=version, burst_size=burst_size, cg3_fb_size=cg3_fb_size, - cg3_base=(self.wb_mem_map["main_ram"] + avail_sdram)) + cg3_base=base_fb) #self.submodules.sbus_bus = _sbus_bus self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus) self.submodules.sbus_bus_stat = SBusFPGABusStat(soc = self, sbus_bus = self.sbus_bus) @@ -456,7 +457,7 @@ class SBusFPGA(SoCCore): if (cg6): - self.submodules.cg6_accel = cg6_accel.CG6Accel(self.platform) + self.submodules.cg6_accel = cg6_accel.CG6Accel(soc = self, base_fb = base_fb, hres = hres, vres = vres) self.bus.add_slave("cg6_fbc", self.cg6_accel.bus, SoCRegion(origin=self.mem_map.get("cg6_fbc", None), size=0x2000, cached=False)) self.bus.add_slave("cg6_fhc", self.cg6.bus2, SoCRegion(origin=self.mem_map.get("cg6_fhc", None), size=0x2000, cached=False)) self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus)