From 3c96a56dfb560116087db42326b723ca78c1fece Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Sat, 6 Nov 2021 10:18:23 +0100 Subject: [PATCH] fix checksum-less building --- sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py index 5cba651..072e976 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py @@ -79,8 +79,8 @@ class ExchangeWithMem(Module, AutoCSR): ]) self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM") - if (do_checksum): - self.checksum = CSRStorage(data_width_bits, write_from_dev=True, description = "checksum (XOR)"); + #if (do_checksum): + self.checksum = CSRStorage(data_width_bits, write_from_dev=True, description = "checksum (XOR)"); self.submodules.req_r_fsm = req_r_fsm = FSM(reset_state="Reset") self.submodules.req_w_fsm = req_w_fsm = FSM(reset_state="Reset")