From 45292aea6f9c0354edb6e61e3583bf4dae645576 Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Sat, 4 Dec 2021 15:56:59 +0100 Subject: [PATCH] layout for dma_blk fifo (instead of raw offsets) --- .../sbus_to_fpga_blk_dma.py | 21 ++++++++---- .../sbus_to_fpga_fsm.py | 32 +++++++++++++------ .../sbus_to_fpga_soc.py | 31 ++++++++++++++---- 3 files changed, 62 insertions(+), 22 deletions(-) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py index bb30fd1..1c563ca 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py @@ -20,6 +20,13 @@ class ExchangeWithMem(Module, AutoCSR): self.dram_dma_writer = dram_dma_writer self.dram_dma_reader = dram_dma_reader + tosbus_fifo_din = Record(soc.tosbus_layout) + self.comb += self.tosbus_fifo.din.eq(tosbus_fifo_din.raw_bits()) + fromsbus_req_fifo_din = Record(soc.fromsbus_req_layout) + self.comb += self.fromsbus_req_fifo.din.eq(fromsbus_req_fifo_din.raw_bits()) + fromsbus_fifo_dout = Record(soc.fromsbus_layout) + self.comb += fromsbus_fifo_dout.raw_bits().eq(self.fromsbus_fifo.dout) + print(f"Configuring the SDRAM for {mem_size} MiB\n") data_width = burst_size * 4 @@ -186,7 +193,8 @@ class ExchangeWithMem(Module, AutoCSR): req_r_fsm.act("WaitForData", If(self.dram_dma_reader.source.valid & self.tosbus_fifo.writable, self.tosbus_fifo.we.eq(1), - self.tosbus_fifo.din.eq(Cat(dma_r_addr, self.dram_dma_reader.source.data)), + tosbus_fifo_din.address.eq(dma_r_addr), + tosbus_fifo_din.data.eq(self.dram_dma_reader.source.data), If(do_checksum, self.checksum.we.eq(1), self.checksum.dat_w.eq(self.checksum.storage ^ self.dram_dma_reader.source.data), @@ -209,7 +217,8 @@ class ExchangeWithMem(Module, AutoCSR): req_r_fsm.act("QueueReqToMemory", If(self.fromsbus_req_fifo.writable, self.fromsbus_req_fifo.we.eq(1), - self.fromsbus_req_fifo.din.eq(Cat(local_r_addr, dma_r_addr)), + fromsbus_req_fifo_din.blkaddress.eq(local_r_addr), + fromsbus_req_fifo_din.dmaaddress.eq(dma_r_addr), NextValue(self.last_blk.status, local_r_addr), NextValue(self.last_dma.status, dma_r_addr), NextValue(self.blk_rem.status, self.blk_rem.status - 1), @@ -257,16 +266,16 @@ class ExchangeWithMem(Module, AutoCSR): ) req_w_fsm.act("Idle", If(self.fromsbus_fifo.readable, - self.dram_dma_writer.sink.address.eq(self.fromsbus_fifo.dout[0:blk_addr_width]), - self.dram_dma_writer.sink.data.eq(self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]), + self.dram_dma_writer.sink.address.eq(fromsbus_fifo_dout.blkaddress), + self.dram_dma_writer.sink.data.eq(fromsbus_fifo_dout.data), self.dram_dma_writer.sink.valid.eq(1), - NextValue(self.wr_tosdram.status, self.fromsbus_fifo.dout[0:blk_addr_width]), + NextValue(self.wr_tosdram.status, fromsbus_fifo_dout.blkaddress), If(self.dram_dma_writer.sink.ready, self.fromsbus_fifo.re.eq(1), NextValue(self.dma_wrdone.status, self.dma_wrdone.status + 1), If(do_checksum, self.checksum.we.eq(1), - self.checksum.dat_w.eq(self.checksum.storage ^ self.fromsbus_fifo.dout[blk_addr_width:(blk_addr_width + data_width_bits)]), + self.checksum.dat_w.eq(self.checksum.storage ^ fromsbus_fifo_dout.data), ) ) ) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index 880a9b4..c8bffc8 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -180,7 +180,7 @@ LED_M_READ = 0x20 LED_M_CACHE = 0x40 class SBusFPGABus(Module): - def __init__(self, platform, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, version, burst_size = 8, cg3_fb_size = 0, cg3_base=0x8ff00000 ): + def __init__(self, soc, platform, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, version, burst_size = 8, cg3_fb_size = 0, cg3_base=0x8ff00000 ): self.platform = platform self.hold_reset = hold_reset @@ -191,6 +191,17 @@ class SBusFPGABus(Module): self.fromsbus_fifo = fromsbus_fifo self.fromsbus_req_fifo = fromsbus_req_fifo + + tosbus_fifo_dout = Record(soc.tosbus_layout) + self.comb += tosbus_fifo_dout.raw_bits().eq(self.tosbus_fifo.dout) + + fromsbus_req_fifo_dout = Record(soc.fromsbus_req_layout) + self.comb += fromsbus_req_fifo_dout.raw_bits().eq(self.fromsbus_req_fifo.dout) + + fromsbus_fifo_din = Record(soc.fromsbus_layout) + self.comb += self.fromsbus_fifo.din.eq(fromsbus_fifo_din.raw_bits()) + + if (cg3_fb_size <= 1*1048576): CG3_UPPER_BITS=12 CG3_KEPT_UPPER_BIT=20 @@ -959,11 +970,11 @@ class SBusFPGABus(Module): NextValue(sbus_oe_master_in, 0), ## ERRs, ACKs are input NextValue(burst_counter, 0), NextValue(burst_limit_m1, burst_size - 1), - NextValue(SBUS_3V3_D_o, self.tosbus_fifo.dout[0:32]), - NextValue(sbus_master_last_virtual, self.tosbus_fifo.dout[0:32]), - NextValue(master_addr, self.tosbus_fifo.dout[2:32]), - NextValue(master_data, self.tosbus_fifo.dout[32:64]), - NextValue(fifo_buffer, self.tosbus_fifo.dout[32:]), + NextValue(SBUS_3V3_D_o, tosbus_fifo_dout.address), + NextValue(sbus_master_last_virtual, tosbus_fifo_dout.address), + NextValue(master_addr, tosbus_fifo_dout.address[2:32]), + NextValue(master_data, tosbus_fifo_dout.data[0:32]), + NextValue(fifo_buffer, tosbus_fifo_dout.data), NextValue(master_src, MASTER_SRC_BLKDMAFIFO), self.tosbus_fifo.re.eq(1), Case(burst_size, { @@ -995,9 +1006,9 @@ class SBusFPGABus(Module): NextValue(sbus_oe_master_in, 0), ## ERRs, ACKs are input NextValue(burst_counter, 0), NextValue(burst_limit_m1, burst_size - 1), - NextValue(SBUS_3V3_D_o, self.fromsbus_req_fifo.dout[blk_addr_width:blk_addr_width+32]), - NextValue(sbus_master_last_virtual, self.fromsbus_req_fifo.dout[blk_addr_width:blk_addr_width+32]), - NextValue(fifo_blk_addr, self.fromsbus_req_fifo.dout[0:blk_addr_width]), + NextValue(SBUS_3V3_D_o, fromsbus_req_fifo_dout.dmaaddress), + NextValue(sbus_master_last_virtual, fromsbus_req_fifo_dout.dmaaddress), + NextValue(fifo_blk_addr, fromsbus_req_fifo_dout.blkaddress), NextValue(master_src, MASTER_SRC_BLKDMAFIFO), self.fromsbus_req_fifo.re.eq(1), Case(burst_size, { @@ -1635,7 +1646,8 @@ class SBusFPGABus(Module): Case(master_src, { MASTER_SRC_BLKDMAFIFO: [fromsbus_fifo.we.eq(1), - fromsbus_fifo.din.eq(Cat(fifo_blk_addr, fifo_buffer)), + fromsbus_fifo_din.blkaddress.eq(fifo_blk_addr), + fromsbus_fifo_din.data.eq(fifo_buffer), ], }), NextValue(sbus_oe_data, 0), diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index c83faae..8a2804b 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -383,15 +383,33 @@ class SBusFPGA(SoCCore): # burst_size=16 should work on Ultra systems, but then they probably should go for 64-bits ET as well... # Older systems are probably limited to burst_size=4, (it should always be available) burst_size=8 - self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=(32+burst_size*32), depth=burst_size)) - self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+burst_size*32), depth=burst_size)) - self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+32), depth=burst_size)) + + data_width = burst_size * 4 + data_width_bits = burst_size * 32 + blk_addr_width = 32 - log2_int(data_width) + + self.tosbus_layout = [ + ("address", 32), + ("data", data_width_bits), + ] + self.fromsbus_layout = [ + ("blkaddress", blk_addr_width), + ("data", data_width_bits), + ] + self.fromsbus_req_layout = [ + ("blkaddress", blk_addr_width), + ("dmaaddress", 32), + ] + + self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=burst_size)) + self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=burst_size)) + self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=burst_size)) if (sdram): - self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=burst_size*32), + self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) - self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=burst_size*32), + self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) @@ -414,7 +432,8 @@ class SBusFPGA(SoCCore): self.comb += pad_sdram_interrupt.eq(sig_sdram_interrupt) self.comb += sig_sdram_interrupt.eq(~self.exchange_with_mem.irq) ## - _sbus_bus = SBusFPGABus(platform=self.platform, + _sbus_bus = SBusFPGABus(soc=self, + platform=self.platform, hold_reset=hold_reset, wishbone_slave=wishbone_slave_sbus, wishbone_master=self.wishbone_master_sbus,