changes to be able to test cg3/cg6 support with original PROM contents
This commit is contained in:
Romain Dolbeau
parent
7fb915237d
commit
479b976567
@ -11,7 +11,7 @@ class CG6Accel(Module): # AutoCSR ?
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def __init__(self, soc, base_fb, hres, vres):
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platform = soc.platform
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# for FBC and TEC - where we just ignore TEC
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# for FBC and TEC
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self.bus = bus = wishbone.Interface()
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self.COORD_BITS = COORD_BITS = 12
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@ -86,7 +86,7 @@ class CG6Accel(Module): # AutoCSR ?
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wishbone_fsm.act("Idle",
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self.fbc_fifo_font.we.eq(0),
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If(bus.cyc & bus.stb & bus.we & ~bus.ack, #write
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Case(bus.adr[0:11], {
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Case(bus.adr[0:12], { # the thirteenth bit is to match the FBC but not the TEC
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"default": [ ],
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# 0: fbc_config R/O
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1: [ NextValue(fbc_mode, bus.dat_w) ],
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@ -166,7 +166,7 @@ class CG6Accel(Module): # AutoCSR ?
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}),
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NextValue(bus.ack, 1),
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).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
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Case(bus.adr[0:11], {
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Case(bus.adr[0:12], { # the thirteenth bit is to match the FBC but not the TEC
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"default": [ NextValue(bus.dat_r, 0xDEADBEEF) ],
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0: [ NextValue(bus.dat_r, fbc_config) ],
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1: [ NextValue(bus.dat_r, fbc_mode) ],
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@ -177,13 +177,13 @@ class CG6Accel(Module): # AutoCSR ?
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],
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# 5: fbc_draw R/O -> start a "draw" on R
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5: [ NextValue(fbc_do_draw, ~fbc_s[GX_INPROGRESS_BIT]), # ignore command while working
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NextValue(bus.dat_r, 0),
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NextValue(bus.dat_r, fbc_s), # FIXME, returns the FULL and INPROGRESS bit only
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_do_draw | fbc_do_blit),
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_s[GX_INPROGRESS_BIT]),
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],
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# 6: fbc_blit R/O -> start a "blit" on R
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6: [ NextValue(fbc_do_blit, ~fbc_s[GX_INPROGRESS_BIT]), # ignore command while working
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NextValue(bus.dat_r, 0),
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NextValue(bus.dat_r, fbc_s), # FIXME, returns the FULL and INPROGRESS bit only
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_do_draw | fbc_do_blit),
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_s[GX_INPROGRESS_BIT]),
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],
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@ -197,21 +197,23 @@ class CG6Accel(Module): # AutoCSR ?
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41: [ NextValue(bus.dat_r, fbc_y[2]) ],
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44: [ NextValue(bus.dat_r, fbc_x[3]) ], # 0x0b0
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45: [ NextValue(bus.dat_r, fbc_y[3]) ], # 0x0b4
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48: [ NextValue(bus.dat_r, fbc_offx) ],
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48: [ NextValue(bus.dat_r, fbc_offx) ], # 0x0c0
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49: [ NextValue(bus.dat_r, fbc_offy) ],
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52: [ NextValue(bus.dat_r, fbc_incx) ], # 0x0d0
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53: [ NextValue(bus.dat_r, fbc_incy) ],
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# 54-55: pad81
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56: [ NextValue(bus.dat_r, fbc_clipminx) ],
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56: [ NextValue(bus.dat_r, fbc_clipminx) ], # 0x0e0
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57: [ NextValue(bus.dat_r, fbc_clipminy) ],
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# 58-59: pad9
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60: [ NextValue(bus.dat_r, fbc_clipmaxx) ],
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60: [ NextValue(bus.dat_r, fbc_clipmaxx) ], # 0x0f0
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61: [ NextValue(bus.dat_r, fbc_clipmaxy) ],
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# 62-63: pad10
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64: [ NextValue(bus.dat_r, fbc_fg) ], # 0x100
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65: [ NextValue(bus.dat_r, fbc_bg) ], # 0x104
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66: [ NextValue(bus.dat_r, fbc_alu) ], # 0x108
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67: [ NextValue(bus.dat_r, fbc_pm) ], # 0x10c
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67: [ NextValue(bus.dat_r, fbc_pm) ], # 0x10c # planemask
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#68: pixelmask (written to 0xFFFFFFFF by 510-2325 prom)
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#72-79: patterns (written to 0xFFFFFFFF by 510-2325 prom)
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576: [ NextValue(bus.dat_r, fbc_arectx),
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],
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577: [ NextValue(bus.dat_r, fbc_arecty),
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@ -287,7 +289,7 @@ class CG6Accel(Module): # AutoCSR ?
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If(fbc_r5_cmd[FUN_DONE_BIT],
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fbc_r5_cmd.eq(0),
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fbc_s[GX_INPROGRESS_BIT].eq(0),
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#fbc_s[GX_FULL_BIT].eq(0),
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fbc_s[GX_FULL_BIT].eq(0),
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local_reset.eq(1),
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#timeout.eq(timeout_rst),
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).Elif(self.fbc_fifo_font.readable & fbc_s[GX_INPROGRESS_BIT] & fbc_r5_cmd[FUN_FONT_NEXT_REQ_BIT] & (fbc_r5_cmd[0:4] == 0x4),
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@ -313,21 +315,21 @@ class CG6Accel(Module): # AutoCSR ?
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fbc_next_y0.eq(fbc_fifo_font_out.y0),
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fbc_r5_cmd.eq(FUN_FONT), # includes FUN_FONT_NEXT_RDY_BIT
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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#fbc_s[GX_FULL_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(fbc_do_draw & ~fbc_s[GX_INPROGRESS_BIT],
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fbc_do_draw.eq(0),
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fbc_r5_cmd.eq(FUN_DRAW),
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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#fbc_s[GX_FULL_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(fbc_do_blit & ~fbc_s[GX_INPROGRESS_BIT],
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fbc_do_blit.eq(0),
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fbc_r5_cmd.eq(FUN_BLIT),
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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#fbc_s[GX_FULL_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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@ -336,7 +338,7 @@ class CG6Accel(Module): # AutoCSR ?
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#).Elif((timeout == 0) & fbc_s[GX_INPROGRESS_BIT], # OUPS
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# fbc_r5_cmd.eq(0),
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# fbc_s[GX_INPROGRESS_BIT].eq(0),
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# #fbc_s[GX_FULL_BIT].eq(0),
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# fbc_s[GX_FULL_BIT].eq(0),
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# local_reset.eq(1),
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# timeout.eq(timeout_rst),
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#),
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@ -163,7 +163,8 @@ class cg6(Module, AutoCSR):
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#pad_SBUS_DATA_OE_LED = soc.platform.request("SBUS_DATA_OE_LED")
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#self.comb += pad_SBUS_DATA_OE_LED.eq((hwcursor_x < 1280) & (hwcursor_y < 1024));
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# FHC / THC
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self.bus2 = bus2 = wishbone.Interface()
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self.submodules.wishbone_fsm2 = wishbone_fsm2 = FSM(reset_state = "Reset")
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wishbone_fsm2.act("Reset",
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@ -171,13 +172,13 @@ class cg6(Module, AutoCSR):
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NextState("Idle"))
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wishbone_fsm2.act("Idle",
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If(bus2.cyc & bus2.stb & bus2.we & ~bus2.ack, #write
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Case(bus2.adr[0:11], {
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Case(bus2.adr[0:12], {
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"default": [ ],
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1599: [ NextValue(hwcursor_x, bus2.dat_w[16:28]),
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NextValue(hwcursor_y, bus2.dat_w[ 0:12]),
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],
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}),
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Case(bus2.adr[5:11], {
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Case(bus2.adr[5:12], {
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"default": [ ],
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50 : [ upd_overlay_fifo.we.eq(1), # 50*32 = 1600..1631
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upd_overlay_fifo.din.eq(Cat(Signal(1, reset = 0), 31-bus2.adr[0:5], bus2.dat_w))
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@ -188,13 +189,32 @@ class cg6(Module, AutoCSR):
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}),
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NextValue(bus2.ack, 1),
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).Elif(bus2.cyc & bus2.stb & ~bus2.we & ~bus2.ack, #read
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Case(bus2.adr[0:10], {
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Case(bus2.adr[0:12], {
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"default": [ NextValue(bus2.dat_r, 0xDEADBEEF) ],
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0: [ NextValue(bus2.dat_r, 0x60b00000) ], # claim revision 11 (TurboGX)
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# my TGX+ is 0x64b009ff as a console in 1152x900
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#0: [ NextValue(bus2.dat_r, 0x64b009ff) ], # claim revision 11 (TurboGX), that's the 0xb<<20
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0: [ NextValue(bus2.dat_r, 0x64b509ff) ], # claim revision 11 (TurboGX), that's the 0xb<<20
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}),
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NextValue(bus2.ack, 1),
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).Else(
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NextValue(bus2.ack, 0),
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)
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)
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# ALT catch-all
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self.bus3 = bus3 = wishbone.Interface()
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self.submodules.wishbone_fsm3 = wishbone_fsm3 = FSM(reset_state = "Reset")
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wishbone_fsm3.act("Reset",
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NextValue(bus3.ack, 0),
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NextState("Idle"))
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wishbone_fsm3.act("Idle",
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If(bus3.cyc & bus3.stb & bus3.we & ~bus3.ack, #write
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NextValue(bus3.ack, 1),
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).Elif(bus3.cyc & bus3.stb & ~bus3.we & ~bus3.ack, #read
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NextValue(bus3.dat_r, 0xDEADBEEF),
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NextValue(bus3.ack, 1),
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).Else(
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NextValue(bus3.ack, 0),
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)
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)
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@ -150,8 +150,8 @@ class ExchangeWithMem(Module, AutoCSR):
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self.irqctrl.we.eq(0),
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)
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pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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self.comb += pad_SBUS_DATA_OE_LED.eq(self.irq)
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#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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#self.comb += pad_SBUS_DATA_OE_LED.eq(self.irq)
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#self.comb += self.dma_status.status[16:17].eq(self.wishbone_w_master.cyc) # show the WB iface status (W)
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#self.comb += self.dma_status.status[17:18].eq(self.wishbone_w_master.stb)
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@ -32,6 +32,7 @@ SRAM_ADDR_PFX = Signal(12, reset = 0x009) # unmapped ; LE
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ENGINE_ADDR_PFXA = Signal(12, reset = 0x00a)
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ENGINE_ADDR_PFXB = Signal(12, reset = 0x00b)
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CG6_BT_ADDR_PFX = Signal(12, reset = 0x020)
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CG6_ALT_ADDR_PFX = Signal(12, reset = 0x028)
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CG6_FHC_ADDR_PFX = Signal(12, reset = 0x030)
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CG3_BT_ADDR_PFX = Signal(12, reset = 0x040)
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FBC_ROM_ADDR_PFX = Signal(12, reset = 0x041)
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@ -492,6 +493,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_PARITY),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
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@ -502,6 +504,7 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXA) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXB) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_ALT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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@ -548,6 +551,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_ADDRESS),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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)
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# ***** Slave Byte Read *****
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@ -603,6 +607,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_ADDRESS),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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)
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# ***** Slave HalfWord Read *****
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@ -616,9 +621,11 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_PARITY),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ROM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
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@ -664,6 +671,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_ADDRESS),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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)
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# ***** Slave (Multi-)Word Write *****
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@ -685,6 +693,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_PARITY),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == FBC_ROM_ADDR_PFX) |
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@ -694,6 +703,7 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXA) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == ENGINE_ADDR_PFXB) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_ALT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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@ -727,6 +737,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_ADDRESS),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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)
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# ***** Slave Byte Write *****
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@ -768,6 +779,7 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_ADDRESS),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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)
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# ***** Slave HalfWord Write *****
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@ -781,8 +793,10 @@ class SBusFPGABus(Module):
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NextValue(SBUS_3V3_ERRs_o, 1),
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#NextValue(led0123, led0123 | LED_PARITY),
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NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
|
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).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
|
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
|
||||
(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
|
||||
NextValue(sbus_wishbone_le,
|
||||
@ -815,6 +829,7 @@ class SBusFPGABus(Module):
|
||||
NextValue(SBUS_3V3_ERRs_o, 1),
|
||||
#NextValue(led0123, led0123 | LED_ADDRESS),
|
||||
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
|
||||
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
|
||||
NextState("Slave_Error")
|
||||
)
|
||||
).Elif(self.wishbone_slave.cyc &
|
||||
@ -1033,6 +1048,7 @@ class SBusFPGABus(Module):
|
||||
#NextValue(self.led_display.value, 0x000000000F | Cat(Signal(8, reset = 0x00), SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, SBUS_3V3_PPRD_i)),
|
||||
#NextValue(led0123, led0123 | LED_UNKNOWNREQ),
|
||||
NextValue(stat_slave_early_error_counter, stat_slave_early_error_counter + 1),
|
||||
#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
|
||||
NextState("Slave_Error")
|
||||
).Elif(~SBUS_3V3_BGs_i,
|
||||
### ouch we got the bus but nothing more to do ?!?
|
||||
|
||||
@ -277,6 +277,7 @@ class SBusFPGA(SoCCore):
|
||||
"curve25519engine": 0x000a0000, # includes microcode (4 KiB@0) and registers (16 KiB @ 64 KiB)
|
||||
"cg6_bt": 0x00200000, # required for compatibility, bt_regs for cg6
|
||||
#"cg6_dhc": 0x00240000, # required for compatibility, unused
|
||||
"cg6_alt": 0x00280000, # required for compatibility
|
||||
"cg6_fhc": 0x00300000, # required for compatibility
|
||||
#"cg6_thc": 0x00301000, # required for compatibility
|
||||
"cg3_bt": 0x00400000, # required for compatibility, bt_regs for cg3 & bw2
|
||||
@ -337,15 +338,18 @@ class SBusFPGA(SoCCore):
|
||||
#self.comb += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_INT1s_o)
|
||||
|
||||
prom_file = "prom_{}.fc".format(version.replace(".", "_"))
|
||||
#prom_file = "SUNW,501-2325.bin" # real TGX
|
||||
#prom_file = "SUNW,501-1415.bin" # real cg3
|
||||
#prom_file = "SUNW,501-2253.bin" # real TGX+
|
||||
prom_data = soc_core.get_mem_data(prom_file, "big")
|
||||
# prom = Array(prom_data)
|
||||
#print("\n****************************************\n")
|
||||
#for i in range(len(prom)):
|
||||
# print(hex(prom[i]))
|
||||
#print("\n****************************************\n")
|
||||
self.add_ram("prom", origin=self.mem_map["prom"], size=2**14, contents=prom_data, mode="r") ### FIXME: round up the prom_data size & check for <= 2**16!
|
||||
self.add_ram("prom", origin=self.mem_map["prom"], size=2**15, contents=prom_data, mode="r") ### FIXME: round up the prom_data size & check for <= 2**16!
|
||||
#getattr(self,"prom").mem.init = prom_data
|
||||
#getattr(self,"prom").mem.depth = 2**14
|
||||
#getattr(self,"prom").mem.depth = 2**15
|
||||
|
||||
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR3",
|
||||
@ -357,6 +361,9 @@ class SBusFPGA(SoCCore):
|
||||
l2_cache_size = 0,
|
||||
)
|
||||
avail_sdram = self.bus.regions["main_ram"].size
|
||||
###from sdram_init import DDR3FBInit
|
||||
###self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25)
|
||||
###self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus)
|
||||
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram - 1048576 # placeholder
|
||||
if (framebuffer):
|
||||
@ -510,6 +517,7 @@ class SBusFPGA(SoCCore):
|
||||
self.submodules.cg6_accel = cg6_accel.CG6Accel(soc = self, base_fb = base_fb, hres = hres, vres = vres)
|
||||
self.bus.add_slave("cg6_fbc", self.cg6_accel.bus, SoCRegion(origin=self.mem_map.get("cg6_fbc", None), size=0x2000, cached=False))
|
||||
self.bus.add_slave("cg6_fhc", self.cg6.bus2, SoCRegion(origin=self.mem_map.get("cg6_fhc", None), size=0x2000, cached=False))
|
||||
self.bus.add_slave("cg6_alt", self.cg6.bus3, SoCRegion(origin=self.mem_map.get("cg6_alt", None), size=0x2000, cached=False))
|
||||
self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus)
|
||||
self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus)
|
||||
cg6_rom_file = "blit.raw"
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user