diff --git a/sbus-to-ztex-gateware-migen/netbsd_csr.h b/sbus-to-ztex-gateware-migen/netbsd_csr.h index 3b9549d..534c79e 100644 --- a/sbus-to-ztex-gateware-migen/netbsd_csr.h +++ b/sbus-to-ztex-gateware-migen/netbsd_csr.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-18 09:29:51 +// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-07-18 12:35:05 //-------------------------------------------------------------------------------- #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H diff --git a/sbus-to-ztex-gateware-migen/prom_migen.fth b/sbus-to-ztex-gateware-migen/prom_migen.fth index d07a0cb..6b0821d 100644 --- a/sbus-to-ztex-gateware-migen/prom_migen.fth +++ b/sbus-to-ztex-gateware-migen/prom_migen.fth @@ -41,7 +41,7 @@ finish-device new-device \ Absolute minimal stuff; name & registers def. -" DISABLED-generic-ohci" device-name +" generic-ohci" device-name \ USB registers are in the device space, not the CSR space my-address sbusfpga_regionaddr_usb_host_ctrl + my-space h# 1000 reg diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index 658203b..40333e8 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -297,10 +297,10 @@ class SBusFPGABus(Module): #self.submodules.led_display = LedDisplay(platform.request_all("user_led")) self.sync += platform.request("user_led", 4).eq(self.wishbone_slave.cyc) - #self.sync += platform.request("user_led", 5).eq(self.wishbone_slave.stb) - #self.sync += platform.request("user_led", 6).eq(self.wishbone_slave.we) - #self.sync += platform.request("user_led", 7).eq(self.wishbone_slave.ack) - #self.sync += platform.request("user_led", 4).eq(self.wishbone_slave.err) + self.sync += platform.request("user_led", 5).eq(self.wishbone_slave.stb) + self.sync += platform.request("user_led", 6).eq(self.wishbone_slave.we) + self.sync += platform.request("user_led", 7).eq(self.wishbone_slave.ack) + #self.sync += platform.request("user_led", 0).eq(self.wishbone_slave.err) #led4 = platform.request("user_led", 4) #led5 = platform.request("user_led", 5) #led6 = platform.request("user_led", 6) @@ -345,21 +345,22 @@ class SBusFPGABus(Module): self.master_read_buffer_done = Array(Signal() for a in range(4)) self.master_read_buffer_read = Array(Signal() for a in range(4)) self.master_read_buffer_start = Signal() + + #self.sync += platform.request("user_led", 1).eq(self.master_read_buffer_start) - self.master_write_buffer_data = Array(Signal(32) for a in range(4)) - self.master_write_buffer_addr = Signal(28) - self.master_write_buffer_todo = Array(Signal() for a in range(4)) - self.master_write_buffer_start = Signal() + #self.master_write_buffer_data = Array(Signal(32) for a in range(4)) + #self.master_write_buffer_addr = Signal(28) + #self.master_write_buffer_todo = Array(Signal() for a in range(4)) + #self.master_write_buffer_start = Signal() self.submodules.slave_fsm = slave_fsm = FSM(reset_state="Reset") - self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle")) - self.sync += platform.request("user_led", 0).eq(slave_fsm.ongoing("Master_Translation")) - self.sync += platform.request("user_led", 1).eq(slave_fsm.ongoing("Master_Read") | - slave_fsm.ongoing("Master_Read_Ack") | - slave_fsm.ongoing("Master_Read_Finish") | - slave_fsm.ongoing("Master_Write") | - slave_fsm.ongoing("Master_Write_Final")) + #self.sync += platform.request("user_led", 0).eq(slave_fsm.ongoing("Master_Translation")) + #self.sync += platform.request("user_led", 1).eq(slave_fsm.ongoing("Master_Read") | + # slave_fsm.ongoing("Master_Read_Ack") | + # slave_fsm.ongoing("Master_Read_Finish") | + # slave_fsm.ongoing("Master_Write") | + # slave_fsm.ongoing("Master_Write_Final")) self.sync += platform.request("user_led", 2).eq(slave_fsm.ongoing("Slave_Do_Read") | slave_fsm.ongoing("Slave_Ack_Read_Reg_Burst") | slave_fsm.ongoing("Slave_Ack_Read_Reg_Burst_Wait_For_Data") | @@ -378,8 +379,9 @@ class SBusFPGABus(Module): slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte") | slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte_Wait_For_Wishbone")) - self.sync += platform.request("user_led", 6).eq(master_data_src_tosbus_fifo) - self.sync += platform.request("user_led", 7).eq(master_data_src_fromsbus_fifo) + #self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle")) + #self.sync += platform.request("user_led", 6).eq(master_data_src_tosbus_fifo) + #self.sync += platform.request("user_led", 7).eq(master_data_src_fromsbus_fifo) slave_fsm.act("Reset", #NextValue(self.led_display.value, 0x0000000000), @@ -634,7 +636,6 @@ class SBusFPGABus(Module): (wishbone_slave_timeout == 0), ## sel == 0 so nothing to write, don't acquire the SBus NextValue(self.wishbone_slave.ack, 1), - NextValue(wishbone_slave_timeout, wishbone_default_timeout), ).Elif(SBUS_3V3_BGs_i & self.wishbone_slave.cyc & self.wishbone_slave.stb & @@ -1283,7 +1284,9 @@ class SBusFPGABus(Module): ), NextValue(burst_counter, burst_counter + 1), If(burst_counter == burst_limit_m1, - NextValue(self.master_read_buffer_start, 0), + If(~master_data_src_fromsbus_fifo, + NextValue(self.master_read_buffer_start, 0), + ), NextState("Master_Read_Finish") ).Else( Case(SBUS_3V3_ACKs_i, { @@ -1460,7 +1463,8 @@ class SBusFPGABus(Module): # ##### Slave read buffering FSM #### last_read_word_idx = Signal(2) self.submodules.wishbone_slave_read_buffering_fsm = wishbone_slave_read_buffering_fsm = FSM(reset_state="Reset") - #self.sync += led4.eq(self.master_read_buffer_start) + self.sync += platform.request("user_led", 0).eq(~wishbone_slave_read_buffering_fsm.ongoing("Idle")) + self.sync += platform.request("user_led", 1).eq(self.master_read_buffer_done[last_read_word_idx]) wishbone_slave_read_buffering_fsm.act("Reset", NextState("Idle") ) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index 9b243ba..78f4152 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -184,6 +184,9 @@ class SBusFPGA(SoCCore): self.submodules.wishbone_master_sbus = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="sbus", cd_slave="sys") self.submodules.wishbone_slave_sys = wishbone.WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_sbus, cd_master="sys", cd_slave="sbus") + # SPARCstation 20 slave interface to the main memory are limited to 32-bytes burst (32-bits wide, 8 word long) + # burst_size=16 should work on Ultra systems, but then they probably should go for 64-bits ET as well... + # Older systems are probably limited to burst_size=4, (it should always be available) burst_size=8 self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=(32+burst_size*32), depth=4)) self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+burst_size*32), depth=4))